* [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0
@ 2023-10-25 15:13 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Max Chou
This patchset updates the RISC-V vector cryptography support to the
ratified version v1.0.0 (commit 1769c26, released on 2023/10) with
following items:
- Add Zvkb, Zvkt, and other shorthand extensions(Zvkn, Zvknc, Zvkng,
Zvks, Zvksc, Zvksg).
- Supports the disassembler for vector crypto extensions.
- Move vector crypto extensions from experimental extensions to ratified
extensions.
- Replace TAB indentations with spaces in disas/riscv.c.
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0
Max Chou (14):
target/riscv: Add cfg property for Zvkt extension
target/riscv: Expose Zvkt extension property
target/riscv: Add cfg property for Zvkb extension
target/riscv: Replace Zvbb checking by Zvkb
target/riscv: Expose Zvkb extension property
target/riscv: Add cfg properties for Zvkn[c|g] extensions
target/riscv: Expose Zvkn[c|g] extnesion properties
target/riscv: Add cfg properties for Zvks[c|g] extensions
target/riscv: Expose Zvks[c|g] extnesion properties
target/riscv: Move vector crypto extensions to riscv_cpu_extensions
disas/riscv: Add rv_fmt_vd_vs2_uimm format
disas/riscv: Add rv_codec_vror_vi for vror.vi
disas/riscv: Add support for vector crypto extensions
disas/riscv: Replace TABs with space
disas/riscv.c | 154 ++++++++++++++++++++++-
disas/riscv.h | 2 +
target/riscv/cpu.c | 36 ++++--
target/riscv/cpu_cfg.h | 8 ++
target/riscv/insn_trans/trans_rvvk.c.inc | 37 ++++--
target/riscv/tcg/tcg-cpu.c | 48 ++++++-
6 files changed, 256 insertions(+), 29 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-30 4:47 ` Alistair Francis
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
` (12 subsequent siblings)
13 siblings, 1 reply; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e7ce977189c..d8d17dedeed 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -94,6 +94,7 @@ struct RISCVCPUConfig {
bool ext_zvknhb;
bool ext_zvksed;
bool ext_zvksh;
+ bool ext_zvkt;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c5ff03efce9..b9eaecb699c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zvkt) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+ }
+
/*
* In principle Zve*x would also suffice here, were they supported
* in qemu
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 02/14] target/riscv: Expose Zvkt extension property
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a2881bfa383..5099c786415 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
+ ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
+ MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index d8d17dedeed..935335e5721 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -88,6 +88,7 @@ struct RISCVCPUConfig {
bool ext_zve64d;
bool ext_zvbb;
bool ext_zvbc;
+ bool ext_zvkb;
bool ext_zvkg;
bool ext_zvkned;
bool ext_zvknha;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b9eaecb699c..1b08f27eee4 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -508,9 +508,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
* In principle Zve*x would also suffice here, were they supported
* in qemu
*/
- if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
- cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
- !cpu->cfg.ext_zve32f) {
+ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
+ cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
+ cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
error_setg(errp,
"Vector crypto extensions require V or Zve* extensions");
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (2 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Nazar Kazakov,
Lawrence Hunter
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++++++++++++++---------
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index e691519ed78..3801c16829d 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -112,24 +112,27 @@ GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
return false; \
}
-static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a)
+static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a)
{
- return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+ return opivv_check(s, a) &&
+ (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
}
-static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a)
+static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a)
{
- return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true;
+ return opivx_check(s, a) &&
+ (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
}
/* vrol.v[vx] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check)
-GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvkb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvkb_vx_check)
/* vror.v[vxi] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check)
-GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check)
-GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvkb_vv_check)
+GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvkb_vx_check)
+GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri,
+ zvkb_vx_check)
#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
@@ -147,8 +150,8 @@ GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check
}
/* vandn.v[vx] */
-GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check)
-GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check)
+GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvkb_vv_check)
+GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
#define GEN_OPIV_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
@@ -188,8 +191,16 @@ static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
vext_check_ss(s, a->rd, a->rs2, a->vm);
}
-GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check)
-GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check)
+static bool zvkb_opiv_check(DisasContext *s, arg_rmr *a)
+{
+ return (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true) &&
+ require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
+}
+
+GEN_OPIV_TRANS(vbrev8_v, zvkb_opiv_check)
+GEN_OPIV_TRANS(vrev8_v, zvkb_opiv_check)
GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check)
GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check)
GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check)
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 05/14] target/riscv: Expose Zvkb extension property
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (3 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5099c786415..992f8e0f7b0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
+ ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
@@ -1370,6 +1371,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
/* Vector cryptography extensions */
MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
+ MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false),
MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (4 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 935335e5721..fd07aa96a27 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -96,6 +96,9 @@ struct RISCVCPUConfig {
bool ext_zvksed;
bool ext_zvksh;
bool ext_zvkt;
+ bool ext_zvkn;
+ bool ext_zvknc;
+ bool ext_zvkng;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 1b08f27eee4..e460701a13c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -499,6 +499,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ /*
+ * Shorthand vector crypto extensions
+ */
+ if (cpu->cfg.ext_zvknc) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+ }
+
+ if (cpu->cfg.ext_zvkng) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
+ }
+
+ if (cpu->cfg.ext_zvkn) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
+ }
+
if (cpu->cfg.ext_zvkt) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (5 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 992f8e0f7b0..8eae8d3e59c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,7 +127,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
+ ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
+ ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc),
ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
+ ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
@@ -1379,6 +1382,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
+ MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
+ MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
+ MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (6 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Andrew Jones
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 17 +++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fd07aa96a27..7b0ca657a6a 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -99,6 +99,9 @@ struct RISCVCPUConfig {
bool ext_zvkn;
bool ext_zvknc;
bool ext_zvkng;
+ bool ext_zvks;
+ bool ext_zvksc;
+ bool ext_zvksg;
bool ext_zmmul;
bool ext_zvfbfmin;
bool ext_zvfbfwma;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index e460701a13c..f9023ca75c7 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -519,6 +519,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
}
+ if (cpu->cfg.ext_zvksc) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+ }
+
+ if (cpu->cfg.ext_zvksg) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
+ }
+
+ if (cpu->cfg.ext_zvks) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
+ }
+
if (cpu->cfg.ext_zvkt) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (7 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Expose the properties of ShangMi Algorithm Suite related extensions
(Zvks, Zvksc, Zvksg).
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8eae8d3e59c..1709df76a9b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,7 +133,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
+ ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks),
+ ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc),
ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
+ ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
@@ -1385,6 +1388,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
+ MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false),
+ MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false),
+ MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (8 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Max Chou, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1709df76a9b..5b5805399ee 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1342,6 +1342,24 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
+ /* Vector cryptography extensions */
+ MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+ MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
+ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+ MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
+ MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
+ MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
+ MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false),
+ MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false),
+ MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false),
+ MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false),
+ MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false),
+ MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false),
+ MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false),
+ MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false),
+ MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false),
+ MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false),
+
DEFINE_PROP_END_OF_LIST(),
};
@@ -1374,24 +1392,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false),
MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false),
- /* Vector cryptography extensions */
- MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false),
- MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false),
- MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false),
- MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false),
- MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false),
- MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
- MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false),
- MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false),
- MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false),
- MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false),
- MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
- MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
- MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
- MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false),
- MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false),
- MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false),
-
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (9 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Max Chou, Palmer Dabbelt, Alistair Francis
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
disas/riscv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/disas/riscv.h b/disas/riscv.h
index 8abb578b515..b242d73b25e 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -274,6 +274,7 @@ enum {
#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
+#define rv_fmt_vd_vs2_uimm "O\tD,F,u"
#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (10 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Max Chou, Palmer Dabbelt, Alistair Francis
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
disas/riscv.c | 11 +++++++++++
disas/riscv.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 8e89e1d1157..6d60033abab 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst)
return (inst << 34) >> 54;
}
+static uint32_t operand_vzimm6(rv_inst inst)
+{
+ return ((inst << 37) >> 63) << 5 |
+ ((inst << 44) >> 59);
+}
+
static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
@@ -4393,6 +4399,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = operand_vimm(inst);
dec->vm = operand_vm(inst);
break;
+ case rv_codec_vror_vi:
+ dec->rd = operand_rd(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_vzimm6(inst);
+ break;
case rv_codec_vsetvli:
dec->rd = operand_rd(inst);
dec->rs1 = operand_rs1(inst);
diff --git a/disas/riscv.h b/disas/riscv.h
index b242d73b25e..19e5ed2ce63 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -152,6 +152,7 @@ typedef enum {
rv_codec_v_i,
rv_codec_vsetvli,
rv_codec_vsetivli,
+ rv_codec_vror_vi,
rv_codec_zcb_ext,
rv_codec_zcb_mul,
rv_codec_zcb_lb,
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 13/14] disas/riscv: Add support for vector crypto extensions
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (11 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
@ 2023-10-25 15:13 ` Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Max Chou, Palmer Dabbelt, Alistair Francis
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou <max.chou@sifive.com>
---
disas/riscv.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 6d60033abab..5bfa9390c45 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -862,6 +862,47 @@ typedef enum {
rv_op_fltq_q = 831,
rv_op_fleq_h = 832,
rv_op_fltq_h = 833,
+ rv_op_vaesdf_vv = 834,
+ rv_op_vaesdf_vs = 835,
+ rv_op_vaesdm_vv = 836,
+ rv_op_vaesdm_vs = 837,
+ rv_op_vaesef_vv = 838,
+ rv_op_vaesef_vs = 839,
+ rv_op_vaesem_vv = 840,
+ rv_op_vaesem_vs = 841,
+ rv_op_vaeskf1_vi = 842,
+ rv_op_vaeskf2_vi = 843,
+ rv_op_vaesz_vs = 845,
+ rv_op_vandn_vv = 846,
+ rv_op_vandn_vx = 847,
+ rv_op_vbrev_v = 848,
+ rv_op_vbrev8_v = 849,
+ rv_op_vclmul_vv = 850,
+ rv_op_vclmul_vx = 851,
+ rv_op_vclmulh_vv = 852,
+ rv_op_vclmulh_vx = 853,
+ rv_op_vclz_v = 854,
+ rv_op_vcpop_v = 855,
+ rv_op_vctz_v = 856,
+ rv_op_vghsh_vv = 857,
+ rv_op_vgmul_vv = 858,
+ rv_op_vrev8_v = 859,
+ rv_op_vrol_vv = 860,
+ rv_op_vrol_vx = 861,
+ rv_op_vror_vv = 862,
+ rv_op_vror_vx = 863,
+ rv_op_vror_vi = 864,
+ rv_op_vsha2ch_vv = 865,
+ rv_op_vsha2cl_vv = 866,
+ rv_op_vsha2ms_vv = 867,
+ rv_op_vsm3c_vi = 868,
+ rv_op_vsm3me_vv = 869,
+ rv_op_vsm4k_vi = 870,
+ rv_op_vsm4r_vv = 871,
+ rv_op_vsm4r_vs = 872,
+ rv_op_vwsll_vv = 873,
+ rv_op_vwsll_vx = 874,
+ rv_op_vwsll_vi = 875,
} rv_op;
/* register names */
@@ -2008,6 +2049,47 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
{ "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
{ "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
+ { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
+ { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -3176,6 +3258,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0:
switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vv; break;
+ case 1: op = rv_op_vandn_vv; break;
case 2: op = rv_op_vsub_vv; break;
case 4: op = rv_op_vminu_vv; break;
case 5: op = rv_op_vmin_vv; break;
@@ -3198,6 +3281,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 19: op = rv_op_vmsbc_vvm; break;
+ case 20: op = rv_op_vror_vv; break;
+ case 21: op = rv_op_vrol_vv; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_v;
@@ -3226,6 +3311,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 47: op = rv_op_vnclip_wv; break;
case 48: op = rv_op_vwredsumu_vs; break;
case 49: op = rv_op_vwredsum_vs; break;
+ case 53: op = rv_op_vwsll_vv; break;
}
break;
case 1:
@@ -3323,6 +3409,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 9: op = rv_op_vaadd_vv; break;
case 10: op = rv_op_vasubu_vv; break;
case 11: op = rv_op_vasub_vv; break;
+ case 12: op = rv_op_vclmul_vv; break;
+ case 13: op = rv_op_vclmulh_vv; break;
case 16:
switch ((inst >> 15) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
@@ -3338,6 +3426,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5: op = rv_op_vsext_vf4; break;
case 6: op = rv_op_vzext_vf2; break;
case 7: op = rv_op_vsext_vf2; break;
+ case 8: op = rv_op_vbrev8_v; break;
+ case 9: op = rv_op_vrev8_v; break;
+ case 10: op = rv_op_vbrev_v; break;
+ case 12: op = rv_op_vclz_v; break;
+ case 13: op = rv_op_vctz_v; break;
+ case 14: op = rv_op_vcpop_v; break;
}
break;
case 20:
@@ -3406,6 +3500,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 17: op = rv_op_vmadc_vim; break;
+ case 20: case 21: op = rv_op_vror_vi; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_i;
@@ -3437,11 +3532,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 45: op = rv_op_vnsra_wi; break;
case 46: op = rv_op_vnclipu_wi; break;
case 47: op = rv_op_vnclip_wi; break;
+ case 53: op = rv_op_vwsll_vi; break;
}
break;
case 4:
switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vx; break;
+ case 1: op = rv_op_vandn_vx; break;
case 2: op = rv_op_vsub_vx; break;
case 3: op = rv_op_vrsub_vx; break;
case 4: op = rv_op_vminu_vx; break;
@@ -3466,6 +3563,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 19: op = rv_op_vmsbc_vxm; break;
+ case 20: op = rv_op_vror_vx; break;
+ case 21: op = rv_op_vrol_vx; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_x;
@@ -3494,6 +3593,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 45: op = rv_op_vnsra_wx; break;
case 46: op = rv_op_vnclipu_wx; break;
case 47: op = rv_op_vnclip_wx; break;
+ case 53: op = rv_op_vwsll_vx; break;
}
break;
case 5:
@@ -3554,6 +3654,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 9: op = rv_op_vaadd_vx; break;
case 10: op = rv_op_vasubu_vx; break;
case 11: op = rv_op_vasub_vx; break;
+ case 12: op = rv_op_vclmul_vx; break;
+ case 13: op = rv_op_vclmulh_vx; break;
case 14: op = rv_op_vslide1up_vx; break;
case 15: op = rv_op_vslide1down_vx; break;
case 16:
@@ -3686,6 +3788,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 7: op = rv_op_csrrci; break;
}
break;
+ case 29:
+ if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
+ switch ((inst >> 26) & 0b111111) {
+ case 32: op = rv_op_vsm3me_vv; break;
+ case 33: op = rv_op_vsm4k_vi; break;
+ case 34: op = rv_op_vaeskf1_vi; break;
+ case 40:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vaesdm_vv; break;
+ case 1: op = rv_op_vaesdf_vv; break;
+ case 2: op = rv_op_vaesem_vv; break;
+ case 3: op = rv_op_vaesef_vv; break;
+ case 16: op = rv_op_vsm4r_vv; break;
+ case 17: op = rv_op_vgmul_vv; break;
+ }
+ break;
+ case 41:
+ switch ((inst >> 15) & 0b11111) {
+ case 0: op = rv_op_vaesdm_vs; break;
+ case 1: op = rv_op_vaesdf_vs; break;
+ case 2: op = rv_op_vaesem_vs; break;
+ case 3: op = rv_op_vaesef_vs; break;
+ case 7: op = rv_op_vaesz_vs; break;
+ case 16: op = rv_op_vsm4r_vs; break;
+ }
+ break;
+ case 42: op = rv_op_vaeskf2_vi; break;
+ case 43: op = rv_op_vsm3c_vi; break;
+ case 44: op = rv_op_vghsh_vv; break;
+ case 45: op = rv_op_vsha2ms_vv; break;
+ case 46: op = rv_op_vsha2ch_vv; break;
+ case 47: op = rv_op_vsha2cl_vv; break;
+ }
+ }
+ break;
case 30:
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 14/14] disas/riscv: Replace TABs with space
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
` (12 preceding siblings ...)
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
@ 2023-10-25 15:13 ` Max Chou
13 siblings, 0 replies; 16+ messages in thread
From: Max Chou @ 2023-10-25 15:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Max Chou, Palmer Dabbelt, Alistair Francis
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 5bfa9390c45..128478a3a09 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3136,12 +3136,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 89:
- switch (((inst >> 12) & 0b111)) {
+ switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_d_x; break;
}
break;
case 91:
- switch (((inst >> 12) & 0b111)) {
+ switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_q_x; break;
}
break;
@@ -4578,7 +4578,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
break;
case rv_codec_zcmt_jt:
dec->imm = operand_tbl_index(inst);
- break;
+ break;
case rv_codec_fli:
dec->rd = operand_rd(inst);
dec->imm = operand_rs1(inst);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
@ 2023-10-30 4:47 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2023-10-30 4:47 UTC (permalink / raw)
To: Max Chou
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Andrew Jones
On Thu, Oct 26, 2023 at 1:15 AM Max Chou <max.chou@sifive.com> wrote:
>
> Vector crypto spec defines the Zvkt extension that included all of the
> instructions of Zvbb & Zvbc extensions and some vector instructions.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/tcg/tcg-cpu.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e7ce977189c..d8d17dedeed 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -94,6 +94,7 @@ struct RISCVCPUConfig {
> bool ext_zvknhb;
> bool ext_zvksed;
> bool ext_zvksh;
> + bool ext_zvkt;
> bool ext_zmmul;
> bool ext_zvfbfmin;
> bool ext_zvfbfwma;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c5ff03efce9..b9eaecb699c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (cpu->cfg.ext_zvkt) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> + }
> +
> /*
> * In principle Zve*x would also suffice here, were they supported
> * in qemu
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-10-30 4:48 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-25 15:13 [PATCH 00/14] Update RISC-V vector crypto to ratified v1.0.0 Max Chou
2023-10-25 15:13 ` [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Max Chou
2023-10-30 4:47 ` Alistair Francis
2023-10-25 15:13 ` [PATCH 02/14] target/riscv: Expose Zvkt extension property Max Chou
2023-10-25 15:13 ` [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Max Chou
2023-10-25 15:13 ` [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Max Chou
2023-10-25 15:13 ` [PATCH 05/14] target/riscv: Expose Zvkb extension property Max Chou
2023-10-25 15:13 ` [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Max Chou
2023-10-25 15:13 ` [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Max Chou
2023-10-25 15:13 ` [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Max Chou
2023-10-25 15:13 ` [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Max Chou
2023-10-25 15:13 ` [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Max Chou
2023-10-25 15:13 ` [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Max Chou
2023-10-25 15:13 ` [PATCH 14/14] disas/riscv: Replace TABs with space Max Chou
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