[PATCH 0/2] Support JTAG for VisionFive2 board

[PATCH 0/2] Support JTAG for VisionFive2 board

[Chanho Park]

To support JTAG for VisionFive2 board, we need to control JTAG pins by
S/W. spl_board_init_f function seems to be proper place to initialize
these pins.

Chanho Park (2):
  riscv: cpu: jh7110: Add gpio helper macros
  board: starfive: spl: Support jtag for VisionFive2 board

 arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++++++++++++++++++++++
 board/starfive/visionfive2/spl.c          | 23 ++++++
 2 files changed, 108 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h

-- 
2.39.2

[PATCH 1/2] riscv: cpu: jh7110: Add gpio helper macros

[Chanho Park]

Add gpio.h header file that includes JH7110 helper macros. The file is
imported from StarFive github[1] with small changes such as alignment.

[1]: https://github.com/starfive-tech/u-boot

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h

diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
new file mode 100644
index 000000000000..90aa2f8a9ed4
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author:	yanhong <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _GPIO_STARFIVE_H_
+#define _GPIO_STARFIVE_H_
+
+#include <asm/arch/regs.h>
+
+#define GPIO_NUM_SHIFT		2 /*one dword include 4 gpios*/
+#define GPIO_BYTE_SHIFT		3
+
+#define GPIO_INDEX_MASK		0x3
+
+#define GPIO_DOEN_MASK		0x3f
+#define GPIO_DOUT_MASK		0x7f
+#define GPIO_DIN_MASK		0x7f
+#define GPIO_DS_MASK		0x06
+#define GPIO_DS_SHIFT		1
+#define GPIO_SLEW_MASK		BIT(5)
+#define GPIO_SLEW_SHIFT		5
+#define GPIO_PULL_MASK		0x18
+#define GPIO_PULL_SHIFT		3
+#define GPIO_PULL_UP		1
+#define GPIO_PULL_DOWN		2
+
+#define NR_GPIOS		64
+
+#define GPIO_OFFSET(gpio)	\
+	(((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT)
+
+#define GPIO_SHIFT(gpio) \
+	(((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT)
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+#define GPIO_DOEN		0x0
+#define GPIO_DOUT		0x40
+#define GPIO_DIN		0x80
+#define GPIO_EN			0xdc
+#define GPIO_LOW_IE		0x100
+#define GPIO_HIGH_IE		0x104
+#define GPIO_CONFIG		0x120
+
+#define SYS_IOMUX_DOEN(gpio, oen) \
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \
+		GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
+		(oen) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DOUT(gpio, gpo) \
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \
+			GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \
+			((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DIN(gpio, gpi)\
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+			GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+			((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
+#define SYS_IOMUX_SET_DS(gpio, ds) \
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+			GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
+
+#define SYS_IOMUX_SET_SLEW(gpio, slew) \
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+			GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT)
+
+#define SYS_IOMUX_SET_PULL(gpio, pull) \
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+			GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT)
+
+#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \
+	do { \
+		SYS_IOMUX_DOEN(gpio, oen); \
+		SYS_IOMUX_DOUT(gpio, gpo); \
+		SYS_IOMUX_DIN(gpio, gpi); \
+	} while (0)
+
+#endif /* _GPIO_STARFIVE_H_ */
-- 
2.39.2

[PATCH 2/2] board: starfive: spl: Support jtag for VisionFive2 board

[Chanho Park]

JTAG pins are mapped as below. To access the JTAG pins, we need to
control the GPIO pins from SPL which seems to be the earliest stage for
JTAG.

- JTAG nTRST:	GPIO36 / Input
- JTAG TDI:	GPIO61 / Input
- JTAG TMS:	GPIO63 / Input
- JTAG TCK:	GPIO60 / Input
- JTAG TDO:	GPIO44 / Output

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 board/starfive/visionfive2/spl.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ad5f71a20180..336f0cdfc90f 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/arch/eeprom.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/regs.h>
 #include <asm/arch/spl.h>
 #include <asm/io.h>
@@ -172,10 +173,32 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
 	/* Update the memory size which read form eeprom or DT */
 	fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
 }
+
+static void jh7110_jtag_init(void)
+{
+	/* nTRST: GPIO36 */
+	SYS_IOMUX_DOEN(36, HIGH);
+	SYS_IOMUX_DIN(36, 4);
+	/* TDI: GPIO61 */
+	SYS_IOMUX_DOEN(61, HIGH);
+	SYS_IOMUX_DIN(61, 19);
+	/* TMS: GPIO63 */
+	SYS_IOMUX_DOEN(63, HIGH);
+	SYS_IOMUX_DIN(63, 20);
+	/* TCK: GPIO60 */
+	SYS_IOMUX_DOEN(60, HIGH);
+	SYS_IOMUX_DIN(60, 29);
+	/* TDO: GPIO44 */
+	SYS_IOMUX_DOEN(44, 8);
+	SYS_IOMUX_DOUT(44, 22);
+}
+
 int spl_board_init_f(void)
 {
 	int ret;
 
+	jh7110_jtag_init();
+
 	ret = spl_soc_init();
 	if (ret) {
 		debug("JH7110 SPL init failed: %d\n", ret);
-- 
2.39.2

Re: [PATCH 1/2] riscv: cpu: jh7110: Add gpio helper macros

[Leo Liang]

On Tue, Oct 31, 2023 at 05:55:59PM +0900, Chanho Park wrote:
> Add gpio.h header file that includes JH7110 helper macros. The file is
> imported from StarFive github[1] with small changes such as alignment.
> 
> [1]: https://github.com/starfive-tech/u-boot
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 2/2] board: starfive: spl: Support jtag for VisionFive2 board

[Leo Liang]

On Tue, Oct 31, 2023 at 05:56:00PM +0900, Chanho Park wrote:
> JTAG pins are mapped as below. To access the JTAG pins, we need to
> control the GPIO pins from SPL which seems to be the earliest stage for
> JTAG.
> 
> - JTAG nTRST:	GPIO36 / Input
> - JTAG TDI:	GPIO61 / Input
> - JTAG TMS:	GPIO63 / Input
> - JTAG TCK:	GPIO60 / Input
> - JTAG TDO:	GPIO44 / Output
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  board/starfive/visionfive2/spl.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>