From: Biju Das <biju.das.jz@bp.renesas.com> To: Mark Brown <broonie@kernel.org> Cc: Biju Das <biju.das.jz@bp.renesas.com>, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, Geert Uytterhoeven <geert+renesas@glider.be>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Michael Walle <michael@walle.cc>, Biju Das <biju.das.au@gmail.com>, linux-renesas-soc@vger.kernel.org Subject: [PATCH RFC 1/4] spi: spi-mem: Add set_iofv() callback Date: Wed, 8 Nov 2023 17:11:46 +0000 [thread overview] Message-ID: <20231108171149.258656-2-biju.das.jz@bp.renesas.com> (raw) In-Reply-To: <20231108171149.258656-1-biju.das.jz@bp.renesas.com> As per section 8.14 on the AT25QL128A hardware manual, IO0..IO3 must be set to Hi-Z state for this flash for fast read quad IO. Snippet from HW manual section 8.14: The upper nibble of the Mode(M7-4) controls the length of the next FAST Read Quad IO instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode(M3-0) are don't care. However, the IO pins must be high-impedance before the falling edge of the first data out clock. Add set_iofv() callback for configuring IO fixed values to control the pin state. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/spi/spi-mem.c | 20 ++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 24 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index edd7430d4c05..0cfca8c438e3 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -297,6 +297,26 @@ static void spi_mem_access_end(struct spi_mem *mem) pm_runtime_put(ctlr->dev.parent); } +/** + * spi_mem_set_iofv() - Set IO fixed values to control the pin state + * @mem: the SPI memory + * @val: the IO fixed values + * + * Set IO fixed values to control the pin state. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int spi_mem_set_iofv(struct spi_mem *mem, u32 val) +{ + struct spi_controller *ctlr = mem->spi->controller; + + if (ctlr->mem_ops && ctlr->mem_ops->set_iofv) + return ctlr->mem_ops->set_iofv(mem, val); + + return 0; +} +EXPORT_SYMBOL_GPL(spi_mem_set_iofv); + /** * spi_mem_exec_op() - Execute a memory operation * @mem: the SPI memory diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 6b0a7dc48a4b..e50f89bf5ba9 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -232,6 +232,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) * limitations (can be alignment or max RX/TX size * limitations) * @supports_op: check if an operation is supported by the controller + * @set_iofv: set IO fixed values to control the pin state * @exec_op: execute a SPI memory operation * @get_name: get a custom name for the SPI mem device from the controller. * This might be needed if the controller driver has been ported @@ -274,6 +275,7 @@ struct spi_controller_mem_ops { int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op); bool (*supports_op)(struct spi_mem *mem, const struct spi_mem_op *op); + int (*set_iofv)(struct spi_mem *mem, u32 val); int (*exec_op)(struct spi_mem *mem, const struct spi_mem_op *op); const char *(*get_name)(struct spi_mem *mem); @@ -367,6 +369,8 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); +int spi_mem_set_iofv(struct spi_mem *mem, u32 val); + int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op); -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Biju Das <biju.das.jz@bp.renesas.com> To: Mark Brown <broonie@kernel.org> Cc: Biju Das <biju.das.jz@bp.renesas.com>, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, Geert Uytterhoeven <geert+renesas@glider.be>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Michael Walle <michael@walle.cc>, Biju Das <biju.das.au@gmail.com>, linux-renesas-soc@vger.kernel.org Subject: [PATCH RFC 1/4] spi: spi-mem: Add set_iofv() callback Date: Wed, 8 Nov 2023 17:11:46 +0000 [thread overview] Message-ID: <20231108171149.258656-2-biju.das.jz@bp.renesas.com> (raw) In-Reply-To: <20231108171149.258656-1-biju.das.jz@bp.renesas.com> As per section 8.14 on the AT25QL128A hardware manual, IO0..IO3 must be set to Hi-Z state for this flash for fast read quad IO. Snippet from HW manual section 8.14: The upper nibble of the Mode(M7-4) controls the length of the next FAST Read Quad IO instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode(M3-0) are don't care. However, the IO pins must be high-impedance before the falling edge of the first data out clock. Add set_iofv() callback for configuring IO fixed values to control the pin state. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/spi/spi-mem.c | 20 ++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 24 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index edd7430d4c05..0cfca8c438e3 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -297,6 +297,26 @@ static void spi_mem_access_end(struct spi_mem *mem) pm_runtime_put(ctlr->dev.parent); } +/** + * spi_mem_set_iofv() - Set IO fixed values to control the pin state + * @mem: the SPI memory + * @val: the IO fixed values + * + * Set IO fixed values to control the pin state. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int spi_mem_set_iofv(struct spi_mem *mem, u32 val) +{ + struct spi_controller *ctlr = mem->spi->controller; + + if (ctlr->mem_ops && ctlr->mem_ops->set_iofv) + return ctlr->mem_ops->set_iofv(mem, val); + + return 0; +} +EXPORT_SYMBOL_GPL(spi_mem_set_iofv); + /** * spi_mem_exec_op() - Execute a memory operation * @mem: the SPI memory diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 6b0a7dc48a4b..e50f89bf5ba9 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -232,6 +232,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) * limitations (can be alignment or max RX/TX size * limitations) * @supports_op: check if an operation is supported by the controller + * @set_iofv: set IO fixed values to control the pin state * @exec_op: execute a SPI memory operation * @get_name: get a custom name for the SPI mem device from the controller. * This might be needed if the controller driver has been ported @@ -274,6 +275,7 @@ struct spi_controller_mem_ops { int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op); bool (*supports_op)(struct spi_mem *mem, const struct spi_mem_op *op); + int (*set_iofv)(struct spi_mem *mem, u32 val); int (*exec_op)(struct spi_mem *mem, const struct spi_mem_op *op); const char *(*get_name)(struct spi_mem *mem); @@ -367,6 +369,8 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); +int spi_mem_set_iofv(struct spi_mem *mem, u32 val); + int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op); -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2023-11-08 17:12 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-11-08 17:11 [PATCH RFC 0/4] Add set_iofv() callback Biju Das 2023-11-08 17:11 ` Biju Das 2023-11-08 17:11 ` Biju Das [this message] 2023-11-08 17:11 ` [PATCH RFC 1/4] spi: spi-mem: " Biju Das 2023-11-09 7:56 ` Geert Uytterhoeven 2023-11-09 7:56 ` Geert Uytterhoeven 2023-11-09 8:28 ` Biju Das 2023-11-08 17:11 ` [PATCH RFC 2/4] mtd: spi-nor: Add post_sfdp() callback Biju Das 2023-11-08 17:11 ` Biju Das 2023-11-08 17:11 ` [PATCH RFC 3/4] memory: renesas-rpc-if: Add support for overriding IO fixed values Biju Das 2023-11-21 9:08 ` Krzysztof Kozlowski 2023-11-08 17:11 ` [PATCH RFC 4/4] spi: rpc-if: Add set_iofv() callback Biju Das 2023-11-09 9:01 ` [PATCH RFC 0/4] " Michael Walle 2023-11-09 9:01 ` Michael Walle 2023-11-09 10:04 ` Biju Das 2023-11-09 10:48 ` Michael Walle 2023-11-09 10:48 ` Michael Walle 2023-11-09 11:48 ` Biju Das 2023-11-09 12:40 ` Michael Walle 2023-11-09 12:40 ` Michael Walle 2023-11-09 18:02 ` Biju Das 2023-11-10 10:11 ` Michael Walle 2023-11-10 10:11 ` Michael Walle 2023-11-10 11:35 ` Biju Das 2023-11-11 12:26 ` Biju Das 2023-11-11 13:08 ` Biju Das 2023-11-13 14:04 ` Michael Walle 2023-11-13 14:04 ` Michael Walle 2023-11-13 14:27 ` Biju Das 2023-11-13 14:48 ` Michael Walle 2023-11-13 14:48 ` Michael Walle 2023-11-13 14:59 ` Biju Das 2023-11-13 15:10 ` Michael Walle 2023-11-13 15:10 ` Michael Walle 2023-11-13 15:55 ` Biju Das 2023-11-14 10:05 ` Michael Walle 2023-11-14 10:05 ` Michael Walle 2023-11-12 20:24 ` Biju Das 2023-11-13 14:37 ` Michael Walle 2023-11-13 14:37 ` Michael Walle 2023-11-13 14:47 ` Michael Walle 2023-11-13 14:47 ` Michael Walle
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