* [PATCH v2 0/9] Add NSS clock controller support for Qualcomm IPQ5332
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add bindings, driver and devicetree node for networking sub system clock
controller on IPQ5332. Some of the nssnoc clocks present in GCC driver is
enabled by default and its RCG is configured by bootloaders, so enable
those clocks in driver probe.
The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in v2:
- Change logs are in respective patches
- Link to v1: https://lore.kernel.org/r/20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com
---
Kathiravan Thirumoorthy (9):
clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
dt-bindings: clock: ipq5332: drop the few nss clocks definition
dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock
clk: qcom: ipq5332: add gpll0_out_aux clock
dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions
clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
arm64: dts: qcom: ipq5332: add support for the NSSCC
arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
.../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 ++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 122 +--
drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 4 +-
include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++
9 files changed, 1264 insertions(+), 80 deletions(-)
---
base-commit: 07b677953b9dca02928be323e2db853511305fa9
change-id: 20231030-ipq5332-nsscc-aeac9e153045
Best regards,
--
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 0/9] Add NSS clock controller support for Qualcomm IPQ5332
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add bindings, driver and devicetree node for networking sub system clock
controller on IPQ5332. Some of the nssnoc clocks present in GCC driver is
enabled by default and its RCG is configured by bootloaders, so enable
those clocks in driver probe.
The NSS clock controller driver depends on the below patchset which adds
support for multiple configurations for same frequency.
https://lore.kernel.org/linux-arm-msm/20230531222654.25475-1-ansuelsmth@gmail.com/
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in v2:
- Change logs are in respective patches
- Link to v1: https://lore.kernel.org/r/20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com
---
Kathiravan Thirumoorthy (9):
clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
dt-bindings: clock: ipq5332: drop the few nss clocks definition
dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock
clk: qcom: ipq5332: add gpll0_out_aux clock
dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions
clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
arm64: dts: qcom: ipq5332: add support for the NSSCC
arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
.../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 ++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 122 +--
drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 4 +-
include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++
9 files changed, 1264 insertions(+), 80 deletions(-)
---
base-commit: 07b677953b9dca02928be323e2db853511305fa9
change-id: 20231030-ipq5332-nsscc-aeac9e153045
Best regards,
--
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
There are few places where clk_init_data structure doesn't carry the const
qualifier. Let's add the same.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- New patch
---
drivers/clk/qcom/gcc-ipq5332.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index f98591148a97..66d5399798fe 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -65,7 +65,7 @@ static struct clk_alpha_pll gpll0_main = {
static struct clk_fixed_factor gpll0_div2 = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gpll0_div2",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
@@ -78,7 +78,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
@@ -106,7 +106,7 @@ static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2_main",
.parent_hws = (const struct clk_hw *[]) {
&gpll2_main.clkr.hw },
@@ -145,7 +145,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]) {
&gpll4_main.clkr.hw },
@@ -572,7 +572,7 @@ static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
.clkr = {
.enable_reg = 0x2907c,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
@@ -615,7 +615,7 @@ static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
.clkr = {
.enable_reg = 0x2a078,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
@@ -678,7 +678,7 @@ static struct clk_branch gcc_pcie3x2_rchg_clk = {
.clkr = {
.enable_reg = 0x28078,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x2_rchg_clk_src.clkr.hw },
@@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
.reg = 0x28064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK,
@@ -725,7 +725,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
@@ -739,7 +739,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
@@ -826,7 +826,7 @@ static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -839,7 +839,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
.mult = 1,
.div = 3,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div3_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -851,7 +851,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
.mult = 1,
.div = 4,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -863,7 +863,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
.mult = 1,
.div = 8,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div8_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -875,7 +875,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
.mult = 1,
.div = 16,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div16_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw },
@@ -1069,7 +1069,7 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
.reg = 0x2c074,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
@@ -1111,7 +1111,7 @@ static struct clk_rcg2 gcc_xo_clk_src = {
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw },
@@ -2431,7 +2431,7 @@ static struct clk_branch gcc_qdss_etr_usb_clk = {
static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
.mult = 1,
.div = 6,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_eud_at_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_at_clk_src.clkr.hw },
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
There are few places where clk_init_data structure doesn't carry the const
qualifier. Let's add the same.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- New patch
---
drivers/clk/qcom/gcc-ipq5332.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index f98591148a97..66d5399798fe 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -65,7 +65,7 @@ static struct clk_alpha_pll gpll0_main = {
static struct clk_fixed_factor gpll0_div2 = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gpll0_div2",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
@@ -78,7 +78,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
.parent_hws = (const struct clk_hw *[]) {
&gpll0_main.clkr.hw },
@@ -106,7 +106,7 @@ static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2_main",
.parent_hws = (const struct clk_hw *[]) {
&gpll2_main.clkr.hw },
@@ -145,7 +145,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.width = 4,
- .clkr.hw.init = &(struct clk_init_data) {
+ .clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
.parent_hws = (const struct clk_hw *[]) {
&gpll4_main.clkr.hw },
@@ -572,7 +572,7 @@ static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
.clkr = {
.enable_reg = 0x2907c,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
@@ -615,7 +615,7 @@ static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
.clkr = {
.enable_reg = 0x2a078,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
@@ -678,7 +678,7 @@ static struct clk_branch gcc_pcie3x2_rchg_clk = {
.clkr = {
.enable_reg = 0x28078,
.enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_rchg_clk",
.parent_hws = (const struct clk_hw *[]) {
&gcc_pcie3x2_rchg_clk_src.clkr.hw },
@@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
.reg = 0x28064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x2_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK,
@@ -725,7 +725,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
@@ -739,7 +739,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie3x1_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
@@ -826,7 +826,7 @@ static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -839,7 +839,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
.mult = 1,
.div = 3,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div3_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -851,7 +851,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
.mult = 1,
.div = 4,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -863,7 +863,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
.mult = 1,
.div = 8,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div8_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -875,7 +875,7 @@ static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
.mult = 1,
.div = 16,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_qdss_tsctr_div16_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_tsctr_clk_src.clkr.hw },
@@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
.mult = 1,
.div = 2,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_system_noc_bfdcd_div2_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_system_noc_bfdcd_clk_src.clkr.hw },
@@ -1069,7 +1069,7 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
.reg = 0x2c074,
.clkr = {
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_usb0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data) {
.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
@@ -1111,7 +1111,7 @@ static struct clk_rcg2 gcc_xo_clk_src = {
static struct clk_fixed_factor gcc_xo_div4_clk_src = {
.mult = 1,
.div = 4,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_xo_div4_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_xo_clk_src.clkr.hw },
@@ -2431,7 +2431,7 @@ static struct clk_branch gcc_qdss_etr_usb_clk = {
static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
.mult = 1,
.div = 6,
- .hw.init = &(struct clk_init_data) {
+ .hw.init = &(const struct clk_init_data) {
.name = "gcc_eud_at_div_clk_src",
.parent_hws = (const struct clk_hw *[]) {
&gcc_qdss_at_clk_src.clkr.hw },
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
enabled by default and it's RCG is properly configured by bootloader.
Some of the NSS clocks needs these clocks to be enabled. To avoid
these clocks being disabled by clock framework, drop these entries
from the clock table and enable it in the driver probe itself.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- enabled the clocks in driver probe
---
drivers/clk/qcom/gcc-ipq5332.c | 70 ++++++++----------------------------------
1 file changed, 12 insertions(+), 58 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 66d5399798fe..38a570b68813 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -1672,24 +1672,6 @@ static struct clk_branch gcc_nssnoc_atb_clk = {
},
};
-static struct clk_branch gcc_nssnoc_nsscc_clk = {
- .halt_reg = 0x17030,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17030,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_nssnoc_nsscc_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
@@ -2585,42 +2567,6 @@ static struct clk_branch gcc_snoc_lpass_cfg_clk = {
},
};
-static struct clk_branch gcc_snoc_nssnoc_1_clk = {
- .halt_reg = 0x17090,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17090,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_snoc_nssnoc_1_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_system_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch gcc_snoc_nssnoc_clk = {
- .halt_reg = 0x17084,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17084,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_snoc_nssnoc_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_system_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
.halt_reg = 0x2e050,
.halt_check = BRANCH_HALT,
@@ -3330,7 +3276,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
- [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
@@ -3398,8 +3343,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
- [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
- [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
@@ -3660,7 +3603,18 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
static int gcc_ipq5332_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* Keep the critical clocks always-On */
+ regmap_update_bits(regmap, 0x17030, BIT(0), BIT(0)); /* gcc_nssnoc_nsscc_clk */
+ regmap_update_bits(regmap, 0x17084, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_clk */
+ regmap_update_bits(regmap, 0x17090, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_1_clk */
+
+ return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);
}
static const struct of_device_id gcc_ipq5332_match_table[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
enabled by default and it's RCG is properly configured by bootloader.
Some of the NSS clocks needs these clocks to be enabled. To avoid
these clocks being disabled by clock framework, drop these entries
from the clock table and enable it in the driver probe itself.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- enabled the clocks in driver probe
---
drivers/clk/qcom/gcc-ipq5332.c | 70 ++++++++----------------------------------
1 file changed, 12 insertions(+), 58 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 66d5399798fe..38a570b68813 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -1672,24 +1672,6 @@ static struct clk_branch gcc_nssnoc_atb_clk = {
},
};
-static struct clk_branch gcc_nssnoc_nsscc_clk = {
- .halt_reg = 0x17030,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17030,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_nssnoc_nsscc_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
.halt_reg = 0x1701c,
.halt_check = BRANCH_HALT,
@@ -2585,42 +2567,6 @@ static struct clk_branch gcc_snoc_lpass_cfg_clk = {
},
};
-static struct clk_branch gcc_snoc_nssnoc_1_clk = {
- .halt_reg = 0x17090,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17090,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_snoc_nssnoc_1_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_system_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
-static struct clk_branch gcc_snoc_nssnoc_clk = {
- .halt_reg = 0x17084,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x17084,
- .enable_mask = BIT(0),
- .hw.init = &(const struct clk_init_data) {
- .name = "gcc_snoc_nssnoc_clk",
- .parent_hws = (const struct clk_hw*[]) {
- &gcc_system_noc_bfdcd_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
.halt_reg = 0x2e050,
.halt_check = BRANCH_HALT,
@@ -3330,7 +3276,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
- [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
@@ -3398,8 +3343,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
- [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
- [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
[GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
@@ -3660,7 +3603,18 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
static int gcc_ipq5332_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* Keep the critical clocks always-On */
+ regmap_update_bits(regmap, 0x17030, BIT(0), BIT(0)); /* gcc_nssnoc_nsscc_clk */
+ regmap_update_bits(regmap, 0x17084, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_clk */
+ regmap_update_bits(regmap, 0x17090, BIT(0), BIT(0)); /* gcc_snoc_nssnoc_1_clk */
+
+ return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);
}
static const struct of_device_id gcc_ipq5332_match_table[] = {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
So let's drop the binding definition as well.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- No changes
---
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..4649026da332 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -55,7 +55,6 @@
#define GCC_NSSCC_CLK 46
#define GCC_NSSCFG_CLK 47
#define GCC_NSSNOC_ATB_CLK 48
-#define GCC_NSSNOC_NSSCC_CLK 49
#define GCC_NSSNOC_QOSGEN_REF_CLK 50
#define GCC_NSSNOC_SNOC_1_CLK 51
#define GCC_NSSNOC_SNOC_CLK 52
@@ -124,8 +123,6 @@
#define GCC_SDCC1_APPS_CLK_SRC 115
#define GCC_SLEEP_CLK_SRC 116
#define GCC_SNOC_LPASS_CFG_CLK 117
-#define GCC_SNOC_NSSNOC_1_CLK 118
-#define GCC_SNOC_NSSNOC_CLK 119
#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
So let's drop the binding definition as well.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- No changes
---
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..4649026da332 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -55,7 +55,6 @@
#define GCC_NSSCC_CLK 46
#define GCC_NSSCFG_CLK 47
#define GCC_NSSNOC_ATB_CLK 48
-#define GCC_NSSNOC_NSSCC_CLK 49
#define GCC_NSSNOC_QOSGEN_REF_CLK 50
#define GCC_NSSNOC_SNOC_1_CLK 51
#define GCC_NSSNOC_SNOC_CLK 52
@@ -124,8 +123,6 @@
#define GCC_SDCC1_APPS_CLK_SRC 115
#define GCC_SLEEP_CLK_SRC 116
#define GCC_SNOC_LPASS_CFG_CLK 117
-#define GCC_SNOC_NSSNOC_1_CLK 118
-#define GCC_SNOC_NSSNOC_CLK 119
#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 4/9] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add the definition for GPLL0_OUT_AUX clock.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Pick up the A-b tag
---
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 4649026da332..486b6cf2e916 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -176,6 +176,7 @@
#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
#define GCC_USB0_PIPE_CLK_SRC 172
+#define GPLL0_OUT_AUX 173
#define GCC_ADSS_BCR 0
#define GCC_ADSS_PWM_CLK_ARES 1
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 4/9] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add the definition for GPLL0_OUT_AUX clock.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Pick up the A-b tag
---
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 4649026da332..486b6cf2e916 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -176,6 +176,7 @@
#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
#define GCC_USB0_PIPE_CLK_SRC 172
+#define GPLL0_OUT_AUX 173
#define GCC_ADSS_BCR 0
#define GCC_ADSS_PWM_CLK_ARES 1
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (NSS) clocks.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- add the const qualifier to the struct initdata
---
drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 38a570b68813..9a5f0c98f734 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = {
},
};
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_out_aux",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
@@ -3393,6 +3406,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
+ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
};
static const struct qcom_reset_map gcc_ipq5332_resets[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Add support for gpll0_out_aux clock which acts as the parent for
certain networking subsystem (NSS) clocks.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- add the const qualifier to the struct initdata
---
drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 38a570b68813..9a5f0c98f734 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = {
},
};
+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll0_out_aux",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
@@ -3393,6 +3406,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
+ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
};
static const struct qcom_reset_map gcc_ipq5332_resets[] = {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 6/9] dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add NSSCC clock and reset definitions for Qualcomm IPQ5332.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Pick up R-b tag
---
.../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 +++++++++++++++
include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++++++++++++++++++++++
2 files changed, 146 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml
new file mode 100644
index 000000000000..59f8d1e99229
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ Qualcomm networking sub system clock control module provides the clocks,
+ resets and power domains on IPQ5332
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq5332-nsscc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-nsscc
+
+ clocks:
+ items:
+ - description: Common PLL nss clock 200M source
+ - description: Common PLL nss clock 300M source
+ - description: GCC GPLL0 out aux clock source
+ - description: Uniphy0 NSS Rx clock source
+ - description: Uniphy0 NSS Tx clock source
+ - description: Uniphy1 NSS Rx clock source
+ - description: Uniphy1 NSS Tx clock source
+ - description: Board XO source
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@39b00000 {
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&gcc_gpll0_out_aux>,
+ <&uniphy 0>,
+ <&uniphy 1>,
+ <&uniphy 2>,
+ <&uniphy 3>,
+ <&xo_board_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq5332-nsscc.h b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h
new file mode 100644
index 000000000000..c077cde7f57d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+
+/* NSS_CC clocks */
+#define NSS_CC_CE_APB_CLK 0
+#define NSS_CC_CE_AXI_CLK 1
+#define NSS_CC_CE_CLK_SRC 2
+#define NSS_CC_CFG_CLK_SRC 3
+#define NSS_CC_DEBUG_CLK 4
+#define NSS_CC_EIP_BFDCD_CLK_SRC 5
+#define NSS_CC_EIP_CLK 6
+#define NSS_CC_NSS_CSR_CLK 7
+#define NSS_CC_NSSNOC_CE_APB_CLK 8
+#define NSS_CC_NSSNOC_CE_AXI_CLK 9
+#define NSS_CC_NSSNOC_EIP_CLK 10
+#define NSS_CC_NSSNOC_NSS_CSR_CLK 11
+#define NSS_CC_NSSNOC_PPE_CFG_CLK 12
+#define NSS_CC_NSSNOC_PPE_CLK 13
+#define NSS_CC_PORT1_MAC_CLK 14
+#define NSS_CC_PORT1_RX_CLK 15
+#define NSS_CC_PORT1_RX_CLK_SRC 16
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17
+#define NSS_CC_PORT1_TX_CLK 18
+#define NSS_CC_PORT1_TX_CLK_SRC 19
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20
+#define NSS_CC_PORT2_MAC_CLK 21
+#define NSS_CC_PORT2_RX_CLK 22
+#define NSS_CC_PORT2_RX_CLK_SRC 23
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24
+#define NSS_CC_PORT2_TX_CLK 25
+#define NSS_CC_PORT2_TX_CLK_SRC 26
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27
+#define NSS_CC_PPE_CLK_SRC 28
+#define NSS_CC_PPE_EDMA_CFG_CLK 29
+#define NSS_CC_PPE_EDMA_CLK 30
+#define NSS_CC_PPE_SWITCH_BTQ_CLK 31
+#define NSS_CC_PPE_SWITCH_CFG_CLK 32
+#define NSS_CC_PPE_SWITCH_CLK 33
+#define NSS_CC_PPE_SWITCH_IPE_CLK 34
+#define NSS_CC_UNIPHY_PORT1_RX_CLK 35
+#define NSS_CC_UNIPHY_PORT1_TX_CLK 36
+#define NSS_CC_UNIPHY_PORT2_RX_CLK 37
+#define NSS_CC_UNIPHY_PORT2_TX_CLK 38
+#define NSS_CC_XGMAC0_PTP_REF_CLK 39
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40
+#define NSS_CC_XGMAC1_PTP_REF_CLK 41
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42
+
+#define NSS_CC_CE_APB_CLK_ARES 0
+#define NSS_CC_CE_AXI_CLK_ARES 1
+#define NSS_CC_DEBUG_CLK_ARES 2
+#define NSS_CC_EIP_CLK_ARES 3
+#define NSS_CC_NSS_CSR_CLK_ARES 4
+#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5
+#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6
+#define NSS_CC_NSSNOC_EIP_CLK_ARES 7
+#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8
+#define NSS_CC_NSSNOC_PPE_CLK_ARES 9
+#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10
+#define NSS_CC_PORT1_MAC_CLK_ARES 11
+#define NSS_CC_PORT1_RX_CLK_ARES 12
+#define NSS_CC_PORT1_TX_CLK_ARES 13
+#define NSS_CC_PORT2_MAC_CLK_ARES 14
+#define NSS_CC_PORT2_RX_CLK_ARES 15
+#define NSS_CC_PORT2_TX_CLK_ARES 16
+#define NSS_CC_PPE_BCR 17
+#define NSS_CC_PPE_EDMA_CLK_ARES 18
+#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19
+#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20
+#define NSS_CC_PPE_SWITCH_CLK_ARES 21
+#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22
+#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23
+#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24
+#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25
+#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26
+#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27
+#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28
+#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 6/9] dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy, Krzysztof Kozlowski
Add NSSCC clock and reset definitions for Qualcomm IPQ5332.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Pick up R-b tag
---
.../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 +++++++++++++++
include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++++++++++++++++++++++
2 files changed, 146 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml
new file mode 100644
index 000000000000..59f8d1e99229
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ Qualcomm networking sub system clock control module provides the clocks,
+ resets and power domains on IPQ5332
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq5332-nsscc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-nsscc
+
+ clocks:
+ items:
+ - description: Common PLL nss clock 200M source
+ - description: Common PLL nss clock 300M source
+ - description: GCC GPLL0 out aux clock source
+ - description: Uniphy0 NSS Rx clock source
+ - description: Uniphy0 NSS Tx clock source
+ - description: Uniphy1 NSS Rx clock source
+ - description: Uniphy1 NSS Tx clock source
+ - description: Board XO source
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@39b00000 {
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&bias_pll_cc_clk>,
+ <&bias_pll_nss_noc_clk>,
+ <&gcc_gpll0_out_aux>,
+ <&uniphy 0>,
+ <&uniphy 1>,
+ <&uniphy 2>,
+ <&uniphy 3>,
+ <&xo_board_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq5332-nsscc.h b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h
new file mode 100644
index 000000000000..c077cde7f57d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H
+
+/* NSS_CC clocks */
+#define NSS_CC_CE_APB_CLK 0
+#define NSS_CC_CE_AXI_CLK 1
+#define NSS_CC_CE_CLK_SRC 2
+#define NSS_CC_CFG_CLK_SRC 3
+#define NSS_CC_DEBUG_CLK 4
+#define NSS_CC_EIP_BFDCD_CLK_SRC 5
+#define NSS_CC_EIP_CLK 6
+#define NSS_CC_NSS_CSR_CLK 7
+#define NSS_CC_NSSNOC_CE_APB_CLK 8
+#define NSS_CC_NSSNOC_CE_AXI_CLK 9
+#define NSS_CC_NSSNOC_EIP_CLK 10
+#define NSS_CC_NSSNOC_NSS_CSR_CLK 11
+#define NSS_CC_NSSNOC_PPE_CFG_CLK 12
+#define NSS_CC_NSSNOC_PPE_CLK 13
+#define NSS_CC_PORT1_MAC_CLK 14
+#define NSS_CC_PORT1_RX_CLK 15
+#define NSS_CC_PORT1_RX_CLK_SRC 16
+#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17
+#define NSS_CC_PORT1_TX_CLK 18
+#define NSS_CC_PORT1_TX_CLK_SRC 19
+#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20
+#define NSS_CC_PORT2_MAC_CLK 21
+#define NSS_CC_PORT2_RX_CLK 22
+#define NSS_CC_PORT2_RX_CLK_SRC 23
+#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24
+#define NSS_CC_PORT2_TX_CLK 25
+#define NSS_CC_PORT2_TX_CLK_SRC 26
+#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27
+#define NSS_CC_PPE_CLK_SRC 28
+#define NSS_CC_PPE_EDMA_CFG_CLK 29
+#define NSS_CC_PPE_EDMA_CLK 30
+#define NSS_CC_PPE_SWITCH_BTQ_CLK 31
+#define NSS_CC_PPE_SWITCH_CFG_CLK 32
+#define NSS_CC_PPE_SWITCH_CLK 33
+#define NSS_CC_PPE_SWITCH_IPE_CLK 34
+#define NSS_CC_UNIPHY_PORT1_RX_CLK 35
+#define NSS_CC_UNIPHY_PORT1_TX_CLK 36
+#define NSS_CC_UNIPHY_PORT2_RX_CLK 37
+#define NSS_CC_UNIPHY_PORT2_TX_CLK 38
+#define NSS_CC_XGMAC0_PTP_REF_CLK 39
+#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40
+#define NSS_CC_XGMAC1_PTP_REF_CLK 41
+#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42
+
+#define NSS_CC_CE_APB_CLK_ARES 0
+#define NSS_CC_CE_AXI_CLK_ARES 1
+#define NSS_CC_DEBUG_CLK_ARES 2
+#define NSS_CC_EIP_CLK_ARES 3
+#define NSS_CC_NSS_CSR_CLK_ARES 4
+#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5
+#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6
+#define NSS_CC_NSSNOC_EIP_CLK_ARES 7
+#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8
+#define NSS_CC_NSSNOC_PPE_CLK_ARES 9
+#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10
+#define NSS_CC_PORT1_MAC_CLK_ARES 11
+#define NSS_CC_PORT1_RX_CLK_ARES 12
+#define NSS_CC_PORT1_TX_CLK_ARES 13
+#define NSS_CC_PORT2_MAC_CLK_ARES 14
+#define NSS_CC_PORT2_RX_CLK_ARES 15
+#define NSS_CC_PORT2_TX_CLK_ARES 16
+#define NSS_CC_PPE_BCR 17
+#define NSS_CC_PPE_EDMA_CLK_ARES 18
+#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19
+#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20
+#define NSS_CC_PPE_SWITCH_CLK_ARES 21
+#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22
+#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23
+#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24
+#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25
+#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26
+#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27
+#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28
+#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29
+
+#endif
--
2.34.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
IPQ5332 based devices.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- For the port rx and tx clock source, use clk_rcg2_fm_ops
instead of clk_rcg2_ops
- added space between ){ wherever applicable
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++++++++++++++++++++
3 files changed, 1043 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ad1acd9b7426..2e3efcdef9fa 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -162,6 +162,13 @@ config IPQ_GCC_5332
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_NSSCC_5332
+ tristate "IPQ5332 NSS Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ depends on IPQ_GCC_5332
+ help
+ Support for NSS clock controller on ipq5332 devices.
+
config IPQ_GCC_6018
tristate "IPQ6018 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 17edd73f9839..3aab744ecc99 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
+obj-$(CONFIG_IPQ_NSSCC_5332) += nsscc-ipq5332.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/nsscc-ipq5332.c b/drivers/clk/qcom/nsscc-ipq5332.c
new file mode 100644
index 000000000000..b521e807931f
--- /dev/null
+++ b/drivers/clk/qcom/nsscc-ipq5332.c
@@ -0,0 +1,1035 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,ipq5332-nsscc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_CMN_PLL_NSS_CLK_200M,
+ DT_CMN_PLL_NSS_CLK_300M,
+ DT_GCC_GPLL0_OUT_AUX,
+ DT_UNIPHY0_NSS_TX_CLK,
+ DT_UNIPHY0_NSS_RX_CLK,
+ DT_UNIPHY1_NSS_TX_CLK,
+ DT_UNIPHY1_NSS_RX_CLK,
+ DT_XO,
+};
+
+enum {
+ P_CMN_PLL_NSS_CLK_200M,
+ P_CMN_PLL_NSS_CLK_300M,
+ P_GCC_GPLL0_OUT_AUX,
+ P_UNIPHY0_NSS_TX_CLK,
+ P_UNIPHY0_NSS_RX_CLK,
+ P_UNIPHY1_NSS_TX_CLK,
+ P_UNIPHY1_NSS_RX_CLK,
+ P_XO,
+};
+
+static const struct parent_map nss_cc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct parent_map nss_cc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_UNIPHY0_NSS_RX_CLK, 3 },
+ { P_UNIPHY0_NSS_TX_CLK, 4 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct parent_map nss_cc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_UNIPHY1_NSS_RX_CLK, 3 },
+ { P_UNIPHY1_NSS_TX_CLK, 4 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_UNIPHY1_NSS_RX_CLK },
+ { .index = DT_UNIPHY1_NSS_TX_CLK },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(200000000, P_CMN_PLL_NSS_CLK_200M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ce_clk_src = {
+ .cmd_rcgr = 0x518,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
+ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_cfg_clk_src = {
+ .cmd_rcgr = 0x5e0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = {
+ F(300000000, P_CMN_PLL_NSS_CLK_300M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = {
+ .cmd_rcgr = 0x57c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_eip_bfdcd_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
+ .cmd_rcgr = 0x450,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
+ .cmd_rcgr = 0x45c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
+ .cmd_rcgr = 0x468,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
+ .cmd_rcgr = 0x474,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ppe_clk_src = {
+ .cmd_rcgr = 0x3e8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
+ .reg = 0x458,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
+ .reg = 0x464,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
+ .reg = 0x470,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
+ .reg = 0x47c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
+ .reg = 0x3f0,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
+ .reg = 0x3f4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch nss_cc_ce_apb_clk = {
+ .halt_reg = 0x520,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x520,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ce_axi_clk = {
+ .halt_reg = 0x524,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x524,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_debug_clk = {
+ .halt_reg = 0x644,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x644,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_debug_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_eip_clk = {
+ .halt_reg = 0x590,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x590,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_eip_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_eip_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nss_csr_clk = {
+ .halt_reg = 0x5e8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5e8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nss_csr_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x52c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x52c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x530,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x530,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_eip_clk = {
+ .halt_reg = 0x598,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x598,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_eip_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_eip_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
+ .halt_reg = 0x5ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_nss_csr_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x424,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x424,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_clk = {
+ .halt_reg = 0x420,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x420,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_mac_clk = {
+ .halt_reg = 0x428,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x428,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_mac_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_rx_clk = {
+ .halt_reg = 0x480,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x480,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_tx_clk = {
+ .halt_reg = 0x488,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x488,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_mac_clk = {
+ .halt_reg = 0x430,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x430,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_mac_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_rx_clk = {
+ .halt_reg = 0x490,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x490,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_tx_clk = {
+ .halt_reg = 0x498,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x498,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
+ .halt_reg = 0x41c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x41c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_clk = {
+ .halt_reg = 0x414,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x414,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_btq_clk = {
+ .halt_reg = 0x400,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x400,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_btq_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
+ .halt_reg = 0x410,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x410,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_clk = {
+ .halt_reg = 0x408,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x408,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
+ .halt_reg = 0x3f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_ipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
+ .halt_reg = 0x4b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
+ .halt_reg = 0x4b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
+ .halt_reg = 0x4bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
+ .halt_reg = 0x4c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
+ .halt_reg = 0x438,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x438,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
+ .halt_reg = 0x43c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x43c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nss_cc_ipq5332_clocks[] = {
+ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
+ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
+ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
+ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
+ [NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr,
+ [NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr,
+ [NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr,
+ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
+ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
+ [NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr,
+ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
+ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
+ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
+ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
+ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
+ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
+ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
+ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
+ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
+ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
+ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
+ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
+ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
+ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
+ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
+ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
+};
+
+static const struct qcom_reset_map nss_cc_ipq5332_resets[] = {
+ [NSS_CC_CE_APB_CLK_ARES] = { 0x520, 2 },
+ [NSS_CC_CE_AXI_CLK_ARES] = { 0x524, 2 },
+ [NSS_CC_DEBUG_CLK_ARES] = { 0x644, 2 },
+ [NSS_CC_EIP_CLK_ARES] = { 0x590, 2 },
+ [NSS_CC_NSS_CSR_CLK_ARES] = { 0x5e8, 2 },
+ [NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x52c, 2 },
+ [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x530, 2 },
+ [NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x598, 2 },
+ [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x5ec, 2 },
+ [NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x420, 2 },
+ [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x424, 2 },
+ [NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 },
+ [NSS_CC_PORT1_RX_CLK_ARES] = { 0x480, 2 },
+ [NSS_CC_PORT1_TX_CLK_ARES] = { 0x488, 2 },
+ [NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 },
+ [NSS_CC_PORT2_RX_CLK_ARES] = { 0x490, 2 },
+ [NSS_CC_PORT2_TX_CLK_ARES] = { 0x498, 2 },
+ [NSS_CC_PPE_BCR] = { 0x3e4 },
+ [NSS_CC_PPE_EDMA_CLK_ARES] = { 0x414, 2 },
+ [NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x41c, 2 },
+ [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x400, 2 },
+ [NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x408, 2 },
+ [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x410, 2 },
+ [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x3f8, 2 },
+ [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x4b4, 2 },
+ [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x4b8, 2 },
+ [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x4bc, 2 },
+ [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x4c0, 2 },
+ [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x438, 2 },
+ [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x43c, 2 },
+};
+
+static const struct regmap_config nss_cc_ipq5332_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x800,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc nss_cc_ipq5332_desc = {
+ .config = &nss_cc_ipq5332_regmap_config,
+ .clks = nss_cc_ipq5332_clocks,
+ .num_clks = ARRAY_SIZE(nss_cc_ipq5332_clocks),
+ .resets = nss_cc_ipq5332_resets,
+ .num_resets = ARRAY_SIZE(nss_cc_ipq5332_resets),
+};
+
+static const struct of_device_id nss_cc_ipq5332_match_table[] = {
+ { .compatible = "qcom,ipq5332-nsscc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nss_cc_ipq5332_match_table);
+
+static int nss_cc_ipq5332_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &nss_cc_ipq5332_desc);
+}
+
+static struct platform_driver nss_cc_ipq5332_driver = {
+ .probe = nss_cc_ipq5332_probe,
+ .driver = {
+ .name = "qcom,ipq5332-nsscc",
+ .of_match_table = nss_cc_ipq5332_match_table,
+ },
+};
+module_platform_driver(nss_cc_ipq5332_driver);
+
+MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
IPQ5332 based devices.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- For the port rx and tx clock source, use clk_rcg2_fm_ops
instead of clk_rcg2_ops
- added space between ){ wherever applicable
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++++++++++++++++++++
3 files changed, 1043 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ad1acd9b7426..2e3efcdef9fa 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -162,6 +162,13 @@ config IPQ_GCC_5332
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_NSSCC_5332
+ tristate "IPQ5332 NSS Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ depends on IPQ_GCC_5332
+ help
+ Support for NSS clock controller on ipq5332 devices.
+
config IPQ_GCC_6018
tristate "IPQ6018 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 17edd73f9839..3aab744ecc99 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
+obj-$(CONFIG_IPQ_NSSCC_5332) += nsscc-ipq5332.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/nsscc-ipq5332.c b/drivers/clk/qcom/nsscc-ipq5332.c
new file mode 100644
index 000000000000..b521e807931f
--- /dev/null
+++ b/drivers/clk/qcom/nsscc-ipq5332.c
@@ -0,0 +1,1035 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,ipq5332-nsscc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_CMN_PLL_NSS_CLK_200M,
+ DT_CMN_PLL_NSS_CLK_300M,
+ DT_GCC_GPLL0_OUT_AUX,
+ DT_UNIPHY0_NSS_TX_CLK,
+ DT_UNIPHY0_NSS_RX_CLK,
+ DT_UNIPHY1_NSS_TX_CLK,
+ DT_UNIPHY1_NSS_RX_CLK,
+ DT_XO,
+};
+
+enum {
+ P_CMN_PLL_NSS_CLK_200M,
+ P_CMN_PLL_NSS_CLK_300M,
+ P_GCC_GPLL0_OUT_AUX,
+ P_UNIPHY0_NSS_TX_CLK,
+ P_UNIPHY0_NSS_RX_CLK,
+ P_UNIPHY1_NSS_TX_CLK,
+ P_UNIPHY1_NSS_RX_CLK,
+ P_XO,
+};
+
+static const struct parent_map nss_cc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct parent_map nss_cc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_UNIPHY0_NSS_RX_CLK, 3 },
+ { P_UNIPHY0_NSS_TX_CLK, 4 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_UNIPHY0_NSS_RX_CLK },
+ { .index = DT_UNIPHY0_NSS_TX_CLK },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct parent_map nss_cc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_GCC_GPLL0_OUT_AUX, 2 },
+ { P_UNIPHY1_NSS_RX_CLK, 3 },
+ { P_UNIPHY1_NSS_TX_CLK, 4 },
+ { P_CMN_PLL_NSS_CLK_300M, 5 },
+ { P_CMN_PLL_NSS_CLK_200M, 6 },
+};
+
+static const struct clk_parent_data nss_cc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .index = DT_GCC_GPLL0_OUT_AUX },
+ { .index = DT_UNIPHY1_NSS_RX_CLK },
+ { .index = DT_UNIPHY1_NSS_TX_CLK },
+ { .index = DT_CMN_PLL_NSS_CLK_300M },
+ { .index = DT_CMN_PLL_NSS_CLK_200M },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(200000000, P_CMN_PLL_NSS_CLK_200M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ce_clk_src = {
+ .cmd_rcgr = 0x518,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
+ F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_cfg_clk_src = {
+ .cmd_rcgr = 0x5e0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_cfg_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_cfg_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = {
+ F(300000000, P_CMN_PLL_NSS_CLK_300M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = {
+ .cmd_rcgr = 0x57c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_eip_bfdcd_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
+ .cmd_rcgr = 0x450,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
+ C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
+ .cmd_rcgr = 0x45c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_1,
+ .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk_src",
+ .parent_data = nss_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
+ .cmd_rcgr = 0x468,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
+ C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+};
+
+static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
+ FMS(24000000, P_XO, 1, 0, 0),
+ FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25),
+ FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
+ FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125),
+ FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
+ FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
+ .cmd_rcgr = 0x474,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_2,
+ .freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk_src",
+ .parent_data = nss_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
+ .ops = &clk_rcg2_fm_ops,
+ },
+};
+
+static struct clk_rcg2 nss_cc_ppe_clk_src = {
+ .cmd_rcgr = 0x3e8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = nss_cc_parent_map_0,
+ .freq_tbl = ftbl_nss_cc_ce_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_clk_src",
+ .parent_data = nss_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
+ .reg = 0x458,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
+ .reg = 0x464,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
+ .reg = 0x470,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
+ .reg = 0x47c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
+ .reg = 0x3f0,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
+ .reg = 0x3f4,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch nss_cc_ce_apb_clk = {
+ .halt_reg = 0x520,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x520,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ce_axi_clk = {
+ .halt_reg = 0x524,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x524,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ce_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_debug_clk = {
+ .halt_reg = 0x644,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x644,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_debug_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_eip_clk = {
+ .halt_reg = 0x590,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x590,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_eip_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_eip_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nss_csr_clk = {
+ .halt_reg = 0x5e8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5e8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nss_csr_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x52c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x52c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_apb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x530,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x530,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ce_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ce_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_eip_clk = {
+ .halt_reg = 0x598,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x598,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_eip_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_eip_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
+ .halt_reg = 0x5ec,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5ec,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_nss_csr_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_cfg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x424,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x424,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_nssnoc_ppe_clk = {
+ .halt_reg = 0x420,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x420,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_nssnoc_ppe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_mac_clk = {
+ .halt_reg = 0x428,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x428,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_mac_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_rx_clk = {
+ .halt_reg = 0x480,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x480,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port1_tx_clk = {
+ .halt_reg = 0x488,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x488,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port1_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_mac_clk = {
+ .halt_reg = 0x430,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x430,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_mac_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_rx_clk = {
+ .halt_reg = 0x490,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x490,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_port2_tx_clk = {
+ .halt_reg = 0x498,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x498,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_port2_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
+ .halt_reg = 0x41c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x41c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_edma_clk = {
+ .halt_reg = 0x414,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x414,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_edma_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_btq_clk = {
+ .halt_reg = 0x400,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x400,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_btq_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
+ .halt_reg = 0x410,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x410,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_clk = {
+ .halt_reg = 0x408,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x408,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
+ .halt_reg = 0x3f8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3f8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ppe_switch_ipe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_ppe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
+ .halt_reg = 0x4b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
+ .halt_reg = 0x4b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port1_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
+ .halt_reg = 0x4bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_rx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
+ .halt_reg = 0x4c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_uniphy_port2_tx_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_port2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
+ .halt_reg = 0x438,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x438,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac0_ptp_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
+ .halt_reg = 0x43c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x43c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_xgmac1_ptp_ref_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nss_cc_ipq5332_clocks[] = {
+ [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
+ [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
+ [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
+ [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
+ [NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr,
+ [NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr,
+ [NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr,
+ [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
+ [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
+ [NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr,
+ [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
+ [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
+ [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
+ [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
+ [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
+ [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
+ [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
+ [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
+ [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
+ [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
+ [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
+ [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
+ [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
+ [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
+ [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
+ [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
+ [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
+ [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
+ [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
+ [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
+ [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
+ [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
+};
+
+static const struct qcom_reset_map nss_cc_ipq5332_resets[] = {
+ [NSS_CC_CE_APB_CLK_ARES] = { 0x520, 2 },
+ [NSS_CC_CE_AXI_CLK_ARES] = { 0x524, 2 },
+ [NSS_CC_DEBUG_CLK_ARES] = { 0x644, 2 },
+ [NSS_CC_EIP_CLK_ARES] = { 0x590, 2 },
+ [NSS_CC_NSS_CSR_CLK_ARES] = { 0x5e8, 2 },
+ [NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x52c, 2 },
+ [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x530, 2 },
+ [NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x598, 2 },
+ [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x5ec, 2 },
+ [NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x420, 2 },
+ [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x424, 2 },
+ [NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 },
+ [NSS_CC_PORT1_RX_CLK_ARES] = { 0x480, 2 },
+ [NSS_CC_PORT1_TX_CLK_ARES] = { 0x488, 2 },
+ [NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 },
+ [NSS_CC_PORT2_RX_CLK_ARES] = { 0x490, 2 },
+ [NSS_CC_PORT2_TX_CLK_ARES] = { 0x498, 2 },
+ [NSS_CC_PPE_BCR] = { 0x3e4 },
+ [NSS_CC_PPE_EDMA_CLK_ARES] = { 0x414, 2 },
+ [NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x41c, 2 },
+ [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x400, 2 },
+ [NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x408, 2 },
+ [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x410, 2 },
+ [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x3f8, 2 },
+ [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x4b4, 2 },
+ [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x4b8, 2 },
+ [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x4bc, 2 },
+ [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x4c0, 2 },
+ [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x438, 2 },
+ [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x43c, 2 },
+};
+
+static const struct regmap_config nss_cc_ipq5332_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x800,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc nss_cc_ipq5332_desc = {
+ .config = &nss_cc_ipq5332_regmap_config,
+ .clks = nss_cc_ipq5332_clocks,
+ .num_clks = ARRAY_SIZE(nss_cc_ipq5332_clocks),
+ .resets = nss_cc_ipq5332_resets,
+ .num_resets = ARRAY_SIZE(nss_cc_ipq5332_resets),
+};
+
+static const struct of_device_id nss_cc_ipq5332_match_table[] = {
+ { .compatible = "qcom,ipq5332-nsscc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nss_cc_ipq5332_match_table);
+
+static int nss_cc_ipq5332_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &nss_cc_ipq5332_desc);
+}
+
+static struct platform_driver nss_cc_ipq5332_driver = {
+ .probe = nss_cc_ipq5332_probe,
+ .driver = {
+ .name = "qcom,ipq5332-nsscc",
+ .of_match_table = nss_cc_ipq5332_match_table,
+ },
+};
+module_platform_driver(nss_cc_ipq5332_driver);
+
+MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Describe the NSS clock controller node and it's relevant external
clocks.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Update the node names with proper suffix
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 42e2e48b2bc3..5cbe72f03869 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -15,6 +15,18 @@ / {
#size-cells = <2>;
clocks {
+ cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ #clock-cells = <0>;
+ };
+
+ cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -473,6 +485,22 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000{
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&cmn_pll_nss_200m_clk>,
+ <&cmn_pll_nss_300m_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&xo_board>;
+ #clock-cells = <0x1>;
+ #reset-cells = <0x1>;
+ #power-domain-cells = <1>;
+ };
};
timer {
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
Describe the NSS clock controller node and it's relevant external
clocks.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Update the node names with proper suffix
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 42e2e48b2bc3..5cbe72f03869 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -15,6 +15,18 @@ / {
#size-cells = <2>;
clocks {
+ cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ #clock-cells = <0>;
+ };
+
+ cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -473,6 +485,22 @@ frame@b128000 {
status = "disabled";
};
};
+
+ nsscc: clock-controller@39b00000{
+ compatible = "qcom,ipq5332-nsscc";
+ reg = <0x39b00000 0x80000>;
+ clocks = <&cmn_pll_nss_200m_clk>,
+ <&cmn_pll_nss_300m_clk>,
+ <&gcc GPLL0_OUT_AUX>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&xo_board>;
+ #clock-cells = <0x1>;
+ #reset-cells = <0x1>;
+ #power-domain-cells = <1>;
+ };
};
timer {
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
NSSCC driver is needed to enable the ethernet interfaces and not
necessary for the bootup of the SoC, hence build it as a module.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Repharse the commit message to indicate why driver should be
built as m.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b60aa1f89343..c075202d255d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1223,6 +1223,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5332=y
+CONFIG_IPQ_NSSCC_5332=m
CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
--
2.34.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
@ 2023-11-21 14:30 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-21 14:30 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel, Kathiravan Thirumoorthy
NSSCC driver is needed to enable the ethernet interfaces and not
necessary for the bootup of the SoC, hence build it as a module.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Changes in V2:
- Repharse the commit message to indicate why driver should be
built as m.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b60aa1f89343..c075202d255d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1223,6 +1223,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_GCC_5332=y
+CONFIG_IPQ_NSSCC_5332=m
CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_6018=y
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* Re: [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 15:02 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-21 15:02 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> NSSCC driver is needed to enable the ethernet interfaces and not
> necessary for the bootup of the SoC, hence build it as a module.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332
@ 2023-11-21 15:02 ` Krzysztof Kozlowski
0 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-21 15:02 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> NSSCC driver is needed to enable the ethernet interfaces and not
> necessary for the bootup of the SoC, hence build it as a module.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-21 15:06 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-21 15:06 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
Where is this commit coming from?
> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
Implementation can change and for example bring back these clocks. Are
you going to change bindings? No, drop the patch.
Bindings should be dropped only in a few rare cases like clocks not
available for OS or bugs.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-21 15:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-21 15:06 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
Where is this commit coming from?
> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
Implementation can change and for example bring back these clocks. Are
you going to change bindings? No, drop the patch.
Bindings should be dropped only in a few rare cases like clocks not
available for OS or bugs.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-21 15:06 ` Krzysztof Kozlowski
@ 2023-11-22 10:08 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>
> Where is this commit coming from?
>
>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>
> Implementation can change and for example bring back these clocks. Are
> you going to change bindings? No, drop the patch.
>
> Bindings should be dropped only in a few rare cases like clocks not
> available for OS or bugs.
Thanks Krzysztof. Will drop this patch in V3.
One more question to understand further. In IPQ SoCs there are bunch of
coresight / QDSS clocks but coresight framework doesn't handle all
clocks. Those clocks are enabled in bootloader stage itself. In such
case, should I drop the clocks from both binding and driver or only from
driver?
Thanks,
Kathiravan.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-22 10:08 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>
> Where is this commit coming from?
>
>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>
> Implementation can change and for example bring back these clocks. Are
> you going to change bindings? No, drop the patch.
>
> Bindings should be dropped only in a few rare cases like clocks not
> available for OS or bugs.
Thanks Krzysztof. Will drop this patch in V3.
One more question to understand further. In IPQ SoCs there are bunch of
coresight / QDSS clocks but coresight framework doesn't handle all
clocks. Those clocks are enabled in bootloader stage itself. In such
case, should I drop the clocks from both binding and driver or only from
driver?
Thanks,
Kathiravan.
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-22 10:08 ` Kathiravan Thirumoorthy
@ 2023-11-22 10:12 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-22 10:12 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>
>
> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>
>> Where is this commit coming from?
>>
>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>
>> Implementation can change and for example bring back these clocks. Are
>> you going to change bindings? No, drop the patch.
>>
>> Bindings should be dropped only in a few rare cases like clocks not
>> available for OS or bugs.
>
> Thanks Krzysztof. Will drop this patch in V3.
>
> One more question to understand further. In IPQ SoCs there are bunch of
> coresight / QDSS clocks but coresight framework doesn't handle all
> clocks. Those clocks are enabled in bootloader stage itself. In such
> case, should I drop the clocks from both binding and driver or only from
> driver?
That's not really the reason to drop them at all. Neither from driver,
nor from bindings. You should not rely on bootloader handling your clocks
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-22 10:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 50+ messages in thread
From: Krzysztof Kozlowski @ 2023-11-22 10:12 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>
>
> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>
>> Where is this commit coming from?
>>
>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>
>> Implementation can change and for example bring back these clocks. Are
>> you going to change bindings? No, drop the patch.
>>
>> Bindings should be dropped only in a few rare cases like clocks not
>> available for OS or bugs.
>
> Thanks Krzysztof. Will drop this patch in V3.
>
> One more question to understand further. In IPQ SoCs there are bunch of
> coresight / QDSS clocks but coresight framework doesn't handle all
> clocks. Those clocks are enabled in bootloader stage itself. In such
> case, should I drop the clocks from both binding and driver or only from
> driver?
That's not really the reason to drop them at all. Neither from driver,
nor from bindings. You should not rely on bootloader handling your clocks
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-22 10:12 ` Krzysztof Kozlowski
@ 2023-11-22 10:18 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:18 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
> On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>>
>>
>> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>>
>>> Where is this commit coming from?
>>>
>>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>>
>>> Implementation can change and for example bring back these clocks. Are
>>> you going to change bindings? No, drop the patch.
>>>
>>> Bindings should be dropped only in a few rare cases like clocks not
>>> available for OS or bugs.
>>
>> Thanks Krzysztof. Will drop this patch in V3.
>>
>> One more question to understand further. In IPQ SoCs there are bunch of
>> coresight / QDSS clocks but coresight framework doesn't handle all
>> clocks. Those clocks are enabled in bootloader stage itself. In such
>> case, should I drop the clocks from both binding and driver or only from
>> driver?
>
> That's not really the reason to drop them at all. Neither from driver,
> nor from bindings. You should not rely on bootloader handling your clocks
Thanks, lets say if those clocks are not needed at all by OS since QDSS
is not used and needed only for the boot loaders to access the
corresponding address space, in such case what can be done? I
understand, at first those clocks should not have been added to the driver.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-22 10:18 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:18 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
> On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>>
>>
>> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>>
>>> Where is this commit coming from?
>>>
>>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>>
>>> Implementation can change and for example bring back these clocks. Are
>>> you going to change bindings? No, drop the patch.
>>>
>>> Bindings should be dropped only in a few rare cases like clocks not
>>> available for OS or bugs.
>>
>> Thanks Krzysztof. Will drop this patch in V3.
>>
>> One more question to understand further. In IPQ SoCs there are bunch of
>> coresight / QDSS clocks but coresight framework doesn't handle all
>> clocks. Those clocks are enabled in bootloader stage itself. In such
>> case, should I drop the clocks from both binding and driver or only from
>> driver?
>
> That's not really the reason to drop them at all. Neither from driver,
> nor from bindings. You should not rely on bootloader handling your clocks
Thanks, lets say if those clocks are not needed at all by OS since QDSS
is not used and needed only for the boot loaders to access the
corresponding address space, in such case what can be done? I
understand, at first those clocks should not have been added to the driver.
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-22 10:18 ` Kathiravan Thirumoorthy
@ 2023-11-22 10:23 ` Dmitry Baryshkov
-1 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-11-22 10:23 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon, linux-arm-msm, linux-clk,
linux-kernel, devicetree, netdev, linux-arm-kernel
On Wed, 22 Nov 2023 at 12:19, Kathiravan Thirumoorthy
<quic_kathirav@quicinc.com> wrote:
>
>
>
> On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
> > On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
> >>
> >>
> >> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
> >>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> >>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
> >>>
> >>> Where is this commit coming from?
> >>>
> >>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
> >>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
> >>>
> >>> Implementation can change and for example bring back these clocks. Are
> >>> you going to change bindings? No, drop the patch.
> >>>
> >>> Bindings should be dropped only in a few rare cases like clocks not
> >>> available for OS or bugs.
> >>
> >> Thanks Krzysztof. Will drop this patch in V3.
> >>
> >> One more question to understand further. In IPQ SoCs there are bunch of
> >> coresight / QDSS clocks but coresight framework doesn't handle all
> >> clocks. Those clocks are enabled in bootloader stage itself. In such
> >> case, should I drop the clocks from both binding and driver or only from
> >> driver?
> >
> > That's not really the reason to drop them at all. Neither from driver,
> > nor from bindings. You should not rely on bootloader handling your clocks
>
>
> Thanks, lets say if those clocks are not needed at all by OS since QDSS
> is not used and needed only for the boot loaders to access the
> corresponding address space, in such case what can be done? I
> understand, at first those clocks should not have been added to the driver.
First, what is QDSS? Yet another acronym?
Second, if they are not used now, they can get used later.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-22 10:23 ` Dmitry Baryshkov
0 siblings, 0 replies; 50+ messages in thread
From: Dmitry Baryshkov @ 2023-11-22 10:23 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon, linux-arm-msm, linux-clk,
linux-kernel, devicetree, netdev, linux-arm-kernel
On Wed, 22 Nov 2023 at 12:19, Kathiravan Thirumoorthy
<quic_kathirav@quicinc.com> wrote:
>
>
>
> On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
> > On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
> >>
> >>
> >> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
> >>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
> >>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
> >>>
> >>> Where is this commit coming from?
> >>>
> >>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
> >>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
> >>>
> >>> Implementation can change and for example bring back these clocks. Are
> >>> you going to change bindings? No, drop the patch.
> >>>
> >>> Bindings should be dropped only in a few rare cases like clocks not
> >>> available for OS or bugs.
> >>
> >> Thanks Krzysztof. Will drop this patch in V3.
> >>
> >> One more question to understand further. In IPQ SoCs there are bunch of
> >> coresight / QDSS clocks but coresight framework doesn't handle all
> >> clocks. Those clocks are enabled in bootloader stage itself. In such
> >> case, should I drop the clocks from both binding and driver or only from
> >> driver?
> >
> > That's not really the reason to drop them at all. Neither from driver,
> > nor from bindings. You should not rely on bootloader handling your clocks
>
>
> Thanks, lets say if those clocks are not needed at all by OS since QDSS
> is not used and needed only for the boot loaders to access the
> corresponding address space, in such case what can be done? I
> understand, at first those clocks should not have been added to the driver.
First, what is QDSS? Yet another acronym?
Second, if they are not used now, they can get used later.
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
2023-11-22 10:23 ` Dmitry Baryshkov
@ 2023-11-22 10:45 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon, linux-arm-msm, linux-clk,
linux-kernel, devicetree, netdev, linux-arm-kernel
On 11/22/2023 3:53 PM, Dmitry Baryshkov wrote:
> On Wed, 22 Nov 2023 at 12:19, Kathiravan Thirumoorthy
> <quic_kathirav@quicinc.com> wrote:
>>
>>
>>
>> On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
>>> On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>>>>
>>>>
>>>> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>>>>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>>>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>>>>
>>>>> Where is this commit coming from?
>>>>>
>>>>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>>>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>>>>
>>>>> Implementation can change and for example bring back these clocks. Are
>>>>> you going to change bindings? No, drop the patch.
>>>>>
>>>>> Bindings should be dropped only in a few rare cases like clocks not
>>>>> available for OS or bugs.
>>>>
>>>> Thanks Krzysztof. Will drop this patch in V3.
>>>>
>>>> One more question to understand further. In IPQ SoCs there are bunch of
>>>> coresight / QDSS clocks but coresight framework doesn't handle all
>>>> clocks. Those clocks are enabled in bootloader stage itself. In such
>>>> case, should I drop the clocks from both binding and driver or only from
>>>> driver?
>>>
>>> That's not really the reason to drop them at all. Neither from driver,
>>> nor from bindings. You should not rely on bootloader handling your clocks
>>
>>
>> Thanks, lets say if those clocks are not needed at all by OS since QDSS
>> is not used and needed only for the boot loaders to access the
>> corresponding address space, in such case what can be done? I
>> understand, at first those clocks should not have been added to the driver.
>
> First, what is QDSS? Yet another acronym?
Qualcomm Debug Sub System - which compromises of various debug infra
like coresight, DCC and so on.
>
> Second, if they are not used now, they can get used later.
>
Thanks. I will drop it from driver and leave the bindings as it is.
Thanks,
Kathiravan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition
@ 2023-11-22 10:45 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-22 10:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon, linux-arm-msm, linux-clk,
linux-kernel, devicetree, netdev, linux-arm-kernel
On 11/22/2023 3:53 PM, Dmitry Baryshkov wrote:
> On Wed, 22 Nov 2023 at 12:19, Kathiravan Thirumoorthy
> <quic_kathirav@quicinc.com> wrote:
>>
>>
>>
>> On 11/22/2023 3:42 PM, Krzysztof Kozlowski wrote:
>>> On 22/11/2023 11:08, Kathiravan Thirumoorthy wrote:
>>>>
>>>>
>>>> On 11/21/2023 8:36 PM, Krzysztof Kozlowski wrote:
>>>>> On 21/11/2023 15:30, Kathiravan Thirumoorthy wrote:
>>>>>> In commit 0dd3f263c810 ("clk: qcom: ipq5332: enable few nssnoc clocks in
>>>>>
>>>>> Where is this commit coming from?
>>>>>
>>>>>> driver probe"), gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk,
>>>>>> gcc_nssnoc_nsscc_clk are enabled in driver probe to keep it always-on.
>>>>>
>>>>> Implementation can change and for example bring back these clocks. Are
>>>>> you going to change bindings? No, drop the patch.
>>>>>
>>>>> Bindings should be dropped only in a few rare cases like clocks not
>>>>> available for OS or bugs.
>>>>
>>>> Thanks Krzysztof. Will drop this patch in V3.
>>>>
>>>> One more question to understand further. In IPQ SoCs there are bunch of
>>>> coresight / QDSS clocks but coresight framework doesn't handle all
>>>> clocks. Those clocks are enabled in bootloader stage itself. In such
>>>> case, should I drop the clocks from both binding and driver or only from
>>>> driver?
>>>
>>> That's not really the reason to drop them at all. Neither from driver,
>>> nor from bindings. You should not rely on bootloader handling your clocks
>>
>>
>> Thanks, lets say if those clocks are not needed at all by OS since QDSS
>> is not used and needed only for the boot loaders to access the
>> corresponding address space, in such case what can be done? I
>> understand, at first those clocks should not have been added to the driver.
>
> First, what is QDSS? Yet another acronym?
Qualcomm Debug Sub System - which compromises of various debug infra
like coresight, DCC and so on.
>
> Second, if they are not used now, they can get used later.
>
Thanks. I will drop it from driver and leave the bindings as it is.
Thanks,
Kathiravan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-22 16:31 ` Konrad Dybcio
-1 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 16:31 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> There are few places where clk_init_data structure doesn't carry the const
> qualifier. Let's add the same.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure
@ 2023-11-22 16:31 ` Konrad Dybcio
0 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 16:31 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> There are few places where clk_init_data structure doesn't carry the const
> qualifier. Let's add the same.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-22 16:32 ` Konrad Dybcio
-1 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 16:32 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
> enabled by default and it's RCG is properly configured by bootloader.
>
> Some of the NSS clocks needs these clocks to be enabled. To avoid
> these clocks being disabled by clock framework, drop these entries
> from the clock table and enable it in the driver probe itself.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe
@ 2023-11-22 16:32 ` Konrad Dybcio
0 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 16:32 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are
> enabled by default and it's RCG is properly configured by bootloader.
>
> Some of the NSS clocks needs these clocks to be enabled. To avoid
> these clocks being disabled by clock framework, drop these entries
> from the clock table and enable it in the driver probe itself.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-22 20:20 ` Konrad Dybcio
-1 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:20 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
> IPQ5332 based devices.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
LGTM except a single nit
> +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
@ 2023-11-22 20:20 ` Konrad Dybcio
0 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:20 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
> IPQ5332 based devices.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
LGTM except a single nit
> +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-22 20:22 ` Konrad Dybcio
-1 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:22 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Describe the NSS clock controller node and it's relevant external
> clocks.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
> Changes in V2:
> - Update the node names with proper suffix
> ---
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 42e2e48b2bc3..5cbe72f03869 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -15,6 +15,18 @@ / {
> #size-cells = <2>;
>
> clocks {
> + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <200000000>;
> + #clock-cells = <0>;
> + };
> +
> + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <300000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -473,6 +485,22 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + nsscc: clock-controller@39b00000{
> + compatible = "qcom,ipq5332-nsscc";
> + reg = <0x39b00000 0x80000>;
> + clocks = <&cmn_pll_nss_200m_clk>,
> + <&cmn_pll_nss_300m_clk>,
> + <&gcc GPLL0_OUT_AUX>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&xo_board>;
> + #clock-cells = <0x1>;
> + #reset-cells = <0x1>;
0x1 -> 1, it's a number and not a register
Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
@ 2023-11-22 20:22 ` Konrad Dybcio
0 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:22 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Describe the NSS clock controller node and it's relevant external
> clocks.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
> Changes in V2:
> - Update the node names with proper suffix
> ---
> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 42e2e48b2bc3..5cbe72f03869 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -15,6 +15,18 @@ / {
> #size-cells = <2>;
>
> clocks {
> + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <200000000>;
> + #clock-cells = <0>;
> + };
> +
> + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <300000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -473,6 +485,22 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + nsscc: clock-controller@39b00000{
> + compatible = "qcom,ipq5332-nsscc";
> + reg = <0x39b00000 0x80000>;
> + clocks = <&cmn_pll_nss_200m_clk>,
> + <&cmn_pll_nss_300m_clk>,
> + <&gcc GPLL0_OUT_AUX>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <&xo_board>;
> + #clock-cells = <0x1>;
> + #reset-cells = <0x1>;
0x1 -> 1, it's a number and not a register
Konrad
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-22 20:22 ` Konrad Dybcio
-1 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:22 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (NSS) clocks.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock
@ 2023-11-22 20:22 ` Konrad Dybcio
0 siblings, 0 replies; 50+ messages in thread
From: Konrad Dybcio @ 2023-11-22 20:22 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (NSS) clocks.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
2023-11-22 20:22 ` Konrad Dybcio
@ 2023-11-23 7:13 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-23 7:13 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/23/2023 1:52 AM, Konrad Dybcio wrote:
>
>
> On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
>> Describe the NSS clock controller node and it's relevant external
>> clocks.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
>> Changes in V2:
>> - Update the node names with proper suffix
>> ---
>> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index 42e2e48b2bc3..5cbe72f03869 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -15,6 +15,18 @@ / {
>> #size-cells = <2>;
>> clocks {
>> + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <200000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <300000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -473,6 +485,22 @@ frame@b128000 {
>> status = "disabled";
>> };
>> };
>> +
>> + nsscc: clock-controller@39b00000{
>> + compatible = "qcom,ipq5332-nsscc";
>> + reg = <0x39b00000 0x80000>;
>> + clocks = <&cmn_pll_nss_200m_clk>,
>> + <&cmn_pll_nss_300m_clk>,
>> + <&gcc GPLL0_OUT_AUX>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&xo_board>;
>> + #clock-cells = <0x1>;
>> + #reset-cells = <0x1>;
> 0x1 -> 1, it's a number and not a register
Thanks for pointing it out, will fix it in next spin.
>
> Konrad
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC
@ 2023-11-23 7:13 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-23 7:13 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/23/2023 1:52 AM, Konrad Dybcio wrote:
>
>
> On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
>> Describe the NSS clock controller node and it's relevant external
>> clocks.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
>> Changes in V2:
>> - Update the node names with proper suffix
>> ---
>> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index 42e2e48b2bc3..5cbe72f03869 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -15,6 +15,18 @@ / {
>> #size-cells = <2>;
>> clocks {
>> + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <200000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <300000000>;
>> + #clock-cells = <0>;
>> + };
>> +
>> sleep_clk: sleep-clk {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> @@ -473,6 +485,22 @@ frame@b128000 {
>> status = "disabled";
>> };
>> };
>> +
>> + nsscc: clock-controller@39b00000{
>> + compatible = "qcom,ipq5332-nsscc";
>> + reg = <0x39b00000 0x80000>;
>> + clocks = <&cmn_pll_nss_200m_clk>,
>> + <&cmn_pll_nss_300m_clk>,
>> + <&gcc GPLL0_OUT_AUX>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&xo_board>;
>> + #clock-cells = <0x1>;
>> + #reset-cells = <0x1>;
> 0x1 -> 1, it's a number and not a register
Thanks for pointing it out, will fix it in next spin.
>
> Konrad
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
2023-11-22 20:20 ` Konrad Dybcio
@ 2023-11-23 7:14 ` Kathiravan Thirumoorthy
-1 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-23 7:14 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/23/2023 1:50 AM, Konrad Dybcio wrote:
>
>
> On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
>> IPQ5332 based devices.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
> LGTM except a single nit
Thanks, will modify it as below
MODULE_DESCRIPTION("QTI NSSCC IPQ5332 Driver");
>
>> +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
>
> Konrad
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
@ 2023-11-23 7:14 ` Kathiravan Thirumoorthy
0 siblings, 0 replies; 50+ messages in thread
From: Kathiravan Thirumoorthy @ 2023-11-23 7:14 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Richard Cochran, Catalin Marinas, Will Deacon
Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, netdev,
linux-arm-kernel
On 11/23/2023 1:50 AM, Konrad Dybcio wrote:
>
>
> On 11/21/23 15:30, Kathiravan Thirumoorthy wrote:
>> Add Networking Sub System Clock Controller(NSSCC) driver for Qualcomm
>> IPQ5332 based devices.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
> LGTM except a single nit
Thanks, will modify it as below
MODULE_DESCRIPTION("QTI NSSCC IPQ5332 Driver");
>
>> +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver");
>
> Konrad
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
2023-11-21 14:30 ` Kathiravan Thirumoorthy
@ 2023-11-24 13:19 ` kernel test robot
-1 siblings, 0 replies; 50+ messages in thread
From: kernel test robot @ 2023-11-24 13:19 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: llvm, oe-kbuild-all, linux-arm-msm, linux-clk, linux-kernel,
devicetree, netdev, linux-arm-kernel, Kathiravan Thirumoorthy
Hi Kathiravan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 07b677953b9dca02928be323e2db853511305fa9]
url: https://github.com/intel-lab-lkp/linux/commits/Kathiravan-Thirumoorthy/clk-qcom-ipq5332-add-const-qualifier-to-the-clk_init_data-structure/20231121-223615
base: 07b677953b9dca02928be323e2db853511305fa9
patch link: https://lore.kernel.org/r/20231121-ipq5332-nsscc-v2-7-a7ff61beab72%40quicinc.com
patch subject: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20231124/202311241420.9uiff44i-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231124/202311241420.9uiff44i-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311241420.9uiff44i-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/qcom/nsscc-ipq5332.c:161:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:162:2: error: call to undeclared function 'C'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
^
drivers/clk/qcom/nsscc-ipq5332.c:166:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:171:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:172:2: error: call to undeclared function 'FMS'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
FMS(24000000, P_XO, 1, 0, 0),
^
>> drivers/clk/qcom/nsscc-ipq5332.c:173:2: error: call to undeclared function 'FM'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
^
>> drivers/clk/qcom/nsscc-ipq5332.c:191:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:195:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:200:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:205:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:225:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:229:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:234:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:239:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:259:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:263:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:268:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:273:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:293:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
19 errors generated.
vim +161 drivers/clk/qcom/nsscc-ipq5332.c
160
> 161 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
> 162 C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
163 C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
164 };
165
166 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
167 C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
168 C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
169 };
170
> 171 static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
> 172 FMS(24000000, P_XO, 1, 0, 0),
> 173 FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
174 FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
175 FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
176 FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
177 FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
178 { }
179 };
180
181 static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
182 .cmd_rcgr = 0x450,
183 .mnd_width = 0,
184 .hid_width = 5,
185 .parent_map = nss_cc_parent_map_1,
186 .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
187 .clkr.hw.init = &(const struct clk_init_data) {
188 .name = "nss_cc_port1_rx_clk_src",
189 .parent_data = nss_cc_parent_data_1,
190 .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
> 191 .ops = &clk_rcg2_fm_ops,
192 },
193 };
194
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
@ 2023-11-24 13:19 ` kernel test robot
0 siblings, 0 replies; 50+ messages in thread
From: kernel test robot @ 2023-11-24 13:19 UTC (permalink / raw)
To: Kathiravan Thirumoorthy, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Richard Cochran,
Catalin Marinas, Will Deacon
Cc: llvm, oe-kbuild-all, linux-arm-msm, linux-clk, linux-kernel,
devicetree, netdev, linux-arm-kernel, Kathiravan Thirumoorthy
Hi Kathiravan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 07b677953b9dca02928be323e2db853511305fa9]
url: https://github.com/intel-lab-lkp/linux/commits/Kathiravan-Thirumoorthy/clk-qcom-ipq5332-add-const-qualifier-to-the-clk_init_data-structure/20231121-223615
base: 07b677953b9dca02928be323e2db853511305fa9
patch link: https://lore.kernel.org/r/20231121-ipq5332-nsscc-v2-7-a7ff61beab72%40quicinc.com
patch subject: [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20231124/202311241420.9uiff44i-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231124/202311241420.9uiff44i-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311241420.9uiff44i-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/qcom/nsscc-ipq5332.c:161:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:162:2: error: call to undeclared function 'C'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
^
drivers/clk/qcom/nsscc-ipq5332.c:166:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:171:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
>> drivers/clk/qcom/nsscc-ipq5332.c:172:2: error: call to undeclared function 'FMS'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
FMS(24000000, P_XO, 1, 0, 0),
^
>> drivers/clk/qcom/nsscc-ipq5332.c:173:2: error: call to undeclared function 'FM'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
^
>> drivers/clk/qcom/nsscc-ipq5332.c:191:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:195:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:200:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:205:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:225:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:229:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:234:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:239:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:259:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
drivers/clk/qcom/nsscc-ipq5332.c:263:62: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:268:63: error: array has incomplete element type 'const struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:161:21: note: forward declaration of 'struct freq_conf'
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:273:64: error: array has incomplete element type 'const struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:171:21: note: forward declaration of 'struct freq_multi_tbl'
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
^
drivers/clk/qcom/nsscc-ipq5332.c:293:11: error: use of undeclared identifier 'clk_rcg2_fm_ops'; did you mean 'clk_rcg2_ops'?
.ops = &clk_rcg2_fm_ops,
^~~~~~~~~~~~~~~
clk_rcg2_ops
drivers/clk/qcom/clk-rcg.h:170:29: note: 'clk_rcg2_ops' declared here
extern const struct clk_ops clk_rcg2_ops;
^
19 errors generated.
vim +161 drivers/clk/qcom/nsscc-ipq5332.c
160
> 161 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
> 162 C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
163 C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
164 };
165
166 static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
167 C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
168 C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
169 };
170
> 171 static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
> 172 FMS(24000000, P_XO, 1, 0, 0),
> 173 FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
174 FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
175 FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
176 FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
177 FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
178 { }
179 };
180
181 static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
182 .cmd_rcgr = 0x450,
183 .mnd_width = 0,
184 .hid_width = 5,
185 .parent_map = nss_cc_parent_map_1,
186 .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
187 .clkr.hw.init = &(const struct clk_init_data) {
188 .name = "nss_cc_port1_rx_clk_src",
189 .parent_data = nss_cc_parent_data_1,
190 .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
> 191 .ops = &clk_rcg2_fm_ops,
192 },
193 };
194
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2023-11-24 13:21 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-21 14:30 [PATCH v2 0/9] Add NSS clock controller support for Qualcomm IPQ5332 Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-21 14:30 ` [PATCH v2 1/9] clk: qcom: ipq5332: add const qualifier to the clk_init_data structure Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-22 16:31 ` Konrad Dybcio
2023-11-22 16:31 ` Konrad Dybcio
2023-11-21 14:30 ` [PATCH v2 2/9] clk: qcom: ipq5332: enable few nssnoc clocks in driver probe Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-22 16:32 ` Konrad Dybcio
2023-11-22 16:32 ` Konrad Dybcio
2023-11-21 14:30 ` [PATCH v2 3/9] dt-bindings: clock: ipq5332: drop the few nss clocks definition Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-21 15:06 ` Krzysztof Kozlowski
2023-11-21 15:06 ` Krzysztof Kozlowski
2023-11-22 10:08 ` Kathiravan Thirumoorthy
2023-11-22 10:08 ` Kathiravan Thirumoorthy
2023-11-22 10:12 ` Krzysztof Kozlowski
2023-11-22 10:12 ` Krzysztof Kozlowski
2023-11-22 10:18 ` Kathiravan Thirumoorthy
2023-11-22 10:18 ` Kathiravan Thirumoorthy
2023-11-22 10:23 ` Dmitry Baryshkov
2023-11-22 10:23 ` Dmitry Baryshkov
2023-11-22 10:45 ` Kathiravan Thirumoorthy
2023-11-22 10:45 ` Kathiravan Thirumoorthy
2023-11-21 14:30 ` [PATCH v2 4/9] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-21 14:30 ` [PATCH v2 5/9] clk: qcom: ipq5332: add gpll0_out_aux clock Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-22 20:22 ` Konrad Dybcio
2023-11-22 20:22 ` Konrad Dybcio
2023-11-21 14:30 ` [PATCH v2 6/9] dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-21 14:30 ` [PATCH v2 7/9] clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332 Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-22 20:20 ` Konrad Dybcio
2023-11-22 20:20 ` Konrad Dybcio
2023-11-23 7:14 ` Kathiravan Thirumoorthy
2023-11-23 7:14 ` Kathiravan Thirumoorthy
2023-11-24 13:19 ` kernel test robot
2023-11-24 13:19 ` kernel test robot
2023-11-21 14:30 ` [PATCH v2 8/9] arm64: dts: qcom: ipq5332: add support for the NSSCC Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-22 20:22 ` Konrad Dybcio
2023-11-22 20:22 ` Konrad Dybcio
2023-11-23 7:13 ` Kathiravan Thirumoorthy
2023-11-23 7:13 ` Kathiravan Thirumoorthy
2023-11-21 14:30 ` [PATCH v2 9/9] arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332 Kathiravan Thirumoorthy
2023-11-21 14:30 ` Kathiravan Thirumoorthy
2023-11-21 15:02 ` Krzysztof Kozlowski
2023-11-21 15:02 ` Krzysztof Kozlowski
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