* [Intel-gfx] [PATCH 0/3] Implement CMRR Support
@ 2023-11-22 6:59 Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw)
To: intel-gfx
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.
enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.
Mitul Golani (3):
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Add Enable/Disable for CMRR based on VRR state
drm/i915: Compute CMRR and calculate vtotal
.../drm/i915/display/intel_crtc_state_dump.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++-
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_vrr.c | 129 ++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 10 ++
6 files changed, 184 insertions(+), 20 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
@ 2023-11-22 6:59 ` Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw)
To: intel-gfx
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++
4 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f8503d917c3d..cae399a6c54d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -920,6 +920,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4871,6 +4878,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
@@ -5251,10 +5268,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
#undef PIPE_CONF_CHECK_P
@@ -6594,7 +6614,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9a44350ba05d..e42a0807227b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1406,6 +1406,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..c889b0aa69a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_n));
+ intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_n));
+ }
+
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
@@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (crtc_state->cmrr.enable) {
+ crtc_state->cmrr.cmrr_n =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ TRANS_CMRR_N_HI(cpu_transcoder));
+ crtc_state->cmrr.cmrr_m =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ TRANS_CMRR_M_HI(cpu_transcoder));
+ }
+
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..b59cb9cbd187 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2011,6 +2011,7 @@
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
@@ -2087,6 +2088,15 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define _TRANS_CMRR_M_LO_A 0x604F0
+#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
+#define _TRANS_CMRR_M_HI_A 0x604F4
+#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
+#define _TRANS_CMRR_N_LO_A 0x604F8
+#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
+#define _TRANS_CMRR_N_HI_A 0x604FC
+#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
@ 2023-11-22 6:59 ` Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw)
To: intel-gfx
Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling. (Similar to enable case).[Jani]
- Correct messed up condition in intel_vrr_enable while fixing rev2. [Jani]
--v4:
- Removing RFC tag.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
.../drm/i915/display/intel_crtc_state_dump.c | 4 ++-
drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++-----
3 files changed, 49 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2d15e82c0b3d..908a4c4ccb00 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
intel_dump_buffer(i915, "ELD: ", pipe_config->eld,
drm_eld_size(pipe_config->eld));
- drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+ drm_dbg_kms(&i915->drm,
+ "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+ str_yes_no(pipe_config->cmrr.enable),
str_yes_no(pipe_config->vrr.enable),
pipe_config->vrr.vmin, pipe_config->vrr.vmax,
pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cae399a6c54d..d54b629c5379 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -936,6 +936,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
+static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!new_crtc_state->hw.active)
+ return false;
+
+ return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state);
+}
+
static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -945,6 +954,15 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
+static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ if (!old_crtc_state->hw.active)
+ return false;
+
+ return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state);
+}
+
#undef is_disabling
#undef is_enabling
@@ -1063,7 +1081,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
- if (vrr_disabling(old_crtc_state, new_crtc_state)) {
+ if (vrr_disabling(old_crtc_state, new_crtc_state) ||
+ cmrr_disabling(old_crtc_state, new_crtc_state)) {
intel_vrr_disable(old_crtc_state);
intel_crtc_update_active_timings(old_crtc_state, false);
}
@@ -6558,7 +6577,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
- if (vrr_enabling(old_crtc_state, new_crtc_state))
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ cmrr_enabling(old_crtc_state, new_crtc_state))
intel_vrr_enable(new_crtc_state);
}
@@ -6655,9 +6675,11 @@ static void intel_update_crtc(struct intel_atomic_state *state,
* FIXME Should be synchronized with the start of vblank somehow...
*/
if (vrr_enabling(old_crtc_state, new_crtc_state) ||
- new_crtc_state->update_m_n || new_crtc_state->update_lrr)
+ new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
+ cmrr_enabling(old_crtc_state, new_crtc_state))
intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
+ new_crtc_state->vrr.enable ||
+ new_crtc_state->cmrr.enable);
/*
* We usually enable FIFO underrun interrupts as part of the
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c889b0aa69a4..8f1d241e1f79 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable))
return;
intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
@@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable))
return false;
return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
@@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable &&
+ crtc_state->cmrr.enable))
return;
- intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
- intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->vrr.enable) {
+ intel_de_write(dev_priv,
+ TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
+
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv,
+ TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- if (!old_crtc_state->vrr.enable)
+ if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable))
return;
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
@@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
}
- if (crtc_state->vrr.enable)
+ if (crtc_state->vrr.enable || crtc_state->cmrr.enable)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
@ 2023-11-22 6:59 ` Mitul Golani
2023-11-22 8:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev5) Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-22 6:59 UTC (permalink / raw)
To: intel-gfx
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 79 +++++++++++++++++--
3 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d54b629c5379..5f12c7b3c404 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5289,6 +5289,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 4299cc452e05..66cbc3a6bbe8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8f1d241e1f79..db01cfe206d3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_vrr.h"
+#include "intel_dp.h"
bool intel_vrr_is_capable(struct intel_connector *connector)
{
@@ -105,6 +106,53 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
}
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+{
+ int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ actual_refresh_k = drm_mode_vrefresh(adjusted_mode) * 1000;
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ calculated_refresh_k =
+ pixel_clock_per_line * 1000 / adjusted_mode->crtc_vtotal;
+
+ if (calculated_refresh_k == actual_refresh_k)
+ return false;
+
+ return true;
+}
+
+static unsigned int
+cmrr_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+ int multiplier_m = 1, multiplier_n = 1, vtotal;
+ int actual_refresh_rate, desired_refresh_rate;
+ long long actual_pixel_rate, adjusted_pixel_rate;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ actual_refresh_rate = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
+ adjusted_mode->crtc_htotal) * 1000;
+ actual_refresh_rate /= adjusted_mode->crtc_vtotal;
+ desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+ actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal;
+ actual_pixel_rate = (actual_pixel_rate * adjusted_mode->crtc_htotal) / 1000;
+
+ if (is_cmrr_frac_required(crtc_state)) {
+ multiplier_m = 1001;
+ multiplier_n = 1000;
+ }
+
+ crtc_state->cmrr.cmrr_n = DIV_ROUND_UP(desired_refresh_rate *
+ adjusted_mode->crtc_htotal * multiplier_n, multiplier_m) * multiplier_n;
+ vtotal = DIV_ROUND_UP(actual_pixel_rate * multiplier_n, crtc_state->cmrr.cmrr_n);
+ adjusted_pixel_rate = actual_pixel_rate * multiplier_m;
+ crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+
+ return vtotal;
+}
+
void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -113,6 +161,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ bool is_edp = intel_dp_is_edp(intel_attached_dp(connector));
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
const struct drm_display_info *info = &connector->base.display_info;
int vmin, vmax;
@@ -149,6 +198,22 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
+ /*
+ * When panel is VRR capable and userspace has
+ * not enabled adaptive sync mode then Fixed Average
+ * Vtotal mode should be enabled.
+ */
+ if (crtc_state->uapi.vrr_enabled) {
+ crtc_state->vrr.enable = true;
+ crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+ } else if (HAS_CMRR(i915) && is_edp) {
+ crtc_state->cmrr.enable = true;
+ crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state);
+ crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+ crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+ crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+ }
+
/*
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
@@ -161,11 +226,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
crtc_state->framestart_delay - 1);
}
-
- if (crtc_state->uapi.vrr_enabled) {
- crtc_state->vrr.enable = true;
- crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- }
}
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
@@ -292,7 +352,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
- crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (HAS_CMRR(dev_priv)) {
+ crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) &&
+ (trans_vrr_ctl & VRR_CTL_VRR_ENABLE);
+ crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE &&
+ !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+ } else {
+ crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ }
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev5)
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
` (2 preceding siblings ...)
2023-11-22 6:59 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
@ 2023-11-22 8:16 ` Patchwork
2023-11-22 8:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-11-22 8:16 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
== Series Details ==
Series: Implement CMRR Support (rev5)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
9f772b978eb6 drm/i915: Define and compute Transcoder CMRR registers
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.c:4881:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:42: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#42: FILE: drivers/gpu/drm/i915/display/intel_display.c:4881:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 2 checks, 119 lines checked
d55923e6b692 drm/i915: Add Enable/Disable for CMRR based on VRR state
-:21: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#21:
- Check pipe active state in cmrr disabling. (Similar to enable case).[Jani]
total: 0 errors, 1 warnings, 0 checks, 130 lines checked
5ea7a5f2fbe0 drm/i915: Compute CMRR and calculate vtotal
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Implement CMRR Support (rev5)
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
` (3 preceding siblings ...)
2023-11-22 8:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev5) Patchwork
@ 2023-11-22 8:16 ` Patchwork
2023-11-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-11-22 8:16 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
== Series Details ==
Series: Implement CMRR Support (rev5)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Implement CMRR Support (rev5)
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
` (4 preceding siblings ...)
2023-11-22 8:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-11-22 8:49 ` Patchwork
2023-11-22 11:04 ` [Intel-gfx] [PATCH 0/3] Implement CMRR Support Jani Nikula
2023-11-22 22:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Implement CMRR Support (rev5) Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-11-22 8:49 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18839 bytes --]
== Series Details ==
Series: Implement CMRR Support (rev5)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13909 -> Patchwork_126443v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/index.html
Participating hosts (32 -> 35)
------------------------------
Additional (5): bat-adlp-11 bat-adlp-9 bat-dg2-8 bat-dg2-9 bat-mtlp-8
Missing (2): bat-kbl-2 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_126443v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- bat-adlp-9: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@debugfs_test@basic-hwmon.html
- bat-adlp-11: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@debugfs_test@basic-hwmon.html
* igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: NOTRUN -> [FAIL][4] ([fdo#103375]) +6 other tests fail
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-9: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg2-9: NOTRUN -> [SKIP][7] ([i915#4083])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@gem_mmap@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#4083])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-9: NOTRUN -> [SKIP][15] ([i915#3282])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@gem_tiled_pread_basic.html
- bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#4079]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@gem_tiled_pread_basic.html
- bat-adlp-11: NOTRUN -> [SKIP][17] ([i915#3282])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@reload:
- bat-dg2-11: [PASS][18] -> [DMESG-WARN][19] ([i915#1982])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/bat-dg2-11/igt@i915_module_load@reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-11/igt@i915_module_load@reload.html
* igt@i915_pm_rps@basic-api:
- bat-adlp-9: NOTRUN -> [SKIP][20] ([i915#6621])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@i915_pm_rps@basic-api.html
- bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#6621])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#6621])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-dg2-8: NOTRUN -> [SKIP][23] ([i915#6621])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][24] ([i915#6645])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
- bat-dg2-8: NOTRUN -> [SKIP][25] ([i915#6645])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][26] ([i915#5190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][27] ([i915#5190])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][28] ([i915#5190])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][29] ([i915#4215] / [i915#5190])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][30] ([i915#4212]) +8 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][31] ([i915#4215] / [i915#5190])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][32] ([i915#4212]) +6 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
- bat-dg2-8: NOTRUN -> [SKIP][33] ([i915#4212]) +6 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9: NOTRUN -> [SKIP][34] ([i915#4212] / [i915#5608])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html
- bat-dg2-8: NOTRUN -> [SKIP][35] ([i915#4212] / [i915#5608])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-adlp-9: NOTRUN -> [SKIP][36] ([i915#4103] / [i915#5608]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][37] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-adlp-11: NOTRUN -> [SKIP][38] ([i915#4103] / [i915#5608]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][39] ([i915#4213]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][40] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adlp-11: NOTRUN -> [SKIP][41] ([i915#3555] / [i915#3840])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@kms_dsc@dsc-basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][42] ([i915#3555] / [i915#3840] / [i915#9159])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
- bat-adlp-9: NOTRUN -> [SKIP][43] ([i915#3555] / [i915#3840])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9: NOTRUN -> [SKIP][44] ([fdo#109285])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][45] ([fdo#109285])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-8: NOTRUN -> [SKIP][46] ([fdo#109285])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-adlp-9: NOTRUN -> [SKIP][47] ([fdo#109285])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9: NOTRUN -> [SKIP][48] ([i915#5274])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-adlp-11: NOTRUN -> [SKIP][49] ([i915#4093]) +3 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][50] ([i915#5274])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-dg2-8: NOTRUN -> [SKIP][51] ([i915#5274])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- bat-adlp-11: NOTRUN -> [SKIP][52] ([i915#4369])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-11/igt@kms_hdmi_inject@inject-audio.html
- fi-kbl-guc: [PASS][53] -> [FAIL][54] ([IGT#3])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][55] ([i915#1845] / [i915#9197]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-9: NOTRUN -> [SKIP][56] ([i915#3555])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-9: NOTRUN -> [SKIP][57] ([i915#3555] / [i915#4098])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][58] ([i915#3555] / [i915#8809])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-8: NOTRUN -> [SKIP][59] ([i915#3555] / [i915#4098])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-9: NOTRUN -> [SKIP][60] ([i915#3708])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
- bat-dg2-8: NOTRUN -> [SKIP][61] ([i915#3708])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][62] ([i915#3708] / [i915#4077]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
- bat-dg2-9: NOTRUN -> [SKIP][63] ([i915#3708] / [i915#4077]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][64] ([i915#3708] / [i915#4077]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][65] ([i915#3708]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
- bat-adlp-9: NOTRUN -> [SKIP][66] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-adlp-9/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-write:
- bat-dg2-9: NOTRUN -> [SKIP][67] ([i915#3291] / [i915#3708]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-9/igt@prime_vgem@basic-write.html
- bat-dg2-8: NOTRUN -> [SKIP][68] ([i915#3291] / [i915#3708]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][69] ([i915#8668]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8981]: https://gitlab.freedesktop.org/drm/intel/issues/8981
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
Build changes
-------------
* Linux: CI_DRM_13909 -> Patchwork_126443v5
CI-20190529: 20190529
CI_DRM_13909: cd560a69c56be9eb8db94a5f35fa51b21928be86 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7595: cfa00d99b1dfa0621ea552d1ed54907798da1a1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126443v5: cd560a69c56be9eb8db94a5f35fa51b21928be86 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
c30d600f97dd drm/i915: Compute CMRR and calculate vtotal
0c5f497a6a08 drm/i915: Add Enable/Disable for CMRR based on VRR state
98cad45df0bf drm/i915: Define and compute Transcoder CMRR registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/index.html
[-- Attachment #2: Type: text/html, Size: 24463 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Implement CMRR Support
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
` (5 preceding siblings ...)
2023-11-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-11-22 11:04 ` Jani Nikula
2023-11-22 11:05 ` Jani Nikula
2023-11-22 22:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Implement CMRR Support (rev5) Patchwork
7 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2023-11-22 11:04 UTC (permalink / raw)
To: Mitul Golani, intel-gfx
On Wed, 22 Nov 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> CMRR is a display feature that uses adaptive sync
> framework to vary Vtotal slightly to match the
> content rate exactly without frame drops. This
> feature is a variation of VRR where it varies Vtotal
> slightly (between additional 0 and 1 Vtotal scanlines)
> to match content rate exactly without frame drops
> using the adaptive sync framework.
Please check and use the -v<N> option of git-send-email.
BR,
Jani.
>
> enable this feature by programing new registers for
> CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
> CMRR_M/CMRR_N ratio represents the fractional part
> in (actual refresh rate/target refresh rate) * origVTotal.
>
> Mitul Golani (3):
> drm/i915: Define and compute Transcoder CMRR registers
> drm/i915: Add Enable/Disable for CMRR based on VRR state
> drm/i915: Compute CMRR and calculate vtotal
>
> .../drm/i915/display/intel_crtc_state_dump.c | 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++-
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 129 ++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 10 ++
> 6 files changed, 184 insertions(+), 20 deletions(-)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Implement CMRR Support
2023-11-22 11:04 ` [Intel-gfx] [PATCH 0/3] Implement CMRR Support Jani Nikula
@ 2023-11-22 11:05 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2023-11-22 11:05 UTC (permalink / raw)
To: Mitul Golani, intel-gfx
On Wed, 22 Nov 2023, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 22 Nov 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> CMRR is a display feature that uses adaptive sync
>> framework to vary Vtotal slightly to match the
>> content rate exactly without frame drops. This
>> feature is a variation of VRR where it varies Vtotal
>> slightly (between additional 0 and 1 Vtotal scanlines)
>> to match content rate exactly without frame drops
>> using the adaptive sync framework.
>
> Please check and use the -v<N> option of git-send-email.
More precisely it's a git format-patch option, but send-email passes it
along.
>
> BR,
> Jani.
>
>
>>
>> enable this feature by programing new registers for
>> CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
>> CMRR_M/CMRR_N ratio represents the fractional part
>> in (actual refresh rate/target refresh rate) * origVTotal.
>>
>> Mitul Golani (3):
>> drm/i915: Define and compute Transcoder CMRR registers
>> drm/i915: Add Enable/Disable for CMRR based on VRR state
>> drm/i915: Compute CMRR and calculate vtotal
>>
>> .../drm/i915/display/intel_crtc_state_dump.c | 4 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 54 +++++++-
>> .../drm/i915/display/intel_display_device.h | 1 +
>> .../drm/i915/display/intel_display_types.h | 6 +
>> drivers/gpu/drm/i915/display/intel_vrr.c | 129 ++++++++++++++++--
>> drivers/gpu/drm/i915/i915_reg.h | 10 ++
>> 6 files changed, 184 insertions(+), 20 deletions(-)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Implement CMRR Support (rev5)
2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
` (6 preceding siblings ...)
2023-11-22 11:04 ` [Intel-gfx] [PATCH 0/3] Implement CMRR Support Jani Nikula
@ 2023-11-22 22:10 ` Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-11-22 22:10 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 56968 bytes --]
== Series Details ==
Series: Implement CMRR Support (rev5)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13909_full -> Patchwork_126443v5_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-mtlp0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_126443v5_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0}:
- shard-tglu: [FAIL][1] ([i915#3591]) -> [WARN][2] +1 other test warn
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* {igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3}:
- shard-dg1: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-13/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
Known issues
------------
Here are the changes found in Patchwork_126443v5_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [FAIL][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#8293])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk9/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk8/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk8/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk2/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk2/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk2/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk8/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk2/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk2/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#9318])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@drm_fdinfo@busy-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#8414]) +9 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@drm_fdinfo@busy-check-all@vecs1.html
* igt@drm_fdinfo@isolation@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#8414]) +11 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@drm_fdinfo@isolation@rcs0.html
* igt@gem_ccs@suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#9323]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][58] ([i915#7297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_create@hog-create@smem0:
- shard-mtlp: NOTRUN -> [FAIL][59] ([i915#8758])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@gem_create@hog-create@smem0.html
* igt@gem_ctx_persistence@engines-persistence:
- shard-snb: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#1099]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-snb5/igt@gem_ctx_persistence@engines-persistence.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#8555])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_sseu@engines:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#280])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@kms:
- shard-dg1: [PASS][63] -> [FAIL][64] ([i915#5784])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg1-12/igt@gem_eio@kms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-16/igt@gem_eio@kms.html
* igt@gem_eio@wait-10ms:
- shard-mtlp: [PASS][65] -> [ABORT][66] ([i915#9414])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-mtlp-6/igt@gem_eio@wait-10ms.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@gem_eio@wait-10ms.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#4812])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_fair@basic-deadline:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#4473] / [i915#4771])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4473])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fence@submit3:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#4812]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#3539])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#3539] / [i915#4852]) +2 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#5107])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#3281]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#3281]) +3 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4537] / [i915#4812])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#4537] / [i915#4812])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#4860]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html
* igt@gem_lmem_swapping@random:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#4613]) +3 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#4613])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4077]) +6 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_mmap_gtt@cpuset-medium-copy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4077]) +7 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#4083]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_mmap_wc@copy.html
* igt@gem_mmap_wc@read:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#4083]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_mmap_wc@read.html
* igt@gem_pxp@create-regular-context-1:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#4270]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@create-regular-context-2:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#4270])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-tglu: NOTRUN -> [SKIP][87] ([i915#4270]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_readwrite@read-bad-handle:
- shard-mtlp: NOTRUN -> [SKIP][88] ([i915#3282]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_readwrite@read-bad-handle.html
* igt@gem_readwrite@read-write:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#3282]) +2 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_readwrite@read-write.html
* igt@gem_render_copy@y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#8428]) +2 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gem_render_copy@y-tiled.html
* igt@gem_render_tiled_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#4079]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gem_render_tiled_blits@basic.html
* igt@gem_softpin@evict-snoop:
- shard-tglu: NOTRUN -> [SKIP][92] ([fdo#109312])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#3297]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#3297]) +2 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gen7_exec_parse@bitmasks:
- shard-dg2: NOTRUN -> [SKIP][95] ([fdo#109289]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gen7_exec_parse@bitmasks.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-mtlp: NOTRUN -> [SKIP][96] ([fdo#109289]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglu: NOTRUN -> [SKIP][97] ([i915#2527] / [i915#2856])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#2856]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#2856]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][100] -> [DMESG-WARN][101] ([i915#9559])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-tglu: NOTRUN -> [SKIP][102] ([i915#6590])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-mtlp: NOTRUN -> [SKIP][103] ([i915#6621])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][104] -> [INCOMPLETE][105] ([i915#7790])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-snb5/igt@i915_pm_rps@reset.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-snb2/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#8925])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#4387])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-mtlp: NOTRUN -> [SKIP][108] ([i915#6188])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-dg2: NOTRUN -> [SKIP][109] ([fdo#109303])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@i915_query@query-topology-known-pci-ids.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#4212]) +2 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-mtlp: NOTRUN -> [SKIP][111] ([i915#4212])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][112] ([i915#8247]) +3 other tests fail
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-3/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][113] ([i915#8247]) +3 other tests fail
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-13/igt@kms_async_flips@crc@pipe-b-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][114] ([fdo#111614]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [PASS][115] -> [FAIL][116] ([i915#5138]) +1 other test fail
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][117] ([fdo#111614])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][118] ([fdo#111614])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#5190]) +8 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-mtlp: NOTRUN -> [SKIP][120] ([fdo#111615]) +5 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#4538] / [i915#5190]) +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#6187])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][123] ([fdo#111615]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#4087] / [i915#7213]) +3 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-mtlp: NOTRUN -> [SKIP][125] ([fdo#111827])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_chamelium_color@ctm-0-75.html
* igt@kms_chamelium_color@degamma:
- shard-tglu: NOTRUN -> [SKIP][126] ([fdo#111827])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@dp-mode-timings:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#7828]) +6 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_chamelium_edid@dp-mode-timings.html
* igt@kms_chamelium_hpd@dp-hpd-fast:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#7828]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_chamelium_hpd@dp-hpd-fast.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#7828]) +4 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#7118])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#3299])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][132] ([i915#7173])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@kms_content_protection@lic@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-32x10:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#3555]) +1 other test skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_cursor_crc@cursor-offscreen-32x10.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#3359])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#3359])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#8814])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-tglu: NOTRUN -> [SKIP][137] ([i915#3555])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#3546]) +2 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-tglu: NOTRUN -> [SKIP][139] ([fdo#109274])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#4103] / [i915#4213] / [i915#5608])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-dg2: NOTRUN -> [SKIP][141] ([fdo#109274] / [i915#5354])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#4103])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#4103] / [i915#4213])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#8588])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#8812])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-tglu: NOTRUN -> [SKIP][146] ([fdo#109274] / [i915#3637])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][147] ([i915#3637]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-tglu: NOTRUN -> [SKIP][148] ([fdo#109274] / [fdo#111767] / [i915#3637])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-dg2: NOTRUN -> [SKIP][149] ([fdo#109274]) +5 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#2672]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#2587] / [i915#2672])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][152] ([i915#2672] / [i915#3555]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#2672]) +2 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-mtlp: NOTRUN -> [SKIP][154] ([fdo#109285])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#8708]) +4 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#5354]) +13 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-tglu: NOTRUN -> [SKIP][157] ([fdo#109280]) +9 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
- shard-dg2: [PASS][158] -> [FAIL][159] ([i915#6880])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][160] ([fdo#110189]) +4 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#3458]) +8 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#8708]) +9 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-snb: NOTRUN -> [SKIP][163] ([fdo#109271]) +73 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][164] ([i915#1825]) +20 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-tglu: NOTRUN -> [SKIP][166] ([fdo#109289])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8806])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][168] ([i915#8292])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-16/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#5235]) +7 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#5235]) +3 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#5235]) +11 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-15/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#6524] / [i915#6805])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-10/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#9683])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#9681]) +3 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#4235]) +1 other test skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-mtlp: NOTRUN -> [SKIP][176] ([i915#5289])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-tglu: NOTRUN -> [SKIP][177] ([fdo#111615] / [i915#5289])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#4235] / [i915#5190])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][179] ([i915#4235]) +1 other test skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#3555] / [i915#8809])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_writeback@writeback-fb-id:
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#2437])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#2437])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#7387])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@perf@global-sseu-config-invalid.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#8850])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@perf_pmu@cpu-hotplug.html
* igt@prime_vgem@basic-write:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3291] / [i915#3708])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-flip-hang:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#3708])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@prime_vgem@fence-flip-hang.html
* igt@runner@aborted:
- shard-snb: NOTRUN -> [FAIL][187] ([i915#7812])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-snb5/igt@runner@aborted.html
* igt@v3d/v3d_get_param@get-bad-param:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#2575]) +6 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@v3d/v3d_get_param@get-bad-param.html
* igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#2575]) +5 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html
* igt@v3d/v3d_submit_cl@bad-multisync-pad:
- shard-tglu: NOTRUN -> [SKIP][190] ([fdo#109315] / [i915#2575]) +2 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@v3d/v3d_submit_cl@bad-multisync-pad.html
* igt@vc4/vc4_perfmon@create-perfmon-0:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#7711]) +3 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@vc4/vc4_perfmon@create-perfmon-0.html
* igt@vc4/vc4_purgeable_bo@free-purged-bo:
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#2575]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-6/igt@vc4/vc4_purgeable_bo@free-purged-bo.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#7711]) +3 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-6/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html
#### Possible fixes ####
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][194] ([i915#7297]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][196] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-tglu-10/igt@gem_eio@hibernate.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-8/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- shard-dg2: [FAIL][198] ([i915#5784]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-10/igt@gem_eio@unwedge-stress.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][200] ([i915#2842]) -> [PASS][201] +1 other test pass
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-dg2: [INCOMPLETE][202] -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-7/igt@gem_workarounds@suspend-resume-fd.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-11/igt@gem_workarounds@suspend-resume-fd.html
* {igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0}:
- shard-dg1: [FAIL][204] ([i915#3591]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [FAIL][206] ([i915#5138]) -> [PASS][207]
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu: [FAIL][208] ([i915#3743]) -> [PASS][209]
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][210] ([i915#2346]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* {igt@kms_pm_backlight@fade-with-suspend@edp-1}:
- shard-mtlp: [ABORT][212] ([i915#9414]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-mtlp-5/igt@kms_pm_backlight@fade-with-suspend@edp-1.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-4/igt@kms_pm_backlight@fade-with-suspend@edp-1.html
* {igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait}:
- shard-dg2: [SKIP][214] ([i915#9519]) -> [PASS][215] +2 other tests pass
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* {igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-3}:
- shard-dg2: [ABORT][216] -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-1/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-3.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-3.html
* igt@perf_pmu@busy-accuracy-2@vcs1:
- shard-tglu: [INCOMPLETE][218] -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-tglu-8/igt@perf_pmu@busy-accuracy-2@vcs1.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-tglu-6/igt@perf_pmu@busy-accuracy-2@vcs1.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [FAIL][220] ([i915#4349]) -> [PASS][221] +3 other tests pass
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html
* igt@sw_sync@timeline_closed:
- shard-mtlp: [DMESG-WARN][222] ([i915#2017]) -> [PASS][223] +1 other test pass
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-mtlp-4/igt@sw_sync@timeline_closed.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-mtlp-5/igt@sw_sync@timeline_closed.html
#### Warnings ####
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][224] ([i915#5493]) -> [CRASH][225] ([i915#9351])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13909/shard-dg2-2/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7812]: https://gitlab.freedesktop.org/drm/intel/issues/7812
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758
[i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
[i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9559]: https://gitlab.freedesktop.org/drm/intel/issues/9559
[i915#9681]: https://gitlab.freedesktop.org/drm/intel/issues/9681
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
Build changes
-------------
* Linux: CI_DRM_13909 -> Patchwork_126443v5
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13909: cd560a69c56be9eb8db94a5f35fa51b21928be86 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7595: cfa00d99b1dfa0621ea552d1ed54907798da1a1a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126443v5: cd560a69c56be9eb8db94a5f35fa51b21928be86 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v5/index.html
[-- Attachment #2: Type: text/html, Size: 65864 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers
2023-12-05 18:36 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
@ 2023-12-05 18:36 ` Mitul Golani
0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-12-05 18:36 UTC (permalink / raw)
To: intel-gfx
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++
4 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d48bcdd5797..62dd8513a07a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -966,6 +966,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4957,6 +4964,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5324,10 +5341,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -6666,7 +6686,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b3e942f2eeb0..9fd0b82e93b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1412,6 +1412,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..c889b0aa69a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_n));
+ intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_n));
+ }
+
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
@@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (crtc_state->cmrr.enable) {
+ crtc_state->cmrr.cmrr_n =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ TRANS_CMRR_N_HI(cpu_transcoder));
+ crtc_state->cmrr.cmrr_m =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ TRANS_CMRR_M_HI(cpu_transcoder));
+ }
+
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..b59cb9cbd187 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2011,6 +2011,7 @@
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
@@ -2087,6 +2088,15 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define _TRANS_CMRR_M_LO_A 0x604F0
+#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
+#define _TRANS_CMRR_M_HI_A 0x604F4
+#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
+#define _TRANS_CMRR_N_LO_A 0x604F8
+#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
+#define _TRANS_CMRR_N_HI_A 0x604FC
+#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers
2023-11-21 17:35 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
@ 2023-11-21 17:35 ` Mitul Golani
0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-21 17:35 UTC (permalink / raw)
To: intel-gfx
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++
4 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 959db3f61e84..ea545414109e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -920,6 +920,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4896,6 +4903,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
@@ -5276,10 +5293,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
#undef PIPE_CONF_CHECK_P
@@ -6619,7 +6639,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9a44350ba05d..e42a0807227b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1406,6 +1406,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..c889b0aa69a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_n));
+ intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_n));
+ }
+
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
@@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (crtc_state->cmrr.enable) {
+ crtc_state->cmrr.cmrr_n =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ TRANS_CMRR_N_HI(cpu_transcoder));
+ crtc_state->cmrr.cmrr_m =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ TRANS_CMRR_M_HI(cpu_transcoder));
+ }
+
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..b59cb9cbd187 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2011,6 +2011,7 @@
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
@@ -2087,6 +2088,15 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define _TRANS_CMRR_M_LO_A 0x604F0
+#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
+#define _TRANS_CMRR_M_HI_A 0x604F4
+#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
+#define _TRANS_CMRR_N_LO_A 0x604F8
+#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
+#define _TRANS_CMRR_N_HI_A 0x604FC
+#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers
2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
@ 2023-11-15 13:43 ` Mitul Golani
0 siblings, 0 replies; 13+ messages in thread
From: Mitul Golani @ 2023-11-15 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++
4 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 125903007a29..f99d2de840bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
@@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
#undef PIPE_CONF_CHECK_P
@@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9a44350ba05d..e42a0807227b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1406,6 +1406,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..c889b0aa69a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_n));
+ intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_n));
+ }
+
intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
@@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (crtc_state->cmrr.enable) {
+ crtc_state->cmrr.cmrr_n =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+ TRANS_CMRR_N_HI(cpu_transcoder));
+ crtc_state->cmrr.cmrr_m =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+ TRANS_CMRR_M_HI(cpu_transcoder));
+ }
+
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 135e8d8dbdf0..06c1e1c47e0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2013,6 +2013,7 @@
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
@@ -2089,6 +2090,15 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define _TRANS_CMRR_M_LO_A 0x604F0
+#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A)
+#define _TRANS_CMRR_M_HI_A 0x604F4
+#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A)
+#define _TRANS_CMRR_N_LO_A 0x604F8
+#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A)
+#define _TRANS_CMRR_N_HI_A 0x604FC
+#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A)
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2023-12-05 18:41 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
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2023-11-22 6:59 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state Mitul Golani
2023-11-22 6:59 ` [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2023-11-22 8:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev5) Patchwork
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2023-11-22 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-22 11:04 ` [Intel-gfx] [PATCH 0/3] Implement CMRR Support Jani Nikula
2023-11-22 11:05 ` Jani Nikula
2023-11-22 22:10 ` [Intel-gfx] ✓ Fi.CI.IGT: success for Implement CMRR Support (rev5) Patchwork
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2023-12-05 18:36 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-12-05 18:36 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2023-11-21 17:35 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-21 17:35 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2023-11-15 13:43 [Intel-gfx] [PATCH 0/3] Implement CMRR Support Mitul Golani
2023-11-15 13:43 ` [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
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