[kvmtool PATCH 00/10] SBI debug console and few ISA extensions

[kvmtool PATCH 00/10] SBI debug console and few ISA extensions

[Anup Patel]

This series adds support for:
1) ISA extensions: Zba, Zbs, Zicntr, Zihpm, Zicsr, Zifencei, Zicond,
   and Smstateen
2) SBI debug console (DBCN) extension

These patches can also be found in the riscv_zbx_zicntr_smstateen_condops_v1
branch at: https://github.com/avpatel/kvmtool.git

Anup Patel (10):
  Sync-up header with Linux-6.7-rc3 for KVM RISC-V
  riscv: Improve warning in generate_cpu_nodes()
  riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size
  riscv: Add Zba and Zbs extension support
  riscv: Add Zicntr and Zihpm extension support
  riscv: Add Zicsr and Zifencei extension support
  riscv: Add Smstateen extension support
  riscv: Add Zicond extension support
  riscv: Set mmu-type DT property based on satp_mode ONE_REG interface
  riscv: Handle SBI DBCN calls from Guest/VM

 arm/aarch64/include/asm/kvm.h       | 32 ++++++++++++++++
 include/linux/kvm.h                 | 11 ++++++
 include/linux/virtio_config.h       |  5 +++
 include/linux/virtio_pci.h          | 11 ++++++
 riscv/fdt.c                         | 57 ++++++++++++++++++++++++-----
 riscv/include/asm/kvm.h             | 12 ++++++
 riscv/include/kvm/kvm-config-arch.h | 29 ++++++++++++++-
 riscv/include/kvm/sbi.h             | 14 ++++++-
 riscv/kvm-cpu.c                     | 57 +++++++++++++++++++++++++++++
 9 files changed, 216 insertions(+), 12 deletions(-)

-- 
2.34.1

[kvmtool PATCH 01/10] Sync-up header with Linux-6.7-rc3 for KVM RISC-V

[Anup Patel]

We sync-up Linux headers to get latest KVM RISC-V headers having
Zba, Zbs, Zicntr, Zifencei, Zihpm, Smstateen, XVentanaCondOps Zicond,
and SBI DBCN support.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arm/aarch64/include/asm/kvm.h | 32 ++++++++++++++++++++++++++++++++
 include/linux/kvm.h           | 11 +++++++++++
 include/linux/virtio_config.h |  5 +++++
 include/linux/virtio_pci.h    | 11 +++++++++++
 riscv/include/asm/kvm.h       | 12 ++++++++++++
 5 files changed, 71 insertions(+)

diff --git a/arm/aarch64/include/asm/kvm.h b/arm/aarch64/include/asm/kvm.h
index f7ddd73..89d2fc8 100644
--- a/arm/aarch64/include/asm/kvm.h
+++ b/arm/aarch64/include/asm/kvm.h
@@ -505,6 +505,38 @@ struct kvm_smccc_filter {
 #define KVM_HYPERCALL_EXIT_SMC		(1U << 0)
 #define KVM_HYPERCALL_EXIT_16BIT	(1U << 1)
 
+/*
+ * Get feature ID registers userspace writable mask.
+ *
+ * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model
+ * Feature Register 2"):
+ *
+ * "The Feature ID space is defined as the System register space in
+ * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7},
+ * op2=={0-7}."
+ *
+ * This covers all currently known R/O registers that indicate
+ * anything useful feature wise, including the ID registers.
+ *
+ * If we ever need to introduce a new range, it will be described as
+ * such in the range field.
+ */
+#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)		\
+	({								\
+		__u64 __op1 = (op1) & 3;				\
+		__op1 -= (__op1 == 3);					\
+		(__op1 << 6 | ((crm) & 7) << 3 | (op2));		\
+	})
+
+#define KVM_ARM_FEATURE_ID_RANGE	0
+#define KVM_ARM_FEATURE_ID_RANGE_SIZE	(3 * 8 * 8)
+
+struct reg_mask_range {
+	__u64 addr;		/* Pointer to mask array */
+	__u32 range;		/* Requested range */
+	__u32 reserved[13];
+};
+
 #endif
 
 #endif /* __ARM_KVM_H__ */
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 13065dd..211b86d 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -264,6 +264,7 @@ struct kvm_xen_exit {
 #define KVM_EXIT_RISCV_SBI        35
 #define KVM_EXIT_RISCV_CSR        36
 #define KVM_EXIT_NOTIFY           37
+#define KVM_EXIT_LOONGARCH_IOCSR  38
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -336,6 +337,13 @@ struct kvm_run {
 			__u32 len;
 			__u8  is_write;
 		} mmio;
+		/* KVM_EXIT_LOONGARCH_IOCSR */
+		struct {
+			__u64 phys_addr;
+			__u8  data[8];
+			__u32 len;
+			__u8  is_write;
+		} iocsr_io;
 		/* KVM_EXIT_HYPERCALL */
 		struct {
 			__u64 nr;
@@ -1192,6 +1200,7 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_COUNTER_OFFSET 227
 #define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228
 #define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229
+#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
@@ -1362,6 +1371,7 @@ struct kvm_dirty_tlb {
 #define KVM_REG_ARM64		0x6000000000000000ULL
 #define KVM_REG_MIPS		0x7000000000000000ULL
 #define KVM_REG_RISCV		0x8000000000000000ULL
+#define KVM_REG_LOONGARCH	0x9000000000000000ULL
 
 #define KVM_REG_SIZE_SHIFT	52
 #define KVM_REG_SIZE_MASK	0x00f0000000000000ULL
@@ -1562,6 +1572,7 @@ struct kvm_s390_ucas_mapping {
 #define KVM_ARM_MTE_COPY_TAGS	  _IOR(KVMIO,  0xb4, struct kvm_arm_copy_mte_tags)
 /* Available with KVM_CAP_COUNTER_OFFSET */
 #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO,  0xb5, struct kvm_arm_counter_offset)
+#define KVM_ARM_GET_REG_WRITABLE_MASKS _IOR(KVMIO,  0xb6, struct reg_mask_range)
 
 /* ioctl for vm fd */
 #define KVM_CREATE_DEVICE	  _IOWR(KVMIO,  0xe0, struct kvm_create_device)
diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h
index 2c712c6..8881aea 100644
--- a/include/linux/virtio_config.h
+++ b/include/linux/virtio_config.h
@@ -105,6 +105,11 @@
  */
 #define VIRTIO_F_NOTIFICATION_DATA	38
 
+/* This feature indicates that the driver uses the data provided by the device
+ * as a virtqueue identifier in available buffer notifications.
+ */
+#define VIRTIO_F_NOTIF_CONFIG_DATA	39
+
 /*
  * This feature indicates that the driver can reset a queue individually.
  */
diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h
index f703afc..44f4dd2 100644
--- a/include/linux/virtio_pci.h
+++ b/include/linux/virtio_pci.h
@@ -166,6 +166,17 @@ struct virtio_pci_common_cfg {
 	__le32 queue_used_hi;		/* read-write */
 };
 
+/*
+ * Warning: do not use sizeof on this: use offsetofend for
+ * specific fields you need.
+ */
+struct virtio_pci_modern_common_cfg {
+	struct virtio_pci_common_cfg cfg;
+
+	__le16 queue_notify_data;	/* read-write */
+	__le16 queue_reset;		/* read-write */
+};
+
 /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
 struct virtio_pci_cfg_cap {
 	struct virtio_pci_cap cap;
diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h
index 992c5e4..60d3b21 100644
--- a/riscv/include/asm/kvm.h
+++ b/riscv/include/asm/kvm.h
@@ -80,6 +80,7 @@ struct kvm_riscv_csr {
 	unsigned long sip;
 	unsigned long satp;
 	unsigned long scounteren;
+	unsigned long senvcfg;
 };
 
 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
@@ -93,6 +94,11 @@ struct kvm_riscv_aia_csr {
 	unsigned long iprio2h;
 };
 
+/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
+struct kvm_riscv_smstateen_csr {
+	unsigned long sstateen0;
+};
+
 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 struct kvm_riscv_timer {
 	__u64 frequency;
@@ -131,6 +137,8 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_ZICSR,
 	KVM_RISCV_ISA_EXT_ZIFENCEI,
 	KVM_RISCV_ISA_EXT_ZIHPM,
+	KVM_RISCV_ISA_EXT_SMSTATEEN,
+	KVM_RISCV_ISA_EXT_ZICOND,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
@@ -148,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID {
 	KVM_RISCV_SBI_EXT_PMU,
 	KVM_RISCV_SBI_EXT_EXPERIMENTAL,
 	KVM_RISCV_SBI_EXT_VENDOR,
+	KVM_RISCV_SBI_EXT_DBCN,
 	KVM_RISCV_SBI_EXT_MAX,
 };
 
@@ -178,10 +187,13 @@ enum KVM_RISCV_SBI_EXT_ID {
 #define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_GENERAL	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_AIA		(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
+#define KVM_REG_RISCV_CSR_SMSTATEEN	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 #define KVM_REG_RISCV_CSR_REG(name)	\
 		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
 #define KVM_REG_RISCV_CSR_AIA_REG(name)	\
 	(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
+#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)  \
+	(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
 
 /* Timer registers are mapped as type 4 */
 #define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
-- 
2.34.1

[kvmtool PATCH 02/10] riscv: Improve warning in generate_cpu_nodes()

[Anup Patel]

Let's print name of the ISA extension in warning if generate_cpu_nodes()
drops the ISA extension from generated ISA string due to lack of space.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 9af71b5..b45f731 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -108,7 +108,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
 			}
 
 			if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) {
-				pr_warning("Insufficient space to append ISA exension\n");
+				pr_warning("Insufficient space to append ISA exension %s\n",
+					   isa_info_arr[i].name);
 				break;
 			}
 			pos += snprintf(cpu_isa + pos, CPU_ISA_MAX_LEN, "_%s",
-- 
2.34.1

[kvmtool PATCH 03/10] riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size

[Anup Patel]

Currently, the CPU_ISA_MAX_LEN is a fixed value so we will easily
run out of space when all possible ISA extensions supported by
KVM RISC-V are available.

Instead of above, let us make CPU_ISA_MAX_LEN depend upon the
isa_info_arr[] array size so that CPU_ISA_MAX_LEN automatically
adapts to growing number of ISA extensions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index b45f731..230d1f8 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -44,7 +44,6 @@ static void dump_fdt(const char *dtb_file, void *fdt)
 }
 
 #define CPU_NAME_MAX_LEN 15
-#define CPU_ISA_MAX_LEN 128
 static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
 {
 	int cpu, pos, i, index, valid_isa_len;
@@ -60,6 +59,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
 
 	for (cpu = 0; cpu < kvm->nrcpus; ++cpu) {
 		char cpu_name[CPU_NAME_MAX_LEN];
+#define CPU_ISA_MAX_LEN (ARRAY_SIZE(isa_info_arr) * 16)
 		char cpu_isa[CPU_ISA_MAX_LEN];
 		struct kvm_cpu *vcpu = kvm->cpus[cpu];
 		struct kvm_one_reg reg;
-- 
2.34.1

[kvmtool PATCH 04/10] riscv: Add Zba and Zbs extension support

[Anup Patel]

When the Zba and Zbs extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 230d1f8..cfe4678 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -21,7 +21,9 @@ struct isa_ext_info isa_info_arr[] = {
 	{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
 	{"svnapot", KVM_RISCV_ISA_EXT_SVNAPOT},
 	{"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
+	{"zba", KVM_RISCV_ISA_EXT_ZBA},
 	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
+	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 863baea..978037a 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -40,9 +40,15 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-svpbmt",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SVPBMT],	\
 		    "Disable Svpbmt Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zba",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBA],	\
+		    "Disable Zba Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zbb",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBB],	\
 		    "Disable Zbb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbs",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
+		    "Disable Zbs Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zicbom",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM],	\
 		    "Disable Zicbom Extension"),			\
-- 
2.34.1

[kvmtool PATCH 05/10] riscv: Add Zicntr and Zihpm extension support

[Anup Patel]

When the Zicntr and Zihpm extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index cfe4678..19786af 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -26,7 +26,9 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
+	{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
+	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
 };
 
 static void dump_fdt(const char *dtb_file, void *fdt)
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 978037a..af5c4b8 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -55,9 +55,15 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zicboz",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOZ],	\
 		    "Disable Zicboz Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zicntr",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR],	\
+		    "Disable Zicntr Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zihintpause",			\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\
 		    "Disable Zihintpause Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zihpm",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHPM],	\
+		    "Disable Zihpm Extension"),				\
 	OPT_BOOLEAN('\0', "disable-sbi-legacy",				\
 		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01],	\
 		    "Disable SBI Legacy Extensions"),			\
-- 
2.34.1

[kvmtool PATCH 06/10] riscv: Add Zicsr and Zifencei extension support

[Anup Patel]

When the Zicsr and Zifencei extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 19786af..a4d54eb 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -27,6 +27,8 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
 	{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
+	{"zicsr", KVM_RISCV_ISA_EXT_ZICSR},
+	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
 	{"zihpm", KVM_RISCV_ISA_EXT_ZIHPM},
 };
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index af5c4b8..c524771 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -58,6 +58,12 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zicntr",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR],	\
 		    "Disable Zicntr Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zicsr",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICSR],	\
+		    "Disable Zicsr Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zifencei",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIFENCEI],	\
+		    "Disable Zifencei Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zihintpause",			\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\
 		    "Disable Zihintpause Extension"),			\
-- 
2.34.1

[kvmtool PATCH 07/10] riscv: Add Smstateen extension support

[Anup Patel]

When the Smstateen extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 1 +
 riscv/include/kvm/kvm-config-arch.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index a4d54eb..0fe0f0b 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -16,6 +16,7 @@ struct isa_ext_info {
 
 struct isa_ext_info isa_info_arr[] = {
 	/* sorted alphabetically */
+	{"smstateen", KVM_RISCV_ISA_EXT_SMSTATEEN},
 	{"ssaia", KVM_RISCV_ISA_EXT_SSAIA},
 	{"sstc", KVM_RISCV_ISA_EXT_SSTC},
 	{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index c524771..49eb3e6 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -25,6 +25,9 @@ struct kvm_config_arch {
 	OPT_U64('\0', "custom-mimpid",					\
 		&(cfg)->custom_mimpid,					\
 		"Show custom mimpid to Guest VCPU"),			\
+	OPT_BOOLEAN('\0', "disable-smstateen",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SMSTATEEN],	\
+		    "Disable Smstateen Extension"),			\
 	OPT_BOOLEAN('\0', "disable-ssaia",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSAIA],	\
 		    "Disable Ssaia Extension"),				\
-- 
2.34.1

[kvmtool PATCH 08/10] riscv: Add Zicond extension support

[Anup Patel]

When the Zicond extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 1 +
 riscv/include/kvm/kvm-config-arch.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 0fe0f0b..1124fa1 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -28,6 +28,7 @@ struct isa_ext_info isa_info_arr[] = {
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
 	{"zicntr", KVM_RISCV_ISA_EXT_ZICNTR},
+	{"zicond", KVM_RISCV_ISA_EXT_ZICOND},
 	{"zicsr", KVM_RISCV_ISA_EXT_ZICSR},
 	{"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 49eb3e6..48d0770 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -61,6 +61,9 @@ struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-zicntr",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR],	\
 		    "Disable Zicntr Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zicond",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICOND],	\
+		    "Disable Zicond Extension"),			\
 	OPT_BOOLEAN('\0', "disable-zicsr",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICSR],	\
 		    "Disable Zicsr Extension"),				\
-- 
2.34.1

[kvmtool PATCH 09/10] riscv: Set mmu-type DT property based on satp_mode ONE_REG interface

[Anup Patel]

Instead of hard-coding the mmu-type DT property, we should set it
based on satp_mode ONE_REG interface.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c | 44 +++++++++++++++++++++++++++++++++++++-------
 1 file changed, 37 insertions(+), 7 deletions(-)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 1124fa1..8485acf 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -57,7 +57,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
 	int cpu, pos, i, index, valid_isa_len;
 	const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG";
 	int arr_sz = ARRAY_SIZE(isa_info_arr);
-	unsigned long cbom_blksz = 0, cboz_blksz = 0;
+	unsigned long cbom_blksz = 0, cboz_blksz = 0, satp_mode = 0;
 
 	_FDT(fdt_begin_node(fdt, "cpus"));
 	_FDT(fdt_property_cell(fdt, "#address-cells", 0x1));
@@ -125,15 +125,45 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
 		}
 		cpu_isa[pos] = '\0';
 
+		reg.id = RISCV_CONFIG_REG(satp_mode);
+		reg.addr = (unsigned long)&satp_mode;
+		if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, &reg) < 0)
+			satp_mode = (vcpu->riscv_xlen == 64) ? 8 : 1;
+
 		_FDT(fdt_begin_node(fdt, cpu_name));
 		_FDT(fdt_property_string(fdt, "device_type", "cpu"));
 		_FDT(fdt_property_string(fdt, "compatible", "riscv"));
-		if (vcpu->riscv_xlen == 64)
-			_FDT(fdt_property_string(fdt, "mmu-type",
-						 "riscv,sv48"));
-		else
-			_FDT(fdt_property_string(fdt, "mmu-type",
-						 "riscv,sv32"));
+		if (vcpu->riscv_xlen == 64) {
+			switch (satp_mode) {
+			case 10:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,sv57"));
+				break;
+			case 9:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,sv48"));
+				break;
+			case 8:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,sv39"));
+				break;
+			default:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,none"));
+				break;
+			}
+		} else {
+			switch (satp_mode) {
+			case 1:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,sv32"));
+				break;
+			default:
+				_FDT(fdt_property_string(fdt, "mmu-type",
+							 "riscv,none"));
+				break;
+			}
+		}
 		_FDT(fdt_property_string(fdt, "riscv,isa", cpu_isa));
 		if (cbom_blksz)
 			_FDT(fdt_property_cell(fdt, "riscv,cbom-block-size", cbom_blksz));
-- 
2.34.1

[kvmtool PATCH 10/10] riscv: Handle SBI DBCN calls from Guest/VM

[Anup Patel]

The new SBI DBCN functions are forwarded by in-kernel KVM RISC-V module
to user-space so let us handle these calls in kvm_cpu_riscv_sbi() function.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/include/kvm/kvm-config-arch.h |  5 ++-
 riscv/include/kvm/sbi.h             | 14 ++++++-
 riscv/kvm-cpu.c                     | 57 +++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 3 deletions(-)

diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 48d0770..d2fc2d4 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -102,6 +102,9 @@ struct kvm_config_arch {
 		    "Disable SBI Experimental Extensions"),		\
 	OPT_BOOLEAN('\0', "disable-sbi-vendor",				\
 		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_VENDOR],	\
-		    "Disable SBI Vendor Extensions"),
+		    "Disable SBI Vendor Extensions"),			\
+	OPT_BOOLEAN('\0', "disable-sbi-dbcn",				\
+		    &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN],	\
+		    "Disable SBI DBCN Extension"),
 
 #endif /* KVM__KVM_CONFIG_ARCH_H */
diff --git a/riscv/include/kvm/sbi.h b/riscv/include/kvm/sbi.h
index f4b4182..a0f2c70 100644
--- a/riscv/include/kvm/sbi.h
+++ b/riscv/include/kvm/sbi.h
@@ -20,6 +20,7 @@ enum sbi_ext_id {
 	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
 	SBI_EXT_0_1_SHUTDOWN = 0x8,
 	SBI_EXT_BASE = 0x10,
+	SBI_EXT_DBCN = 0x4442434E,
 };
 
 enum sbi_ext_base_fid {
@@ -32,6 +33,12 @@ enum sbi_ext_base_fid {
 	SBI_BASE_GET_MIMPID,
 };
 
+enum sbi_ext_dbcn_fid {
+	SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+	SBI_EXT_DBCN_CONSOLE_READ = 1,
+	SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_OFFSET	24
 #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
@@ -41,8 +48,11 @@ enum sbi_ext_base_fid {
 #define SBI_SUCCESS		0
 #define SBI_ERR_FAILURE		-1
 #define SBI_ERR_NOT_SUPPORTED	-2
-#define SBI_ERR_INVALID_PARAM   -3
+#define SBI_ERR_INVALID_PARAM	-3
 #define SBI_ERR_DENIED		-4
-#define SBI_ERR_INVALID_ADDRESS -5
+#define SBI_ERR_INVALID_ADDRESS	-5
+#define SBI_ERR_ALREADY_AVAILABLE -6
+#define SBI_ERR_ALREADY_STARTED -7
+#define SBI_ERR_ALREADY_STOPPED -8
 
 #endif
diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c
index 540baec..c4e83c4 100644
--- a/riscv/kvm-cpu.c
+++ b/riscv/kvm-cpu.c
@@ -105,6 +105,17 @@ struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id)
 			die("KVM_SET_ONE_REG failed (sbi_ext %d)", i);
 	}
 
+	/* Force enable SBI debug console if not disabled from command line */
+	if (!kvm->cfg.arch.sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN]) {
+		id = 1;
+		reg.id = RISCV_SBI_EXT_REG(KVM_REG_RISCV_SBI_SINGLE,
+					   KVM_RISCV_SBI_EXT_DBCN);
+		reg.addr = (unsigned long)&id;
+		if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, &reg) < 0)
+			pr_warning("KVM_SET_ONE_REG failed (sbi_ext %d)",
+				   KVM_RISCV_SBI_EXT_DBCN);
+	}
+
 	/* Populate the vcpu structure. */
 	vcpu->kvm		= kvm;
 	vcpu->cpu_id		= cpu_id;
@@ -128,7 +139,9 @@ void kvm_cpu__delete(struct kvm_cpu *vcpu)
 static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
 {
 	char ch;
+	u64 addr;
 	bool ret = true;
+	char *str_start, *str_end;
 	int dfd = kvm_cpu__get_debug_fd();
 
 	switch (vcpu->kvm_run->riscv_sbi.extension_id) {
@@ -144,6 +157,50 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu)
 		else
 			vcpu->kvm_run->riscv_sbi.ret[0] = SBI_ERR_FAILURE;
 		break;
+	case SBI_EXT_DBCN:
+		switch (vcpu->kvm_run->riscv_sbi.function_id) {
+		case SBI_EXT_DBCN_CONSOLE_WRITE:
+		case SBI_EXT_DBCN_CONSOLE_READ:
+			addr = vcpu->kvm_run->riscv_sbi.args[1];
+#if __riscv_xlen == 32
+			addr |= (u64)vcpu->kvm_run->riscv_sbi.args[2] << 32;
+#endif
+			if (!vcpu->kvm_run->riscv_sbi.args[0])
+				break;
+			str_start = guest_flat_to_host(vcpu->kvm, addr);
+			addr += vcpu->kvm_run->riscv_sbi.args[0] - 1;
+			str_end = guest_flat_to_host(vcpu->kvm, addr);
+			if (!str_start || !str_end) {
+				vcpu->kvm_run->riscv_sbi.ret[0] =
+						SBI_ERR_INVALID_PARAM;
+				break;
+			}
+			vcpu->kvm_run->riscv_sbi.ret[1] = 0;
+			while (str_start <= str_end) {
+				if (vcpu->kvm_run->riscv_sbi.function_id ==
+				    SBI_EXT_DBCN_CONSOLE_WRITE) {
+					term_putc(str_start, 1, 0);
+				} else {
+					if (!term_readable(0))
+						break;
+					*str_start = term_getc(vcpu->kvm, 0);
+				}
+				vcpu->kvm_run->riscv_sbi.ret[1]++;
+				str_start++;
+			}
+			break;
+		case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+			ch = vcpu->kvm_run->riscv_sbi.args[0];
+			term_putc(&ch, 1, 0);
+			vcpu->kvm_run->riscv_sbi.ret[0] = 0;
+			vcpu->kvm_run->riscv_sbi.ret[1] = 0;
+			break;
+		default:
+			vcpu->kvm_run->riscv_sbi.ret[0] =
+						SBI_ERR_NOT_SUPPORTED;
+			break;
+		}
+		break;
 	default:
 		dprintf(dfd, "Unhandled SBI call\n");
 		dprintf(dfd, "extension_id=0x%lx function_id=0x%lx\n",
-- 
2.34.1

Re: [kvmtool PATCH 00/10] SBI debug console and few ISA extensions

[Will Deacon]

On Tue, 28 Nov 2023 20:26:18 +0530, Anup Patel wrote:
> This series adds support for:
> 1) ISA extensions: Zba, Zbs, Zicntr, Zihpm, Zicsr, Zifencei, Zicond,
>    and Smstateen
> 2) SBI debug console (DBCN) extension
> 
> These patches can also be found in the riscv_zbx_zicntr_smstateen_condops_v1
> branch at: https://github.com/avpatel/kvmtool.git
> 
> [...]

Applied to kvmtool (master), thanks!

(I updated the headers to 6.7 separately)

[02/10] riscv: Improve warning in generate_cpu_nodes()
        https://git.kernel.org/will/kvmtool/c/fcb076756ab2
[03/10] riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size
        https://git.kernel.org/will/kvmtool/c/7887b3989ac2
[04/10] riscv: Add Zba and Zbs extension support
        https://git.kernel.org/will/kvmtool/c/6331850d6bc0
[05/10] riscv: Add Zicntr and Zihpm extension support
        https://git.kernel.org/will/kvmtool/c/667685691c5d
[06/10] riscv: Add Zicsr and Zifencei extension support
        https://git.kernel.org/will/kvmtool/c/3436684940bc
[07/10] riscv: Add Smstateen extension support
        https://git.kernel.org/will/kvmtool/c/8d02d5a895c3
[08/10] riscv: Add Zicond extension support
        https://git.kernel.org/will/kvmtool/c/8cd71ca57fb0
[09/10] riscv: Set mmu-type DT property based on satp_mode ONE_REG interface
        https://git.kernel.org/will/kvmtool/c/ef89838e3760
[10/10] riscv: Handle SBI DBCN calls from Guest/VM
        https://git.kernel.org/will/kvmtool/c/4ddaa4249e0c

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

Re: [kvmtool PATCH 00/10] SBI debug console and few ISA extensions

[Anup Patel]

On Fri, Feb 9, 2024 at 9:26 PM Will Deacon <will@kernel.org> wrote:
>
> On Tue, 28 Nov 2023 20:26:18 +0530, Anup Patel wrote:
> > This series adds support for:
> > 1) ISA extensions: Zba, Zbs, Zicntr, Zihpm, Zicsr, Zifencei, Zicond,
> >    and Smstateen
> > 2) SBI debug console (DBCN) extension
> >
> > These patches can also be found in the riscv_zbx_zicntr_smstateen_condops_v1
> > branch at: https://github.com/avpatel/kvmtool.git
> >
> > [...]
>
> Applied to kvmtool (master), thanks!
>
> (I updated the headers to 6.7 separately)

Thanks Will.

>
> [02/10] riscv: Improve warning in generate_cpu_nodes()
>         https://git.kernel.org/will/kvmtool/c/fcb076756ab2
> [03/10] riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size
>         https://git.kernel.org/will/kvmtool/c/7887b3989ac2
> [04/10] riscv: Add Zba and Zbs extension support
>         https://git.kernel.org/will/kvmtool/c/6331850d6bc0
> [05/10] riscv: Add Zicntr and Zihpm extension support
>         https://git.kernel.org/will/kvmtool/c/667685691c5d
> [06/10] riscv: Add Zicsr and Zifencei extension support
>         https://git.kernel.org/will/kvmtool/c/3436684940bc
> [07/10] riscv: Add Smstateen extension support
>         https://git.kernel.org/will/kvmtool/c/8d02d5a895c3
> [08/10] riscv: Add Zicond extension support
>         https://git.kernel.org/will/kvmtool/c/8cd71ca57fb0
> [09/10] riscv: Set mmu-type DT property based on satp_mode ONE_REG interface
>         https://git.kernel.org/will/kvmtool/c/ef89838e3760
> [10/10] riscv: Handle SBI DBCN calls from Guest/VM
>         https://git.kernel.org/will/kvmtool/c/4ddaa4249e0c
>
> Cheers,
> --
> Will
>
> https://fixes.arm64.dev
> https://next.arm64.dev
> https://will.arm64.dev

Regards,
Anup