[PATCH v2 0/5] Add power-controller and gpu for RK3128

[PATCH v2 0/5] Add power-controller and gpu for RK3128

[Alex Bee]

The first patch in this series fixes the pm-domain driver and adds
power-domains which are currently missing. This touches the ABI which is
not and was never used until now. Not all of them are used yet, but when
the power-controller is added to the DT in patch 2 the ABI should not
be changed again.
Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
node and the respective operating points to SoC DT and finally enabling it
for XPI-3128 board.

Note: DT patches are based on maintainer's repo.

Alex Bee (5):
  pmdomain: rockchip: Add missing powerdomains for RK3128
  ARM: dts: rockchip: Add power-controller for RK3128
  dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
  ARM: dts: rockchip: Add GPU node for RK3128
  ARM: dts: rockchip: Enable GPU for XPI-3128

 .../bindings/gpu/arm,mali-utgard.yaml         |   1 +
 .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts |   5 +
 arch/arm/boot/dts/rockchip/rk3128.dtsi        | 145 ++++++++++++++++++
 drivers/pmdomain/rockchip/pm-domains.c        |  13 +-
 include/dt-bindings/power/rk3128-power.h      |   3 +
 5 files changed, 162 insertions(+), 5 deletions(-)


base-commit: fd610e604837936440ef7c64ab6998b004631647
-- 
2.43.0

[PATCH v2 0/5] Add power-controller and gpu for RK3128

[Alex Bee]

The first patch in this series fixes the pm-domain driver and adds
power-domains which are currently missing. This touches the ABI which is
not and was never used until now. Not all of them are used yet, but when
the power-controller is added to the DT in patch 2 the ABI should not
be changed again.
Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
node and the respective operating points to SoC DT and finally enabling it
for XPI-3128 board.

Note: DT patches are based on maintainer's repo.

Alex Bee (5):
  pmdomain: rockchip: Add missing powerdomains for RK3128
  ARM: dts: rockchip: Add power-controller for RK3128
  dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
  ARM: dts: rockchip: Add GPU node for RK3128
  ARM: dts: rockchip: Enable GPU for XPI-3128

 .../bindings/gpu/arm,mali-utgard.yaml         |   1 +
 .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts |   5 +
 arch/arm/boot/dts/rockchip/rk3128.dtsi        | 145 ++++++++++++++++++
 drivers/pmdomain/rockchip/pm-domains.c        |  13 +-
 include/dt-bindings/power/rk3128-power.h      |   3 +
 5 files changed, 162 insertions(+), 5 deletions(-)


base-commit: fd610e604837936440ef7c64ab6998b004631647
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 0/5] Add power-controller and gpu for RK3128

[Alex Bee]

The first patch in this series fixes the pm-domain driver and adds
power-domains which are currently missing. This touches the ABI which is
not and was never used until now. Not all of them are used yet, but when
the power-controller is added to the DT in patch 2 the ABI should not
be changed again.
Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
node and the respective operating points to SoC DT and finally enabling it
for XPI-3128 board.

Note: DT patches are based on maintainer's repo.

Alex Bee (5):
  pmdomain: rockchip: Add missing powerdomains for RK3128
  ARM: dts: rockchip: Add power-controller for RK3128
  dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
  ARM: dts: rockchip: Add GPU node for RK3128
  ARM: dts: rockchip: Enable GPU for XPI-3128

 .../bindings/gpu/arm,mali-utgard.yaml         |   1 +
 .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts |   5 +
 arch/arm/boot/dts/rockchip/rk3128.dtsi        | 145 ++++++++++++++++++
 drivers/pmdomain/rockchip/pm-domains.c        |  13 +-
 include/dt-bindings/power/rk3128-power.h      |   3 +
 5 files changed, 162 insertions(+), 5 deletions(-)


base-commit: fd610e604837936440ef7c64ab6998b004631647
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 0/5] Add power-controller and gpu for RK3128

[Alex Bee]

The first patch in this series fixes the pm-domain driver and adds
power-domains which are currently missing. This touches the ABI which is
not and was never used until now. Not all of them are used yet, but when
the power-controller is added to the DT in patch 2 the ABI should not
be changed again.
Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
node and the respective operating points to SoC DT and finally enabling it
for XPI-3128 board.

Note: DT patches are based on maintainer's repo.

Alex Bee (5):
  pmdomain: rockchip: Add missing powerdomains for RK3128
  ARM: dts: rockchip: Add power-controller for RK3128
  dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
  ARM: dts: rockchip: Add GPU node for RK3128
  ARM: dts: rockchip: Enable GPU for XPI-3128

 .../bindings/gpu/arm,mali-utgard.yaml         |   1 +
 .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts |   5 +
 arch/arm/boot/dts/rockchip/rk3128.dtsi        | 145 ++++++++++++++++++
 drivers/pmdomain/rockchip/pm-domains.c        |  13 +-
 include/dt-bindings/power/rk3128-power.h      |   3 +
 5 files changed, 162 insertions(+), 5 deletions(-)


base-commit: fd610e604837936440ef7c64ab6998b004631647
-- 
2.43.0

[PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Alex Bee]

For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
missing.
Add them.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
 include/dt-bindings/power/rk3128-power.h |  3 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 9b76b62869d0..62ba4129f6bb 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -998,11 +998,14 @@ static const struct rockchip_domain_info rk3066_pm_domains[] = {
 };
 
 static const struct rockchip_domain_info rk3128_pm_domains[] = {
-	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",  BIT(0), BIT(0), BIT(4), false),
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",  0,      0,      BIT(6), true),
-	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",   BIT(3), BIT(3), BIT(2), false),
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
-	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",   BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",   BIT(0), BIT(0), BIT(4), false),
+	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",   0,      0,      BIT(6), true),
+	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",    BIT(3), BIT(3), BIT(2), false),
+	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video",  BIT(2), BIT(2), BIT(1), false),
+	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",    BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_PERI]	= DOMAIN_RK3288("peri",   0,      0,      BIT(0), false),
+	[RK3128_PD_SYS]		= DOMAIN_RK3288("sys",    0,      0,      BIT(5), true),
+	[RK3128_PD_CRYPTO]	= DOMAIN_RK3288("crypto", 0,      0,      BIT(7), false),
 };
 
 static const struct rockchip_domain_info rk3188_pm_domains[] = {
diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h
index c051dc3108db..68af6c68c272 100644
--- a/include/dt-bindings/power/rk3128-power.h
+++ b/include/dt-bindings/power/rk3128-power.h
@@ -10,5 +10,8 @@
 #define RK3128_PD_VIDEO		2
 #define RK3128_PD_GPU		3
 #define RK3128_PD_MSCH		4
+#define RK3128_PD_PERI		5
+#define RK3128_PD_SYS		6
+#define RK3128_PD_CRYPTO	7
 
 #endif
-- 
2.43.0

[PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Alex Bee]

For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
missing.
Add them.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
 include/dt-bindings/power/rk3128-power.h |  3 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 9b76b62869d0..62ba4129f6bb 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -998,11 +998,14 @@ static const struct rockchip_domain_info rk3066_pm_domains[] = {
 };
 
 static const struct rockchip_domain_info rk3128_pm_domains[] = {
-	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",  BIT(0), BIT(0), BIT(4), false),
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",  0,      0,      BIT(6), true),
-	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",   BIT(3), BIT(3), BIT(2), false),
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
-	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",   BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",   BIT(0), BIT(0), BIT(4), false),
+	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",   0,      0,      BIT(6), true),
+	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",    BIT(3), BIT(3), BIT(2), false),
+	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video",  BIT(2), BIT(2), BIT(1), false),
+	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",    BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_PERI]	= DOMAIN_RK3288("peri",   0,      0,      BIT(0), false),
+	[RK3128_PD_SYS]		= DOMAIN_RK3288("sys",    0,      0,      BIT(5), true),
+	[RK3128_PD_CRYPTO]	= DOMAIN_RK3288("crypto", 0,      0,      BIT(7), false),
 };
 
 static const struct rockchip_domain_info rk3188_pm_domains[] = {
diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h
index c051dc3108db..68af6c68c272 100644
--- a/include/dt-bindings/power/rk3128-power.h
+++ b/include/dt-bindings/power/rk3128-power.h
@@ -10,5 +10,8 @@
 #define RK3128_PD_VIDEO		2
 #define RK3128_PD_GPU		3
 #define RK3128_PD_MSCH		4
+#define RK3128_PD_PERI		5
+#define RK3128_PD_SYS		6
+#define RK3128_PD_CRYPTO	7
 
 #endif
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Alex Bee]

For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
missing.
Add them.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
 include/dt-bindings/power/rk3128-power.h |  3 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 9b76b62869d0..62ba4129f6bb 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -998,11 +998,14 @@ static const struct rockchip_domain_info rk3066_pm_domains[] = {
 };
 
 static const struct rockchip_domain_info rk3128_pm_domains[] = {
-	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",  BIT(0), BIT(0), BIT(4), false),
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",  0,      0,      BIT(6), true),
-	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",   BIT(3), BIT(3), BIT(2), false),
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
-	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",   BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",   BIT(0), BIT(0), BIT(4), false),
+	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",   0,      0,      BIT(6), true),
+	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",    BIT(3), BIT(3), BIT(2), false),
+	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video",  BIT(2), BIT(2), BIT(1), false),
+	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",    BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_PERI]	= DOMAIN_RK3288("peri",   0,      0,      BIT(0), false),
+	[RK3128_PD_SYS]		= DOMAIN_RK3288("sys",    0,      0,      BIT(5), true),
+	[RK3128_PD_CRYPTO]	= DOMAIN_RK3288("crypto", 0,      0,      BIT(7), false),
 };
 
 static const struct rockchip_domain_info rk3188_pm_domains[] = {
diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h
index c051dc3108db..68af6c68c272 100644
--- a/include/dt-bindings/power/rk3128-power.h
+++ b/include/dt-bindings/power/rk3128-power.h
@@ -10,5 +10,8 @@
 #define RK3128_PD_VIDEO		2
 #define RK3128_PD_GPU		3
 #define RK3128_PD_MSCH		4
+#define RK3128_PD_PERI		5
+#define RK3128_PD_SYS		6
+#define RK3128_PD_CRYPTO	7
 
 #endif
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Alex Bee]

For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
missing.
Add them.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
 include/dt-bindings/power/rk3128-power.h |  3 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 9b76b62869d0..62ba4129f6bb 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -998,11 +998,14 @@ static const struct rockchip_domain_info rk3066_pm_domains[] = {
 };
 
 static const struct rockchip_domain_info rk3128_pm_domains[] = {
-	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",  BIT(0), BIT(0), BIT(4), false),
-	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",  0,      0,      BIT(6), true),
-	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",   BIT(3), BIT(3), BIT(2), false),
-	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
-	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",   BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_CORE]	= DOMAIN_RK3288("core",   BIT(0), BIT(0), BIT(4), false),
+	[RK3128_PD_MSCH]	= DOMAIN_RK3288("msch",   0,      0,      BIT(6), true),
+	[RK3128_PD_VIO]		= DOMAIN_RK3288("vio",    BIT(3), BIT(3), BIT(2), false),
+	[RK3128_PD_VIDEO]	= DOMAIN_RK3288("video",  BIT(2), BIT(2), BIT(1), false),
+	[RK3128_PD_GPU]		= DOMAIN_RK3288("gpu",    BIT(1), BIT(1), BIT(3), false),
+	[RK3128_PD_PERI]	= DOMAIN_RK3288("peri",   0,      0,      BIT(0), false),
+	[RK3128_PD_SYS]		= DOMAIN_RK3288("sys",    0,      0,      BIT(5), true),
+	[RK3128_PD_CRYPTO]	= DOMAIN_RK3288("crypto", 0,      0,      BIT(7), false),
 };
 
 static const struct rockchip_domain_info rk3188_pm_domains[] = {
diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h
index c051dc3108db..68af6c68c272 100644
--- a/include/dt-bindings/power/rk3128-power.h
+++ b/include/dt-bindings/power/rk3128-power.h
@@ -10,5 +10,8 @@
 #define RK3128_PD_VIDEO		2
 #define RK3128_PD_GPU		3
 #define RK3128_PD_MSCH		4
+#define RK3128_PD_PERI		5
+#define RK3128_PD_SYS		6
+#define RK3128_PD_CRYPTO	7
 
 #endif
-- 
2.43.0

[PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
 
 / {
 	compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
+
+		power: power-controller {
+			compatible = "rockchip,rk3128-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			power-domain@RK3128_PD_VIO {
+				reg = <RK3128_PD_VIO>;
+				clocks = <&cru ACLK_CIF>,
+					 <&cru HCLK_CIF>,
+					 <&cru DCLK_EBC>,
+					 <&cru HCLK_EBC>,
+					 <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>,
+					 <&cru ACLK_LCDC0>,
+					 <&cru HCLK_LCDC0>,
+					 <&cru PCLK_MIPI>,
+					 <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>,
+					 <&cru ACLK_VIO0>,
+					 <&cru ACLK_VIO1>,
+					 <&cru HCLK_VIO>,
+					 <&cru HCLK_VIO_H2P>,
+					 <&cru DCLK_VOP>,
+					 <&cru SCLK_VOP>;
+				pm_qos = <&qos_ebc>,
+					 <&qos_iep>,
+					 <&qos_lcdc>,
+					 <&qos_rga>,
+					 <&qos_vip>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_VIDEO {
+				reg = <RK3128_PD_VIDEO>;
+				clocks = <&cru ACLK_VDPU>,
+					 <&cru HCLK_VDPU>,
+					 <&cru ACLK_VEPU>,
+					 <&cru HCLK_VEPU>,
+					 <&cru SCLK_HEVC_CORE>;
+				pm_qos = <&qos_vpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_GPU {
+				reg = <RK3128_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_CRYPTO {
+				reg = <RK3128_PD_CRYPTO>;
+				clocks = <&cru HCLK_CRYPTO>,
+					 <&cru SCLK_CRYPTO>;
+				pm_qos = <&qos_crypto>;
+				#power-domain-cells = <0>;
+			};
+		};
+	};
+
+	qos_crypto: qos@10128080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x10128080 0x20>;
+	};
+
+	qos_gpu: qos@1012d000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012d000 0x20>;
+	};
+
+	qos_vpu: qos@1012e000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012e000 0x20>;
+	};
+
+	qos_rga: qos@1012f000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f000 0x20>;
+	};
+
+	qos_ebc: qos@1012f080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f080 0x20>;
+	};
+
+	qos_iep: qos@1012f100 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f100 0x20>;
+	};
+
+	qos_lcdc: qos@1012f180 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f180 0x20>;
+	};
+
+	qos_vip: qos@1012f200 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f200 0x20>;
 	};
 
 	gic: interrupt-controller@10139000 {
-- 
2.43.0

[PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
 
 / {
 	compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
+
+		power: power-controller {
+			compatible = "rockchip,rk3128-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			power-domain@RK3128_PD_VIO {
+				reg = <RK3128_PD_VIO>;
+				clocks = <&cru ACLK_CIF>,
+					 <&cru HCLK_CIF>,
+					 <&cru DCLK_EBC>,
+					 <&cru HCLK_EBC>,
+					 <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>,
+					 <&cru ACLK_LCDC0>,
+					 <&cru HCLK_LCDC0>,
+					 <&cru PCLK_MIPI>,
+					 <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>,
+					 <&cru ACLK_VIO0>,
+					 <&cru ACLK_VIO1>,
+					 <&cru HCLK_VIO>,
+					 <&cru HCLK_VIO_H2P>,
+					 <&cru DCLK_VOP>,
+					 <&cru SCLK_VOP>;
+				pm_qos = <&qos_ebc>,
+					 <&qos_iep>,
+					 <&qos_lcdc>,
+					 <&qos_rga>,
+					 <&qos_vip>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_VIDEO {
+				reg = <RK3128_PD_VIDEO>;
+				clocks = <&cru ACLK_VDPU>,
+					 <&cru HCLK_VDPU>,
+					 <&cru ACLK_VEPU>,
+					 <&cru HCLK_VEPU>,
+					 <&cru SCLK_HEVC_CORE>;
+				pm_qos = <&qos_vpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_GPU {
+				reg = <RK3128_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_CRYPTO {
+				reg = <RK3128_PD_CRYPTO>;
+				clocks = <&cru HCLK_CRYPTO>,
+					 <&cru SCLK_CRYPTO>;
+				pm_qos = <&qos_crypto>;
+				#power-domain-cells = <0>;
+			};
+		};
+	};
+
+	qos_crypto: qos@10128080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x10128080 0x20>;
+	};
+
+	qos_gpu: qos@1012d000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012d000 0x20>;
+	};
+
+	qos_vpu: qos@1012e000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012e000 0x20>;
+	};
+
+	qos_rga: qos@1012f000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f000 0x20>;
+	};
+
+	qos_ebc: qos@1012f080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f080 0x20>;
+	};
+
+	qos_iep: qos@1012f100 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f100 0x20>;
+	};
+
+	qos_lcdc: qos@1012f180 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f180 0x20>;
+	};
+
+	qos_vip: qos@1012f200 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f200 0x20>;
 	};
 
 	gic: interrupt-controller@10139000 {
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
 
 / {
 	compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
+
+		power: power-controller {
+			compatible = "rockchip,rk3128-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			power-domain@RK3128_PD_VIO {
+				reg = <RK3128_PD_VIO>;
+				clocks = <&cru ACLK_CIF>,
+					 <&cru HCLK_CIF>,
+					 <&cru DCLK_EBC>,
+					 <&cru HCLK_EBC>,
+					 <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>,
+					 <&cru ACLK_LCDC0>,
+					 <&cru HCLK_LCDC0>,
+					 <&cru PCLK_MIPI>,
+					 <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>,
+					 <&cru ACLK_VIO0>,
+					 <&cru ACLK_VIO1>,
+					 <&cru HCLK_VIO>,
+					 <&cru HCLK_VIO_H2P>,
+					 <&cru DCLK_VOP>,
+					 <&cru SCLK_VOP>;
+				pm_qos = <&qos_ebc>,
+					 <&qos_iep>,
+					 <&qos_lcdc>,
+					 <&qos_rga>,
+					 <&qos_vip>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_VIDEO {
+				reg = <RK3128_PD_VIDEO>;
+				clocks = <&cru ACLK_VDPU>,
+					 <&cru HCLK_VDPU>,
+					 <&cru ACLK_VEPU>,
+					 <&cru HCLK_VEPU>,
+					 <&cru SCLK_HEVC_CORE>;
+				pm_qos = <&qos_vpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_GPU {
+				reg = <RK3128_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_CRYPTO {
+				reg = <RK3128_PD_CRYPTO>;
+				clocks = <&cru HCLK_CRYPTO>,
+					 <&cru SCLK_CRYPTO>;
+				pm_qos = <&qos_crypto>;
+				#power-domain-cells = <0>;
+			};
+		};
+	};
+
+	qos_crypto: qos@10128080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x10128080 0x20>;
+	};
+
+	qos_gpu: qos@1012d000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012d000 0x20>;
+	};
+
+	qos_vpu: qos@1012e000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012e000 0x20>;
+	};
+
+	qos_rga: qos@1012f000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f000 0x20>;
+	};
+
+	qos_ebc: qos@1012f080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f080 0x20>;
+	};
+
+	qos_iep: qos@1012f100 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f100 0x20>;
+	};
+
+	qos_lcdc: qos@1012f180 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f180 0x20>;
+	};
+
+	qos_vip: qos@1012f200 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f200 0x20>;
 	};
 
 	gic: interrupt-controller@10139000 {
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
 
 / {
 	compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
+
+		power: power-controller {
+			compatible = "rockchip,rk3128-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			power-domain@RK3128_PD_VIO {
+				reg = <RK3128_PD_VIO>;
+				clocks = <&cru ACLK_CIF>,
+					 <&cru HCLK_CIF>,
+					 <&cru DCLK_EBC>,
+					 <&cru HCLK_EBC>,
+					 <&cru ACLK_IEP>,
+					 <&cru HCLK_IEP>,
+					 <&cru ACLK_LCDC0>,
+					 <&cru HCLK_LCDC0>,
+					 <&cru PCLK_MIPI>,
+					 <&cru ACLK_RGA>,
+					 <&cru HCLK_RGA>,
+					 <&cru ACLK_VIO0>,
+					 <&cru ACLK_VIO1>,
+					 <&cru HCLK_VIO>,
+					 <&cru HCLK_VIO_H2P>,
+					 <&cru DCLK_VOP>,
+					 <&cru SCLK_VOP>;
+				pm_qos = <&qos_ebc>,
+					 <&qos_iep>,
+					 <&qos_lcdc>,
+					 <&qos_rga>,
+					 <&qos_vip>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_VIDEO {
+				reg = <RK3128_PD_VIDEO>;
+				clocks = <&cru ACLK_VDPU>,
+					 <&cru HCLK_VDPU>,
+					 <&cru ACLK_VEPU>,
+					 <&cru HCLK_VEPU>,
+					 <&cru SCLK_HEVC_CORE>;
+				pm_qos = <&qos_vpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_GPU {
+				reg = <RK3128_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3128_PD_CRYPTO {
+				reg = <RK3128_PD_CRYPTO>;
+				clocks = <&cru HCLK_CRYPTO>,
+					 <&cru SCLK_CRYPTO>;
+				pm_qos = <&qos_crypto>;
+				#power-domain-cells = <0>;
+			};
+		};
+	};
+
+	qos_crypto: qos@10128080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x10128080 0x20>;
+	};
+
+	qos_gpu: qos@1012d000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012d000 0x20>;
+	};
+
+	qos_vpu: qos@1012e000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012e000 0x20>;
+	};
+
+	qos_rga: qos@1012f000 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f000 0x20>;
+	};
+
+	qos_ebc: qos@1012f080 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f080 0x20>;
+	};
+
+	qos_iep: qos@1012f100 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f100 0x20>;
+	};
+
+	qos_lcdc: qos@1012f180 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f180 0x20>;
+	};
+
+	qos_vip: qos@1012f200 {
+		compatible = "rockchip,rk3128-qos", "syscon";
+		reg = <0x1012f200 0x20>;
 	};
 
 	gic: interrupt-controller@10139000 {
-- 
2.43.0

[PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible

[Alex Bee]

Rockchip RK312x SoC family has a Mali400 MP2.
Add a compatible for it.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
index 0fae1ef013be..abd4aa335fbc 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
@@ -29,6 +29,7 @@ properties:
               - allwinner,sun50i-a64-mali
               - rockchip,rk3036-mali
               - rockchip,rk3066-mali
+              - rockchip,rk3128-mali
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
-- 
2.43.0

[PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible

[Alex Bee]

Rockchip RK312x SoC family has a Mali400 MP2.
Add a compatible for it.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
index 0fae1ef013be..abd4aa335fbc 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
@@ -29,6 +29,7 @@ properties:
               - allwinner,sun50i-a64-mali
               - rockchip,rk3036-mali
               - rockchip,rk3066-mali
+              - rockchip,rk3128-mali
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible

[Alex Bee]

Rockchip RK312x SoC family has a Mali400 MP2.
Add a compatible for it.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
index 0fae1ef013be..abd4aa335fbc 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
@@ -29,6 +29,7 @@ properties:
               - allwinner,sun50i-a64-mali
               - rockchip,rk3036-mali
               - rockchip,rk3066-mali
+              - rockchip,rk3128-mali
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible

[Alex Bee]

Rockchip RK312x SoC family has a Mali400 MP2.
Add a compatible for it.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
index 0fae1ef013be..abd4aa335fbc 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
@@ -29,6 +29,7 @@ properties:
               - allwinner,sun50i-a64-mali
               - rockchip,rk3036-mali
               - rockchip,rk3066-mali
+              - rockchip,rk3128-mali
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
-- 
2.43.0

[PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128

[Alex Bee]

RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.

The frequencies and voltages of the opp-table have been taken from
downstream kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index b72905db04f7..b05ee3d926aa 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -101,6 +101,27 @@ opp-1200000000 {
 		};
 	};
 
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <975000 975000 1250000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1250000 1250000 1250000>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -131,6 +152,29 @@ smp-sram@0 {
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "rockchip,rk3128-mali", "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "ppmmu0",
+				  "pp1",
+				  "ppmmu1";
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "bus", "core";
+		power-domains = <&power RK3128_PD_GPU>;
+		resets = <&cru SRST_GPU>;
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+	};
+
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
-- 
2.43.0

[PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128

[Alex Bee]

RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.

The frequencies and voltages of the opp-table have been taken from
downstream kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index b72905db04f7..b05ee3d926aa 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -101,6 +101,27 @@ opp-1200000000 {
 		};
 	};
 
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <975000 975000 1250000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1250000 1250000 1250000>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -131,6 +152,29 @@ smp-sram@0 {
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "rockchip,rk3128-mali", "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "ppmmu0",
+				  "pp1",
+				  "ppmmu1";
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "bus", "core";
+		power-domains = <&power RK3128_PD_GPU>;
+		resets = <&cru SRST_GPU>;
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+	};
+
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128

[Alex Bee]

RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.

The frequencies and voltages of the opp-table have been taken from
downstream kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index b72905db04f7..b05ee3d926aa 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -101,6 +101,27 @@ opp-1200000000 {
 		};
 	};
 
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <975000 975000 1250000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1250000 1250000 1250000>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -131,6 +152,29 @@ smp-sram@0 {
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "rockchip,rk3128-mali", "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "ppmmu0",
+				  "pp1",
+				  "ppmmu1";
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "bus", "core";
+		power-domains = <&power RK3128_PD_GPU>;
+		resets = <&cru SRST_GPU>;
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+	};
+
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128

[Alex Bee]

RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.

The frequencies and voltages of the opp-table have been taken from
downstream kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128.dtsi | 44 ++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index b72905db04f7..b05ee3d926aa 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -101,6 +101,27 @@ opp-1200000000 {
 		};
 	};
 
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <975000 975000 1250000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1250000 1250000 1250000>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -131,6 +152,29 @@ smp-sram@0 {
 		};
 	};
 
+	gpu: gpu@10090000 {
+		compatible = "rockchip,rk3128-mali", "arm,mali-400";
+		reg = <0x10090000 0x10000>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gp",
+				  "gpmmu",
+				  "pp0",
+				  "ppmmu0",
+				  "pp1",
+				  "ppmmu1";
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+		clock-names = "bus", "core";
+		power-domains = <&power RK3128_PD_GPU>;
+		resets = <&cru SRST_GPU>;
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+	};
+
 	pmu: syscon@100a0000 {
 		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 		reg = <0x100a0000 0x1000>;
-- 
2.43.0

[PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128

[Alex Bee]

Add the supply and enable gpu node for XPI-3128 board.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
index 61b9f069c8a2..0a8ead0bfe09 100644
--- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
+++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
@@ -315,6 +315,11 @@ &gpio3 {
 			  "", "", "", "";
 };
 
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
 &pinctrl {
 	dp83848c {
 		dp83848c_rst: dp83848c-rst {
-- 
2.43.0

[PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128

[Alex Bee]

Add the supply and enable gpu node for XPI-3128 board.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
index 61b9f069c8a2..0a8ead0bfe09 100644
--- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
+++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
@@ -315,6 +315,11 @@ &gpio3 {
 			  "", "", "", "";
 };
 
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
 &pinctrl {
 	dp83848c {
 		dp83848c_rst: dp83848c-rst {
-- 
2.43.0


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128

[Alex Bee]

Add the supply and enable gpu node for XPI-3128 board.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
index 61b9f069c8a2..0a8ead0bfe09 100644
--- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
+++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
@@ -315,6 +315,11 @@ &gpio3 {
 			  "", "", "", "";
 };
 
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
 &pinctrl {
 	dp83848c {
 		dp83848c_rst: dp83848c-rst {
-- 
2.43.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128

[Alex Bee]

Add the supply and enable gpu node for XPI-3128 board.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
 arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
index 61b9f069c8a2..0a8ead0bfe09 100644
--- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
+++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
@@ -315,6 +315,11 @@ &gpio3 {
 			  "", "", "", "";
 };
 
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
 &pinctrl {
 	dp83848c {
 		dp83848c_rst: dp83848c-rst {
-- 
2.43.0

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.

does the power-domain controller work with the incomplete set of
pm-domains too?

What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts


And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
  and a separate patch for the code addition.


Heiko

> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>  
>  / {
>  	compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
>  	pmu: syscon@100a0000 {
>  		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>  		reg = <0x100a0000 0x1000>;
> +
> +		power: power-controller {
> +			compatible = "rockchip,rk3128-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			power-domain@RK3128_PD_VIO {
> +				reg = <RK3128_PD_VIO>;
> +				clocks = <&cru ACLK_CIF>,
> +					 <&cru HCLK_CIF>,
> +					 <&cru DCLK_EBC>,
> +					 <&cru HCLK_EBC>,
> +					 <&cru ACLK_IEP>,
> +					 <&cru HCLK_IEP>,
> +					 <&cru ACLK_LCDC0>,
> +					 <&cru HCLK_LCDC0>,
> +					 <&cru PCLK_MIPI>,
> +					 <&cru ACLK_RGA>,
> +					 <&cru HCLK_RGA>,
> +					 <&cru ACLK_VIO0>,
> +					 <&cru ACLK_VIO1>,
> +					 <&cru HCLK_VIO>,
> +					 <&cru HCLK_VIO_H2P>,
> +					 <&cru DCLK_VOP>,
> +					 <&cru SCLK_VOP>;
> +				pm_qos = <&qos_ebc>,
> +					 <&qos_iep>,
> +					 <&qos_lcdc>,
> +					 <&qos_rga>,
> +					 <&qos_vip>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_VIDEO {
> +				reg = <RK3128_PD_VIDEO>;
> +				clocks = <&cru ACLK_VDPU>,
> +					 <&cru HCLK_VDPU>,
> +					 <&cru ACLK_VEPU>,
> +					 <&cru HCLK_VEPU>,
> +					 <&cru SCLK_HEVC_CORE>;
> +				pm_qos = <&qos_vpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_GPU {
> +				reg = <RK3128_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_CRYPTO {
> +				reg = <RK3128_PD_CRYPTO>;
> +				clocks = <&cru HCLK_CRYPTO>,
> +					 <&cru SCLK_CRYPTO>;
> +				pm_qos = <&qos_crypto>;
> +				#power-domain-cells = <0>;
> +			};
> +		};
> +	};
> +
> +	qos_crypto: qos@10128080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x10128080 0x20>;
> +	};
> +
> +	qos_gpu: qos@1012d000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012d000 0x20>;
> +	};
> +
> +	qos_vpu: qos@1012e000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012e000 0x20>;
> +	};
> +
> +	qos_rga: qos@1012f000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f000 0x20>;
> +	};
> +
> +	qos_ebc: qos@1012f080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f080 0x20>;
> +	};
> +
> +	qos_iep: qos@1012f100 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f100 0x20>;
> +	};
> +
> +	qos_lcdc: qos@1012f180 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f180 0x20>;
> +	};
> +
> +	qos_vip: qos@1012f200 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f200 0x20>;
>  	};
>  
>  	gic: interrupt-controller@10139000 {
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.

does the power-domain controller work with the incomplete set of
pm-domains too?

What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts


And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
  and a separate patch for the code addition.


Heiko

> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>  
>  / {
>  	compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
>  	pmu: syscon@100a0000 {
>  		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>  		reg = <0x100a0000 0x1000>;
> +
> +		power: power-controller {
> +			compatible = "rockchip,rk3128-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			power-domain@RK3128_PD_VIO {
> +				reg = <RK3128_PD_VIO>;
> +				clocks = <&cru ACLK_CIF>,
> +					 <&cru HCLK_CIF>,
> +					 <&cru DCLK_EBC>,
> +					 <&cru HCLK_EBC>,
> +					 <&cru ACLK_IEP>,
> +					 <&cru HCLK_IEP>,
> +					 <&cru ACLK_LCDC0>,
> +					 <&cru HCLK_LCDC0>,
> +					 <&cru PCLK_MIPI>,
> +					 <&cru ACLK_RGA>,
> +					 <&cru HCLK_RGA>,
> +					 <&cru ACLK_VIO0>,
> +					 <&cru ACLK_VIO1>,
> +					 <&cru HCLK_VIO>,
> +					 <&cru HCLK_VIO_H2P>,
> +					 <&cru DCLK_VOP>,
> +					 <&cru SCLK_VOP>;
> +				pm_qos = <&qos_ebc>,
> +					 <&qos_iep>,
> +					 <&qos_lcdc>,
> +					 <&qos_rga>,
> +					 <&qos_vip>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_VIDEO {
> +				reg = <RK3128_PD_VIDEO>;
> +				clocks = <&cru ACLK_VDPU>,
> +					 <&cru HCLK_VDPU>,
> +					 <&cru ACLK_VEPU>,
> +					 <&cru HCLK_VEPU>,
> +					 <&cru SCLK_HEVC_CORE>;
> +				pm_qos = <&qos_vpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_GPU {
> +				reg = <RK3128_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_CRYPTO {
> +				reg = <RK3128_PD_CRYPTO>;
> +				clocks = <&cru HCLK_CRYPTO>,
> +					 <&cru SCLK_CRYPTO>;
> +				pm_qos = <&qos_crypto>;
> +				#power-domain-cells = <0>;
> +			};
> +		};
> +	};
> +
> +	qos_crypto: qos@10128080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x10128080 0x20>;
> +	};
> +
> +	qos_gpu: qos@1012d000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012d000 0x20>;
> +	};
> +
> +	qos_vpu: qos@1012e000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012e000 0x20>;
> +	};
> +
> +	qos_rga: qos@1012f000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f000 0x20>;
> +	};
> +
> +	qos_ebc: qos@1012f080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f080 0x20>;
> +	};
> +
> +	qos_iep: qos@1012f100 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f100 0x20>;
> +	};
> +
> +	qos_lcdc: qos@1012f180 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f180 0x20>;
> +	};
> +
> +	qos_vip: qos@1012f200 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f200 0x20>;
>  	};
>  
>  	gic: interrupt-controller@10139000 {
> 





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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.

does the power-domain controller work with the incomplete set of
pm-domains too?

What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts


And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
  and a separate patch for the code addition.


Heiko

> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>  
>  / {
>  	compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
>  	pmu: syscon@100a0000 {
>  		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>  		reg = <0x100a0000 0x1000>;
> +
> +		power: power-controller {
> +			compatible = "rockchip,rk3128-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			power-domain@RK3128_PD_VIO {
> +				reg = <RK3128_PD_VIO>;
> +				clocks = <&cru ACLK_CIF>,
> +					 <&cru HCLK_CIF>,
> +					 <&cru DCLK_EBC>,
> +					 <&cru HCLK_EBC>,
> +					 <&cru ACLK_IEP>,
> +					 <&cru HCLK_IEP>,
> +					 <&cru ACLK_LCDC0>,
> +					 <&cru HCLK_LCDC0>,
> +					 <&cru PCLK_MIPI>,
> +					 <&cru ACLK_RGA>,
> +					 <&cru HCLK_RGA>,
> +					 <&cru ACLK_VIO0>,
> +					 <&cru ACLK_VIO1>,
> +					 <&cru HCLK_VIO>,
> +					 <&cru HCLK_VIO_H2P>,
> +					 <&cru DCLK_VOP>,
> +					 <&cru SCLK_VOP>;
> +				pm_qos = <&qos_ebc>,
> +					 <&qos_iep>,
> +					 <&qos_lcdc>,
> +					 <&qos_rga>,
> +					 <&qos_vip>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_VIDEO {
> +				reg = <RK3128_PD_VIDEO>;
> +				clocks = <&cru ACLK_VDPU>,
> +					 <&cru HCLK_VDPU>,
> +					 <&cru ACLK_VEPU>,
> +					 <&cru HCLK_VEPU>,
> +					 <&cru SCLK_HEVC_CORE>;
> +				pm_qos = <&qos_vpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_GPU {
> +				reg = <RK3128_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_CRYPTO {
> +				reg = <RK3128_PD_CRYPTO>;
> +				clocks = <&cru HCLK_CRYPTO>,
> +					 <&cru SCLK_CRYPTO>;
> +				pm_qos = <&qos_crypto>;
> +				#power-domain-cells = <0>;
> +			};
> +		};
> +	};
> +
> +	qos_crypto: qos@10128080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x10128080 0x20>;
> +	};
> +
> +	qos_gpu: qos@1012d000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012d000 0x20>;
> +	};
> +
> +	qos_vpu: qos@1012e000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012e000 0x20>;
> +	};
> +
> +	qos_rga: qos@1012f000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f000 0x20>;
> +	};
> +
> +	qos_ebc: qos@1012f080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f080 0x20>;
> +	};
> +
> +	qos_iep: qos@1012f100 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f100 0x20>;
> +	};
> +
> +	qos_lcdc: qos@1012f180 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f180 0x20>;
> +	};
> +
> +	qos_vip: qos@1012f200 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f200 0x20>;
>  	};
>  
>  	gic: interrupt-controller@10139000 {
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.

does the power-domain controller work with the incomplete set of
pm-domains too?

What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts


And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
  and a separate patch for the code addition.


Heiko

> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>  1 file changed, 101 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>  
>  / {
>  	compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
>  	pmu: syscon@100a0000 {
>  		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>  		reg = <0x100a0000 0x1000>;
> +
> +		power: power-controller {
> +			compatible = "rockchip,rk3128-power-controller";
> +			#power-domain-cells = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			power-domain@RK3128_PD_VIO {
> +				reg = <RK3128_PD_VIO>;
> +				clocks = <&cru ACLK_CIF>,
> +					 <&cru HCLK_CIF>,
> +					 <&cru DCLK_EBC>,
> +					 <&cru HCLK_EBC>,
> +					 <&cru ACLK_IEP>,
> +					 <&cru HCLK_IEP>,
> +					 <&cru ACLK_LCDC0>,
> +					 <&cru HCLK_LCDC0>,
> +					 <&cru PCLK_MIPI>,
> +					 <&cru ACLK_RGA>,
> +					 <&cru HCLK_RGA>,
> +					 <&cru ACLK_VIO0>,
> +					 <&cru ACLK_VIO1>,
> +					 <&cru HCLK_VIO>,
> +					 <&cru HCLK_VIO_H2P>,
> +					 <&cru DCLK_VOP>,
> +					 <&cru SCLK_VOP>;
> +				pm_qos = <&qos_ebc>,
> +					 <&qos_iep>,
> +					 <&qos_lcdc>,
> +					 <&qos_rga>,
> +					 <&qos_vip>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_VIDEO {
> +				reg = <RK3128_PD_VIDEO>;
> +				clocks = <&cru ACLK_VDPU>,
> +					 <&cru HCLK_VDPU>,
> +					 <&cru ACLK_VEPU>,
> +					 <&cru HCLK_VEPU>,
> +					 <&cru SCLK_HEVC_CORE>;
> +				pm_qos = <&qos_vpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_GPU {
> +				reg = <RK3128_PD_GPU>;
> +				clocks = <&cru ACLK_GPU>;
> +				pm_qos = <&qos_gpu>;
> +				#power-domain-cells = <0>;
> +			};
> +
> +			power-domain@RK3128_PD_CRYPTO {
> +				reg = <RK3128_PD_CRYPTO>;
> +				clocks = <&cru HCLK_CRYPTO>,
> +					 <&cru SCLK_CRYPTO>;
> +				pm_qos = <&qos_crypto>;
> +				#power-domain-cells = <0>;
> +			};
> +		};
> +	};
> +
> +	qos_crypto: qos@10128080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x10128080 0x20>;
> +	};
> +
> +	qos_gpu: qos@1012d000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012d000 0x20>;
> +	};
> +
> +	qos_vpu: qos@1012e000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012e000 0x20>;
> +	};
> +
> +	qos_rga: qos@1012f000 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f000 0x20>;
> +	};
> +
> +	qos_ebc: qos@1012f080 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f080 0x20>;
> +	};
> +
> +	qos_iep: qos@1012f100 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f100 0x20>;
> +	};
> +
> +	qos_lcdc: qos@1012f180 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f180 0x20>;
> +	};
> +
> +	qos_vip: qos@1012f200 {
> +		compatible = "rockchip,rk3128-qos", "syscon";
> +		reg = <0x1012f200 0x20>;
>  	};
>  
>  	gic: interrupt-controller@10139000 {
> 





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Re: (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128

[Heiko Stuebner]

On Sat, 2 Dec 2023 13:51:39 +0100, Alex Bee wrote:
> The first patch in this series fixes the pm-domain driver and adds
> power-domains which are currently missing. This touches the ABI which is
> not and was never used until now. Not all of them are used yet, but when
> the power-controller is added to the DT in patch 2 the ABI should not
> be changed again.
> Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
> node and the respective operating points to SoC DT and finally enabling it
> for XPI-3128 board.
> 
> [...]

Applied, thanks!

[3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
      commit: 5d86c15c3171c3ecebd84d53e30d9812b5591c84

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128

[Heiko Stuebner]

On Sat, 2 Dec 2023 13:51:39 +0100, Alex Bee wrote:
> The first patch in this series fixes the pm-domain driver and adds
> power-domains which are currently missing. This touches the ABI which is
> not and was never used until now. Not all of them are used yet, but when
> the power-controller is added to the DT in patch 2 the ABI should not
> be changed again.
> Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
> node and the respective operating points to SoC DT and finally enabling it
> for XPI-3128 board.
> 
> [...]

Applied, thanks!

[3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
      commit: 5d86c15c3171c3ecebd84d53e30d9812b5591c84

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128

[Heiko Stuebner]

On Sat, 2 Dec 2023 13:51:39 +0100, Alex Bee wrote:
> The first patch in this series fixes the pm-domain driver and adds
> power-domains which are currently missing. This touches the ABI which is
> not and was never used until now. Not all of them are used yet, but when
> the power-controller is added to the DT in patch 2 the ABI should not
> be changed again.
> Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
> node and the respective operating points to SoC DT and finally enabling it
> for XPI-3128 board.
> 
> [...]

Applied, thanks!

[3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
      commit: 5d86c15c3171c3ecebd84d53e30d9812b5591c84

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128

[Heiko Stuebner]

On Sat, 2 Dec 2023 13:51:39 +0100, Alex Bee wrote:
> The first patch in this series fixes the pm-domain driver and adds
> power-domains which are currently missing. This touches the ABI which is
> not and was never used until now. Not all of them are used yet, but when
> the power-controller is added to the DT in patch 2 the ABI should not
> be changed again.
> Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu
> node and the respective operating points to SoC DT and finally enabling it
> for XPI-3128 board.
> 
> [...]

Applied, thanks!

[3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
      commit: 5d86c15c3171c3ecebd84d53e30d9812b5591c84

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>> Add power controller and qos nodes for RK3128 in order to use
>> them as powerdomains.
> does the power-domain controller work with the incomplete set of
> pm-domains too?

Yes, it does - the missing domains can request idle only and can't be 
powered on/off - if no one requests idle they are just up all the time.

> What I have in mind is
> - adding the power-controller node with the existing set of power-domains
> - the gpu pm-domain is in there
> - adding the gpu parts

My main concern about adding them later was the change of the ABI after 
they've been exposed in the SoC DT. If that's not an issue - sure: I can 
add them in a separate series.

>
>
> And a second series with
> - patch1 from here
> - a dts patch adding the additional pm-domains to rk3128.dtsi
> - I guess patch1 also should be split into a patch adding the binding-ids
>    and a separate patch for the code addition.

Yeah, I noticed this also :)

Regards,

Alex

>
>
> Heiko
>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>> ---
>>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> index 4e8b38604ecd..b72905db04f7 100644
>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/interrupt-controller/irq.h>
>>   #include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/power/rk3128-power.h>
>>   
>>   / {
>>   	compatible = "rockchip,rk3128";
>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>   	pmu: syscon@100a0000 {
>>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>   		reg = <0x100a0000 0x1000>;
>> +
>> +		power: power-controller {
>> +			compatible = "rockchip,rk3128-power-controller";
>> +			#power-domain-cells = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			power-domain@RK3128_PD_VIO {
>> +				reg = <RK3128_PD_VIO>;
>> +				clocks = <&cru ACLK_CIF>,
>> +					 <&cru HCLK_CIF>,
>> +					 <&cru DCLK_EBC>,
>> +					 <&cru HCLK_EBC>,
>> +					 <&cru ACLK_IEP>,
>> +					 <&cru HCLK_IEP>,
>> +					 <&cru ACLK_LCDC0>,
>> +					 <&cru HCLK_LCDC0>,
>> +					 <&cru PCLK_MIPI>,
>> +					 <&cru ACLK_RGA>,
>> +					 <&cru HCLK_RGA>,
>> +					 <&cru ACLK_VIO0>,
>> +					 <&cru ACLK_VIO1>,
>> +					 <&cru HCLK_VIO>,
>> +					 <&cru HCLK_VIO_H2P>,
>> +					 <&cru DCLK_VOP>,
>> +					 <&cru SCLK_VOP>;
>> +				pm_qos = <&qos_ebc>,
>> +					 <&qos_iep>,
>> +					 <&qos_lcdc>,
>> +					 <&qos_rga>,
>> +					 <&qos_vip>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_VIDEO {
>> +				reg = <RK3128_PD_VIDEO>;
>> +				clocks = <&cru ACLK_VDPU>,
>> +					 <&cru HCLK_VDPU>,
>> +					 <&cru ACLK_VEPU>,
>> +					 <&cru HCLK_VEPU>,
>> +					 <&cru SCLK_HEVC_CORE>;
>> +				pm_qos = <&qos_vpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_GPU {
>> +				reg = <RK3128_PD_GPU>;
>> +				clocks = <&cru ACLK_GPU>;
>> +				pm_qos = <&qos_gpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_CRYPTO {
>> +				reg = <RK3128_PD_CRYPTO>;
>> +				clocks = <&cru HCLK_CRYPTO>,
>> +					 <&cru SCLK_CRYPTO>;
>> +				pm_qos = <&qos_crypto>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
>> +	qos_crypto: qos@10128080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x10128080 0x20>;
>> +	};
>> +
>> +	qos_gpu: qos@1012d000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012d000 0x20>;
>> +	};
>> +
>> +	qos_vpu: qos@1012e000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012e000 0x20>;
>> +	};
>> +
>> +	qos_rga: qos@1012f000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f000 0x20>;
>> +	};
>> +
>> +	qos_ebc: qos@1012f080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f080 0x20>;
>> +	};
>> +
>> +	qos_iep: qos@1012f100 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f100 0x20>;
>> +	};
>> +
>> +	qos_lcdc: qos@1012f180 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f180 0x20>;
>> +	};
>> +
>> +	qos_vip: qos@1012f200 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f200 0x20>;
>>   	};
>>   
>>   	gic: interrupt-controller@10139000 {
>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>> Add power controller and qos nodes for RK3128 in order to use
>> them as powerdomains.
> does the power-domain controller work with the incomplete set of
> pm-domains too?

Yes, it does - the missing domains can request idle only and can't be 
powered on/off - if no one requests idle they are just up all the time.

> What I have in mind is
> - adding the power-controller node with the existing set of power-domains
> - the gpu pm-domain is in there
> - adding the gpu parts

My main concern about adding them later was the change of the ABI after 
they've been exposed in the SoC DT. If that's not an issue - sure: I can 
add them in a separate series.

>
>
> And a second series with
> - patch1 from here
> - a dts patch adding the additional pm-domains to rk3128.dtsi
> - I guess patch1 also should be split into a patch adding the binding-ids
>    and a separate patch for the code addition.

Yeah, I noticed this also :)

Regards,

Alex

>
>
> Heiko
>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>> ---
>>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> index 4e8b38604ecd..b72905db04f7 100644
>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/interrupt-controller/irq.h>
>>   #include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/power/rk3128-power.h>
>>   
>>   / {
>>   	compatible = "rockchip,rk3128";
>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>   	pmu: syscon@100a0000 {
>>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>   		reg = <0x100a0000 0x1000>;
>> +
>> +		power: power-controller {
>> +			compatible = "rockchip,rk3128-power-controller";
>> +			#power-domain-cells = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			power-domain@RK3128_PD_VIO {
>> +				reg = <RK3128_PD_VIO>;
>> +				clocks = <&cru ACLK_CIF>,
>> +					 <&cru HCLK_CIF>,
>> +					 <&cru DCLK_EBC>,
>> +					 <&cru HCLK_EBC>,
>> +					 <&cru ACLK_IEP>,
>> +					 <&cru HCLK_IEP>,
>> +					 <&cru ACLK_LCDC0>,
>> +					 <&cru HCLK_LCDC0>,
>> +					 <&cru PCLK_MIPI>,
>> +					 <&cru ACLK_RGA>,
>> +					 <&cru HCLK_RGA>,
>> +					 <&cru ACLK_VIO0>,
>> +					 <&cru ACLK_VIO1>,
>> +					 <&cru HCLK_VIO>,
>> +					 <&cru HCLK_VIO_H2P>,
>> +					 <&cru DCLK_VOP>,
>> +					 <&cru SCLK_VOP>;
>> +				pm_qos = <&qos_ebc>,
>> +					 <&qos_iep>,
>> +					 <&qos_lcdc>,
>> +					 <&qos_rga>,
>> +					 <&qos_vip>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_VIDEO {
>> +				reg = <RK3128_PD_VIDEO>;
>> +				clocks = <&cru ACLK_VDPU>,
>> +					 <&cru HCLK_VDPU>,
>> +					 <&cru ACLK_VEPU>,
>> +					 <&cru HCLK_VEPU>,
>> +					 <&cru SCLK_HEVC_CORE>;
>> +				pm_qos = <&qos_vpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_GPU {
>> +				reg = <RK3128_PD_GPU>;
>> +				clocks = <&cru ACLK_GPU>;
>> +				pm_qos = <&qos_gpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_CRYPTO {
>> +				reg = <RK3128_PD_CRYPTO>;
>> +				clocks = <&cru HCLK_CRYPTO>,
>> +					 <&cru SCLK_CRYPTO>;
>> +				pm_qos = <&qos_crypto>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
>> +	qos_crypto: qos@10128080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x10128080 0x20>;
>> +	};
>> +
>> +	qos_gpu: qos@1012d000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012d000 0x20>;
>> +	};
>> +
>> +	qos_vpu: qos@1012e000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012e000 0x20>;
>> +	};
>> +
>> +	qos_rga: qos@1012f000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f000 0x20>;
>> +	};
>> +
>> +	qos_ebc: qos@1012f080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f080 0x20>;
>> +	};
>> +
>> +	qos_iep: qos@1012f100 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f100 0x20>;
>> +	};
>> +
>> +	qos_lcdc: qos@1012f180 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f180 0x20>;
>> +	};
>> +
>> +	qos_vip: qos@1012f200 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f200 0x20>;
>>   	};
>>   
>>   	gic: interrupt-controller@10139000 {
>>
>
>
>

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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>> Add power controller and qos nodes for RK3128 in order to use
>> them as powerdomains.
> does the power-domain controller work with the incomplete set of
> pm-domains too?

Yes, it does - the missing domains can request idle only and can't be 
powered on/off - if no one requests idle they are just up all the time.

> What I have in mind is
> - adding the power-controller node with the existing set of power-domains
> - the gpu pm-domain is in there
> - adding the gpu parts

My main concern about adding them later was the change of the ABI after 
they've been exposed in the SoC DT. If that's not an issue - sure: I can 
add them in a separate series.

>
>
> And a second series with
> - patch1 from here
> - a dts patch adding the additional pm-domains to rk3128.dtsi
> - I guess patch1 also should be split into a patch adding the binding-ids
>    and a separate patch for the code addition.

Yeah, I noticed this also :)

Regards,

Alex

>
>
> Heiko
>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>> ---
>>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> index 4e8b38604ecd..b72905db04f7 100644
>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/interrupt-controller/irq.h>
>>   #include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/power/rk3128-power.h>
>>   
>>   / {
>>   	compatible = "rockchip,rk3128";
>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>   	pmu: syscon@100a0000 {
>>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>   		reg = <0x100a0000 0x1000>;
>> +
>> +		power: power-controller {
>> +			compatible = "rockchip,rk3128-power-controller";
>> +			#power-domain-cells = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			power-domain@RK3128_PD_VIO {
>> +				reg = <RK3128_PD_VIO>;
>> +				clocks = <&cru ACLK_CIF>,
>> +					 <&cru HCLK_CIF>,
>> +					 <&cru DCLK_EBC>,
>> +					 <&cru HCLK_EBC>,
>> +					 <&cru ACLK_IEP>,
>> +					 <&cru HCLK_IEP>,
>> +					 <&cru ACLK_LCDC0>,
>> +					 <&cru HCLK_LCDC0>,
>> +					 <&cru PCLK_MIPI>,
>> +					 <&cru ACLK_RGA>,
>> +					 <&cru HCLK_RGA>,
>> +					 <&cru ACLK_VIO0>,
>> +					 <&cru ACLK_VIO1>,
>> +					 <&cru HCLK_VIO>,
>> +					 <&cru HCLK_VIO_H2P>,
>> +					 <&cru DCLK_VOP>,
>> +					 <&cru SCLK_VOP>;
>> +				pm_qos = <&qos_ebc>,
>> +					 <&qos_iep>,
>> +					 <&qos_lcdc>,
>> +					 <&qos_rga>,
>> +					 <&qos_vip>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_VIDEO {
>> +				reg = <RK3128_PD_VIDEO>;
>> +				clocks = <&cru ACLK_VDPU>,
>> +					 <&cru HCLK_VDPU>,
>> +					 <&cru ACLK_VEPU>,
>> +					 <&cru HCLK_VEPU>,
>> +					 <&cru SCLK_HEVC_CORE>;
>> +				pm_qos = <&qos_vpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_GPU {
>> +				reg = <RK3128_PD_GPU>;
>> +				clocks = <&cru ACLK_GPU>;
>> +				pm_qos = <&qos_gpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_CRYPTO {
>> +				reg = <RK3128_PD_CRYPTO>;
>> +				clocks = <&cru HCLK_CRYPTO>,
>> +					 <&cru SCLK_CRYPTO>;
>> +				pm_qos = <&qos_crypto>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
>> +	qos_crypto: qos@10128080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x10128080 0x20>;
>> +	};
>> +
>> +	qos_gpu: qos@1012d000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012d000 0x20>;
>> +	};
>> +
>> +	qos_vpu: qos@1012e000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012e000 0x20>;
>> +	};
>> +
>> +	qos_rga: qos@1012f000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f000 0x20>;
>> +	};
>> +
>> +	qos_ebc: qos@1012f080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f080 0x20>;
>> +	};
>> +
>> +	qos_iep: qos@1012f100 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f100 0x20>;
>> +	};
>> +
>> +	qos_lcdc: qos@1012f180 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f180 0x20>;
>> +	};
>> +
>> +	qos_vip: qos@1012f200 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f200 0x20>;
>>   	};
>>   
>>   	gic: interrupt-controller@10139000 {
>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>> Add power controller and qos nodes for RK3128 in order to use
>> them as powerdomains.
> does the power-domain controller work with the incomplete set of
> pm-domains too?

Yes, it does - the missing domains can request idle only and can't be 
powered on/off - if no one requests idle they are just up all the time.

> What I have in mind is
> - adding the power-controller node with the existing set of power-domains
> - the gpu pm-domain is in there
> - adding the gpu parts

My main concern about adding them later was the change of the ABI after 
they've been exposed in the SoC DT. If that's not an issue - sure: I can 
add them in a separate series.

>
>
> And a second series with
> - patch1 from here
> - a dts patch adding the additional pm-domains to rk3128.dtsi
> - I guess patch1 also should be split into a patch adding the binding-ids
>    and a separate patch for the code addition.

Yeah, I noticed this also :)

Regards,

Alex

>
>
> Heiko
>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>> ---
>>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> index 4e8b38604ecd..b72905db04f7 100644
>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>> @@ -8,6 +8,7 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/interrupt-controller/irq.h>
>>   #include <dt-bindings/pinctrl/rockchip.h>
>> +#include <dt-bindings/power/rk3128-power.h>
>>   
>>   / {
>>   	compatible = "rockchip,rk3128";
>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>   	pmu: syscon@100a0000 {
>>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>   		reg = <0x100a0000 0x1000>;
>> +
>> +		power: power-controller {
>> +			compatible = "rockchip,rk3128-power-controller";
>> +			#power-domain-cells = <1>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			power-domain@RK3128_PD_VIO {
>> +				reg = <RK3128_PD_VIO>;
>> +				clocks = <&cru ACLK_CIF>,
>> +					 <&cru HCLK_CIF>,
>> +					 <&cru DCLK_EBC>,
>> +					 <&cru HCLK_EBC>,
>> +					 <&cru ACLK_IEP>,
>> +					 <&cru HCLK_IEP>,
>> +					 <&cru ACLK_LCDC0>,
>> +					 <&cru HCLK_LCDC0>,
>> +					 <&cru PCLK_MIPI>,
>> +					 <&cru ACLK_RGA>,
>> +					 <&cru HCLK_RGA>,
>> +					 <&cru ACLK_VIO0>,
>> +					 <&cru ACLK_VIO1>,
>> +					 <&cru HCLK_VIO>,
>> +					 <&cru HCLK_VIO_H2P>,
>> +					 <&cru DCLK_VOP>,
>> +					 <&cru SCLK_VOP>;
>> +				pm_qos = <&qos_ebc>,
>> +					 <&qos_iep>,
>> +					 <&qos_lcdc>,
>> +					 <&qos_rga>,
>> +					 <&qos_vip>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_VIDEO {
>> +				reg = <RK3128_PD_VIDEO>;
>> +				clocks = <&cru ACLK_VDPU>,
>> +					 <&cru HCLK_VDPU>,
>> +					 <&cru ACLK_VEPU>,
>> +					 <&cru HCLK_VEPU>,
>> +					 <&cru SCLK_HEVC_CORE>;
>> +				pm_qos = <&qos_vpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_GPU {
>> +				reg = <RK3128_PD_GPU>;
>> +				clocks = <&cru ACLK_GPU>;
>> +				pm_qos = <&qos_gpu>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +
>> +			power-domain@RK3128_PD_CRYPTO {
>> +				reg = <RK3128_PD_CRYPTO>;
>> +				clocks = <&cru HCLK_CRYPTO>,
>> +					 <&cru SCLK_CRYPTO>;
>> +				pm_qos = <&qos_crypto>;
>> +				#power-domain-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
>> +	qos_crypto: qos@10128080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x10128080 0x20>;
>> +	};
>> +
>> +	qos_gpu: qos@1012d000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012d000 0x20>;
>> +	};
>> +
>> +	qos_vpu: qos@1012e000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012e000 0x20>;
>> +	};
>> +
>> +	qos_rga: qos@1012f000 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f000 0x20>;
>> +	};
>> +
>> +	qos_ebc: qos@1012f080 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f080 0x20>;
>> +	};
>> +
>> +	qos_iep: qos@1012f100 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f100 0x20>;
>> +	};
>> +
>> +	qos_lcdc: qos@1012f180 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f180 0x20>;
>> +	};
>> +
>> +	qos_vip: qos@1012f200 {
>> +		compatible = "rockchip,rk3128-qos", "syscon";
>> +		reg = <0x1012f200 0x20>;
>>   	};
>>   
>>   	gic: interrupt-controller@10139000 {
>>
>
>
>

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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >> Add power controller and qos nodes for RK3128 in order to use
> >> them as powerdomains.
> > does the power-domain controller work with the incomplete set of
> > pm-domains too?
> 
> Yes, it does - the missing domains can request idle only and can't be 
> powered on/off - if no one requests idle they are just up all the time.
> 
> > What I have in mind is
> > - adding the power-controller node with the existing set of power-domains
> > - the gpu pm-domain is in there
> > - adding the gpu parts
> 
> My main concern about adding them later was the change of the ABI after 
> they've been exposed in the SoC DT. If that's not an issue - sure: I can 
> add them in a separate series.

An ABI change would be _changing_ the domain-ids in the rk3128-power.h
I think :-) .

Right now the existing domain ids in the header are already exposed to the
world, so someone could already use them, but not the new ones.



Heiko

> > And a second series with
> > - patch1 from here
> > - a dts patch adding the additional pm-domains to rk3128.dtsi
> > - I guess patch1 also should be split into a patch adding the binding-ids
> >    and a separate patch for the code addition.
> 
> Yeah, I noticed this also :)
> 
> Regards,
> 
> Alex
> 
> >
> >
> > Heiko
> >
> >> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >> ---
> >>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>   1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> index 4e8b38604ecd..b72905db04f7 100644
> >> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/interrupt-controller/irq.h>
> >>   #include <dt-bindings/pinctrl/rockchip.h>
> >> +#include <dt-bindings/power/rk3128-power.h>
> >>   
> >>   / {
> >>   	compatible = "rockchip,rk3128";
> >> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>   	pmu: syscon@100a0000 {
> >>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>   		reg = <0x100a0000 0x1000>;
> >> +
> >> +		power: power-controller {
> >> +			compatible = "rockchip,rk3128-power-controller";
> >> +			#power-domain-cells = <1>;
> >> +			#address-cells = <1>;
> >> +			#size-cells = <0>;
> >> +
> >> +			power-domain@RK3128_PD_VIO {
> >> +				reg = <RK3128_PD_VIO>;
> >> +				clocks = <&cru ACLK_CIF>,
> >> +					 <&cru HCLK_CIF>,
> >> +					 <&cru DCLK_EBC>,
> >> +					 <&cru HCLK_EBC>,
> >> +					 <&cru ACLK_IEP>,
> >> +					 <&cru HCLK_IEP>,
> >> +					 <&cru ACLK_LCDC0>,
> >> +					 <&cru HCLK_LCDC0>,
> >> +					 <&cru PCLK_MIPI>,
> >> +					 <&cru ACLK_RGA>,
> >> +					 <&cru HCLK_RGA>,
> >> +					 <&cru ACLK_VIO0>,
> >> +					 <&cru ACLK_VIO1>,
> >> +					 <&cru HCLK_VIO>,
> >> +					 <&cru HCLK_VIO_H2P>,
> >> +					 <&cru DCLK_VOP>,
> >> +					 <&cru SCLK_VOP>;
> >> +				pm_qos = <&qos_ebc>,
> >> +					 <&qos_iep>,
> >> +					 <&qos_lcdc>,
> >> +					 <&qos_rga>,
> >> +					 <&qos_vip>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_VIDEO {
> >> +				reg = <RK3128_PD_VIDEO>;
> >> +				clocks = <&cru ACLK_VDPU>,
> >> +					 <&cru HCLK_VDPU>,
> >> +					 <&cru ACLK_VEPU>,
> >> +					 <&cru HCLK_VEPU>,
> >> +					 <&cru SCLK_HEVC_CORE>;
> >> +				pm_qos = <&qos_vpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_GPU {
> >> +				reg = <RK3128_PD_GPU>;
> >> +				clocks = <&cru ACLK_GPU>;
> >> +				pm_qos = <&qos_gpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_CRYPTO {
> >> +				reg = <RK3128_PD_CRYPTO>;
> >> +				clocks = <&cru HCLK_CRYPTO>,
> >> +					 <&cru SCLK_CRYPTO>;
> >> +				pm_qos = <&qos_crypto>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +		};
> >> +	};
> >> +
> >> +	qos_crypto: qos@10128080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x10128080 0x20>;
> >> +	};
> >> +
> >> +	qos_gpu: qos@1012d000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012d000 0x20>;
> >> +	};
> >> +
> >> +	qos_vpu: qos@1012e000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012e000 0x20>;
> >> +	};
> >> +
> >> +	qos_rga: qos@1012f000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f000 0x20>;
> >> +	};
> >> +
> >> +	qos_ebc: qos@1012f080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f080 0x20>;
> >> +	};
> >> +
> >> +	qos_iep: qos@1012f100 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f100 0x20>;
> >> +	};
> >> +
> >> +	qos_lcdc: qos@1012f180 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f180 0x20>;
> >> +	};
> >> +
> >> +	qos_vip: qos@1012f200 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f200 0x20>;
> >>   	};
> >>   
> >>   	gic: interrupt-controller@10139000 {
> >>
> >
> >
> >
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >> Add power controller and qos nodes for RK3128 in order to use
> >> them as powerdomains.
> > does the power-domain controller work with the incomplete set of
> > pm-domains too?
> 
> Yes, it does - the missing domains can request idle only and can't be 
> powered on/off - if no one requests idle they are just up all the time.
> 
> > What I have in mind is
> > - adding the power-controller node with the existing set of power-domains
> > - the gpu pm-domain is in there
> > - adding the gpu parts
> 
> My main concern about adding them later was the change of the ABI after 
> they've been exposed in the SoC DT. If that's not an issue - sure: I can 
> add them in a separate series.

An ABI change would be _changing_ the domain-ids in the rk3128-power.h
I think :-) .

Right now the existing domain ids in the header are already exposed to the
world, so someone could already use them, but not the new ones.



Heiko

> > And a second series with
> > - patch1 from here
> > - a dts patch adding the additional pm-domains to rk3128.dtsi
> > - I guess patch1 also should be split into a patch adding the binding-ids
> >    and a separate patch for the code addition.
> 
> Yeah, I noticed this also :)
> 
> Regards,
> 
> Alex
> 
> >
> >
> > Heiko
> >
> >> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >> ---
> >>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>   1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> index 4e8b38604ecd..b72905db04f7 100644
> >> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/interrupt-controller/irq.h>
> >>   #include <dt-bindings/pinctrl/rockchip.h>
> >> +#include <dt-bindings/power/rk3128-power.h>
> >>   
> >>   / {
> >>   	compatible = "rockchip,rk3128";
> >> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>   	pmu: syscon@100a0000 {
> >>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>   		reg = <0x100a0000 0x1000>;
> >> +
> >> +		power: power-controller {
> >> +			compatible = "rockchip,rk3128-power-controller";
> >> +			#power-domain-cells = <1>;
> >> +			#address-cells = <1>;
> >> +			#size-cells = <0>;
> >> +
> >> +			power-domain@RK3128_PD_VIO {
> >> +				reg = <RK3128_PD_VIO>;
> >> +				clocks = <&cru ACLK_CIF>,
> >> +					 <&cru HCLK_CIF>,
> >> +					 <&cru DCLK_EBC>,
> >> +					 <&cru HCLK_EBC>,
> >> +					 <&cru ACLK_IEP>,
> >> +					 <&cru HCLK_IEP>,
> >> +					 <&cru ACLK_LCDC0>,
> >> +					 <&cru HCLK_LCDC0>,
> >> +					 <&cru PCLK_MIPI>,
> >> +					 <&cru ACLK_RGA>,
> >> +					 <&cru HCLK_RGA>,
> >> +					 <&cru ACLK_VIO0>,
> >> +					 <&cru ACLK_VIO1>,
> >> +					 <&cru HCLK_VIO>,
> >> +					 <&cru HCLK_VIO_H2P>,
> >> +					 <&cru DCLK_VOP>,
> >> +					 <&cru SCLK_VOP>;
> >> +				pm_qos = <&qos_ebc>,
> >> +					 <&qos_iep>,
> >> +					 <&qos_lcdc>,
> >> +					 <&qos_rga>,
> >> +					 <&qos_vip>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_VIDEO {
> >> +				reg = <RK3128_PD_VIDEO>;
> >> +				clocks = <&cru ACLK_VDPU>,
> >> +					 <&cru HCLK_VDPU>,
> >> +					 <&cru ACLK_VEPU>,
> >> +					 <&cru HCLK_VEPU>,
> >> +					 <&cru SCLK_HEVC_CORE>;
> >> +				pm_qos = <&qos_vpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_GPU {
> >> +				reg = <RK3128_PD_GPU>;
> >> +				clocks = <&cru ACLK_GPU>;
> >> +				pm_qos = <&qos_gpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_CRYPTO {
> >> +				reg = <RK3128_PD_CRYPTO>;
> >> +				clocks = <&cru HCLK_CRYPTO>,
> >> +					 <&cru SCLK_CRYPTO>;
> >> +				pm_qos = <&qos_crypto>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +		};
> >> +	};
> >> +
> >> +	qos_crypto: qos@10128080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x10128080 0x20>;
> >> +	};
> >> +
> >> +	qos_gpu: qos@1012d000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012d000 0x20>;
> >> +	};
> >> +
> >> +	qos_vpu: qos@1012e000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012e000 0x20>;
> >> +	};
> >> +
> >> +	qos_rga: qos@1012f000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f000 0x20>;
> >> +	};
> >> +
> >> +	qos_ebc: qos@1012f080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f080 0x20>;
> >> +	};
> >> +
> >> +	qos_iep: qos@1012f100 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f100 0x20>;
> >> +	};
> >> +
> >> +	qos_lcdc: qos@1012f180 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f180 0x20>;
> >> +	};
> >> +
> >> +	qos_vip: qos@1012f200 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f200 0x20>;
> >>   	};
> >>   
> >>   	gic: interrupt-controller@10139000 {
> >>
> >
> >
> >
> 





_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >> Add power controller and qos nodes for RK3128 in order to use
> >> them as powerdomains.
> > does the power-domain controller work with the incomplete set of
> > pm-domains too?
> 
> Yes, it does - the missing domains can request idle only and can't be 
> powered on/off - if no one requests idle they are just up all the time.
> 
> > What I have in mind is
> > - adding the power-controller node with the existing set of power-domains
> > - the gpu pm-domain is in there
> > - adding the gpu parts
> 
> My main concern about adding them later was the change of the ABI after 
> they've been exposed in the SoC DT. If that's not an issue - sure: I can 
> add them in a separate series.

An ABI change would be _changing_ the domain-ids in the rk3128-power.h
I think :-) .

Right now the existing domain ids in the header are already exposed to the
world, so someone could already use them, but not the new ones.



Heiko

> > And a second series with
> > - patch1 from here
> > - a dts patch adding the additional pm-domains to rk3128.dtsi
> > - I guess patch1 also should be split into a patch adding the binding-ids
> >    and a separate patch for the code addition.
> 
> Yeah, I noticed this also :)
> 
> Regards,
> 
> Alex
> 
> >
> >
> > Heiko
> >
> >> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >> ---
> >>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>   1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> index 4e8b38604ecd..b72905db04f7 100644
> >> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/interrupt-controller/irq.h>
> >>   #include <dt-bindings/pinctrl/rockchip.h>
> >> +#include <dt-bindings/power/rk3128-power.h>
> >>   
> >>   / {
> >>   	compatible = "rockchip,rk3128";
> >> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>   	pmu: syscon@100a0000 {
> >>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>   		reg = <0x100a0000 0x1000>;
> >> +
> >> +		power: power-controller {
> >> +			compatible = "rockchip,rk3128-power-controller";
> >> +			#power-domain-cells = <1>;
> >> +			#address-cells = <1>;
> >> +			#size-cells = <0>;
> >> +
> >> +			power-domain@RK3128_PD_VIO {
> >> +				reg = <RK3128_PD_VIO>;
> >> +				clocks = <&cru ACLK_CIF>,
> >> +					 <&cru HCLK_CIF>,
> >> +					 <&cru DCLK_EBC>,
> >> +					 <&cru HCLK_EBC>,
> >> +					 <&cru ACLK_IEP>,
> >> +					 <&cru HCLK_IEP>,
> >> +					 <&cru ACLK_LCDC0>,
> >> +					 <&cru HCLK_LCDC0>,
> >> +					 <&cru PCLK_MIPI>,
> >> +					 <&cru ACLK_RGA>,
> >> +					 <&cru HCLK_RGA>,
> >> +					 <&cru ACLK_VIO0>,
> >> +					 <&cru ACLK_VIO1>,
> >> +					 <&cru HCLK_VIO>,
> >> +					 <&cru HCLK_VIO_H2P>,
> >> +					 <&cru DCLK_VOP>,
> >> +					 <&cru SCLK_VOP>;
> >> +				pm_qos = <&qos_ebc>,
> >> +					 <&qos_iep>,
> >> +					 <&qos_lcdc>,
> >> +					 <&qos_rga>,
> >> +					 <&qos_vip>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_VIDEO {
> >> +				reg = <RK3128_PD_VIDEO>;
> >> +				clocks = <&cru ACLK_VDPU>,
> >> +					 <&cru HCLK_VDPU>,
> >> +					 <&cru ACLK_VEPU>,
> >> +					 <&cru HCLK_VEPU>,
> >> +					 <&cru SCLK_HEVC_CORE>;
> >> +				pm_qos = <&qos_vpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_GPU {
> >> +				reg = <RK3128_PD_GPU>;
> >> +				clocks = <&cru ACLK_GPU>;
> >> +				pm_qos = <&qos_gpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_CRYPTO {
> >> +				reg = <RK3128_PD_CRYPTO>;
> >> +				clocks = <&cru HCLK_CRYPTO>,
> >> +					 <&cru SCLK_CRYPTO>;
> >> +				pm_qos = <&qos_crypto>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +		};
> >> +	};
> >> +
> >> +	qos_crypto: qos@10128080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x10128080 0x20>;
> >> +	};
> >> +
> >> +	qos_gpu: qos@1012d000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012d000 0x20>;
> >> +	};
> >> +
> >> +	qos_vpu: qos@1012e000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012e000 0x20>;
> >> +	};
> >> +
> >> +	qos_rga: qos@1012f000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f000 0x20>;
> >> +	};
> >> +
> >> +	qos_ebc: qos@1012f080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f080 0x20>;
> >> +	};
> >> +
> >> +	qos_iep: qos@1012f100 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f100 0x20>;
> >> +	};
> >> +
> >> +	qos_lcdc: qos@1012f180 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f180 0x20>;
> >> +	};
> >> +
> >> +	qos_vip: qos@1012f200 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f200 0x20>;
> >>   	};
> >>   
> >>   	gic: interrupt-controller@10139000 {
> >>
> >
> >
> >
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >> Add power controller and qos nodes for RK3128 in order to use
> >> them as powerdomains.
> > does the power-domain controller work with the incomplete set of
> > pm-domains too?
> 
> Yes, it does - the missing domains can request idle only and can't be 
> powered on/off - if no one requests idle they are just up all the time.
> 
> > What I have in mind is
> > - adding the power-controller node with the existing set of power-domains
> > - the gpu pm-domain is in there
> > - adding the gpu parts
> 
> My main concern about adding them later was the change of the ABI after 
> they've been exposed in the SoC DT. If that's not an issue - sure: I can 
> add them in a separate series.

An ABI change would be _changing_ the domain-ids in the rk3128-power.h
I think :-) .

Right now the existing domain ids in the header are already exposed to the
world, so someone could already use them, but not the new ones.



Heiko

> > And a second series with
> > - patch1 from here
> > - a dts patch adding the additional pm-domains to rk3128.dtsi
> > - I guess patch1 also should be split into a patch adding the binding-ids
> >    and a separate patch for the code addition.
> 
> Yeah, I noticed this also :)
> 
> Regards,
> 
> Alex
> 
> >
> >
> > Heiko
> >
> >> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >> ---
> >>   arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>   1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> index 4e8b38604ecd..b72905db04f7 100644
> >> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> @@ -8,6 +8,7 @@
> >>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>   #include <dt-bindings/interrupt-controller/irq.h>
> >>   #include <dt-bindings/pinctrl/rockchip.h>
> >> +#include <dt-bindings/power/rk3128-power.h>
> >>   
> >>   / {
> >>   	compatible = "rockchip,rk3128";
> >> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>   	pmu: syscon@100a0000 {
> >>   		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>   		reg = <0x100a0000 0x1000>;
> >> +
> >> +		power: power-controller {
> >> +			compatible = "rockchip,rk3128-power-controller";
> >> +			#power-domain-cells = <1>;
> >> +			#address-cells = <1>;
> >> +			#size-cells = <0>;
> >> +
> >> +			power-domain@RK3128_PD_VIO {
> >> +				reg = <RK3128_PD_VIO>;
> >> +				clocks = <&cru ACLK_CIF>,
> >> +					 <&cru HCLK_CIF>,
> >> +					 <&cru DCLK_EBC>,
> >> +					 <&cru HCLK_EBC>,
> >> +					 <&cru ACLK_IEP>,
> >> +					 <&cru HCLK_IEP>,
> >> +					 <&cru ACLK_LCDC0>,
> >> +					 <&cru HCLK_LCDC0>,
> >> +					 <&cru PCLK_MIPI>,
> >> +					 <&cru ACLK_RGA>,
> >> +					 <&cru HCLK_RGA>,
> >> +					 <&cru ACLK_VIO0>,
> >> +					 <&cru ACLK_VIO1>,
> >> +					 <&cru HCLK_VIO>,
> >> +					 <&cru HCLK_VIO_H2P>,
> >> +					 <&cru DCLK_VOP>,
> >> +					 <&cru SCLK_VOP>;
> >> +				pm_qos = <&qos_ebc>,
> >> +					 <&qos_iep>,
> >> +					 <&qos_lcdc>,
> >> +					 <&qos_rga>,
> >> +					 <&qos_vip>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_VIDEO {
> >> +				reg = <RK3128_PD_VIDEO>;
> >> +				clocks = <&cru ACLK_VDPU>,
> >> +					 <&cru HCLK_VDPU>,
> >> +					 <&cru ACLK_VEPU>,
> >> +					 <&cru HCLK_VEPU>,
> >> +					 <&cru SCLK_HEVC_CORE>;
> >> +				pm_qos = <&qos_vpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_GPU {
> >> +				reg = <RK3128_PD_GPU>;
> >> +				clocks = <&cru ACLK_GPU>;
> >> +				pm_qos = <&qos_gpu>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +
> >> +			power-domain@RK3128_PD_CRYPTO {
> >> +				reg = <RK3128_PD_CRYPTO>;
> >> +				clocks = <&cru HCLK_CRYPTO>,
> >> +					 <&cru SCLK_CRYPTO>;
> >> +				pm_qos = <&qos_crypto>;
> >> +				#power-domain-cells = <0>;
> >> +			};
> >> +		};
> >> +	};
> >> +
> >> +	qos_crypto: qos@10128080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x10128080 0x20>;
> >> +	};
> >> +
> >> +	qos_gpu: qos@1012d000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012d000 0x20>;
> >> +	};
> >> +
> >> +	qos_vpu: qos@1012e000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012e000 0x20>;
> >> +	};
> >> +
> >> +	qos_rga: qos@1012f000 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f000 0x20>;
> >> +	};
> >> +
> >> +	qos_ebc: qos@1012f080 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f080 0x20>;
> >> +	};
> >> +
> >> +	qos_iep: qos@1012f100 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f100 0x20>;
> >> +	};
> >> +
> >> +	qos_lcdc: qos@1012f180 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f180 0x20>;
> >> +	};
> >> +
> >> +	qos_vip: qos@1012f200 {
> >> +		compatible = "rockchip,rk3128-qos", "syscon";
> >> +		reg = <0x1012f200 0x20>;
> >>   	};
> >>   
> >>   	gic: interrupt-controller@10139000 {
> >>
> >
> >
> >
> 





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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>> Add power controller and qos nodes for RK3128 in order to use
>>>> them as powerdomains.
>>> does the power-domain controller work with the incomplete set of
>>> pm-domains too?
>> Yes, it does - the missing domains can request idle only and can't be
>> powered on/off - if no one requests idle they are just up all the time.
>>
>>> What I have in mind is
>>> - adding the power-controller node with the existing set of power-domains
>>> - the gpu pm-domain is in there
>>> - adding the gpu parts
>> My main concern about adding them later was the change of the ABI after
>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>> add them in a separate series.
> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> I think :-) .
Well, an addition is still a change.
> Right now the existing domain ids in the header are already exposed to the
> world, so someone could already use them, but not the new ones.

I'm fully aware that nothing would ever hard fail anywhere if the new 
domain ids get added later.

Nevertheless we start using here an ABI which is known to be incomplete. 
For no reason, as the patches (which I am now asked to remove from this 
series) for completion are already there (here).

Anyway, if you prefer it this way: I'm pleased to do so.

Alex

>
> Heiko
>
>>> And a second series with
>>> - patch1 from here
>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>     and a separate patch for the code addition.
>> Yeah, I noticed this also :)
>>
>> Regards,
>>
>> Alex
>>
>>>
>>> Heiko
>>>
>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>> ---
>>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>    1 file changed, 101 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> @@ -8,6 +8,7 @@
>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>    #include <dt-bindings/interrupt-controller/irq.h>
>>>>    #include <dt-bindings/pinctrl/rockchip.h>
>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>    
>>>>    / {
>>>>    	compatible = "rockchip,rk3128";
>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>    	pmu: syscon@100a0000 {
>>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>    		reg = <0x100a0000 0x1000>;
>>>> +
>>>> +		power: power-controller {
>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>> +			#power-domain-cells = <1>;
>>>> +			#address-cells = <1>;
>>>> +			#size-cells = <0>;
>>>> +
>>>> +			power-domain@RK3128_PD_VIO {
>>>> +				reg = <RK3128_PD_VIO>;
>>>> +				clocks = <&cru ACLK_CIF>,
>>>> +					 <&cru HCLK_CIF>,
>>>> +					 <&cru DCLK_EBC>,
>>>> +					 <&cru HCLK_EBC>,
>>>> +					 <&cru ACLK_IEP>,
>>>> +					 <&cru HCLK_IEP>,
>>>> +					 <&cru ACLK_LCDC0>,
>>>> +					 <&cru HCLK_LCDC0>,
>>>> +					 <&cru PCLK_MIPI>,
>>>> +					 <&cru ACLK_RGA>,
>>>> +					 <&cru HCLK_RGA>,
>>>> +					 <&cru ACLK_VIO0>,
>>>> +					 <&cru ACLK_VIO1>,
>>>> +					 <&cru HCLK_VIO>,
>>>> +					 <&cru HCLK_VIO_H2P>,
>>>> +					 <&cru DCLK_VOP>,
>>>> +					 <&cru SCLK_VOP>;
>>>> +				pm_qos = <&qos_ebc>,
>>>> +					 <&qos_iep>,
>>>> +					 <&qos_lcdc>,
>>>> +					 <&qos_rga>,
>>>> +					 <&qos_vip>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_VIDEO {
>>>> +				reg = <RK3128_PD_VIDEO>;
>>>> +				clocks = <&cru ACLK_VDPU>,
>>>> +					 <&cru HCLK_VDPU>,
>>>> +					 <&cru ACLK_VEPU>,
>>>> +					 <&cru HCLK_VEPU>,
>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>> +				pm_qos = <&qos_vpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_GPU {
>>>> +				reg = <RK3128_PD_GPU>;
>>>> +				clocks = <&cru ACLK_GPU>;
>>>> +				pm_qos = <&qos_gpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>> +					 <&cru SCLK_CRYPTO>;
>>>> +				pm_qos = <&qos_crypto>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +		};
>>>> +	};
>>>> +
>>>> +	qos_crypto: qos@10128080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x10128080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_gpu: qos@1012d000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012d000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vpu: qos@1012e000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012e000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_rga: qos@1012f000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_ebc: qos@1012f080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_iep: qos@1012f100 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f100 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_lcdc: qos@1012f180 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f180 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vip: qos@1012f200 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f200 0x20>;
>>>>    	};
>>>>    
>>>>    	gic: interrupt-controller@10139000 {
>>>>
>>>
>>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>> Add power controller and qos nodes for RK3128 in order to use
>>>> them as powerdomains.
>>> does the power-domain controller work with the incomplete set of
>>> pm-domains too?
>> Yes, it does - the missing domains can request idle only and can't be
>> powered on/off - if no one requests idle they are just up all the time.
>>
>>> What I have in mind is
>>> - adding the power-controller node with the existing set of power-domains
>>> - the gpu pm-domain is in there
>>> - adding the gpu parts
>> My main concern about adding them later was the change of the ABI after
>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>> add them in a separate series.
> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> I think :-) .
Well, an addition is still a change.
> Right now the existing domain ids in the header are already exposed to the
> world, so someone could already use them, but not the new ones.

I'm fully aware that nothing would ever hard fail anywhere if the new 
domain ids get added later.

Nevertheless we start using here an ABI which is known to be incomplete. 
For no reason, as the patches (which I am now asked to remove from this 
series) for completion are already there (here).

Anyway, if you prefer it this way: I'm pleased to do so.

Alex

>
> Heiko
>
>>> And a second series with
>>> - patch1 from here
>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>     and a separate patch for the code addition.
>> Yeah, I noticed this also :)
>>
>> Regards,
>>
>> Alex
>>
>>>
>>> Heiko
>>>
>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>> ---
>>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>    1 file changed, 101 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> @@ -8,6 +8,7 @@
>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>    #include <dt-bindings/interrupt-controller/irq.h>
>>>>    #include <dt-bindings/pinctrl/rockchip.h>
>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>    
>>>>    / {
>>>>    	compatible = "rockchip,rk3128";
>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>    	pmu: syscon@100a0000 {
>>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>    		reg = <0x100a0000 0x1000>;
>>>> +
>>>> +		power: power-controller {
>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>> +			#power-domain-cells = <1>;
>>>> +			#address-cells = <1>;
>>>> +			#size-cells = <0>;
>>>> +
>>>> +			power-domain@RK3128_PD_VIO {
>>>> +				reg = <RK3128_PD_VIO>;
>>>> +				clocks = <&cru ACLK_CIF>,
>>>> +					 <&cru HCLK_CIF>,
>>>> +					 <&cru DCLK_EBC>,
>>>> +					 <&cru HCLK_EBC>,
>>>> +					 <&cru ACLK_IEP>,
>>>> +					 <&cru HCLK_IEP>,
>>>> +					 <&cru ACLK_LCDC0>,
>>>> +					 <&cru HCLK_LCDC0>,
>>>> +					 <&cru PCLK_MIPI>,
>>>> +					 <&cru ACLK_RGA>,
>>>> +					 <&cru HCLK_RGA>,
>>>> +					 <&cru ACLK_VIO0>,
>>>> +					 <&cru ACLK_VIO1>,
>>>> +					 <&cru HCLK_VIO>,
>>>> +					 <&cru HCLK_VIO_H2P>,
>>>> +					 <&cru DCLK_VOP>,
>>>> +					 <&cru SCLK_VOP>;
>>>> +				pm_qos = <&qos_ebc>,
>>>> +					 <&qos_iep>,
>>>> +					 <&qos_lcdc>,
>>>> +					 <&qos_rga>,
>>>> +					 <&qos_vip>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_VIDEO {
>>>> +				reg = <RK3128_PD_VIDEO>;
>>>> +				clocks = <&cru ACLK_VDPU>,
>>>> +					 <&cru HCLK_VDPU>,
>>>> +					 <&cru ACLK_VEPU>,
>>>> +					 <&cru HCLK_VEPU>,
>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>> +				pm_qos = <&qos_vpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_GPU {
>>>> +				reg = <RK3128_PD_GPU>;
>>>> +				clocks = <&cru ACLK_GPU>;
>>>> +				pm_qos = <&qos_gpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>> +					 <&cru SCLK_CRYPTO>;
>>>> +				pm_qos = <&qos_crypto>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +		};
>>>> +	};
>>>> +
>>>> +	qos_crypto: qos@10128080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x10128080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_gpu: qos@1012d000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012d000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vpu: qos@1012e000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012e000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_rga: qos@1012f000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_ebc: qos@1012f080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_iep: qos@1012f100 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f100 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_lcdc: qos@1012f180 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f180 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vip: qos@1012f200 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f200 0x20>;
>>>>    	};
>>>>    
>>>>    	gic: interrupt-controller@10139000 {
>>>>
>>>
>>>
>
>
>

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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>> Add power controller and qos nodes for RK3128 in order to use
>>>> them as powerdomains.
>>> does the power-domain controller work with the incomplete set of
>>> pm-domains too?
>> Yes, it does - the missing domains can request idle only and can't be
>> powered on/off - if no one requests idle they are just up all the time.
>>
>>> What I have in mind is
>>> - adding the power-controller node with the existing set of power-domains
>>> - the gpu pm-domain is in there
>>> - adding the gpu parts
>> My main concern about adding them later was the change of the ABI after
>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>> add them in a separate series.
> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> I think :-) .
Well, an addition is still a change.
> Right now the existing domain ids in the header are already exposed to the
> world, so someone could already use them, but not the new ones.

I'm fully aware that nothing would ever hard fail anywhere if the new 
domain ids get added later.

Nevertheless we start using here an ABI which is known to be incomplete. 
For no reason, as the patches (which I am now asked to remove from this 
series) for completion are already there (here).

Anyway, if you prefer it this way: I'm pleased to do so.

Alex

>
> Heiko
>
>>> And a second series with
>>> - patch1 from here
>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>     and a separate patch for the code addition.
>> Yeah, I noticed this also :)
>>
>> Regards,
>>
>> Alex
>>
>>>
>>> Heiko
>>>
>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>> ---
>>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>    1 file changed, 101 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> @@ -8,6 +8,7 @@
>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>    #include <dt-bindings/interrupt-controller/irq.h>
>>>>    #include <dt-bindings/pinctrl/rockchip.h>
>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>    
>>>>    / {
>>>>    	compatible = "rockchip,rk3128";
>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>    	pmu: syscon@100a0000 {
>>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>    		reg = <0x100a0000 0x1000>;
>>>> +
>>>> +		power: power-controller {
>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>> +			#power-domain-cells = <1>;
>>>> +			#address-cells = <1>;
>>>> +			#size-cells = <0>;
>>>> +
>>>> +			power-domain@RK3128_PD_VIO {
>>>> +				reg = <RK3128_PD_VIO>;
>>>> +				clocks = <&cru ACLK_CIF>,
>>>> +					 <&cru HCLK_CIF>,
>>>> +					 <&cru DCLK_EBC>,
>>>> +					 <&cru HCLK_EBC>,
>>>> +					 <&cru ACLK_IEP>,
>>>> +					 <&cru HCLK_IEP>,
>>>> +					 <&cru ACLK_LCDC0>,
>>>> +					 <&cru HCLK_LCDC0>,
>>>> +					 <&cru PCLK_MIPI>,
>>>> +					 <&cru ACLK_RGA>,
>>>> +					 <&cru HCLK_RGA>,
>>>> +					 <&cru ACLK_VIO0>,
>>>> +					 <&cru ACLK_VIO1>,
>>>> +					 <&cru HCLK_VIO>,
>>>> +					 <&cru HCLK_VIO_H2P>,
>>>> +					 <&cru DCLK_VOP>,
>>>> +					 <&cru SCLK_VOP>;
>>>> +				pm_qos = <&qos_ebc>,
>>>> +					 <&qos_iep>,
>>>> +					 <&qos_lcdc>,
>>>> +					 <&qos_rga>,
>>>> +					 <&qos_vip>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_VIDEO {
>>>> +				reg = <RK3128_PD_VIDEO>;
>>>> +				clocks = <&cru ACLK_VDPU>,
>>>> +					 <&cru HCLK_VDPU>,
>>>> +					 <&cru ACLK_VEPU>,
>>>> +					 <&cru HCLK_VEPU>,
>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>> +				pm_qos = <&qos_vpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_GPU {
>>>> +				reg = <RK3128_PD_GPU>;
>>>> +				clocks = <&cru ACLK_GPU>;
>>>> +				pm_qos = <&qos_gpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>> +					 <&cru SCLK_CRYPTO>;
>>>> +				pm_qos = <&qos_crypto>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +		};
>>>> +	};
>>>> +
>>>> +	qos_crypto: qos@10128080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x10128080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_gpu: qos@1012d000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012d000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vpu: qos@1012e000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012e000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_rga: qos@1012f000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_ebc: qos@1012f080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_iep: qos@1012f100 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f100 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_lcdc: qos@1012f180 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f180 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vip: qos@1012f200 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f200 0x20>;
>>>>    	};
>>>>    
>>>>    	gic: interrupt-controller@10139000 {
>>>>
>>>
>>>
>
>
>

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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>> Add power controller and qos nodes for RK3128 in order to use
>>>> them as powerdomains.
>>> does the power-domain controller work with the incomplete set of
>>> pm-domains too?
>> Yes, it does - the missing domains can request idle only and can't be
>> powered on/off - if no one requests idle they are just up all the time.
>>
>>> What I have in mind is
>>> - adding the power-controller node with the existing set of power-domains
>>> - the gpu pm-domain is in there
>>> - adding the gpu parts
>> My main concern about adding them later was the change of the ABI after
>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>> add them in a separate series.
> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> I think :-) .
Well, an addition is still a change.
> Right now the existing domain ids in the header are already exposed to the
> world, so someone could already use them, but not the new ones.

I'm fully aware that nothing would ever hard fail anywhere if the new 
domain ids get added later.

Nevertheless we start using here an ABI which is known to be incomplete. 
For no reason, as the patches (which I am now asked to remove from this 
series) for completion are already there (here).

Anyway, if you prefer it this way: I'm pleased to do so.

Alex

>
> Heiko
>
>>> And a second series with
>>> - patch1 from here
>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>     and a separate patch for the code addition.
>> Yeah, I noticed this also :)
>>
>> Regards,
>>
>> Alex
>>
>>>
>>> Heiko
>>>
>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>> ---
>>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>    1 file changed, 101 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>> @@ -8,6 +8,7 @@
>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>    #include <dt-bindings/interrupt-controller/irq.h>
>>>>    #include <dt-bindings/pinctrl/rockchip.h>
>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>    
>>>>    / {
>>>>    	compatible = "rockchip,rk3128";
>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>    	pmu: syscon@100a0000 {
>>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>    		reg = <0x100a0000 0x1000>;
>>>> +
>>>> +		power: power-controller {
>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>> +			#power-domain-cells = <1>;
>>>> +			#address-cells = <1>;
>>>> +			#size-cells = <0>;
>>>> +
>>>> +			power-domain@RK3128_PD_VIO {
>>>> +				reg = <RK3128_PD_VIO>;
>>>> +				clocks = <&cru ACLK_CIF>,
>>>> +					 <&cru HCLK_CIF>,
>>>> +					 <&cru DCLK_EBC>,
>>>> +					 <&cru HCLK_EBC>,
>>>> +					 <&cru ACLK_IEP>,
>>>> +					 <&cru HCLK_IEP>,
>>>> +					 <&cru ACLK_LCDC0>,
>>>> +					 <&cru HCLK_LCDC0>,
>>>> +					 <&cru PCLK_MIPI>,
>>>> +					 <&cru ACLK_RGA>,
>>>> +					 <&cru HCLK_RGA>,
>>>> +					 <&cru ACLK_VIO0>,
>>>> +					 <&cru ACLK_VIO1>,
>>>> +					 <&cru HCLK_VIO>,
>>>> +					 <&cru HCLK_VIO_H2P>,
>>>> +					 <&cru DCLK_VOP>,
>>>> +					 <&cru SCLK_VOP>;
>>>> +				pm_qos = <&qos_ebc>,
>>>> +					 <&qos_iep>,
>>>> +					 <&qos_lcdc>,
>>>> +					 <&qos_rga>,
>>>> +					 <&qos_vip>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_VIDEO {
>>>> +				reg = <RK3128_PD_VIDEO>;
>>>> +				clocks = <&cru ACLK_VDPU>,
>>>> +					 <&cru HCLK_VDPU>,
>>>> +					 <&cru ACLK_VEPU>,
>>>> +					 <&cru HCLK_VEPU>,
>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>> +				pm_qos = <&qos_vpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_GPU {
>>>> +				reg = <RK3128_PD_GPU>;
>>>> +				clocks = <&cru ACLK_GPU>;
>>>> +				pm_qos = <&qos_gpu>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +
>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>> +					 <&cru SCLK_CRYPTO>;
>>>> +				pm_qos = <&qos_crypto>;
>>>> +				#power-domain-cells = <0>;
>>>> +			};
>>>> +		};
>>>> +	};
>>>> +
>>>> +	qos_crypto: qos@10128080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x10128080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_gpu: qos@1012d000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012d000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vpu: qos@1012e000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012e000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_rga: qos@1012f000 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f000 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_ebc: qos@1012f080 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f080 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_iep: qos@1012f100 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f100 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_lcdc: qos@1012f180 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f180 0x20>;
>>>> +	};
>>>> +
>>>> +	qos_vip: qos@1012f200 {
>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>> +		reg = <0x1012f200 0x20>;
>>>>    	};
>>>>    
>>>>    	gic: interrupt-controller@10139000 {
>>>>
>>>
>>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> >> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> >>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >>>> Add power controller and qos nodes for RK3128 in order to use
> >>>> them as powerdomains.
> >>> does the power-domain controller work with the incomplete set of
> >>> pm-domains too?
> >> Yes, it does - the missing domains can request idle only and can't be
> >> powered on/off - if no one requests idle they are just up all the time.
> >>
> >>> What I have in mind is
> >>> - adding the power-controller node with the existing set of power-domains
> >>> - the gpu pm-domain is in there
> >>> - adding the gpu parts
> >> My main concern about adding them later was the change of the ABI after
> >> they've been exposed in the SoC DT. If that's not an issue - sure: I can
> >> add them in a separate series.
> > An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> > I think :-) .
> Well, an addition is still a change.
> > Right now the existing domain ids in the header are already exposed to the
> > world, so someone could already use them, but not the new ones.
> 
> I'm fully aware that nothing would ever hard fail anywhere if the new 
> domain ids get added later.
> 
> Nevertheless we start using here an ABI which is known to be incomplete. 
> For no reason, as the patches (which I am now asked to remove from this 
> series) for completion are already there (here).
> 
> Anyway, if you prefer it this way: I'm pleased to do so.

I was more thinking of accelerating the gpu-part of the series, as that
really is just waiting for the power-domain node that already has driver
support and domain-ids present.

It looks like you're feeling more strongly about that though, so I'll
definitly not pressure you ;-) .

But I guess the split into IDs and driver change should still be
done, especially as the dt-binding-header likely will want an Ack
from the DT maintainers.

And the power-domain change will go through the new pmdomain
subsystem.


Heiko


> >>> And a second series with
> >>> - patch1 from here
> >>> - a dts patch adding the additional pm-domains to rk3128.dtsi
> >>> - I guess patch1 also should be split into a patch adding the binding-ids
> >>>     and a separate patch for the code addition.
> >> Yeah, I noticed this also :)
> >>
> >> Regards,
> >>
> >> Alex
> >>
> >>>
> >>> Heiko
> >>>
> >>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >>>> ---
> >>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>>>    1 file changed, 101 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> index 4e8b38604ecd..b72905db04f7 100644
> >>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> @@ -8,6 +8,7 @@
> >>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>>>    #include <dt-bindings/pinctrl/rockchip.h>
> >>>> +#include <dt-bindings/power/rk3128-power.h>
> >>>>    
> >>>>    / {
> >>>>    	compatible = "rockchip,rk3128";
> >>>> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>>>    	pmu: syscon@100a0000 {
> >>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>>>    		reg = <0x100a0000 0x1000>;
> >>>> +
> >>>> +		power: power-controller {
> >>>> +			compatible = "rockchip,rk3128-power-controller";
> >>>> +			#power-domain-cells = <1>;
> >>>> +			#address-cells = <1>;
> >>>> +			#size-cells = <0>;
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIO {
> >>>> +				reg = <RK3128_PD_VIO>;
> >>>> +				clocks = <&cru ACLK_CIF>,
> >>>> +					 <&cru HCLK_CIF>,
> >>>> +					 <&cru DCLK_EBC>,
> >>>> +					 <&cru HCLK_EBC>,
> >>>> +					 <&cru ACLK_IEP>,
> >>>> +					 <&cru HCLK_IEP>,
> >>>> +					 <&cru ACLK_LCDC0>,
> >>>> +					 <&cru HCLK_LCDC0>,
> >>>> +					 <&cru PCLK_MIPI>,
> >>>> +					 <&cru ACLK_RGA>,
> >>>> +					 <&cru HCLK_RGA>,
> >>>> +					 <&cru ACLK_VIO0>,
> >>>> +					 <&cru ACLK_VIO1>,
> >>>> +					 <&cru HCLK_VIO>,
> >>>> +					 <&cru HCLK_VIO_H2P>,
> >>>> +					 <&cru DCLK_VOP>,
> >>>> +					 <&cru SCLK_VOP>;
> >>>> +				pm_qos = <&qos_ebc>,
> >>>> +					 <&qos_iep>,
> >>>> +					 <&qos_lcdc>,
> >>>> +					 <&qos_rga>,
> >>>> +					 <&qos_vip>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIDEO {
> >>>> +				reg = <RK3128_PD_VIDEO>;
> >>>> +				clocks = <&cru ACLK_VDPU>,
> >>>> +					 <&cru HCLK_VDPU>,
> >>>> +					 <&cru ACLK_VEPU>,
> >>>> +					 <&cru HCLK_VEPU>,
> >>>> +					 <&cru SCLK_HEVC_CORE>;
> >>>> +				pm_qos = <&qos_vpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_GPU {
> >>>> +				reg = <RK3128_PD_GPU>;
> >>>> +				clocks = <&cru ACLK_GPU>;
> >>>> +				pm_qos = <&qos_gpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_CRYPTO {
> >>>> +				reg = <RK3128_PD_CRYPTO>;
> >>>> +				clocks = <&cru HCLK_CRYPTO>,
> >>>> +					 <&cru SCLK_CRYPTO>;
> >>>> +				pm_qos = <&qos_crypto>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>> +
> >>>> +	qos_crypto: qos@10128080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x10128080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_gpu: qos@1012d000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012d000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vpu: qos@1012e000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012e000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_rga: qos@1012f000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_ebc: qos@1012f080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_iep: qos@1012f100 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f100 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_lcdc: qos@1012f180 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f180 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vip: qos@1012f200 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f200 0x20>;
> >>>>    	};
> >>>>    
> >>>>    	gic: interrupt-controller@10139000 {
> >>>>
> >>>
> >>>
> >
> >
> >
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> >> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> >>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >>>> Add power controller and qos nodes for RK3128 in order to use
> >>>> them as powerdomains.
> >>> does the power-domain controller work with the incomplete set of
> >>> pm-domains too?
> >> Yes, it does - the missing domains can request idle only and can't be
> >> powered on/off - if no one requests idle they are just up all the time.
> >>
> >>> What I have in mind is
> >>> - adding the power-controller node with the existing set of power-domains
> >>> - the gpu pm-domain is in there
> >>> - adding the gpu parts
> >> My main concern about adding them later was the change of the ABI after
> >> they've been exposed in the SoC DT. If that's not an issue - sure: I can
> >> add them in a separate series.
> > An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> > I think :-) .
> Well, an addition is still a change.
> > Right now the existing domain ids in the header are already exposed to the
> > world, so someone could already use them, but not the new ones.
> 
> I'm fully aware that nothing would ever hard fail anywhere if the new 
> domain ids get added later.
> 
> Nevertheless we start using here an ABI which is known to be incomplete. 
> For no reason, as the patches (which I am now asked to remove from this 
> series) for completion are already there (here).
> 
> Anyway, if you prefer it this way: I'm pleased to do so.

I was more thinking of accelerating the gpu-part of the series, as that
really is just waiting for the power-domain node that already has driver
support and domain-ids present.

It looks like you're feeling more strongly about that though, so I'll
definitly not pressure you ;-) .

But I guess the split into IDs and driver change should still be
done, especially as the dt-binding-header likely will want an Ack
from the DT maintainers.

And the power-domain change will go through the new pmdomain
subsystem.


Heiko


> >>> And a second series with
> >>> - patch1 from here
> >>> - a dts patch adding the additional pm-domains to rk3128.dtsi
> >>> - I guess patch1 also should be split into a patch adding the binding-ids
> >>>     and a separate patch for the code addition.
> >> Yeah, I noticed this also :)
> >>
> >> Regards,
> >>
> >> Alex
> >>
> >>>
> >>> Heiko
> >>>
> >>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >>>> ---
> >>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>>>    1 file changed, 101 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> index 4e8b38604ecd..b72905db04f7 100644
> >>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> @@ -8,6 +8,7 @@
> >>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>>>    #include <dt-bindings/pinctrl/rockchip.h>
> >>>> +#include <dt-bindings/power/rk3128-power.h>
> >>>>    
> >>>>    / {
> >>>>    	compatible = "rockchip,rk3128";
> >>>> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>>>    	pmu: syscon@100a0000 {
> >>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>>>    		reg = <0x100a0000 0x1000>;
> >>>> +
> >>>> +		power: power-controller {
> >>>> +			compatible = "rockchip,rk3128-power-controller";
> >>>> +			#power-domain-cells = <1>;
> >>>> +			#address-cells = <1>;
> >>>> +			#size-cells = <0>;
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIO {
> >>>> +				reg = <RK3128_PD_VIO>;
> >>>> +				clocks = <&cru ACLK_CIF>,
> >>>> +					 <&cru HCLK_CIF>,
> >>>> +					 <&cru DCLK_EBC>,
> >>>> +					 <&cru HCLK_EBC>,
> >>>> +					 <&cru ACLK_IEP>,
> >>>> +					 <&cru HCLK_IEP>,
> >>>> +					 <&cru ACLK_LCDC0>,
> >>>> +					 <&cru HCLK_LCDC0>,
> >>>> +					 <&cru PCLK_MIPI>,
> >>>> +					 <&cru ACLK_RGA>,
> >>>> +					 <&cru HCLK_RGA>,
> >>>> +					 <&cru ACLK_VIO0>,
> >>>> +					 <&cru ACLK_VIO1>,
> >>>> +					 <&cru HCLK_VIO>,
> >>>> +					 <&cru HCLK_VIO_H2P>,
> >>>> +					 <&cru DCLK_VOP>,
> >>>> +					 <&cru SCLK_VOP>;
> >>>> +				pm_qos = <&qos_ebc>,
> >>>> +					 <&qos_iep>,
> >>>> +					 <&qos_lcdc>,
> >>>> +					 <&qos_rga>,
> >>>> +					 <&qos_vip>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIDEO {
> >>>> +				reg = <RK3128_PD_VIDEO>;
> >>>> +				clocks = <&cru ACLK_VDPU>,
> >>>> +					 <&cru HCLK_VDPU>,
> >>>> +					 <&cru ACLK_VEPU>,
> >>>> +					 <&cru HCLK_VEPU>,
> >>>> +					 <&cru SCLK_HEVC_CORE>;
> >>>> +				pm_qos = <&qos_vpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_GPU {
> >>>> +				reg = <RK3128_PD_GPU>;
> >>>> +				clocks = <&cru ACLK_GPU>;
> >>>> +				pm_qos = <&qos_gpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_CRYPTO {
> >>>> +				reg = <RK3128_PD_CRYPTO>;
> >>>> +				clocks = <&cru HCLK_CRYPTO>,
> >>>> +					 <&cru SCLK_CRYPTO>;
> >>>> +				pm_qos = <&qos_crypto>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>> +
> >>>> +	qos_crypto: qos@10128080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x10128080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_gpu: qos@1012d000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012d000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vpu: qos@1012e000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012e000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_rga: qos@1012f000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_ebc: qos@1012f080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_iep: qos@1012f100 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f100 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_lcdc: qos@1012f180 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f180 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vip: qos@1012f200 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f200 0x20>;
> >>>>    	};
> >>>>    
> >>>>    	gic: interrupt-controller@10139000 {
> >>>>
> >>>
> >>>
> >
> >
> >
> 





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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> >> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> >>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >>>> Add power controller and qos nodes for RK3128 in order to use
> >>>> them as powerdomains.
> >>> does the power-domain controller work with the incomplete set of
> >>> pm-domains too?
> >> Yes, it does - the missing domains can request idle only and can't be
> >> powered on/off - if no one requests idle they are just up all the time.
> >>
> >>> What I have in mind is
> >>> - adding the power-controller node with the existing set of power-domains
> >>> - the gpu pm-domain is in there
> >>> - adding the gpu parts
> >> My main concern about adding them later was the change of the ABI after
> >> they've been exposed in the SoC DT. If that's not an issue - sure: I can
> >> add them in a separate series.
> > An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> > I think :-) .
> Well, an addition is still a change.
> > Right now the existing domain ids in the header are already exposed to the
> > world, so someone could already use them, but not the new ones.
> 
> I'm fully aware that nothing would ever hard fail anywhere if the new 
> domain ids get added later.
> 
> Nevertheless we start using here an ABI which is known to be incomplete. 
> For no reason, as the patches (which I am now asked to remove from this 
> series) for completion are already there (here).
> 
> Anyway, if you prefer it this way: I'm pleased to do so.

I was more thinking of accelerating the gpu-part of the series, as that
really is just waiting for the power-domain node that already has driver
support and domain-ids present.

It looks like you're feeling more strongly about that though, so I'll
definitly not pressure you ;-) .

But I guess the split into IDs and driver change should still be
done, especially as the dt-binding-header likely will want an Ack
from the DT maintainers.

And the power-domain change will go through the new pmdomain
subsystem.


Heiko


> >>> And a second series with
> >>> - patch1 from here
> >>> - a dts patch adding the additional pm-domains to rk3128.dtsi
> >>> - I guess patch1 also should be split into a patch adding the binding-ids
> >>>     and a separate patch for the code addition.
> >> Yeah, I noticed this also :)
> >>
> >> Regards,
> >>
> >> Alex
> >>
> >>>
> >>> Heiko
> >>>
> >>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >>>> ---
> >>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>>>    1 file changed, 101 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> index 4e8b38604ecd..b72905db04f7 100644
> >>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> @@ -8,6 +8,7 @@
> >>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>>>    #include <dt-bindings/pinctrl/rockchip.h>
> >>>> +#include <dt-bindings/power/rk3128-power.h>
> >>>>    
> >>>>    / {
> >>>>    	compatible = "rockchip,rk3128";
> >>>> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>>>    	pmu: syscon@100a0000 {
> >>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>>>    		reg = <0x100a0000 0x1000>;
> >>>> +
> >>>> +		power: power-controller {
> >>>> +			compatible = "rockchip,rk3128-power-controller";
> >>>> +			#power-domain-cells = <1>;
> >>>> +			#address-cells = <1>;
> >>>> +			#size-cells = <0>;
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIO {
> >>>> +				reg = <RK3128_PD_VIO>;
> >>>> +				clocks = <&cru ACLK_CIF>,
> >>>> +					 <&cru HCLK_CIF>,
> >>>> +					 <&cru DCLK_EBC>,
> >>>> +					 <&cru HCLK_EBC>,
> >>>> +					 <&cru ACLK_IEP>,
> >>>> +					 <&cru HCLK_IEP>,
> >>>> +					 <&cru ACLK_LCDC0>,
> >>>> +					 <&cru HCLK_LCDC0>,
> >>>> +					 <&cru PCLK_MIPI>,
> >>>> +					 <&cru ACLK_RGA>,
> >>>> +					 <&cru HCLK_RGA>,
> >>>> +					 <&cru ACLK_VIO0>,
> >>>> +					 <&cru ACLK_VIO1>,
> >>>> +					 <&cru HCLK_VIO>,
> >>>> +					 <&cru HCLK_VIO_H2P>,
> >>>> +					 <&cru DCLK_VOP>,
> >>>> +					 <&cru SCLK_VOP>;
> >>>> +				pm_qos = <&qos_ebc>,
> >>>> +					 <&qos_iep>,
> >>>> +					 <&qos_lcdc>,
> >>>> +					 <&qos_rga>,
> >>>> +					 <&qos_vip>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIDEO {
> >>>> +				reg = <RK3128_PD_VIDEO>;
> >>>> +				clocks = <&cru ACLK_VDPU>,
> >>>> +					 <&cru HCLK_VDPU>,
> >>>> +					 <&cru ACLK_VEPU>,
> >>>> +					 <&cru HCLK_VEPU>,
> >>>> +					 <&cru SCLK_HEVC_CORE>;
> >>>> +				pm_qos = <&qos_vpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_GPU {
> >>>> +				reg = <RK3128_PD_GPU>;
> >>>> +				clocks = <&cru ACLK_GPU>;
> >>>> +				pm_qos = <&qos_gpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_CRYPTO {
> >>>> +				reg = <RK3128_PD_CRYPTO>;
> >>>> +				clocks = <&cru HCLK_CRYPTO>,
> >>>> +					 <&cru SCLK_CRYPTO>;
> >>>> +				pm_qos = <&qos_crypto>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>> +
> >>>> +	qos_crypto: qos@10128080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x10128080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_gpu: qos@1012d000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012d000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vpu: qos@1012e000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012e000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_rga: qos@1012f000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_ebc: qos@1012f080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_iep: qos@1012f100 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f100 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_lcdc: qos@1012f180 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f180 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vip: qos@1012f200 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f200 0x20>;
> >>>>    	};
> >>>>    
> >>>>    	gic: interrupt-controller@10139000 {
> >>>>
> >>>
> >>>
> >
> >
> >
> 





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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Heiko Stübner]

Hi Alex,

Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> >> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> >>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >>>> Add power controller and qos nodes for RK3128 in order to use
> >>>> them as powerdomains.
> >>> does the power-domain controller work with the incomplete set of
> >>> pm-domains too?
> >> Yes, it does - the missing domains can request idle only and can't be
> >> powered on/off - if no one requests idle they are just up all the time.
> >>
> >>> What I have in mind is
> >>> - adding the power-controller node with the existing set of power-domains
> >>> - the gpu pm-domain is in there
> >>> - adding the gpu parts
> >> My main concern about adding them later was the change of the ABI after
> >> they've been exposed in the SoC DT. If that's not an issue - sure: I can
> >> add them in a separate series.
> > An ABI change would be _changing_ the domain-ids in the rk3128-power.h
> > I think :-) .
> Well, an addition is still a change.
> > Right now the existing domain ids in the header are already exposed to the
> > world, so someone could already use them, but not the new ones.
> 
> I'm fully aware that nothing would ever hard fail anywhere if the new 
> domain ids get added later.
> 
> Nevertheless we start using here an ABI which is known to be incomplete. 
> For no reason, as the patches (which I am now asked to remove from this 
> series) for completion are already there (here).
> 
> Anyway, if you prefer it this way: I'm pleased to do so.

I was more thinking of accelerating the gpu-part of the series, as that
really is just waiting for the power-domain node that already has driver
support and domain-ids present.

It looks like you're feeling more strongly about that though, so I'll
definitly not pressure you ;-) .

But I guess the split into IDs and driver change should still be
done, especially as the dt-binding-header likely will want an Ack
from the DT maintainers.

And the power-domain change will go through the new pmdomain
subsystem.


Heiko


> >>> And a second series with
> >>> - patch1 from here
> >>> - a dts patch adding the additional pm-domains to rk3128.dtsi
> >>> - I guess patch1 also should be split into a patch adding the binding-ids
> >>>     and a separate patch for the code addition.
> >> Yeah, I noticed this also :)
> >>
> >> Regards,
> >>
> >> Alex
> >>
> >>>
> >>> Heiko
> >>>
> >>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> >>>> ---
> >>>>    arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> >>>>    1 file changed, 101 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> index 4e8b38604ecd..b72905db04f7 100644
> >>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >>>> @@ -8,6 +8,7 @@
> >>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>    #include <dt-bindings/interrupt-controller/irq.h>
> >>>>    #include <dt-bindings/pinctrl/rockchip.h>
> >>>> +#include <dt-bindings/power/rk3128-power.h>
> >>>>    
> >>>>    / {
> >>>>    	compatible = "rockchip,rk3128";
> >>>> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>>>    	pmu: syscon@100a0000 {
> >>>>    		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>>>    		reg = <0x100a0000 0x1000>;
> >>>> +
> >>>> +		power: power-controller {
> >>>> +			compatible = "rockchip,rk3128-power-controller";
> >>>> +			#power-domain-cells = <1>;
> >>>> +			#address-cells = <1>;
> >>>> +			#size-cells = <0>;
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIO {
> >>>> +				reg = <RK3128_PD_VIO>;
> >>>> +				clocks = <&cru ACLK_CIF>,
> >>>> +					 <&cru HCLK_CIF>,
> >>>> +					 <&cru DCLK_EBC>,
> >>>> +					 <&cru HCLK_EBC>,
> >>>> +					 <&cru ACLK_IEP>,
> >>>> +					 <&cru HCLK_IEP>,
> >>>> +					 <&cru ACLK_LCDC0>,
> >>>> +					 <&cru HCLK_LCDC0>,
> >>>> +					 <&cru PCLK_MIPI>,
> >>>> +					 <&cru ACLK_RGA>,
> >>>> +					 <&cru HCLK_RGA>,
> >>>> +					 <&cru ACLK_VIO0>,
> >>>> +					 <&cru ACLK_VIO1>,
> >>>> +					 <&cru HCLK_VIO>,
> >>>> +					 <&cru HCLK_VIO_H2P>,
> >>>> +					 <&cru DCLK_VOP>,
> >>>> +					 <&cru SCLK_VOP>;
> >>>> +				pm_qos = <&qos_ebc>,
> >>>> +					 <&qos_iep>,
> >>>> +					 <&qos_lcdc>,
> >>>> +					 <&qos_rga>,
> >>>> +					 <&qos_vip>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_VIDEO {
> >>>> +				reg = <RK3128_PD_VIDEO>;
> >>>> +				clocks = <&cru ACLK_VDPU>,
> >>>> +					 <&cru HCLK_VDPU>,
> >>>> +					 <&cru ACLK_VEPU>,
> >>>> +					 <&cru HCLK_VEPU>,
> >>>> +					 <&cru SCLK_HEVC_CORE>;
> >>>> +				pm_qos = <&qos_vpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_GPU {
> >>>> +				reg = <RK3128_PD_GPU>;
> >>>> +				clocks = <&cru ACLK_GPU>;
> >>>> +				pm_qos = <&qos_gpu>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +
> >>>> +			power-domain@RK3128_PD_CRYPTO {
> >>>> +				reg = <RK3128_PD_CRYPTO>;
> >>>> +				clocks = <&cru HCLK_CRYPTO>,
> >>>> +					 <&cru SCLK_CRYPTO>;
> >>>> +				pm_qos = <&qos_crypto>;
> >>>> +				#power-domain-cells = <0>;
> >>>> +			};
> >>>> +		};
> >>>> +	};
> >>>> +
> >>>> +	qos_crypto: qos@10128080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x10128080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_gpu: qos@1012d000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012d000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vpu: qos@1012e000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012e000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_rga: qos@1012f000 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f000 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_ebc: qos@1012f080 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f080 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_iep: qos@1012f100 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f100 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_lcdc: qos@1012f180 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f180 0x20>;
> >>>> +	};
> >>>> +
> >>>> +	qos_vip: qos@1012f200 {
> >>>> +		compatible = "rockchip,rk3128-qos", "syscon";
> >>>> +		reg = <0x1012f200 0x20>;
> >>>>    	};
> >>>>    
> >>>>    	gic: interrupt-controller@10139000 {
> >>>>
> >>>
> >>>
> >
> >
> >
> 

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 03.12.23 um 17:42 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
>> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>>>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>>>> Add power controller and qos nodes for RK3128 in order to use
>>>>>> them as powerdomains.
>>>>> does the power-domain controller work with the incomplete set of
>>>>> pm-domains too?
>>>> Yes, it does - the missing domains can request idle only and can't be
>>>> powered on/off - if no one requests idle they are just up all the time.
>>>>
>>>>> What I have in mind is
>>>>> - adding the power-controller node with the existing set of power-domains
>>>>> - the gpu pm-domain is in there
>>>>> - adding the gpu parts
>>>> My main concern about adding them later was the change of the ABI after
>>>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>>>> add them in a separate series.
>>> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
>>> I think :-) .
>> Well, an addition is still a change.
>>> Right now the existing domain ids in the header are already exposed to the
>>> world, so someone could already use them, but not the new ones.
>> I'm fully aware that nothing would ever hard fail anywhere if the new
>> domain ids get added later.
>>
>> Nevertheless we start using here an ABI which is known to be incomplete.
>> For no reason, as the patches (which I am now asked to remove from this
>> series) for completion are already there (here).
>>
>> Anyway, if you prefer it this way: I'm pleased to do so.
> I was more thinking of accelerating the gpu-part of the series, as that
> really is just waiting for the power-domain node that already has driver
> support and domain-ids present.
>
> It looks like you're feeling more strongly about that though, so I'll
> definitly not pressure you ;-) .

I'm really not insisting on this - I just didn't understand why you 
would want this. And honestly I haven't considered merging timeline as 
an argument.

So sure: Let's get the low hanging fruits merged for 6.8. Having the 
power domains in the DT will also help for my upcoming hdmi / vop series.

Alex

>
> But I guess the split into IDs and driver change should still be
> done, especially as the dt-binding-header likely will want an Ack
> from the DT maintainers.
>
> And the power-domain change will go through the new pmdomain
> subsystem.
>
>
> Heiko
>
>
>>>>> And a second series with
>>>>> - patch1 from here
>>>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>>>      and a separate patch for the code addition.
>>>> Yeah, I noticed this also :)
>>>>
>>>> Regards,
>>>>
>>>> Alex
>>>>
>>>>> Heiko
>>>>>
>>>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>>>> ---
>>>>>>     arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>>>     1 file changed, 101 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> @@ -8,6 +8,7 @@
>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>     #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>     #include <dt-bindings/pinctrl/rockchip.h>
>>>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>>>     
>>>>>>     / {
>>>>>>     	compatible = "rockchip,rk3128";
>>>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>>>     	pmu: syscon@100a0000 {
>>>>>>     		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>>>     		reg = <0x100a0000 0x1000>;
>>>>>> +
>>>>>> +		power: power-controller {
>>>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>>>> +			#power-domain-cells = <1>;
>>>>>> +			#address-cells = <1>;
>>>>>> +			#size-cells = <0>;
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIO {
>>>>>> +				reg = <RK3128_PD_VIO>;
>>>>>> +				clocks = <&cru ACLK_CIF>,
>>>>>> +					 <&cru HCLK_CIF>,
>>>>>> +					 <&cru DCLK_EBC>,
>>>>>> +					 <&cru HCLK_EBC>,
>>>>>> +					 <&cru ACLK_IEP>,
>>>>>> +					 <&cru HCLK_IEP>,
>>>>>> +					 <&cru ACLK_LCDC0>,
>>>>>> +					 <&cru HCLK_LCDC0>,
>>>>>> +					 <&cru PCLK_MIPI>,
>>>>>> +					 <&cru ACLK_RGA>,
>>>>>> +					 <&cru HCLK_RGA>,
>>>>>> +					 <&cru ACLK_VIO0>,
>>>>>> +					 <&cru ACLK_VIO1>,
>>>>>> +					 <&cru HCLK_VIO>,
>>>>>> +					 <&cru HCLK_VIO_H2P>,
>>>>>> +					 <&cru DCLK_VOP>,
>>>>>> +					 <&cru SCLK_VOP>;
>>>>>> +				pm_qos = <&qos_ebc>,
>>>>>> +					 <&qos_iep>,
>>>>>> +					 <&qos_lcdc>,
>>>>>> +					 <&qos_rga>,
>>>>>> +					 <&qos_vip>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIDEO {
>>>>>> +				reg = <RK3128_PD_VIDEO>;
>>>>>> +				clocks = <&cru ACLK_VDPU>,
>>>>>> +					 <&cru HCLK_VDPU>,
>>>>>> +					 <&cru ACLK_VEPU>,
>>>>>> +					 <&cru HCLK_VEPU>,
>>>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>>>> +				pm_qos = <&qos_vpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_GPU {
>>>>>> +				reg = <RK3128_PD_GPU>;
>>>>>> +				clocks = <&cru ACLK_GPU>;
>>>>>> +				pm_qos = <&qos_gpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>>>> +					 <&cru SCLK_CRYPTO>;
>>>>>> +				pm_qos = <&qos_crypto>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_crypto: qos@10128080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x10128080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_gpu: qos@1012d000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012d000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vpu: qos@1012e000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012e000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_rga: qos@1012f000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_ebc: qos@1012f080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_iep: qos@1012f100 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f100 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_lcdc: qos@1012f180 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f180 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vip: qos@1012f200 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f200 0x20>;
>>>>>>     	};
>>>>>>     
>>>>>>     	gic: interrupt-controller@10139000 {
>>>>>>
>>>>>
>>>
>>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 03.12.23 um 17:42 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
>> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>>>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>>>> Add power controller and qos nodes for RK3128 in order to use
>>>>>> them as powerdomains.
>>>>> does the power-domain controller work with the incomplete set of
>>>>> pm-domains too?
>>>> Yes, it does - the missing domains can request idle only and can't be
>>>> powered on/off - if no one requests idle they are just up all the time.
>>>>
>>>>> What I have in mind is
>>>>> - adding the power-controller node with the existing set of power-domains
>>>>> - the gpu pm-domain is in there
>>>>> - adding the gpu parts
>>>> My main concern about adding them later was the change of the ABI after
>>>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>>>> add them in a separate series.
>>> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
>>> I think :-) .
>> Well, an addition is still a change.
>>> Right now the existing domain ids in the header are already exposed to the
>>> world, so someone could already use them, but not the new ones.
>> I'm fully aware that nothing would ever hard fail anywhere if the new
>> domain ids get added later.
>>
>> Nevertheless we start using here an ABI which is known to be incomplete.
>> For no reason, as the patches (which I am now asked to remove from this
>> series) for completion are already there (here).
>>
>> Anyway, if you prefer it this way: I'm pleased to do so.
> I was more thinking of accelerating the gpu-part of the series, as that
> really is just waiting for the power-domain node that already has driver
> support and domain-ids present.
>
> It looks like you're feeling more strongly about that though, so I'll
> definitly not pressure you ;-) .

I'm really not insisting on this - I just didn't understand why you 
would want this. And honestly I haven't considered merging timeline as 
an argument.

So sure: Let's get the low hanging fruits merged for 6.8. Having the 
power domains in the DT will also help for my upcoming hdmi / vop series.

Alex

>
> But I guess the split into IDs and driver change should still be
> done, especially as the dt-binding-header likely will want an Ack
> from the DT maintainers.
>
> And the power-domain change will go through the new pmdomain
> subsystem.
>
>
> Heiko
>
>
>>>>> And a second series with
>>>>> - patch1 from here
>>>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>>>      and a separate patch for the code addition.
>>>> Yeah, I noticed this also :)
>>>>
>>>> Regards,
>>>>
>>>> Alex
>>>>
>>>>> Heiko
>>>>>
>>>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>>>> ---
>>>>>>     arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>>>     1 file changed, 101 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> @@ -8,6 +8,7 @@
>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>     #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>     #include <dt-bindings/pinctrl/rockchip.h>
>>>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>>>     
>>>>>>     / {
>>>>>>     	compatible = "rockchip,rk3128";
>>>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>>>     	pmu: syscon@100a0000 {
>>>>>>     		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>>>     		reg = <0x100a0000 0x1000>;
>>>>>> +
>>>>>> +		power: power-controller {
>>>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>>>> +			#power-domain-cells = <1>;
>>>>>> +			#address-cells = <1>;
>>>>>> +			#size-cells = <0>;
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIO {
>>>>>> +				reg = <RK3128_PD_VIO>;
>>>>>> +				clocks = <&cru ACLK_CIF>,
>>>>>> +					 <&cru HCLK_CIF>,
>>>>>> +					 <&cru DCLK_EBC>,
>>>>>> +					 <&cru HCLK_EBC>,
>>>>>> +					 <&cru ACLK_IEP>,
>>>>>> +					 <&cru HCLK_IEP>,
>>>>>> +					 <&cru ACLK_LCDC0>,
>>>>>> +					 <&cru HCLK_LCDC0>,
>>>>>> +					 <&cru PCLK_MIPI>,
>>>>>> +					 <&cru ACLK_RGA>,
>>>>>> +					 <&cru HCLK_RGA>,
>>>>>> +					 <&cru ACLK_VIO0>,
>>>>>> +					 <&cru ACLK_VIO1>,
>>>>>> +					 <&cru HCLK_VIO>,
>>>>>> +					 <&cru HCLK_VIO_H2P>,
>>>>>> +					 <&cru DCLK_VOP>,
>>>>>> +					 <&cru SCLK_VOP>;
>>>>>> +				pm_qos = <&qos_ebc>,
>>>>>> +					 <&qos_iep>,
>>>>>> +					 <&qos_lcdc>,
>>>>>> +					 <&qos_rga>,
>>>>>> +					 <&qos_vip>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIDEO {
>>>>>> +				reg = <RK3128_PD_VIDEO>;
>>>>>> +				clocks = <&cru ACLK_VDPU>,
>>>>>> +					 <&cru HCLK_VDPU>,
>>>>>> +					 <&cru ACLK_VEPU>,
>>>>>> +					 <&cru HCLK_VEPU>,
>>>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>>>> +				pm_qos = <&qos_vpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_GPU {
>>>>>> +				reg = <RK3128_PD_GPU>;
>>>>>> +				clocks = <&cru ACLK_GPU>;
>>>>>> +				pm_qos = <&qos_gpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>>>> +					 <&cru SCLK_CRYPTO>;
>>>>>> +				pm_qos = <&qos_crypto>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_crypto: qos@10128080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x10128080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_gpu: qos@1012d000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012d000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vpu: qos@1012e000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012e000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_rga: qos@1012f000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_ebc: qos@1012f080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_iep: qos@1012f100 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f100 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_lcdc: qos@1012f180 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f180 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vip: qos@1012f200 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f200 0x20>;
>>>>>>     	};
>>>>>>     
>>>>>>     	gic: interrupt-controller@10139000 {
>>>>>>
>>>>>
>>>
>>>
>
>
>

_______________________________________________
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Linux-rockchip@lists.infradead.org
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Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 03.12.23 um 17:42 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
>> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>>>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>>>> Add power controller and qos nodes for RK3128 in order to use
>>>>>> them as powerdomains.
>>>>> does the power-domain controller work with the incomplete set of
>>>>> pm-domains too?
>>>> Yes, it does - the missing domains can request idle only and can't be
>>>> powered on/off - if no one requests idle they are just up all the time.
>>>>
>>>>> What I have in mind is
>>>>> - adding the power-controller node with the existing set of power-domains
>>>>> - the gpu pm-domain is in there
>>>>> - adding the gpu parts
>>>> My main concern about adding them later was the change of the ABI after
>>>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>>>> add them in a separate series.
>>> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
>>> I think :-) .
>> Well, an addition is still a change.
>>> Right now the existing domain ids in the header are already exposed to the
>>> world, so someone could already use them, but not the new ones.
>> I'm fully aware that nothing would ever hard fail anywhere if the new
>> domain ids get added later.
>>
>> Nevertheless we start using here an ABI which is known to be incomplete.
>> For no reason, as the patches (which I am now asked to remove from this
>> series) for completion are already there (here).
>>
>> Anyway, if you prefer it this way: I'm pleased to do so.
> I was more thinking of accelerating the gpu-part of the series, as that
> really is just waiting for the power-domain node that already has driver
> support and domain-ids present.
>
> It looks like you're feeling more strongly about that though, so I'll
> definitly not pressure you ;-) .

I'm really not insisting on this - I just didn't understand why you 
would want this. And honestly I haven't considered merging timeline as 
an argument.

So sure: Let's get the low hanging fruits merged for 6.8. Having the 
power domains in the DT will also help for my upcoming hdmi / vop series.

Alex

>
> But I guess the split into IDs and driver change should still be
> done, especially as the dt-binding-header likely will want an Ack
> from the DT maintainers.
>
> And the power-domain change will go through the new pmdomain
> subsystem.
>
>
> Heiko
>
>
>>>>> And a second series with
>>>>> - patch1 from here
>>>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>>>      and a separate patch for the code addition.
>>>> Yeah, I noticed this also :)
>>>>
>>>> Regards,
>>>>
>>>> Alex
>>>>
>>>>> Heiko
>>>>>
>>>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>>>> ---
>>>>>>     arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>>>     1 file changed, 101 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> @@ -8,6 +8,7 @@
>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>     #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>     #include <dt-bindings/pinctrl/rockchip.h>
>>>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>>>     
>>>>>>     / {
>>>>>>     	compatible = "rockchip,rk3128";
>>>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>>>     	pmu: syscon@100a0000 {
>>>>>>     		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>>>     		reg = <0x100a0000 0x1000>;
>>>>>> +
>>>>>> +		power: power-controller {
>>>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>>>> +			#power-domain-cells = <1>;
>>>>>> +			#address-cells = <1>;
>>>>>> +			#size-cells = <0>;
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIO {
>>>>>> +				reg = <RK3128_PD_VIO>;
>>>>>> +				clocks = <&cru ACLK_CIF>,
>>>>>> +					 <&cru HCLK_CIF>,
>>>>>> +					 <&cru DCLK_EBC>,
>>>>>> +					 <&cru HCLK_EBC>,
>>>>>> +					 <&cru ACLK_IEP>,
>>>>>> +					 <&cru HCLK_IEP>,
>>>>>> +					 <&cru ACLK_LCDC0>,
>>>>>> +					 <&cru HCLK_LCDC0>,
>>>>>> +					 <&cru PCLK_MIPI>,
>>>>>> +					 <&cru ACLK_RGA>,
>>>>>> +					 <&cru HCLK_RGA>,
>>>>>> +					 <&cru ACLK_VIO0>,
>>>>>> +					 <&cru ACLK_VIO1>,
>>>>>> +					 <&cru HCLK_VIO>,
>>>>>> +					 <&cru HCLK_VIO_H2P>,
>>>>>> +					 <&cru DCLK_VOP>,
>>>>>> +					 <&cru SCLK_VOP>;
>>>>>> +				pm_qos = <&qos_ebc>,
>>>>>> +					 <&qos_iep>,
>>>>>> +					 <&qos_lcdc>,
>>>>>> +					 <&qos_rga>,
>>>>>> +					 <&qos_vip>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIDEO {
>>>>>> +				reg = <RK3128_PD_VIDEO>;
>>>>>> +				clocks = <&cru ACLK_VDPU>,
>>>>>> +					 <&cru HCLK_VDPU>,
>>>>>> +					 <&cru ACLK_VEPU>,
>>>>>> +					 <&cru HCLK_VEPU>,
>>>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>>>> +				pm_qos = <&qos_vpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_GPU {
>>>>>> +				reg = <RK3128_PD_GPU>;
>>>>>> +				clocks = <&cru ACLK_GPU>;
>>>>>> +				pm_qos = <&qos_gpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>>>> +					 <&cru SCLK_CRYPTO>;
>>>>>> +				pm_qos = <&qos_crypto>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_crypto: qos@10128080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x10128080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_gpu: qos@1012d000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012d000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vpu: qos@1012e000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012e000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_rga: qos@1012f000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_ebc: qos@1012f080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_iep: qos@1012f100 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f100 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_lcdc: qos@1012f180 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f180 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vip: qos@1012f200 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f200 0x20>;
>>>>>>     	};
>>>>>>     
>>>>>>     	gic: interrupt-controller@10139000 {
>>>>>>
>>>>>
>>>
>>>
>
>
>

Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128

[Alex Bee]

Hi Heiko,

Am 03.12.23 um 17:42 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Sonntag, 3. Dezember 2023, 17:05:47 CET schrieb Alex Bee:
>> Am 02.12.23 um 18:46 schrieb Heiko Stübner:
>>> Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
>>>> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
>>>>> Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
>>>>>> Add power controller and qos nodes for RK3128 in order to use
>>>>>> them as powerdomains.
>>>>> does the power-domain controller work with the incomplete set of
>>>>> pm-domains too?
>>>> Yes, it does - the missing domains can request idle only and can't be
>>>> powered on/off - if no one requests idle they are just up all the time.
>>>>
>>>>> What I have in mind is
>>>>> - adding the power-controller node with the existing set of power-domains
>>>>> - the gpu pm-domain is in there
>>>>> - adding the gpu parts
>>>> My main concern about adding them later was the change of the ABI after
>>>> they've been exposed in the SoC DT. If that's not an issue - sure: I can
>>>> add them in a separate series.
>>> An ABI change would be _changing_ the domain-ids in the rk3128-power.h
>>> I think :-) .
>> Well, an addition is still a change.
>>> Right now the existing domain ids in the header are already exposed to the
>>> world, so someone could already use them, but not the new ones.
>> I'm fully aware that nothing would ever hard fail anywhere if the new
>> domain ids get added later.
>>
>> Nevertheless we start using here an ABI which is known to be incomplete.
>> For no reason, as the patches (which I am now asked to remove from this
>> series) for completion are already there (here).
>>
>> Anyway, if you prefer it this way: I'm pleased to do so.
> I was more thinking of accelerating the gpu-part of the series, as that
> really is just waiting for the power-domain node that already has driver
> support and domain-ids present.
>
> It looks like you're feeling more strongly about that though, so I'll
> definitly not pressure you ;-) .

I'm really not insisting on this - I just didn't understand why you 
would want this. And honestly I haven't considered merging timeline as 
an argument.

So sure: Let's get the low hanging fruits merged for 6.8. Having the 
power domains in the DT will also help for my upcoming hdmi / vop series.

Alex

>
> But I guess the split into IDs and driver change should still be
> done, especially as the dt-binding-header likely will want an Ack
> from the DT maintainers.
>
> And the power-domain change will go through the new pmdomain
> subsystem.
>
>
> Heiko
>
>
>>>>> And a second series with
>>>>> - patch1 from here
>>>>> - a dts patch adding the additional pm-domains to rk3128.dtsi
>>>>> - I guess patch1 also should be split into a patch adding the binding-ids
>>>>>      and a separate patch for the code addition.
>>>> Yeah, I noticed this also :)
>>>>
>>>> Regards,
>>>>
>>>> Alex
>>>>
>>>>> Heiko
>>>>>
>>>>>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>>>>>> ---
>>>>>>     arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
>>>>>>     1 file changed, 101 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> index 4e8b38604ecd..b72905db04f7 100644
>>>>>> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
>>>>>> @@ -8,6 +8,7 @@
>>>>>>     #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>>>     #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>     #include <dt-bindings/pinctrl/rockchip.h>
>>>>>> +#include <dt-bindings/power/rk3128-power.h>
>>>>>>     
>>>>>>     / {
>>>>>>     	compatible = "rockchip,rk3128";
>>>>>> @@ -133,6 +134,106 @@ smp-sram@0 {
>>>>>>     	pmu: syscon@100a0000 {
>>>>>>     		compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
>>>>>>     		reg = <0x100a0000 0x1000>;
>>>>>> +
>>>>>> +		power: power-controller {
>>>>>> +			compatible = "rockchip,rk3128-power-controller";
>>>>>> +			#power-domain-cells = <1>;
>>>>>> +			#address-cells = <1>;
>>>>>> +			#size-cells = <0>;
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIO {
>>>>>> +				reg = <RK3128_PD_VIO>;
>>>>>> +				clocks = <&cru ACLK_CIF>,
>>>>>> +					 <&cru HCLK_CIF>,
>>>>>> +					 <&cru DCLK_EBC>,
>>>>>> +					 <&cru HCLK_EBC>,
>>>>>> +					 <&cru ACLK_IEP>,
>>>>>> +					 <&cru HCLK_IEP>,
>>>>>> +					 <&cru ACLK_LCDC0>,
>>>>>> +					 <&cru HCLK_LCDC0>,
>>>>>> +					 <&cru PCLK_MIPI>,
>>>>>> +					 <&cru ACLK_RGA>,
>>>>>> +					 <&cru HCLK_RGA>,
>>>>>> +					 <&cru ACLK_VIO0>,
>>>>>> +					 <&cru ACLK_VIO1>,
>>>>>> +					 <&cru HCLK_VIO>,
>>>>>> +					 <&cru HCLK_VIO_H2P>,
>>>>>> +					 <&cru DCLK_VOP>,
>>>>>> +					 <&cru SCLK_VOP>;
>>>>>> +				pm_qos = <&qos_ebc>,
>>>>>> +					 <&qos_iep>,
>>>>>> +					 <&qos_lcdc>,
>>>>>> +					 <&qos_rga>,
>>>>>> +					 <&qos_vip>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_VIDEO {
>>>>>> +				reg = <RK3128_PD_VIDEO>;
>>>>>> +				clocks = <&cru ACLK_VDPU>,
>>>>>> +					 <&cru HCLK_VDPU>,
>>>>>> +					 <&cru ACLK_VEPU>,
>>>>>> +					 <&cru HCLK_VEPU>,
>>>>>> +					 <&cru SCLK_HEVC_CORE>;
>>>>>> +				pm_qos = <&qos_vpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_GPU {
>>>>>> +				reg = <RK3128_PD_GPU>;
>>>>>> +				clocks = <&cru ACLK_GPU>;
>>>>>> +				pm_qos = <&qos_gpu>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +
>>>>>> +			power-domain@RK3128_PD_CRYPTO {
>>>>>> +				reg = <RK3128_PD_CRYPTO>;
>>>>>> +				clocks = <&cru HCLK_CRYPTO>,
>>>>>> +					 <&cru SCLK_CRYPTO>;
>>>>>> +				pm_qos = <&qos_crypto>;
>>>>>> +				#power-domain-cells = <0>;
>>>>>> +			};
>>>>>> +		};
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_crypto: qos@10128080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x10128080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_gpu: qos@1012d000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012d000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vpu: qos@1012e000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012e000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_rga: qos@1012f000 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f000 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_ebc: qos@1012f080 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f080 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_iep: qos@1012f100 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f100 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_lcdc: qos@1012f180 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f180 0x20>;
>>>>>> +	};
>>>>>> +
>>>>>> +	qos_vip: qos@1012f200 {
>>>>>> +		compatible = "rockchip,rk3128-qos", "syscon";
>>>>>> +		reg = <0x1012f200 0x20>;
>>>>>>     	};
>>>>>>     
>>>>>>     	gic: interrupt-controller@10139000 {
>>>>>>
>>>>>
>>>
>>>
>
>
>

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Re: [PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Rob Herring]

On Sat, Dec 02, 2023 at 01:51:40PM +0100, Alex Bee wrote:
> For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
> missing.
> Add them.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
>  include/dt-bindings/power/rk3128-power.h |  3 +++

Bindings (and DT headers are bindings) should be separate patch.

Rob

Re: [PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Rob Herring]

On Sat, Dec 02, 2023 at 01:51:40PM +0100, Alex Bee wrote:
> For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
> missing.
> Add them.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
>  include/dt-bindings/power/rk3128-power.h |  3 +++

Bindings (and DT headers are bindings) should be separate patch.

Rob

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Re: [PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Rob Herring]

On Sat, Dec 02, 2023 at 01:51:40PM +0100, Alex Bee wrote:
> For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
> missing.
> Add them.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
>  include/dt-bindings/power/rk3128-power.h |  3 +++

Bindings (and DT headers are bindings) should be separate patch.

Rob

Re: [PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128

[Rob Herring]

On Sat, Dec 02, 2023 at 01:51:40PM +0100, Alex Bee wrote:
> For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
> missing.
> Add them.
> 
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
>  drivers/pmdomain/rockchip/pm-domains.c   | 13 ++++++++-----
>  include/dt-bindings/power/rk3128-power.h |  3 +++

Bindings (and DT headers are bindings) should be separate patch.

Rob

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