* [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen'
@ 2024-01-15 22:25 Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg Daniel Henrique Barboza
` (11 more replies)
0 siblings, 12 replies; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Hi,
This v2 contains changes proposed after the review from Richard. Most
notable change is in patch 11, where we simplified our lives a bit and
just calculated 'vlmax' using 'vlenb' instead of trying to use the TCG
global 'cpu_vl'.
Patch 10 also changed a bit to avoid the negative shift we were doing in
v1.
Changes from v1:
- patch 8:
- instead of shifting sew, adjust the amount of shift rights to use 'vlenb'
- patch 9:
- adjust the shifts rights to use 'vlenb' instead of shifting 'vlenb' left beforehand
- patch 10:
- calc 'max_sz' before doing shift rights to retrieve MAX_SZ()
- patches 11 and 12:
- squashed together
- calc 'vlmax' using the same logic from patch 9 in both functions
- v1 link: https://lore.kernel.org/qemu-riscv/20240112213812.173521-1-dbarboza@ventanamicro.com/
Daniel Henrique Barboza (12):
target/riscv: add 'vlenb' field in cpu->cfg
target/riscv/csr.c: use 'vlenb' instead of 'vlen'
target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
target/riscv/vector_helper.c: use 'vlenb'
target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*()
target/riscv/cpu.c: remove cpu->cfg.vlen
target/riscv/cpu.c | 12 +-
target/riscv/cpu.h | 6 +-
target/riscv/cpu_cfg.h | 2 +-
target/riscv/csr.c | 4 +-
target/riscv/gdbstub.c | 6 +-
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 +-
target/riscv/insn_trans/trans_rvv.c.inc | 152 ++++++++++-----------
target/riscv/insn_trans/trans_rvvk.c.inc | 16 +--
target/riscv/tcg/tcg-cpu.c | 4 +-
target/riscv/vector_helper.c | 26 ++--
10 files changed, 124 insertions(+), 116 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:33 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen' Daniel Henrique Barboza
` (10 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
'vlen / 8' in every instance.
In hindsight we would be better if the 'vlenb' property was introduced
instead of 'vlen'. That's not what happened, and now we can't easily get
rid of it due to user scripts all around. What we can do, however, is to
change our internal representation to use 'vlenb'.
Add a 'vlenb' field in cpu->cfg. It'll be set via the existing 'vlen'
property, i.e. setting 'vlen' will also set 'vlenb'.
We'll replace all 'vlen >> 3' code to use 'vlenb' directly. Start with
the single instance we have in target/riscv/cpu.c.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 4 +++-
target/riscv/cpu_cfg.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8d3ec74a1c..f4261d2ffc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -847,7 +847,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
csr_ops[csrno].name, val);
}
}
- uint16_t vlenb = cpu->cfg.vlen >> 3;
+ uint16_t vlenb = cpu->cfg.vlenb;
for (i = 0; i < 32; i++) {
qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
@@ -1314,6 +1314,7 @@ static void riscv_cpu_init(Object *obj)
/* Default values for non-bool cpu properties */
cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
cpu->cfg.vlen = 128;
+ cpu->cfg.vlenb = 128 >> 3;
cpu->cfg.elen = 64;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
}
@@ -1810,6 +1811,7 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
cpu_option_add_user_setting(name, value);
cpu->cfg.vlen = value;
+ cpu->cfg.vlenb = value >> 3;
}
static void prop_vlen_get(Object *obj, Visitor *v, const char *name,
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fea14c275f..50479dd72f 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -140,6 +140,7 @@ struct RISCVCPUConfig {
uint32_t pmu_mask;
uint16_t vlen;
+ uint16_t vlenb;
uint16_t elen;
uint16_t cbom_blocksize;
uint16_t cbop_blocksize;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen'
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:39 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' Daniel Henrique Barboza
` (9 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
reading CSR_VLENB.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..5c8d22452b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -683,7 +683,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
{
- *val = riscv_cpu_cfg(env)->vlen >> 3;
+ *val = riscv_cpu_cfg(env)->vlenb;
return RISCV_EXCP_NONE;
}
@@ -738,7 +738,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
* The vstart CSR is defined to have only enough writable bits
* to hold the largest element index, i.e. lg2(VLEN) bits.
*/
- env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
+ env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3));
return RISCV_EXCP_NONE;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen' Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:39 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb Daniel Henrique Barboza
` (8 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/gdbstub.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 58b3ace0fe..5ab0abda19 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
- uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;
if (n < 32) {
int i;
int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
{
- uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+ uint16_t vlenb = riscv_cpu_cfg(env)->vlenb;
if (n < 32) {
int i;
for (i = 0; i < vlenb; i += 8) {
@@ -266,7 +266,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
RISCVCPU *cpu = RISCV_CPU(cs);
GString *s = g_string_new(NULL);
g_autoptr(GString) ts = g_string_new("");
- int reg_width = cpu->cfg.vlen;
+ int reg_width = cpu->cfg.vlenb << 3;
int num_regs = 0;
int i;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (2 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:40 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' Daniel Henrique Barboza
` (7 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 4e39c00884..8ee99df3f3 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -83,8 +83,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs2), tcg_env,
- ctx->cfg_ptr->vlen / 8,
- ctx->cfg_ptr->vlen / 8, data,
+ ctx->cfg_ptr->vlenb,
+ ctx->cfg_ptr->vlenb, data,
gen_helper_vfncvtbf16_f_f_w);
mark_vs_dirty(ctx);
gen_set_label(over);
@@ -112,8 +112,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs2), tcg_env,
- ctx->cfg_ptr->vlen / 8,
- ctx->cfg_ptr->vlen / 8, data,
+ ctx->cfg_ptr->vlenb,
+ ctx->cfg_ptr->vlenb, data,
gen_helper_vfwcvtbf16_f_f_v);
mark_vs_dirty(ctx);
gen_set_label(over);
@@ -143,8 +143,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
vreg_ofs(ctx, a->rs1),
vreg_ofs(ctx, a->rs2), tcg_env,
- ctx->cfg_ptr->vlen / 8,
- ctx->cfg_ptr->vlen / 8, data,
+ ctx->cfg_ptr->vlenb,
+ ctx->cfg_ptr->vlenb, data,
gen_helper_vfwmaccbf16_vv);
mark_vs_dirty(ctx);
gen_set_label(over);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (3 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:45 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: " Daniel Henrique Barboza
` (6 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
"s->cfg_ptr->vlen >> 3".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 140 ++++++++++++------------
1 file changed, 70 insertions(+), 70 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 3871f0ea73..d743675262 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -217,7 +217,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{
- return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
+ return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlenb;
}
/* check functions */
@@ -627,11 +627,11 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
* As simd_desc supports at most 2048 bytes, and in this implementation,
* the max vector group length is 4096 bytes. So split it into two parts.
*
- * The first part is vlen in bytes, encoded in maxsz of simd_desc.
+ * The first part is vlen in bytes (vlenb), encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
*/
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
@@ -791,8 +791,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
stride = get_gpr(s, rs2, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
@@ -897,8 +897,8 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
@@ -1036,8 +1036,8 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
@@ -1086,7 +1086,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
DisasContext *s, bool is_store)
{
- uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / width;
+ uint32_t evl = s->cfg_ptr->vlenb * nf / width;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
@@ -1096,8 +1096,8 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
@@ -1199,8 +1199,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fn);
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fn);
}
mark_vs_dirty(s);
gen_set_label(over);
@@ -1248,8 +1248,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
@@ -1410,8 +1410,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
@@ -1492,8 +1492,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb,
data, fn);
mark_vs_dirty(s);
gen_set_label(over);
@@ -1568,8 +1568,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fn);
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -1639,8 +1639,8 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
- vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fn);
+ vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -1831,8 +1831,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2036,8 +2036,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data,
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data,
fns[s->sew]);
gen_set_label(over);
}
@@ -2082,8 +2082,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
};
tcg_gen_ext_tl_i64(s1_i64, s1);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1_i64, tcg_env, desc);
}
@@ -2121,8 +2121,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
s1 = tcg_constant_i64(simm);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, tcg_env, desc);
@@ -2275,8 +2275,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2303,8 +2303,8 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2));
@@ -2391,8 +2391,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2465,8 +2465,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2581,8 +2581,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), tcg_env,
- s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fn);
+ s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -2691,8 +2691,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
do_nanbox(s, t1, cpu_fpr[a->rs1]);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, t1, tcg_env, desc);
@@ -2770,8 +2770,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2821,8 +2821,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2888,8 +2888,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2937,8 +2937,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -3027,8 +3027,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, data, fn); \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, fn); \
mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
@@ -3061,8 +3061,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
dst = dest_gpr(s, a->rd);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
@@ -3090,8 +3090,8 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
dst = dest_gpr(s, a->rd);
- desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
@@ -3128,8 +3128,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- tcg_env, s->cfg_ptr->vlen / 8, \
- s->cfg_ptr->vlen / 8, \
+ tcg_env, s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, \
data, fn); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -3171,8 +3171,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
};
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), tcg_env,
- s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fns[s->sew]);
+ s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -3200,8 +3200,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
gen_helper_vid_v_w, gen_helper_vid_v_d,
};
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8,
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb,
data, fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
@@ -3620,8 +3620,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
data = FIELD_DP32(data, VDATA, VTA, s->vta);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data,
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data,
fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
@@ -3641,7 +3641,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
vext_check_isa_ill(s) && \
QEMU_IS_ALIGNED(a->rd, LEN) && \
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
- uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
+ uint32_t maxsz = s->cfg_ptr->vlenb * LEN; \
if (s->vstart_eq_zero) { \
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
@@ -3723,8 +3723,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), tcg_env,
- s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data, fn);
+ s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (4 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:47 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 07/12] target/riscv/vector_helper.c: " Daniel Henrique Barboza
` (5 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvvk.c.inc | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 3801c16829..a5cdd1b67f 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
+ s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -267,7 +267,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
rd_v = tcg_temp_new_ptr(); \
rs2_v = tcg_temp_new_ptr(); \
desc = tcg_constant_i32( \
- simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+ simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
@@ -345,7 +345,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
rs2_v = tcg_temp_new_ptr(); \
uimm_v = tcg_constant_i32(a->rs1); \
desc = tcg_constant_i32( \
- simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \
+ simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
@@ -413,7 +413,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
\
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), tcg_env, \
- s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
+ s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, gen_helper_##NAME); \
\
mark_vs_dirty(s); \
@@ -466,8 +466,8 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data,
+ vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data,
s->sew == MO_32 ?
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
@@ -500,8 +500,8 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8,
- s->cfg_ptr->vlen / 8, data,
+ vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data,
s->sew == MO_32 ?
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 07/12] target/riscv/vector_helper.c: use 'vlenb'
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (5 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: " Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:48 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) Daniel Henrique Barboza
` (4 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/vector_helper.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c1c3a4d1ea..cb944229b0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -558,7 +558,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k, off, pos;
uint32_t nf = vext_nf(desc);
- uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+ uint32_t vlenb = riscv_cpu_cfg(env)->vlenb;
uint32_t max_elems = vlenb >> log2_esz;
k = env->vstart / max_elems;
@@ -929,7 +929,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc); \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
@@ -967,7 +967,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
{ \
uint32_t vl = env->vl; \
uint32_t vm = vext_vm(desc); \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
@@ -1171,7 +1171,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -1236,7 +1236,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -3971,7 +3971,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -4011,7 +4011,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3; \
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t vma = vext_vma(desc); \
uint32_t i; \
@@ -4528,7 +4528,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen; \
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3;\
uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
int a, b; \
@@ -4615,7 +4615,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
- uint32_t total_elems = riscv_cpu_cfg(env)->vlen;
+ uint32_t total_elems = riscv_cpu_cfg(env)->vlenb << 3;
uint32_t vta_all_1s = vext_vta_all_1s(desc);
uint32_t vma = vext_vma(desc);
int i;
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (6 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 07/12] target/riscv/vector_helper.c: " Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:57 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() Daniel Henrique Barboza
` (3 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use the new 'vlenb' CPU config to validate fractional LMUL. The original
comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
to use vlenb.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/vector_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cb944229b0..9e3ae4b5d3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -45,9 +45,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
- /* Fractional LMUL - check LMUL * VLEN >= SEW */
+ /*
+ * Fractional LMUL: check VLEN * LMUL >= SEW,
+ * or VLEN * (8 - lmul) >= SEW. Using VLENB we
+ * need 3 less shifts rights.
+ */
if (lmul == 4 ||
- cpu->cfg.vlen >> (8 - lmul) < sew) {
+ cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) {
vill = true;
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (7 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:58 ` Richard Henderson
2024-01-15 23:14 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() Daniel Henrique Barboza
` (2 subsequent siblings)
11 siblings, 2 replies; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 11df226a00..7304e478c2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -692,7 +692,11 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
- return cpu->cfg.vlen >> (sew + 3 - lmul);
+ /*
+ * vlmax = vlen >> (sew + 3 - lmul). With vlenb,
+ * 3 less shifts: vlenb >> (sew + 3 - 3 - lmul)
+ */
+ return cpu->cfg.vlenb >> (sew - lmul);
}
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (8 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 23:02 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 11/12] trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*() Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen Daniel Henrique Barboza
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Calculate the maximum vector size possible, 'max_sz', which is the size
in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
s->lmul = 3).
'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
which is clearer than doing 'scale = lmul - 3' and then using '-scale'
in the shift right.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d743675262..b4663b6e1f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1160,12 +1160,12 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
/*
* MAXSZ returns the maximum vector size can be operated in bytes,
* which is used in GVEC IR when vl_eq_vlmax flag is set to true
- * to accerlate vector operation.
+ * to accelerate vector operation.
*/
static inline uint32_t MAXSZ(DisasContext *s)
{
- int scale = s->lmul - 3;
- return s->cfg_ptr->vlen >> -scale;
+ int max_sz = s->cfg_ptr->vlenb * 8;
+ return max_sz >> (3 - s->lmul);
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 11/12] trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*()
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (9 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen Daniel Henrique Barboza
11 siblings, 0 replies; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Use the same vext_get_vlmax() logic to retrieve 'vlmax' in
trans_vrgather_vi() and trans_vrgather_vx().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b4663b6e1f..05c243186d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3535,8 +3535,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
- int scale = s->lmul - (s->sew + 3);
- int vlmax = s->cfg_ptr->vlen >> -scale;
+ int vlmax = s->cfg_ptr->vlenb >> (s->sew - s->lmul);
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3566,8 +3565,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
- int scale = s->lmul - (s->sew + 3);
- int vlmax = s->cfg_ptr->vlen >> -scale;
+ int vlmax = s->cfg_ptr->vlenb >> (s->sew - s->lmul);
if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
` (10 preceding siblings ...)
2024-01-15 22:25 ` [PATCH v2 11/12] trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*() Daniel Henrique Barboza
@ 2024-01-15 22:25 ` Daniel Henrique Barboza
2024-01-15 23:15 ` Richard Henderson
11 siblings, 1 reply; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-15 22:25 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
There is no need to keep both 'vlen' and 'vlenb'. All existing code
that requires 'vlen' is retrieving it via 'vlenb << 3'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 8 +++-----
target/riscv/cpu_cfg.h | 1 -
target/riscv/tcg/tcg-cpu.c | 4 +++-
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f4261d2ffc..7b3f69d3fb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1313,7 +1313,6 @@ static void riscv_cpu_init(Object *obj)
/* Default values for non-bool cpu properties */
cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
- cpu->cfg.vlen = 128;
cpu->cfg.vlenb = 128 >> 3;
cpu->cfg.elen = 64;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
@@ -1802,22 +1801,21 @@ static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
return;
}
- if (value != cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) {
+ if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) {
cpu_set_prop_err(cpu, name, errp);
error_append_hint(errp, "Current '%s' val: %u\n",
- name, cpu->cfg.vlen);
+ name, cpu->cfg.vlenb << 3);
return;
}
cpu_option_add_user_setting(name, value);
- cpu->cfg.vlen = value;
cpu->cfg.vlenb = value >> 3;
}
static void prop_vlen_get(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- uint16_t value = RISCV_CPU(obj)->cfg.vlen;
+ uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3;
visit_type_uint16(v, name, &value, errp);
}
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 50479dd72f..e241922f89 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -139,7 +139,6 @@ struct RISCVCPUConfig {
bool ext_XVentanaCondOps;
uint32_t pmu_mask;
- uint16_t vlen;
uint16_t vlenb;
uint16_t elen;
uint16_t cbom_blocksize;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index daff0b8f60..667421b0b7 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -298,7 +298,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
Error **errp)
{
- if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+ uint32_t vlen = cfg->vlenb << 3;
+
+ if (vlen > RV_VLEN_MAX || vlen < 128) {
error_setg(errp,
"Vector extension implementation only supports VLEN "
"in the range [128, %d]", RV_VLEN_MAX);
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg
2024-01-15 22:25 ` [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg Daniel Henrique Barboza
@ 2024-01-15 22:33 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:33 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Our usage of 'vlenb' is overwhelming superior than the use of 'vlen'.
> We're using 'vlenb' most of the time, having to do 'vlen >> 3' or
> 'vlen / 8' in every instance.
>
> In hindsight we would be better if the 'vlenb' property was introduced
> instead of 'vlen'. That's not what happened, and now we can't easily get
> rid of it due to user scripts all around. What we can do, however, is to
> change our internal representation to use 'vlenb'.
>
> Add a 'vlenb' field in cpu->cfg. It'll be set via the existing 'vlen'
> property, i.e. setting 'vlen' will also set 'vlenb'.
>
> We'll replace all 'vlen >> 3' code to use 'vlenb' directly. Start with
> the single instance we have in target/riscv/cpu.c.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 4 +++-
> target/riscv/cpu_cfg.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen'
2024-01-15 22:25 ` [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen' Daniel Henrique Barboza
@ 2024-01-15 22:39 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:39 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
> reading CSR_VLENB.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/csr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
2024-01-15 22:25 ` [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' Daniel Henrique Barboza
@ 2024-01-15 22:39 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:39 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/gdbstub.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
2024-01-15 22:25 ` [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb Daniel Henrique Barboza
@ 2024-01-15 22:40 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:40 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Use ctx->cfg_ptr->vlenb instead of ctx->cfg_ptr->vlen / 8.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
2024-01-15 22:25 ` [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' Daniel Henrique Barboza
@ 2024-01-15 22:45 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:45 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Use s->cfg_ptr->vlenb instead of "s->cfg_ptr->vlen / 8" and
> "s->cfg_ptr->vlen >> 3".
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 140 ++++++++++++------------
> 1 file changed, 70 insertions(+), 70 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
2024-01-15 22:25 ` [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: " Daniel Henrique Barboza
@ 2024-01-15 22:47 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:47 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Use s->cfg_ptr->vlenb instead of s->cfg_ptr->vlen / 8.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/insn_trans/trans_rvvk.c.inc | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 07/12] target/riscv/vector_helper.c: use 'vlenb'
2024-01-15 22:25 ` [PATCH v2 07/12] target/riscv/vector_helper.c: " Daniel Henrique Barboza
@ 2024-01-15 22:48 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:48 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Use 'cpu->cfg.vlenb' instead of 'cpu->cfg.vlen >> 3'.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/vector_helper.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
2024-01-15 22:25 ` [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) Daniel Henrique Barboza
@ 2024-01-15 22:57 ` Richard Henderson
2024-01-16 20:45 ` Daniel Henrique Barboza
0 siblings, 1 reply; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:57 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Use the new 'vlenb' CPU config to validate fractional LMUL. The original
> comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
> to use vlenb.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/vector_helper.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index cb944229b0..9e3ae4b5d3 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -45,9 +45,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>
> if (lmul & 4) {
> - /* Fractional LMUL - check LMUL * VLEN >= SEW */
> + /*
> + * Fractional LMUL: check VLEN * LMUL >= SEW,
> + * or VLEN * (8 - lmul) >= SEW. Using VLENB we
> + * need 3 less shifts rights.
The last sentence is structured oddly. Perhaps
Using VLENB, we decrease the right shift by 3
or perhaps just show the expansion:
/*
* Fractional LMUL, check
*
* VLEN * LMUL >= SEW
* VLEN >> (8 - lmul) >= sew
* (vlenb << 3) >> (8 - lmul) >= sew
* vlenb >> (8 - 3 - lmul) >= sew
*/
Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> + */
> if (lmul == 4 ||
> - cpu->cfg.vlen >> (8 - lmul) < sew) {
> + cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) {
> vill = true;
> }
> }
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
2024-01-15 22:25 ` [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() Daniel Henrique Barboza
@ 2024-01-15 22:58 ` Richard Henderson
2024-01-15 23:14 ` Richard Henderson
1 sibling, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 22:58 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.h | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
2024-01-15 22:25 ` [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() Daniel Henrique Barboza
@ 2024-01-15 23:02 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 23:02 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Calculate the maximum vector size possible, 'max_sz', which is the size
> in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
> s->lmul = 3).
>
> 'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
> which is clearer than doing 'scale = lmul - 3' and then using '-scale'
> in the shift right.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
2024-01-15 22:25 ` [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() Daniel Henrique Barboza
2024-01-15 22:58 ` Richard Henderson
@ 2024-01-15 23:14 ` Richard Henderson
2024-01-16 17:52 ` Daniel Henrique Barboza
1 sibling, 1 reply; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 23:14 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.h | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 11df226a00..7304e478c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -692,7 +692,11 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
> {
> uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
> int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
> - return cpu->cfg.vlen >> (sew + 3 - lmul);
> + /*
> + * vlmax = vlen >> (sew + 3 - lmul). With vlenb,
> + * 3 less shifts: vlenb >> (sew + 3 - 3 - lmul)
> + */
> + return cpu->cfg.vlenb >> (sew - lmul);
> }
I take it back -- this doesn't work without the + 3:
sew = 0
lmul = 3
vlenb >> (0 - 3)
= vlenb >> -3
Need
vlen = vlenb << 3
vlmax = vlen >> (0 + 3 - 3)
= vlen >> 0
= vlen
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen
2024-01-15 22:25 ` [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen Daniel Henrique Barboza
@ 2024-01-15 23:15 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2024-01-15 23:15 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/16/24 09:25, Daniel Henrique Barboza wrote:
> There is no need to keep both 'vlen' and 'vlenb'. All existing code
> that requires 'vlen' is retrieving it via 'vlenb << 3'.
>
> Signed-off-by: Daniel Henrique Barboza<dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 8 +++-----
> target/riscv/cpu_cfg.h | 1 -
> target/riscv/tcg/tcg-cpu.c | 4 +++-
> 3 files changed, 6 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
2024-01-15 23:14 ` Richard Henderson
@ 2024-01-16 17:52 ` Daniel Henrique Barboza
0 siblings, 0 replies; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-16 17:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/15/24 20:14, Richard Henderson wrote:
> On 1/16/24 09:25, Daniel Henrique Barboza wrote:
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.h | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 11df226a00..7304e478c2 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -692,7 +692,11 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
>> {
>> uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
>> int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
>> - return cpu->cfg.vlen >> (sew + 3 - lmul);
>> + /*
>> + * vlmax = vlen >> (sew + 3 - lmul). With vlenb,
>> + * 3 less shifts: vlenb >> (sew + 3 - 3 - lmul)
>> + */
>> + return cpu->cfg.vlenb >> (sew - lmul);
>> }
>
> I take it back -- this doesn't work without the + 3:
>
> sew = 0
> lmul = 3
>
> vlenb >> (0 - 3)
> = vlenb >> -3
>
> Need
>
> vlen = vlenb << 3
> vlmax = vlen >> (0 + 3 - 3)
> = vlen >> 0
> = vlen
I got tricked by the 'sew' variable name there. This formula is using vsew.
I'll fix and re-send. Thanks,
Daniel
>
>
> r~
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
2024-01-15 22:57 ` Richard Henderson
@ 2024-01-16 20:45 ` Daniel Henrique Barboza
0 siblings, 0 replies; 27+ messages in thread
From: Daniel Henrique Barboza @ 2024-01-16 20:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 1/15/24 19:57, Richard Henderson wrote:
> On 1/16/24 09:25, Daniel Henrique Barboza wrote:
>> Use the new 'vlenb' CPU config to validate fractional LMUL. The original
>> comparison is done with 'vlen' and 'sew', both in bits. Adjust the shift
>> to use vlenb.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/vector_helper.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
>> index cb944229b0..9e3ae4b5d3 100644
>> --- a/target/riscv/vector_helper.c
>> +++ b/target/riscv/vector_helper.c
>> @@ -45,9 +45,13 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
>> xlen - 1 - R_VTYPE_RESERVED_SHIFT);
>> if (lmul & 4) {
>> - /* Fractional LMUL - check LMUL * VLEN >= SEW */
>> + /*
>> + * Fractional LMUL: check VLEN * LMUL >= SEW,
>> + * or VLEN * (8 - lmul) >= SEW. Using VLENB we
>> + * need 3 less shifts rights.
>
> The last sentence is structured oddly. Perhaps
>
> Using VLENB, we decrease the right shift by 3
>
> or perhaps just show the expansion:
>
> /*
> * Fractional LMUL, check
> *
> * VLEN * LMUL >= SEW
> * VLEN >> (8 - lmul) >= sew
> * (vlenb << 3) >> (8 - lmul) >= sew
> * vlenb >> (8 - 3 - lmul) >= sew
> */
Just changed the comment to show the expansion. Thanks,
Daniel
>
> Anyway,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
>
>> + */
>> if (lmul == 4 ||
>> - cpu->cfg.vlen >> (8 - lmul) < sew) {
>> + cpu->cfg.vlenb >> (8 - 3 - lmul) < sew) {
>> vill = true;
>> }
>> }
>
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2024-01-16 20:46 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-15 22:25 [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 01/12] target/riscv: add 'vlenb' field in cpu->cfg Daniel Henrique Barboza
2024-01-15 22:33 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 02/12] target/riscv/csr.c: use 'vlenb' instead of 'vlen' Daniel Henrique Barboza
2024-01-15 22:39 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 03/12] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' Daniel Henrique Barboza
2024-01-15 22:39 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 04/12] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb Daniel Henrique Barboza
2024-01-15 22:40 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 05/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' Daniel Henrique Barboza
2024-01-15 22:45 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 06/12] target/riscv/insn_trans/trans_rvvk.c.inc: " Daniel Henrique Barboza
2024-01-15 22:47 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 07/12] target/riscv/vector_helper.c: " Daniel Henrique Barboza
2024-01-15 22:48 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 08/12] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) Daniel Henrique Barboza
2024-01-15 22:57 ` Richard Henderson
2024-01-16 20:45 ` Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 09/12] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() Daniel Henrique Barboza
2024-01-15 22:58 ` Richard Henderson
2024-01-15 23:14 ` Richard Henderson
2024-01-16 17:52 ` Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 10/12] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() Daniel Henrique Barboza
2024-01-15 23:02 ` Richard Henderson
2024-01-15 22:25 ` [PATCH v2 11/12] trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*() Daniel Henrique Barboza
2024-01-15 22:25 ` [PATCH v2 12/12] target/riscv/cpu.c: remove cpu->cfg.vlen Daniel Henrique Barboza
2024-01-15 23:15 ` Richard Henderson
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