* [PULL v2 00/39] tcg patch queue
@ 2024-02-06 3:21 Richard Henderson
2024-02-06 3:21 ` [PULL v2 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Richard Henderson @ 2024-02-06 3:21 UTC (permalink / raw)
To: qemu-devel
v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
r~
The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
----------------------------------------------------------------
tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc
----------------------------------------------------------------
Paolo Bonzini (1):
tcg/i386: Use TEST r,r to test 8/16/32 bits
Philippe Mathieu-Daudé (1):
tcg/aarch64: Massage tcg_out_brcond()
Richard Henderson (37):
tcg: Introduce TCG_COND_TST{EQ,NE}
tcg: Introduce TCG_TARGET_HAS_tst
tcg/optimize: Split out arg_is_const_val
tcg/optimize: Split out do_constant_folding_cond1
tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2
tcg/optimize: Handle TCG_COND_TST{EQ,NE}
tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported
target/alpha: Pass immediate value to gen_bcond_internal()
target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}
target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S}
target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc
tcg: Add TCGConst argument to tcg_target_const_match
tcg/aarch64: Support TCG_COND_TST{EQ,NE}
tcg/aarch64: Generate TBZ, TBNZ
tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX
tcg/arm: Split out tcg_out_cmp()
tcg/arm: Support TCG_COND_TST{EQ,NE}
tcg/i386: Pass x86 condition codes to tcg_out_cmov
tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp
tcg/i386: Support TCG_COND_TST{EQ,NE}
tcg/i386: Improve TSTNE/TESTEQ vs powers of two
tcg/sparc64: Hoist read of tcg_cond_to_rcond
tcg/sparc64: Pass TCGCond to tcg_out_cmp
tcg/sparc64: Support TCG_COND_TST{EQ,NE}
tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
tcg/ppc: Tidy up tcg_target_const_match
tcg/ppc: Add TCG_CT_CONST_CMP
tcg/ppc: Support TCG_COND_TST{EQ,NE}
tcg/s390x: Split constraint A into J+U
tcg/s390x: Add TCG_CT_CONST_CMP
tcg/s390x: Support TCG_COND_TST{EQ,NE}
tcg/tci: Support TCG_COND_TST{EQ,NE}
docs/devel/tcg-ops.rst | 2 +
include/tcg/tcg-cond.h | 74 ++++--
tcg/aarch64/tcg-target-con-set.h | 5 +-
tcg/aarch64/tcg-target-con-str.h | 1 +
tcg/aarch64/tcg-target.h | 2 +
tcg/arm/tcg-target.h | 2 +
tcg/i386/tcg-target-con-set.h | 6 +-
tcg/i386/tcg-target-con-str.h | 1 +
tcg/i386/tcg-target.h | 2 +
tcg/loongarch64/tcg-target.h | 2 +
tcg/mips/tcg-target.h | 2 +
tcg/ppc/tcg-target-con-set.h | 5 +-
tcg/ppc/tcg-target-con-str.h | 1 +
tcg/ppc/tcg-target.h | 2 +
tcg/riscv/tcg-target.h | 2 +
tcg/s390x/tcg-target-con-set.h | 8 +-
tcg/s390x/tcg-target-con-str.h | 3 +-
tcg/s390x/tcg-target.h | 2 +
tcg/sparc64/tcg-target.h | 2 +
tcg/tcg-internal.h | 2 +
tcg/tci/tcg-target.h | 2 +
target/alpha/translate.c | 94 ++++----
target/m68k/translate.c | 74 +++---
target/s390x/tcg/translate.c | 100 +++------
target/sparc/translate.c | 4 +-
tcg/optimize.c | 474 ++++++++++++++++++++++++++++++---------
tcg/tcg.c | 40 +++-
tcg/tci.c | 14 ++
tcg/aarch64/tcg-target.c.inc | 166 +++++++++++---
tcg/arm/tcg-target.c.inc | 62 +++--
tcg/i386/tcg-target.c.inc | 201 ++++++++++++-----
tcg/loongarch64/tcg-target.c.inc | 3 +-
tcg/mips/tcg-target.c.inc | 3 +-
tcg/ppc/tcg-target.c.inc | 294 ++++++++++++++++++------
tcg/riscv/tcg-target.c.inc | 3 +-
tcg/s390x/tcg-target.c.inc | 246 +++++++++++++-------
tcg/sparc64/tcg-target.c.inc | 65 ++++--
tcg/tci/tcg-target.c.inc | 3 +-
38 files changed, 1379 insertions(+), 595 deletions(-)
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PULL v2 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE}
2024-02-06 3:21 [PULL v2 00/39] tcg patch queue Richard Henderson
@ 2024-02-06 3:21 ` Richard Henderson
2024-02-06 21:24 ` [PULL v2 00/39] tcg patch queue Peter Maydell
2024-02-08 20:08 ` Peter Maydell
2 siblings, 0 replies; 8+ messages in thread
From: Richard Henderson @ 2024-02-06 3:21 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 139 +++++++++++++++++++++++++------------
2 files changed, 97 insertions(+), 44 deletions(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 53bed8c8d2..ae448c3a3a 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -138,7 +138,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_qemu_ldst_i128 1
-#define TCG_TARGET_HAS_tst 0
+#define TCG_TARGET_HAS_tst 1
#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR)
#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 7f97080f52..ad587325fc 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -112,6 +112,9 @@ typedef enum S390Opcode {
RI_OILH = 0xa50a,
RI_OILL = 0xa50b,
RI_TMLL = 0xa701,
+ RI_TMLH = 0xa700,
+ RI_TMHL = 0xa703,
+ RI_TMHH = 0xa702,
RIEb_CGRJ = 0xec64,
RIEb_CLGRJ = 0xec65,
@@ -404,10 +407,15 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define S390_CC_NEVER 0
#define S390_CC_ALWAYS 15
+#define S390_TM_EQ 8 /* CC == 0 */
+#define S390_TM_NE 7 /* CC in {1,2,3} */
+
/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
-static const uint8_t tcg_cond_to_s390_cond[] = {
+static const uint8_t tcg_cond_to_s390_cond[16] = {
[TCG_COND_EQ] = S390_CC_EQ,
[TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_TSTEQ] = S390_CC_EQ,
+ [TCG_COND_TSTNE] = S390_CC_NE,
[TCG_COND_LT] = S390_CC_LT,
[TCG_COND_LE] = S390_CC_LE,
[TCG_COND_GT] = S390_CC_GT,
@@ -421,9 +429,11 @@ static const uint8_t tcg_cond_to_s390_cond[] = {
/* Condition codes that result from a LOAD AND TEST. Here, we have no
unsigned instruction variation, however since the test is vs zero we
can re-map the outcomes appropriately. */
-static const uint8_t tcg_cond_to_ltr_cond[] = {
+static const uint8_t tcg_cond_to_ltr_cond[16] = {
[TCG_COND_EQ] = S390_CC_EQ,
[TCG_COND_NE] = S390_CC_NE,
+ [TCG_COND_TSTEQ] = S390_CC_ALWAYS,
+ [TCG_COND_TSTNE] = S390_CC_NEVER,
[TCG_COND_LT] = S390_CC_LT,
[TCG_COND_LE] = S390_CC_LE,
[TCG_COND_GT] = S390_CC_GT,
@@ -542,10 +552,13 @@ static bool risbg_mask(uint64_t c)
static bool tcg_target_const_match(int64_t val, int ct,
TCGType type, TCGCond cond, int vece)
{
+ uint64_t uval = val;
+
if (ct & TCG_CT_CONST) {
return true;
}
if (type == TCG_TYPE_I32) {
+ uval = (uint32_t)val;
val = (int32_t)val;
}
@@ -567,6 +580,15 @@ static bool tcg_target_const_match(int64_t val, int ct,
case TCG_COND_GTU:
ct |= TCG_CT_CONST_U32; /* CLGFI */
break;
+ case TCG_COND_TSTNE:
+ case TCG_COND_TSTEQ:
+ if (is_const_p16(uval) >= 0) {
+ return true; /* TMxx */
+ }
+ if (risbg_mask(uval)) {
+ return true; /* RISBG */
+ }
+ break;
default:
g_assert_not_reached();
}
@@ -588,10 +610,6 @@ static bool tcg_target_const_match(int64_t val, int ct,
if (ct & TCG_CT_CONST_INV) {
val = ~val;
}
- /*
- * Note that is_const_p16 is a subset of is_const_p32,
- * so we don't need both constraints.
- */
if ((ct & TCG_CT_CONST_P32) && is_const_p32(val) >= 0) {
return true;
}
@@ -868,6 +886,9 @@ static const S390Opcode oi_insns[4] = {
static const S390Opcode lif_insns[2] = {
RIL_LLILF, RIL_LLIHF,
};
+static const S390Opcode tm_insns[4] = {
+ RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH
+};
/* load a register with an immediate value */
static void tcg_out_movi(TCGContext *s, TCGType type,
@@ -1228,6 +1249,36 @@ static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
TCGCond inv_c = tcg_invert_cond(c);
S390Opcode op;
+ if (is_tst_cond(c)) {
+ tcg_debug_assert(!need_carry);
+
+ if (!c2const) {
+ if (type == TCG_TYPE_I32) {
+ tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2);
+ } else {
+ tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2);
+ }
+ goto exit;
+ }
+
+ if (type == TCG_TYPE_I32) {
+ c2 = (uint32_t)c2;
+ }
+
+ int i = is_const_p16(c2);
+ if (i >= 0) {
+ tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16));
+ *inv_cc = c == TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ;
+ return *inv_cc ^ 15;
+ }
+
+ if (risbg_mask(c2)) {
+ tgen_andi_risbg(s, TCG_REG_R0, r1, c2);
+ goto exit;
+ }
+ g_assert_not_reached();
+ }
+
if (c2const) {
if (c2 == 0) {
if (!(is_unsigned && need_carry)) {
@@ -1553,46 +1604,49 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
{
int cc;
- bool is_unsigned = is_unsigned_cond(c);
- bool in_range;
- S390Opcode opc;
- cc = tcg_cond_to_s390_cond[c];
+ if (!is_tst_cond(c)) {
+ bool is_unsigned = is_unsigned_cond(c);
+ bool in_range;
+ S390Opcode opc;
- if (!c2const) {
- opc = (type == TCG_TYPE_I32
- ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ)
- : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ));
- tgen_compare_branch(s, opc, cc, r1, c2, l);
- return;
- }
+ cc = tcg_cond_to_s390_cond[c];
- /*
- * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
- * If the immediate we've been given does not fit that range, we'll
- * fall back to separate compare and branch instructions using the
- * larger comparison range afforded by COMPARE IMMEDIATE.
- */
- if (type == TCG_TYPE_I32) {
- if (is_unsigned) {
- opc = RIEc_CLIJ;
- in_range = (uint32_t)c2 == (uint8_t)c2;
- } else {
- opc = RIEc_CIJ;
- in_range = (int32_t)c2 == (int8_t)c2;
+ if (!c2const) {
+ opc = (type == TCG_TYPE_I32
+ ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ)
+ : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ));
+ tgen_compare_branch(s, opc, cc, r1, c2, l);
+ return;
}
- } else {
- if (is_unsigned) {
- opc = RIEc_CLGIJ;
- in_range = (uint64_t)c2 == (uint8_t)c2;
+
+ /*
+ * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
+ * If the immediate we've been given does not fit that range, we'll
+ * fall back to separate compare and branch instructions using the
+ * larger comparison range afforded by COMPARE IMMEDIATE.
+ */
+ if (type == TCG_TYPE_I32) {
+ if (is_unsigned) {
+ opc = RIEc_CLIJ;
+ in_range = (uint32_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIEc_CIJ;
+ in_range = (int32_t)c2 == (int8_t)c2;
+ }
} else {
- opc = RIEc_CGIJ;
- in_range = (int64_t)c2 == (int8_t)c2;
+ if (is_unsigned) {
+ opc = RIEc_CLGIJ;
+ in_range = (uint64_t)c2 == (uint8_t)c2;
+ } else {
+ opc = RIEc_CGIJ;
+ in_range = (int64_t)c2 == (int8_t)c2;
+ }
+ }
+ if (in_range) {
+ tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
+ return;
}
- }
- if (in_range) {
- tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
- return;
}
cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
@@ -1871,11 +1925,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->oi = oi;
ldst->addrlo_reg = addr_reg;
- /* We are expecting a_bits to max out at 7, much lower than TMLL. */
tcg_debug_assert(a_mask <= 0xffff);
tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
- tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
+ tcg_out16(s, RI_BRC | (S390_TM_NE << 4));
ldst->label_ptr[0] = s->code_ptr++;
}
@@ -1956,7 +2009,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
l2 = gen_new_label();
tcg_out_insn(s, RI, TMLL, addr_reg, 15);
- tgen_branch(s, 7, l1); /* CC in {1,2,3} */
+ tgen_branch(s, S390_TM_NE, l1);
}
tcg_debug_assert(!need_bswap);
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PULL v2 00/39] tcg patch queue
2024-02-06 3:21 [PULL v2 00/39] tcg patch queue Richard Henderson
2024-02-06 3:21 ` [PULL v2 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
@ 2024-02-06 21:24 ` Peter Maydell
2024-02-06 21:45 ` Peter Maydell
2024-02-07 16:26 ` Christian Borntraeger
2024-02-08 20:08 ` Peter Maydell
2 siblings, 2 replies; 8+ messages in thread
From: Peter Maydell @ 2024-02-06 21:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Thomas Huth, Christian Borntraeger
On Tue, 6 Feb 2024 at 03:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
>
>
> r~
>
>
> The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
>
> Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
>
> for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
>
> tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
>
> ----------------------------------------------------------------
> tcg: Introduce TCG_COND_TST{EQ,NE}
> target/alpha: Use TCG_COND_TST{EQ,NE}
> target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> target/s390x: Improve general case of disas_jcc
This really doesn't want to pass the ubuntu-20.04-s390x-all job:
https://gitlab.com/qemu-project/qemu/-/jobs/6109442678
https://gitlab.com/qemu-project/qemu/-/jobs/6108249863
https://gitlab.com/qemu-project/qemu/-/jobs/6106928534
https://gitlab.com/qemu-project/qemu/-/jobs/6105718495
Now, this has definitely been a flaky job recently, so maybe it's
not this pullreq's fault.
This is a passing job from the last successful merge:
https://gitlab.com/qemu-project/qemu/-/jobs/6089342252
That took 24 minutes to run, and all the failed jobs above
took 70 minutes plus.
TBH I think there is something weird with the runner. Looking
at the timestamps in the log, it seems like the passing job
completed its compile step in about 14 minutes, whereas one
of the failing jobs took about 39 minutes. So the entire
run of the job slowed down by more than 2.5x, which is enough
to put it into the range where either the whole job or
individual tests time out.
thuth: any idea why that might happen? (I look in on the
machine from time to time and it doesn't seem to be doing
anything it shouldn't that would be eating CPU.)
Christian: this is on the s390x machine we have. Does the
VM setup for that share IO or CPU with other VMs somehow?
Is there some reason why it might have very variable
performance over time?
thanks
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL v2 00/39] tcg patch queue
2024-02-06 21:24 ` [PULL v2 00/39] tcg patch queue Peter Maydell
@ 2024-02-06 21:45 ` Peter Maydell
2024-02-07 16:26 ` Christian Borntraeger
1 sibling, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2024-02-06 21:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Thomas Huth, Christian Borntraeger
On Tue, 6 Feb 2024 at 21:24, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 6 Feb 2024 at 03:22, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
> >
> >
> > r~
> >
> >
> > The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
> >
> > Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
> >
> > are available in the Git repository at:
> >
> > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
> >
> > for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
> >
> > tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
> >
> > ----------------------------------------------------------------
> > tcg: Introduce TCG_COND_TST{EQ,NE}
> > target/alpha: Use TCG_COND_TST{EQ,NE}
> > target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> > target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> > target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> > target/s390x: Improve general case of disas_jcc
>
> This really doesn't want to pass the ubuntu-20.04-s390x-all job:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/6109442678
> https://gitlab.com/qemu-project/qemu/-/jobs/6108249863
> https://gitlab.com/qemu-project/qemu/-/jobs/6106928534
> https://gitlab.com/qemu-project/qemu/-/jobs/6105718495
>
> Now, this has definitely been a flaky job recently, so maybe it's
> not this pullreq's fault.
>
> This is a passing job from the last successful merge:
> https://gitlab.com/qemu-project/qemu/-/jobs/6089342252
> That took 24 minutes to run, and all the failed jobs above
> took 70 minutes plus.
Ruling out anything about this particular merge attempt:
This is a passing job from a recent succesful merge:
https://gitlab.com/qemu-project/qemu/-/jobs/6089089816
That took 37 minutes to run (21 mins in configure-n-compile).
This is a failing job for the same commit:
https://gitlab.com/qemu-project/qemu/-/jobs/6086439717
That took 58 minutes (26 mins in configure-n-compile).
So there's a lot of between run variation, though in that
case it was not so much as in some of these examples.
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL v2 00/39] tcg patch queue
2024-02-06 21:24 ` [PULL v2 00/39] tcg patch queue Peter Maydell
2024-02-06 21:45 ` Peter Maydell
@ 2024-02-07 16:26 ` Christian Borntraeger
1 sibling, 0 replies; 8+ messages in thread
From: Christian Borntraeger @ 2024-02-07 16:26 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: qemu-devel, Thomas Huth
Am 06.02.24 um 22:24 schrieb Peter Maydell:
[..]
> Christian: this is on the s390x machine we have. Does the
> VM setup for that share IO or CPU with other VMs somehow?
Yes it does, this is a shared system. I will talk to the team if there is anything that we can do about this.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL v2 00/39] tcg patch queue
2024-02-06 3:21 [PULL v2 00/39] tcg patch queue Richard Henderson
2024-02-06 3:21 ` [PULL v2 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-02-06 21:24 ` [PULL v2 00/39] tcg patch queue Peter Maydell
@ 2024-02-08 20:08 ` Peter Maydell
2 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2024-02-08 20:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, 6 Feb 2024 at 03:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
>
>
> r~
>
>
> The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
>
> Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
>
> for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
>
> tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
>
> ----------------------------------------------------------------
> tcg: Introduce TCG_COND_TST{EQ,NE}
> target/alpha: Use TCG_COND_TST{EQ,NE}
> target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> target/s390x: Improve general case of disas_jcc
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PULL v2 00/39] tcg patch queue
2023-09-16 17:12 Richard Henderson
@ 2023-09-19 19:12 ` Stefan Hajnoczi
0 siblings, 0 replies; 8+ messages in thread
From: Stefan Hajnoczi @ 2023-09-19 19:12 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PULL v2 00/39] tcg patch queue
@ 2023-09-16 17:12 Richard Henderson
2023-09-19 19:12 ` Stefan Hajnoczi
0 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2023-09-16 17:12 UTC (permalink / raw)
To: qemu-devel
v2: tcg/loongarch64 patch set without last minute tweaks.
r~
The following changes since commit 005ad32358f12fe9313a4a01918a55e60d4f39e5:
Merge tag 'pull-tpm-2023-09-12-3' of https://github.com/stefanberger/qemu-tpm into staging (2023-09-13 13:41:57 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230915-2
for you to fetch changes up to a97a83753c90d79ed15a716610af23fabd84aaed:
tcg: Map code_gen_buffer with PROT_BTI (2023-09-16 14:57:16 +0000)
----------------------------------------------------------------
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX instructions
fpu: Add conversions between bfloat16 and [u]int8
fpu: Handle m68k extended precision denormals properly
accel/tcg: Improve cputlb i/o organization
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Remove false-negative halted assertion
tcg: Add gvec compare with immediate and scalar operand
tcg/aarch64: Emit BTI insns at jump landing pads
----------------------------------------------------------------
Akihiko Odaki (3):
util: Delete checks for old host definitions
softmmu: Delete checks for old host definitions
thunk: Delete checks for old host definitions
Jiajie Chen (16):
tcg/loongarch64: Import LSX instructions
tcg/loongarch64: Lower basic tcg vec ops to LSX
tcg: pass vece to tcg_target_const_match()
tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
tcg/loongarch64: Lower add/sub_vec to vadd/vsub
tcg/loongarch64: Lower vector bitwise operations
tcg/loongarch64: Lower neg_vec to vneg
tcg/loongarch64: Lower mul_vec to vmul
tcg/loongarch64: Lower vector min max ops
tcg/loongarch64: Lower vector saturated ops
tcg/loongarch64: Lower vector shift vector ops
tcg/loongarch64: Lower bitsel_vec to vbitsel
tcg/loongarch64: Lower vector shift integer ops
tcg/loongarch64: Lower rotv_vec ops to LSX
tcg/loongarch64: Lower rotli_vec to vrotri
tcg/loongarch64: Implement 128-bit load & store
LIU Zhiwei (2):
accel/tcg: Fix the comment for CPUTLBEntryFull
fpu: Add conversions between bfloat16 and [u]int8
Nicholas Piggin (1):
accel/tcg: mttcg remove false-negative halted assertion
Richard Henderson (17):
tcg: Add gvec compare with immediate and scalar operand
target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Split out io_prepare and io_failed
accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
plugin: Simplify struct qemu_plugin_hwaddr
accel/tcg: Merge cpu_transaction_failed into io_failed
accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1
accel/tcg: Merge io_readx into do_ld_mmio_beN
accel/tcg: Merge io_writex into do_st_mmio_leN
accel/tcg: Introduce do_ld16_mmio_beN
accel/tcg: Introduce do_st16_mmio_leN
fpu: Handle m68k extended precision denormals properly
tcg: Add tcg_out_tb_start backend hook
util/cpuinfo-aarch64: Add CPUINFO_BTI
tcg/aarch64: Emit BTI insns at jump landing pads
tcg: Map code_gen_buffer with PROT_BTI
accel/tcg/tcg-runtime.h | 25 +
host/include/aarch64/host/cpuinfo.h | 1 +
include/exec/cpu-defs.h | 12 +-
include/exec/user/thunk.h | 3 +-
include/fpu/softfloat.h | 12 +
include/hw/core/cpu.h | 13 -
include/qemu/plugin-memory.h | 11 +-
include/qemu/typedefs.h | 1 -
include/tcg/tcg-op-gvec-common.h | 6 +
tcg/loongarch64/tcg-target-con-set.h | 9 +
tcg/loongarch64/tcg-target-con-str.h | 3 +
tcg/loongarch64/tcg-target.h | 40 +-
tcg/loongarch64/tcg-target.opc.h | 12 +
accel/tcg/cputlb.c | 437 ++-
accel/tcg/tcg-accel-ops-mttcg.c | 9 +-
accel/tcg/tcg-runtime-gvec.c | 26 +
fpu/softfloat.c | 67 +-
plugins/api.c | 27 +-
softmmu/async-teardown.c | 3 -
target/arm/tcg/translate.c | 56 +-
tcg/region.c | 41 +-
tcg/tcg-op-gvec.c | 149 +
tcg/tcg.c | 7 +-
tests/tcg/m68k/denormal.c | 53 +
util/cpuinfo-aarch64.c | 7 +
util/oslib-posix.c | 15 +-
fpu/softfloat-parts.c.inc | 7 +-
tcg/aarch64/tcg-target.c.inc | 59 +-
tcg/arm/tcg-target.c.inc | 7 +-
tcg/i386/tcg-target.c.inc | 7 +-
tcg/loongarch64/tcg-insn-defs.c.inc | 6019 +++++++++++++++++++++++++++++++++-
tcg/loongarch64/tcg-target.c.inc | 624 +++-
tcg/mips/tcg-target.c.inc | 7 +-
tcg/ppc/tcg-target.c.inc | 7 +-
tcg/riscv/tcg-target.c.inc | 7 +-
tcg/s390x/tcg-target.c.inc | 7 +-
tcg/sparc64/tcg-target.c.inc | 7 +-
tcg/tci/tcg-target.c.inc | 7 +-
tests/tcg/m68k/Makefile.target | 2 +-
39 files changed, 7419 insertions(+), 393 deletions(-)
create mode 100644 tcg/loongarch64/tcg-target.opc.h
create mode 100644 tests/tcg/m68k/denormal.c
^ permalink raw reply [flat|nested] 8+ messages in thread
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Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2024-02-06 3:21 [PULL v2 00/39] tcg patch queue Richard Henderson
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2024-02-06 21:24 ` [PULL v2 00/39] tcg patch queue Peter Maydell
2024-02-06 21:45 ` Peter Maydell
2024-02-07 16:26 ` Christian Borntraeger
2024-02-08 20:08 ` Peter Maydell
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