* [PATCH 0/2] Enable fastset for mbus_join state change
@ 2024-02-28 8:02 Stanislav Lisovskiy
2024-02-28 8:02 ` [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-28 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
Currently fastset is not supported, if mbus join state changes,
so whenever we have to switch mbus state, we have to force a full
modeset. This patch series makes fastset possible from MBUS state
point of view.
Stanislav Lisovskiy (2):
drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
drm/i915: Implement vblank synchronized MBUS join changes
drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
drivers/gpu/drm/i915/display/skl_watermark.c | 104 ++++++++++++++++---
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
3 files changed, 99 insertions(+), 19 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
@ 2024-02-28 8:02 ` Stanislav Lisovskiy
2024-03-05 19:52 ` Paz Zcharya
2024-02-28 8:02 ` [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-28 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
According to BSpec we need to do correspondent MBUS updates before
or after DBUF reallocation, depending on whether we are reducing
or increasing amount of pipes(typical scenario is swithing between
multiple and single displays).
As of BSpec 49213 if we are swithing from multiple to single display
MBUS registers should be updated with correspondent values _before_
Dbuf reallocation happens, however if we are switching from single
display to multiple then it should happen _after_ DDB reallocation(i.e
plane programming).
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index c6b9be80d83c4..606b7ba9db9ce 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3534,7 +3534,7 @@ int intel_dbuf_init(struct drm_i915_private *i915)
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3584,7 +3584,10 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
+ || (old_dbuf_state->active_pipes == 0))
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3605,6 +3608,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (hweight8(new_dbuf_state->active_pipes) > hweight8(old_dbuf_state->active_pipes))
+ intel_dbuf_mbus_update(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.37.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-02-28 8:02 ` [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
@ 2024-02-28 8:02 ` Stanislav Lisovskiy
2024-03-05 19:54 ` Paz Zcharya
2024-03-08 10:07 ` Ville Syrjälä
2024-02-28 8:45 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change Patchwork
` (2 subsequent siblings)
4 siblings, 2 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2024-02-28 8:02 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.saarinen, Stanislav.Lisovskiy, ville.syrjala
Currently we can't change MBUS join status without doing a modeset,
because we are lacking mechanism to synchronize those with vblank.
However then this means that we can't do a fastset, if there is a need
to change MBUS join state. Fix that by implementing such change.
We already call correspondent check and update at pre_plane dbuf update,
so the only thing left is to have a non-modeset version of that.
If active pipes stay the same then fastset is possible and only MBUS
join state/ddb allocation updates would be committed.
v2: Implement additional changes according to BSpec.
Vblank wait is needed after MBus/Dbuf programming in case if
no modeset is done and we are switching from single to multiple
displays, i.e mbus join state switches from "joined" to "non-joined"
state. Otherwise vblank wait is not needed according to spec.
v3: Split mbus and dbox programming into to pre/post plane update parts,
how it should be done according to BSpec.
v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
after DDB reallocation, but before crtc enabling(that is where is has
to be according to spec).
- Check if crtc is still active, not only the old state.
- Do a vblank wait if MBUX DBOX register was modified.
- And of course do vblank wait only if crtc was active.
- Do vblank wait only if we are not doing a modeset, if we are doing
something before *commit_modeset_enables, because all crtcs might be
disabled at this moment, so we will get WARN if try waiting for vblank
then.
- Still getting FIFO underrun so try waiting for vblank in pre_plane update
as well.
- Write also pipe that we need to sync with to MBUS_CTL register.
v5: - Do vblank wait only for the first pipe, if mbus is joined
- Check also if new/old_dbuf_state is not NULL, before getting single pipe
and active pipes.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
drivers/gpu/drm/i915/display/skl_watermark.c | 104 +++++++++++++++----
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
3 files changed, 96 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 00ac65a140298..989818f5d342f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6906,6 +6906,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
}
}
+ /*
+ * Some MBUS/DBuf update scenarios(mbus join disable) require that
+ * changes are done _after_ DDB reallocation, but _before_ crtc enabling.
+ * Typically we are disabling resources in post_plane/crtc_enable hooks,
+ * however in that case BSpec explicitly states that this should be done
+ * before we enable additional displays.
+ * FIXME: Should we still call this also there(post_plane hook)
+ * for extra-safety? If so, how to make sure, we don't call it twice?
+ */
+ intel_dbuf_mbus_post_ddb_update(state);
+
update_pipes = modeset_pipes;
/*
@@ -7148,9 +7159,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
intel_encoders_update_prepare(state);
-
intel_dbuf_pre_plane_update(state);
- intel_mbus_dbox_update(state);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 606b7ba9db9ce..f0604ede399f7 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2628,13 +2628,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
if (ret)
return ret;
- if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
- /* TODO: Implement vblank synchronized MBUS joining changes */
- ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
- if (ret)
- return ret;
- }
-
drm_dbg_kms(&i915->drm,
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
@@ -3539,8 +3532,9 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
enum dbuf_slice slice;
- const struct intel_dbuf_state *dbuf_state =
+ const struct intel_dbuf_state *new_dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ enum pipe pipe = ffs(new_dbuf_state->active_pipes) - 1;
if (!HAS_MBUS_JOINING(i915))
return;
@@ -3549,13 +3543,13 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
*/
- if (dbuf_state->joined_mbus) {
+ if (new_dbuf_state->joined_mbus) {
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
- MBUS_JOIN_PIPE_SELECT_NONE;
+ MBUS_JOIN_PIPE_SELECT(pipe);
dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
} else {
mbus_ctl = MBUS_HASHING_MODE_2x2 |
- MBUS_JOIN_PIPE_SELECT_NONE;
+ MBUS_JOIN_PIPE_SELECT(pipe);
dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
}
@@ -3576,21 +3570,35 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
intel_atomic_get_new_dbuf_state(state);
const struct intel_dbuf_state *old_dbuf_state =
intel_atomic_get_old_dbuf_state(state);
+ int new_num_active_pipes = 0;
+ int old_num_active_pipes = 0;
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
return;
+ new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
+
+ if (old_dbuf_state)
+ old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
+
WARN_ON(!new_dbuf_state->base.changed);
- if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
- || (old_dbuf_state->active_pipes == 0))
+ /*
+ * Switching from multiple to single display scenario(enable mbus join).
+ * Also we put here "<=" instead of "<" for suboptimal cases, when
+ * we switch from single => single display, enabling mbus join.
+ */
+ if (new_num_active_pipes <= old_num_active_pipes)
intel_dbuf_mbus_update(state);
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
+
+ if (new_num_active_pipes <= old_num_active_pipes)
+ intel_mbus_dbox_update(state);
}
void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
@@ -3608,13 +3616,59 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- if (hweight8(new_dbuf_state->active_pipes) > hweight8(old_dbuf_state->active_pipes))
- intel_dbuf_mbus_update(state);
-
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
+{
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+ enum pipe pipe;
+ int new_num_active_pipes = 0;
+ int old_num_active_pipes = 0;
+
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ return;
+
+ pipe = ffs(new_dbuf_state->active_pipes) - 1;
+ new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
+
+ if (old_dbuf_state)
+ old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ /*
+ * Switching from single to multiple display scenario
+ */
+ if (new_num_active_pipes > old_num_active_pipes) {
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+ intel_dbuf_mbus_update(state);
+ intel_mbus_dbox_update(state);
+
+ if (state->modeset)
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ /*
+ * According to BSpec we should wait vblank on single display,
+ * before enabling additional displays
+ */
+ if (!new_crtc_state->hw.active || (crtc->pipe != pipe))
+ continue;
+
+ intel_crtc_wait_for_next_vblank(crtc);
+ }
+ }
+}
+
static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
{
switch (pipe) {
@@ -3638,8 +3692,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
- const struct intel_crtc_state *new_crtc_state;
- const struct intel_crtc *crtc;
+ const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
u32 val = 0;
int i;
@@ -3685,12 +3739,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
val |= MBUS_DBOX_B_CREDIT(8);
}
- for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- u32 pipe_val = val;
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ u32 pipe_val = val, old_pipe_val;
if (!new_crtc_state->hw.active)
continue;
+ old_pipe_val = intel_de_read(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe));
+
if (DISPLAY_VER(i915) >= 14) {
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
new_dbuf_state->active_pipes))
@@ -3700,6 +3756,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
}
intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
+
+ /*
+ * BSpec instructs us to wait for vblank, if credits were changed.
+ * However we need to do that here only if crtc was active prior to change.
+ */
+ if (old_pipe_val != pipe_val &&
+ old_crtc_state->hw.active && !state->modeset)
+ intel_crtc_wait_for_next_vblank(crtc);
}
}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index e3d1d74a7b170..5a97556a68c2c 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -73,6 +73,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
int intel_dbuf_init(struct drm_i915_private *i915);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
+void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
void intel_mbus_dbox_update(struct intel_atomic_state *state);
#endif /* __SKL_WATERMARK_H__ */
--
2.37.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-02-28 8:02 ` [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
2024-02-28 8:02 ` [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
@ 2024-02-28 8:45 ` Patchwork
2024-02-28 8:56 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-28 23:21 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-02-28 8:45 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable fastset for mbus_join state change
URL : https://patchwork.freedesktop.org/series/130480/
State : warning
== Summary ==
Error: dim checkpatch failed
5d2ec76ef8f2 drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
-:9: WARNING:TYPO_SPELLING: 'swithing' may be misspelled - perhaps 'switching'?
#9:
or increasing amount of pipes(typical scenario is swithing between
^^^^^^^^
-:12: WARNING:TYPO_SPELLING: 'swithing' may be misspelled - perhaps 'switching'?
#12:
As of BSpec 49213 if we are swithing from multiple to single display
^^^^^^^^
-:38: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'old_dbuf_state->active_pipes == 0'
#38: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3587:
+ if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
+ || (old_dbuf_state->active_pipes == 0))
-:39: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#39: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3588:
+ if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
+ || (old_dbuf_state->active_pipes == 0))
total: 0 errors, 2 warnings, 2 checks, 28 lines checked
763e4c15d36d drm/i915: Implement vblank synchronized MBUS join changes
-:24: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#24:
v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
-:201: WARNING:LINE_SPACING: Missing a blank line after declarations
#201: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3653:
+ int i;
+ intel_dbuf_mbus_update(state);
-:212: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'crtc->pipe != pipe'
#212: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:3664:
+ if (!new_crtc_state->hw.active || (crtc->pipe != pipe))
total: 0 errors, 2 warnings, 1 checks, 211 lines checked
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for Enable fastset for mbus_join state change
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (2 preceding siblings ...)
2024-02-28 8:45 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change Patchwork
@ 2024-02-28 8:56 ` Patchwork
2024-02-28 23:21 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-02-28 8:56 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9204 bytes --]
== Series Details ==
Series: Enable fastset for mbus_join state change
URL : https://patchwork.freedesktop.org/series/130480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14354 -> Patchwork_130480v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): bat-mtlp-8
Missing (2): fi-snb-2520m bat-adls-6
Known issues
------------
Here are the changes found in Patchwork_130480v1 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- bat-arls-1: [PASS][1] -> [FAIL][2] ([i915#10234])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-arls-1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-arls-1/boot.html
#### Possible fixes ####
* boot:
- bat-jsl-1: [FAIL][3] ([i915#8293]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-jsl-1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#9318])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
- bat-jsl-1: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4083])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#6621])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#5190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#4212]) +8 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4213]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][17] ([i915#4103]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840] / [i915#9159])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
- bat-jsl-1: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#9886])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([fdo#109285])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][21] ([fdo#109285])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#5274])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-mtlp-8: NOTRUN -> [SKIP][23] ([i915#4077] / [i915#9688])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_psr@psr-primary-mmap-gtt@edp-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][24] ([i915#3555] / [i915#8809])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-jsl-1: NOTRUN -> [SKIP][25] ([i915#3555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][26] ([i915#3708] / [i915#4077]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][27] ([i915#3708]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- {bat-rpls-3}: [DMESG-WARN][28] ([i915#5591]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/bat-rpls-3/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#10234]: https://gitlab.freedesktop.org/drm/intel/issues/10234
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886
Build changes
-------------
* Linux: CI_DRM_14354 -> Patchwork_130480v1
CI-20190529: 20190529
CI_DRM_14354: 0fbbc7c5d35d6bef7e7849f4e627658c41671188 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7731: 17f897a81868fb35c6a7033a8b07256659742248 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_130480v1: 0fbbc7c5d35d6bef7e7849f4e627658c41671188 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ad09defd0f9e drm/i915: Implement vblank synchronized MBUS join changes
04f9a8d4080b drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/index.html
[-- Attachment #2: Type: text/html, Size: 10929 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for Enable fastset for mbus_join state change
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
` (3 preceding siblings ...)
2024-02-28 8:56 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-02-28 23:21 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2024-02-28 23:21 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 75960 bytes --]
== Series Details ==
Series: Enable fastset for mbus_join state change
URL : https://patchwork.freedesktop.org/series/130480/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14354_full -> Patchwork_130480v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_130480v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-rkl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [FAIL][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) ([i915#8293]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-7/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-7/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-7/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-2/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-2/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-1/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-1/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#8411]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#6230])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@api_intel_bb@crc32.html
* igt@api_intel_bb@render-ccs:
- shard-dg2: NOTRUN -> [FAIL][50] ([i915#10288])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@api_intel_bb@render-ccs.html
* igt@drm_fdinfo@busy-check-all:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271]) +20 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@drm_fdinfo@busy-check-all.html
* igt@drm_fdinfo@busy-check-all@ccs3:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#8414]) +11 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@drm_fdinfo@busy-check-all@ccs3.html
* igt@fbdev@pan:
- shard-snb: NOTRUN -> [FAIL][53] ([i915#4435])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@fbdev@pan.html
* igt@gem_bad_reloc@negative-reloc-bltcopy:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#3281]) +4 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_bad_reloc@negative-reloc-bltcopy.html
* igt@gem_busy@semaphore:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#3936])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@gem_busy@semaphore.html
* igt@gem_caching@writes:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#4873])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_caching@writes.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#6335])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_create@create-ext-cpu-access-big.html
- shard-dg2: NOTRUN -> [ABORT][58] ([i915#10183])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][59] -> [FAIL][60] ([i915#6268])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
- shard-tglu: [PASS][61] -> [FAIL][62] ([i915#6268])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#8555]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_ctx_persistence@heartbeat-hang.html
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#8555])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#5882]) +9 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#5882]) +5 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][67] ([i915#7975] / [i915#8213])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_eio@hibernate.html
* igt@gem_eio@unwedge-stress:
- shard-dg1: [PASS][68] -> [FAIL][69] ([i915#5784])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-13/igt@gem_eio@unwedge-stress.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-17/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#4525])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-dg2: NOTRUN -> [FAIL][71] ([i915#9606])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_capture@many-4k-zero:
- shard-glk: NOTRUN -> [FAIL][72] ([i915#9606])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][73] ([i915#2842])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][74] ([i915#2842]) +3 other tests fail
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#3539] / [i915#4852]) +4 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_exec_fair@basic-pace-share.html
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#4473] / [i915#4771])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_exec_fair@basic-pace-share.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][77] -> [FAIL][78] ([i915#2842])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][79] -> [FAIL][80] ([i915#2842]) +2 other tests fail
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fence@concurrent:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4812])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_exec_fence@concurrent.html
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4812])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#3711])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-active:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3281]) +16 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_exec_reloc@basic-active.html
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#3281])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-read-noreloc.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#4537] / [i915#4812])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_suspend@basic-s0@smem:
- shard-dg2: [PASS][87] -> [INCOMPLETE][88] ([i915#9275])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-2/igt@gem_exec_suspend@basic-s0@smem.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: NOTRUN -> [ABORT][89] ([i915#7975] / [i915#8213])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#4860]) +4 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_fence_thrash@bo-write-verify-x.html
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#4860])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#4613])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-random:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#4613])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap_gtt@basic-copy:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#4077])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_mmap_gtt@basic-copy.html
* igt@gem_mmap_gtt@basic-small-bo:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#4077]) +9 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@gem_mmap_gtt@basic-small-bo.html
* igt@gem_mmap_wc@invalid-flags:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4083]) +7 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_mmap_wc@invalid-flags.html
* igt@gem_mmap_wc@write:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#4083]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_mmap_wc@write.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#3282]) +3 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_pwrite_snooped:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#3282])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_pwrite_snooped.html
* igt@gem_pxp@create-valid-protected-context:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#4270]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#4270]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#8428])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_tiled_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#4079])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@gem_render_tiled_blits@basic.html
* igt@gem_softpin@noreloc-s3:
- shard-mtlp: [PASS][104] -> [ABORT][105] ([i915#8213])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-mtlp-1/igt@gem_softpin@noreloc-s3.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-5/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@coherency-sync:
- shard-rkl: NOTRUN -> [SKIP][106] ([fdo#110542])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#3297] / [i915#4880])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#3297]) +2 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][109] ([fdo#109289]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#2856])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-out:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#2527])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#2856]) +5 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][113] -> [ABORT][114] ([i915#9697])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
- shard-snb: [PASS][115] -> [INCOMPLETE][116] ([i915#10137] / [i915#9849])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb1/igt@i915_module_load@reload-with-fault-injection.html
- shard-tglu: [PASS][117] -> [INCOMPLETE][118] ([i915#10137])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-6/igt@i915_module_load@reload-with-fault-injection.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-glk: [PASS][119] -> [INCOMPLETE][120] ([i915#10137] / [i915#9849])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [PASS][121] -> [FAIL][122] ([i915#3591])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-glk: [PASS][123] -> [DMESG-WARN][124] ([i915#118])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-glk1/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk8/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#4387])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@i915_pm_sseu@full-enable.html
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#8437])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-dg2: NOTRUN -> [SKIP][127] ([fdo#109303])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_query@query-topology-unsupported:
- shard-dg2: NOTRUN -> [SKIP][128] ([fdo#109302])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@i915_query@query-topology-unsupported.html
* igt@i915_selftest@mock@memory_region:
- shard-rkl: NOTRUN -> [DMESG-WARN][129] ([i915#9311])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@i915_selftest@mock@memory_region.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#4212]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#8709]) +3 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#8709]) +11 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][133] ([fdo#111614]) +3 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-1/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][134] ([fdo#111614])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-rkl: NOTRUN -> [SKIP][135] ([i915#5286])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][136] ([fdo#111615]) +2 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][137] ([fdo#110723]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#4538] / [i915#5190]) +11 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-glk: NOTRUN -> [SKIP][139] ([fdo#109271]) +54 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#5190]) +7 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#2705])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#7213]) +3 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-dg2: NOTRUN -> [SKIP][143] ([fdo#111827]) +3 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_chamelium_color@ctm-0-25.html
- shard-mtlp: NOTRUN -> [SKIP][144] ([fdo#111827])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-rkl: NOTRUN -> [SKIP][145] ([fdo#111827])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_chamelium_color@ctm-0-75.html
* igt@kms_chamelium_edid@vga-edid-read:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#7828]) +1 other test skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_chamelium_edid@vga-edid-read.html
* igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#7828])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-after-suspend:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#7828]) +10 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#7118] / [i915#9424])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#3299])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_cursor_crc@cursor-offscreen-32x10:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#3555] / [i915#8814]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-offscreen-32x10.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#3359]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-rkl: NOTRUN -> [SKIP][153] ([i915#3359])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-64x21:
- shard-mtlp: NOTRUN -> [SKIP][154] ([i915#8814])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-sliding-64x21.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#9809])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-rkl: NOTRUN -> [SKIP][156] ([fdo#111767] / [fdo#111825])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: NOTRUN -> [SKIP][157] ([fdo#109274] / [i915#5354]) +3 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][158] -> [FAIL][159] ([i915#2346])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#9833])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][161] ([fdo#110189] / [i915#9723])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-12/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#3555]) +5 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#8812])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-with-formats:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#3555] / [i915#3840])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_dsc@dsc-with-formats.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#4854])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#9337])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_feature_discovery@dp-mst.html
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#9337])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#658])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-dg2: NOTRUN -> [SKIP][169] ([fdo#109274] / [fdo#111767])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
- shard-mtlp: NOTRUN -> [SKIP][170] ([fdo#111767] / [i915#3637])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][171] ([fdo#109274]) +5 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-dg1: NOTRUN -> [SKIP][172] ([fdo#111825] / [i915#9934])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-17/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-rkl: NOTRUN -> [SKIP][173] ([fdo#111825]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#3637])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#2672] / [i915#3555])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#2672]) +4 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#2672])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#2672] / [i915#3555])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-dg2: [PASS][179] -> [FAIL][180] ([i915#6880])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#5354]) +33 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][182] ([fdo#111767] / [i915#5354])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-snb: [PASS][183] -> [SKIP][184] ([fdo#109271]) +6 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#10055])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#3023]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][187] ([fdo#111825] / [i915#1825]) +5 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#8708]) +18 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#10070])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#3458]) +25 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][191] ([i915#1825]) +5 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-rkl: NOTRUN -> [SKIP][192] ([fdo#111767] / [fdo#111825] / [i915#1825])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#8708]) +3 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#6118])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#3555] / [i915#8228])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#3555] / [i915#8228])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-suspend:
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#3555] / [i915#8228])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#4070] / [i915#4816])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-mtlp: NOTRUN -> [SKIP][199] ([fdo#109289]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane_lowres@tiling-x@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#3582]) +3 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_plane_lowres@tiling-x@pipe-a-edp-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#9423]) +7 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#9423]) +5 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#9423]) +15 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-15/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#5176]) +1 other test skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][205] ([i915#5176] / [i915#9423]) +1 other test skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#5235]) +3 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-17/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#5235] / [i915#9423]) +3 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#5235]) +5 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][210] ([i915#5235]) +2 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][211] ([i915#3555] / [i915#5235])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#9519]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][213] -> [SKIP][214] ([i915#9519])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@pc8-residency:
- shard-rkl: NOTRUN -> [SKIP][215] ([fdo#109293] / [fdo#109506])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_pm_rpm@pc8-residency.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][216] ([fdo#110189]) +3 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][217] ([fdo#110189]) +1 other test skip
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-glk: NOTRUN -> [SKIP][218] ([fdo#109271] / [fdo#110189])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@pr-sprite-blt:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#9688]) +3 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@kms_psr@pr-sprite-blt.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#9732]) +25 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_psr@psr-cursor-render.html
* igt@kms_psr@psr-primary-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#9732]) +3 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_psr@psr-primary-mmap-cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#9685])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#4235]) +2 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#4235] / [i915#5190])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][225] ([i915#5465]) +3 other tests fail
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#3555]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][227] -> [FAIL][228] ([i915#9196])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4:
- shard-dg1: [PASS][229] -> [FAIL][230] ([i915#9196])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-16/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-16/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-4.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [PASS][231] -> [FAIL][232] ([i915#9196])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#9906])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-fb-id:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#2437])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#2437] / [i915#9412]) +1 other test skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][236] ([fdo#109271] / [i915#2437])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][237] ([i915#2436] / [i915#7387])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@global-sseu-config:
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#7387])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@perf@global-sseu-config.html
- shard-dg2: NOTRUN -> [SKIP][239] ([i915#7387])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@perf@global-sseu-config.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][240] ([i915#6806])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-1/igt@perf_pmu@frequency@gt0.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: NOTRUN -> [CRASH][241] ([i915#9351])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#3291] / [i915#3708])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#3708] / [i915#4077])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#3708]) +1 other test skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg2: NOTRUN -> [SKIP][245] ([i915#9917])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][246] ([i915#9779])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_get_param@get-bad-flags:
- shard-mtlp: NOTRUN -> [SKIP][247] ([i915#2575]) +2 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@v3d/v3d_get_param@get-bad-flags.html
* igt@v3d/v3d_submit_cl@multisync-out-syncs:
- shard-dg2: NOTRUN -> [SKIP][248] ([i915#2575]) +15 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@v3d/v3d_submit_cl@multisync-out-syncs.html
* igt@v3d/v3d_wait_bo@bad-bo:
- shard-rkl: NOTRUN -> [SKIP][249] ([fdo#109315]) +2 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@v3d/v3d_wait_bo@bad-bo.html
* igt@vc4/vc4_label_bo@set-label:
- shard-rkl: NOTRUN -> [SKIP][250] ([i915#7711])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-dg2: NOTRUN -> [SKIP][251] ([i915#7711]) +8 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
- shard-mtlp: NOTRUN -> [SKIP][252] ([i915#7711])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-3/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][253] ([i915#7742]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [FAIL][255] ([i915#2842]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_sync@basic-store-all:
- shard-snb: [ABORT][257] -> [PASS][258]
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb4/igt@gem_sync@basic-store-all.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@gem_sync@basic-store-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [INCOMPLETE][259] ([i915#10137] / [i915#5566]) -> [PASS][260]
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][261] ([i915#3763] / [i915#5138]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglu: [FAIL][263] ([i915#3743]) -> [PASS][264] +1 other test pass
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-snb: [SKIP][265] ([fdo#109271] / [fdo#111767]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-snb: [DMESG-WARN][267] ([i915#10007]) -> [PASS][268]
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb1/igt@kms_fbcon_fbt@fbc-suspend.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-snb: [SKIP][269] ([fdo#109271]) -> [PASS][270] +8 other tests pass
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: [FAIL][271] ([i915#8292]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][273] ([i915#4281]) -> [PASS][274]
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-8/igt@kms_pm_dc@dc9-dpms.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-10/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [SKIP][275] ([i915#9519]) -> [PASS][276] +1 other test pass
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-5/igt@kms_pm_rpm@dpms-lpsp.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-10/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [SKIP][277] ([i915#9519]) -> [PASS][278] +1 other test pass
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [FAIL][279] ([i915#9196]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [FAIL][281] ([i915#9196]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3:
- shard-dg2: [FAIL][283] ([i915#9196]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-1/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
#### Warnings ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: [INCOMPLETE][285] ([i915#10137] / [i915#9408] / [i915#9618]) -> [ABORT][286] ([i915#9618])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-12/igt@device_reset@unbind-reset-rebind.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-13/igt@device_reset@unbind-reset-rebind.html
* igt@gem_exec_reloc@basic-write-read:
- shard-dg2: [TIMEOUT][287] -> [SKIP][288] ([i915#3281])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-6/igt@gem_exec_reloc@basic-write-read.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_partial_pwrite_pread@reads-display:
- shard-dg2: [TIMEOUT][289] -> [SKIP][290] ([i915#3282])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-6/igt@gem_partial_pwrite_pread@reads-display.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@gem_partial_pwrite_pread@reads-display.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [INCOMPLETE][291] ([i915#10137] / [i915#9849]) -> [INCOMPLETE][292] ([i915#10137] / [i915#9820] / [i915#9849])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-16/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [INCOMPLETE][293] ([i915#10137] / [i915#9849]) -> [DMESG-WARN][294] ([i915#9559])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_content_protection@lic-type-1:
- shard-snb: [INCOMPLETE][295] ([i915#10137]) -> [SKIP][296] ([fdo#109271])
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-snb7/igt@kms_content_protection@lic-type-1.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-snb6/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][297] ([i915#9424]) -> [SKIP][298] ([i915#9433])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg1-17/igt@kms_content_protection@mei-interface.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg1-12/igt@kms_content_protection@mei-interface.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][299] ([i915#3955]) -> [SKIP][300] ([fdo#110189] / [i915#3955])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-3/igt@kms_fbcon_fbt@psr.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][301] ([fdo#110189] / [i915#3955]) -> [SKIP][302] ([i915#3955])
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg2: [TIMEOUT][303] -> [SKIP][304] ([fdo#109274])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-6/igt@kms_flip@2x-absolute-wf_vblank.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [FAIL][305] ([i915#9295]) -> [SKIP][306] ([i915#3361])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-rkl-7/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-dg2: [TIMEOUT][307] -> [SKIP][308] ([i915#9732])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14354/shard-dg2-6/igt@kms_psr@fbc-psr2-sprite-render.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/shard-dg2-2/igt@kms_psr@fbc-psr2-sprite-render.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#10007]: https://gitlab.freedesktop.org/drm/intel/issues/10007
[i915#10055]: https://gitlab.freedesktop.org/drm/intel/issues/10055
[i915#10070]: https://gitlab.freedesktop.org/drm/intel/issues/10070
[i915#10137]: https://gitlab.freedesktop.org/drm/intel/issues/10137
[i915#10183]: https://gitlab.freedesktop.org/drm/intel/issues/10183
[i915#10288]: https://gitlab.freedesktop.org/drm/intel/issues/10288
[i915#10307]: https://gitlab.freedesktop.org/drm/intel/issues/10307
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3711]: https://gitlab.freedesktop.org/drm/intel/issues/3711
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4435]: https://gitlab.freedesktop.org/drm/intel/issues/4435
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8437]: https://gitlab.freedesktop.org/drm/intel/issues/8437
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
[i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/intel/issues/9311
[i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
[i915#9408]: https://gitlab.freedesktop.org/drm/intel/issues/9408
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9559]: https://gitlab.freedesktop.org/drm/intel/issues/9559
[i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606
[i915#9618]: https://gitlab.freedesktop.org/drm/intel/issues/9618
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
[i915#9697]: https://gitlab.freedesktop.org/drm/intel/issues/9697
[i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/intel/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
[i915#9779]: https://gitlab.freedesktop.org/drm/intel/issues/9779
[i915#9809]: https://gitlab.freedesktop.org/drm/intel/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/intel/issues/9833
[i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/intel/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/intel/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/intel/issues/9934
Build changes
-------------
* Linux: CI_DRM_14354 -> Patchwork_130480v1
CI-20190529: 20190529
CI_DRM_14354: 0fbbc7c5d35d6bef7e7849f4e627658c41671188 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7731: 17f897a81868fb35c6a7033a8b07256659742248 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_130480v1: 0fbbc7c5d35d6bef7e7849f4e627658c41671188 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130480v1/index.html
[-- Attachment #2: Type: text/html, Size: 91039 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly
2024-02-28 8:02 ` [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
@ 2024-03-05 19:52 ` Paz Zcharya
0 siblings, 0 replies; 12+ messages in thread
From: Paz Zcharya @ 2024-03-05 19:52 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen, ville.syrjala
On Wed, Feb 28, 2024 at 10:02:12AM +0200, Stanislav Lisovskiy wrote:
> According to BSpec we need to do correspondent MBUS updates before
> or after DBUF reallocation, depending on whether we are reducing
> or increasing amount of pipes(typical scenario is swithing between
> multiple and single displays).
>
> As of BSpec 49213 if we are swithing from multiple to single display
> MBUS registers should be updated with correspondent values _before_
> Dbuf reallocation happens, however if we are switching from single
> display to multiple then it should happen _after_ DDB reallocation(i.e
> plane programming).
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Thank you for this patch, Stanislav!
We tested it on a MTL-U based Chromebook (Screebo),
using different configurations (eDP, eDP + HDMI, HDMI, etc.), and
it worked well -- joined the mbus + no visual issues or i915 errors.
Tested-by: Paz Zcharya <pazz@chromium.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-02-28 8:02 ` [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
@ 2024-03-05 19:54 ` Paz Zcharya
2024-03-08 10:07 ` Ville Syrjälä
1 sibling, 0 replies; 12+ messages in thread
From: Paz Zcharya @ 2024-03-05 19:54 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen, ville.syrjala
On Wed, Feb 28, 2024 at 10:02:13AM +0200, Stanislav Lisovskiy wrote:
> Currently we can't change MBUS join status without doing a modeset,
> because we are lacking mechanism to synchronize those with vblank.
> However then this means that we can't do a fastset, if there is a need
> to change MBUS join state. Fix that by implementing such change.
> We already call correspondent check and update at pre_plane dbuf update,
> so the only thing left is to have a non-modeset version of that.
> If active pipes stay the same then fastset is possible and only MBUS
> join state/ddb allocation updates would be committed.
>
> v2: Implement additional changes according to BSpec.
> Vblank wait is needed after MBus/Dbuf programming in case if
> no modeset is done and we are switching from single to multiple
> displays, i.e mbus join state switches from "joined" to "non-joined"
> state. Otherwise vblank wait is not needed according to spec.
>
> v3: Split mbus and dbox programming into to pre/post plane update parts,
> how it should be done according to BSpec.
>
> v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
> after DDB reallocation, but before crtc enabling(that is where is has
> to be according to spec).
> - Check if crtc is still active, not only the old state.
> - Do a vblank wait if MBUX DBOX register was modified.
> - And of course do vblank wait only if crtc was active.
> - Do vblank wait only if we are not doing a modeset, if we are doing
> something before *commit_modeset_enables, because all crtcs might be
> disabled at this moment, so we will get WARN if try waiting for vblank
> then.
> - Still getting FIFO underrun so try waiting for vblank in pre_plane update
> as well.
> - Write also pipe that we need to sync with to MBUS_CTL register.
>
> v5: - Do vblank wait only for the first pipe, if mbus is joined
> - Check also if new/old_dbuf_state is not NULL, before getting single pipe
> and active pipes.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Thank you for this patch, Stanislav!
We tested it on a MTL-U based Chromebook (Screebo),
using different configurations (eDP, eDP + HDMI, HDMI, etc.), and
it worked well -- joined the mbus + no visual issues or i915 errors.
Tested-by: Paz Zcharya <pazz@chromium.org>
Just a small note, checkpatch.pl is complaining about a few things.
I assume you probably saw it, but flagging just in case.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-02-28 8:02 ` [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
2024-03-05 19:54 ` Paz Zcharya
@ 2024-03-08 10:07 ` Ville Syrjälä
2024-03-08 13:43 ` Lisovskiy, Stanislav
1 sibling, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2024-03-08 10:07 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx, jani.saarinen
On Wed, Feb 28, 2024 at 10:02:13AM +0200, Stanislav Lisovskiy wrote:
> Currently we can't change MBUS join status without doing a modeset,
> because we are lacking mechanism to synchronize those with vblank.
> However then this means that we can't do a fastset, if there is a need
> to change MBUS join state. Fix that by implementing such change.
> We already call correspondent check and update at pre_plane dbuf update,
> so the only thing left is to have a non-modeset version of that.
> If active pipes stay the same then fastset is possible and only MBUS
> join state/ddb allocation updates would be committed.
>
> v2: Implement additional changes according to BSpec.
> Vblank wait is needed after MBus/Dbuf programming in case if
> no modeset is done and we are switching from single to multiple
> displays, i.e mbus join state switches from "joined" to "non-joined"
> state. Otherwise vblank wait is not needed according to spec.
>
> v3: Split mbus and dbox programming into to pre/post plane update parts,
> how it should be done according to BSpec.
>
> v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
> after DDB reallocation, but before crtc enabling(that is where is has
> to be according to spec).
> - Check if crtc is still active, not only the old state.
> - Do a vblank wait if MBUX DBOX register was modified.
> - And of course do vblank wait only if crtc was active.
> - Do vblank wait only if we are not doing a modeset, if we are doing
> something before *commit_modeset_enables, because all crtcs might be
> disabled at this moment, so we will get WARN if try waiting for vblank
> then.
> - Still getting FIFO underrun so try waiting for vblank in pre_plane update
> as well.
> - Write also pipe that we need to sync with to MBUS_CTL register.
>
> v5: - Do vblank wait only for the first pipe, if mbus is joined
> - Check also if new/old_dbuf_state is not NULL, before getting single pipe
> and active pipes.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
> drivers/gpu/drm/i915/display/skl_watermark.c | 104 +++++++++++++++----
> drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> 3 files changed, 96 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 00ac65a140298..989818f5d342f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6906,6 +6906,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> }
> }
>
> + /*
> + * Some MBUS/DBuf update scenarios(mbus join disable) require that
> + * changes are done _after_ DDB reallocation, but _before_ crtc enabling.
> + * Typically we are disabling resources in post_plane/crtc_enable hooks,
> + * however in that case BSpec explicitly states that this should be done
> + * before we enable additional displays.
> + * FIXME: Should we still call this also there(post_plane hook)
> + * for extra-safety? If so, how to make sure, we don't call it twice?
> + */
> + intel_dbuf_mbus_post_ddb_update(state);
> +
> update_pipes = modeset_pipes;
>
> /*
> @@ -7148,9 +7159,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
>
> intel_encoders_update_prepare(state);
> -
> intel_dbuf_pre_plane_update(state);
> - intel_mbus_dbox_update(state);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 606b7ba9db9ce..f0604ede399f7 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2628,13 +2628,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> - /* TODO: Implement vblank synchronized MBUS joining changes */
> - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> - if (ret)
> - return ret;
> - }
> -
> drm_dbg_kms(&i915->drm,
> "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> old_dbuf_state->enabled_slices,
> @@ -3539,8 +3532,9 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> u32 mbus_ctl, dbuf_min_tracker_val;
> enum dbuf_slice slice;
> - const struct intel_dbuf_state *dbuf_state =
> + const struct intel_dbuf_state *new_dbuf_state =
> intel_atomic_get_new_dbuf_state(state);
> + enum pipe pipe = ffs(new_dbuf_state->active_pipes) - 1;
That pipe might not even be enabled at this point.
>
> if (!HAS_MBUS_JOINING(i915))
> return;
> @@ -3549,13 +3543,13 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> * TODO: Implement vblank synchronized MBUS joining changes.
> * Must be properly coordinated with dbuf reprogramming.
> */
> - if (dbuf_state->joined_mbus) {
> + if (new_dbuf_state->joined_mbus) {
> mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> - MBUS_JOIN_PIPE_SELECT_NONE;
> + MBUS_JOIN_PIPE_SELECT(pipe);
> dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> } else {
> mbus_ctl = MBUS_HASHING_MODE_2x2 |
> - MBUS_JOIN_PIPE_SELECT_NONE;
> + MBUS_JOIN_PIPE_SELECT(pipe);
> dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> }
>
> @@ -3576,21 +3570,35 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> intel_atomic_get_new_dbuf_state(state);
> const struct intel_dbuf_state *old_dbuf_state =
> intel_atomic_get_old_dbuf_state(state);
> + int new_num_active_pipes = 0;
> + int old_num_active_pipes = 0;
>
> if (!new_dbuf_state ||
> (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> return;
>
> + new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
> +
> + if (old_dbuf_state)
> + old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
> +
> WARN_ON(!new_dbuf_state->base.changed);
>
> - if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
> - || (old_dbuf_state->active_pipes == 0))
> + /*
> + * Switching from multiple to single display scenario(enable mbus join).
> + * Also we put here "<=" instead of "<" for suboptimal cases, when
> + * we switch from single => single display, enabling mbus join.
> + */
> + if (new_num_active_pipes <= old_num_active_pipes)
> intel_dbuf_mbus_update(state);
>
> gen9_dbuf_slices_update(i915,
> old_dbuf_state->enabled_slices |
> new_dbuf_state->enabled_slices);
> +
> + if (new_num_active_pipes <= old_num_active_pipes)
> + intel_mbus_dbox_update(state);
> }
>
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> @@ -3608,13 +3616,59 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>
> WARN_ON(!new_dbuf_state->base.changed);
>
> - if (hweight8(new_dbuf_state->active_pipes) > hweight8(old_dbuf_state->active_pipes))
> - intel_dbuf_mbus_update(state);
> -
> gen9_dbuf_slices_update(i915,
> new_dbuf_state->enabled_slices);
> }
>
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
> +{
> + const struct intel_dbuf_state *new_dbuf_state =
> + intel_atomic_get_new_dbuf_state(state);
> + const struct intel_dbuf_state *old_dbuf_state =
> + intel_atomic_get_old_dbuf_state(state);
> + enum pipe pipe;
> + int new_num_active_pipes = 0;
> + int old_num_active_pipes = 0;
> +
> + if (!new_dbuf_state ||
> + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> + return;
> +
> + pipe = ffs(new_dbuf_state->active_pipes) - 1;
> + new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
> +
> + if (old_dbuf_state)
> + old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
> +
> + WARN_ON(!new_dbuf_state->base.changed);
> +
> + /*
> + * Switching from single to multiple display scenario
> + */
> + if (new_num_active_pipes > old_num_active_pipes) {
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int i;
> + intel_dbuf_mbus_update(state);
> + intel_mbus_dbox_update(state);
> +
> + if (state->modeset)
> + return;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + /*
> + * According to BSpec we should wait vblank on single display,
> + * before enabling additional displays
> + */
> + if (!new_crtc_state->hw.active || (crtc->pipe != pipe))
> + continue;
> +
> + intel_crtc_wait_for_next_vblank(crtc);
We should only need this when disabling mbus joining.
> + }
> + }
> +}
> +
> static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
> {
> switch (pipe) {
> @@ -3638,8 +3692,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> - const struct intel_crtc_state *new_crtc_state;
> - const struct intel_crtc *crtc;
> + const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + struct intel_crtc *crtc;
> u32 val = 0;
> int i;
>
> @@ -3685,12 +3739,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> val |= MBUS_DBOX_B_CREDIT(8);
> }
>
> - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - u32 pipe_val = val;
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> + u32 pipe_val = val, old_pipe_val;
>
> if (!new_crtc_state->hw.active)
> continue;
>
> + old_pipe_val = intel_de_read(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe));
> +
> if (DISPLAY_VER(i915) >= 14) {
> if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> new_dbuf_state->active_pipes))
> @@ -3700,6 +3756,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> }
>
> intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
> +
> + /*
> + * BSpec instructs us to wait for vblank, if credits were changed.
> + * However we need to do that here only if crtc was active prior to change.
> + */
Supposedly only needed when changing B credits, which we never do.
If this is actually needed for other types of credits as well, then
we're going to have to do things more carefully than this because
the order in which the credits are increased vs. decreased actually
matters.
> + if (old_pipe_val != pipe_val &&
> + old_crtc_state->hw.active && !state->modeset)
> + intel_crtc_wait_for_next_vblank(crtc);
> }
> }
The patch is pretty hard to follow. And I think in
general that is because in the current code all the
functions are doing way too many things. It's really
hard to sequence anything correctly.
I think we really need to chunk things up into more sensible pieces. Eg:
mbus_dbox_ctl() -> calculate per-pipe PIPE_MBUS_DBOX_CTL value
update_mbus_dbox() -> write PIPE_MBUS_DBOX_CTL, perhaps looping over all the pipes
update_dbuf_min_tracker() -> update DBUF_CTL_S min tracker stuff
mbus_update_pipe() -> determine the pipe for MBUS_CTL update
update_mbus_ctl() -> write MBUS_CTL
And then at the high level we should be able to just have something
like:
intel_mbus_pre_ddb_update() {
if (!enabling_mbus_joining)
return;
pipe = mbus_update_pipe(new_dbuf_state)
if (pipe != INVALID)
return;
update_mbus_ctl(pipe)
update_mbus_dbox()
update_dbuf_min_tracker()
}
intel_mbus_post_ddb_update() {
if (disabling_mbus_joining)
pipe = mbus_update_pipe(old_dbuf_state);
else
pipe = INVALID
update_dbuf_min_tracker();
update_mbus_dbox();
update_mbus_ctl(pipe);
if (pipe != INVALID)
wait_for_vblank(pipe);
}
Another dodgy thing I noticed is that active_pipes now affects
PIPE_MBUS_DBOX_CTL BW credits on MTL+, but we're not taking that
into account when calculating the state. So we don't necessarily
serialize, nor do we necessarily add all the active crtcs into
the state AFAICS, so we might not program PIPE_MBUS_DBOX_CTL for
all pipes that need it. That could perhaps be fixed by the propsed
update_mbus_dbox() just looping over all active pipes (based on
dbuf_state->active_pipes), and not depend on having the crtcs in
the state.
I suppose another option would be to precompute the
PIPE_MBUS_DBOX_CTL values and serialize/etc. based on those
changing.
Although the final solution for that is going to depend on
whether we need to carefully sequence the non-B credit updates
across multiple pipes or not.
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index e3d1d74a7b170..5a97556a68c2c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -73,6 +73,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
> int intel_dbuf_init(struct drm_i915_private *i915);
> void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> void intel_mbus_dbox_update(struct intel_atomic_state *state);
>
> #endif /* __SKL_WATERMARK_H__ */
> --
> 2.37.3
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-08 10:07 ` Ville Syrjälä
@ 2024-03-08 13:43 ` Lisovskiy, Stanislav
2024-03-08 15:11 ` Ville Syrjälä
0 siblings, 1 reply; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2024-03-08 13:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 08, 2024 at 12:07:19PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 28, 2024 at 10:02:13AM +0200, Stanislav Lisovskiy wrote:
> > Currently we can't change MBUS join status without doing a modeset,
> > because we are lacking mechanism to synchronize those with vblank.
> > However then this means that we can't do a fastset, if there is a need
> > to change MBUS join state. Fix that by implementing such change.
> > We already call correspondent check and update at pre_plane dbuf update,
> > so the only thing left is to have a non-modeset version of that.
> > If active pipes stay the same then fastset is possible and only MBUS
> > join state/ddb allocation updates would be committed.
> >
> > v2: Implement additional changes according to BSpec.
> > Vblank wait is needed after MBus/Dbuf programming in case if
> > no modeset is done and we are switching from single to multiple
> > displays, i.e mbus join state switches from "joined" to "non-joined"
> > state. Otherwise vblank wait is not needed according to spec.
> >
> > v3: Split mbus and dbox programming into to pre/post plane update parts,
> > how it should be done according to BSpec.
> >
> > v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
> > after DDB reallocation, but before crtc enabling(that is where is has
> > to be according to spec).
> > - Check if crtc is still active, not only the old state.
> > - Do a vblank wait if MBUX DBOX register was modified.
> > - And of course do vblank wait only if crtc was active.
> > - Do vblank wait only if we are not doing a modeset, if we are doing
> > something before *commit_modeset_enables, because all crtcs might be
> > disabled at this moment, so we will get WARN if try waiting for vblank
> > then.
> > - Still getting FIFO underrun so try waiting for vblank in pre_plane update
> > as well.
> > - Write also pipe that we need to sync with to MBUS_CTL register.
> >
> > v5: - Do vblank wait only for the first pipe, if mbus is joined
> > - Check also if new/old_dbuf_state is not NULL, before getting single pipe
> > and active pipes.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
> > drivers/gpu/drm/i915/display/skl_watermark.c | 104 +++++++++++++++----
> > drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> > 3 files changed, 96 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 00ac65a140298..989818f5d342f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6906,6 +6906,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > }
> > }
> >
> > + /*
> > + * Some MBUS/DBuf update scenarios(mbus join disable) require that
> > + * changes are done _after_ DDB reallocation, but _before_ crtc enabling.
> > + * Typically we are disabling resources in post_plane/crtc_enable hooks,
> > + * however in that case BSpec explicitly states that this should be done
> > + * before we enable additional displays.
> > + * FIXME: Should we still call this also there(post_plane hook)
> > + * for extra-safety? If so, how to make sure, we don't call it twice?
> > + */
> > + intel_dbuf_mbus_post_ddb_update(state);
> > +
> > update_pipes = modeset_pipes;
> >
> > /*
> > @@ -7148,9 +7159,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > }
> >
> > intel_encoders_update_prepare(state);
> > -
> > intel_dbuf_pre_plane_update(state);
> > - intel_mbus_dbox_update(state);
> >
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (new_crtc_state->do_async_flip)
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 606b7ba9db9ce..f0604ede399f7 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -2628,13 +2628,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> > - /* TODO: Implement vblank synchronized MBUS joining changes */
> > - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> > - if (ret)
> > - return ret;
> > - }
> > -
> > drm_dbg_kms(&i915->drm,
> > "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> > old_dbuf_state->enabled_slices,
> > @@ -3539,8 +3532,9 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > u32 mbus_ctl, dbuf_min_tracker_val;
> > enum dbuf_slice slice;
> > - const struct intel_dbuf_state *dbuf_state =
> > + const struct intel_dbuf_state *new_dbuf_state =
> > intel_atomic_get_new_dbuf_state(state);
> > + enum pipe pipe = ffs(new_dbuf_state->active_pipes) - 1;
>
> That pipe might not even be enabled at this point.
Which scenario do you mean?
intel_dbuf_mbus_update is called in two cases:
1) When switching from single display to multiple displays, according
to spec we should program it before enabling additional displays,
but after ddb allocation happens.
2) When switching from multiple displays to a single display,
we program it after disabling all displays except one, but
before ddb reallocation happens.
Probably you mean the case when its called from intel_dbuf_pre_plane_update,
because commit_modeset_enables hasn't been yet called?
That would be the case of switching from multiple displays to single one,
for non-modeset at least shoudln't be a problem, as I understand.
But where should this be called then from?
We always called this function from intel_dbuf_pre_plane_update.
>
> >
> > if (!HAS_MBUS_JOINING(i915))
> > return;
> > @@ -3549,13 +3543,13 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> > * TODO: Implement vblank synchronized MBUS joining changes.
> > * Must be properly coordinated with dbuf reprogramming.
> > */
> > - if (dbuf_state->joined_mbus) {
> > + if (new_dbuf_state->joined_mbus) {
> > mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> > - MBUS_JOIN_PIPE_SELECT_NONE;
> > + MBUS_JOIN_PIPE_SELECT(pipe);
> > dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
> > } else {
> > mbus_ctl = MBUS_HASHING_MODE_2x2 |
> > - MBUS_JOIN_PIPE_SELECT_NONE;
> > + MBUS_JOIN_PIPE_SELECT(pipe);
> > dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
> > }
> >
> > @@ -3576,21 +3570,35 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
> > intel_atomic_get_new_dbuf_state(state);
> > const struct intel_dbuf_state *old_dbuf_state =
> > intel_atomic_get_old_dbuf_state(state);
> > + int new_num_active_pipes = 0;
> > + int old_num_active_pipes = 0;
> >
> > if (!new_dbuf_state ||
> > (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > return;
> >
> > + new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
> > +
> > + if (old_dbuf_state)
> > + old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
> > +
> > WARN_ON(!new_dbuf_state->base.changed);
> >
> > - if ((hweight8(new_dbuf_state->active_pipes) <= hweight8(old_dbuf_state->active_pipes))
> > - || (old_dbuf_state->active_pipes == 0))
> > + /*
> > + * Switching from multiple to single display scenario(enable mbus join).
> > + * Also we put here "<=" instead of "<" for suboptimal cases, when
> > + * we switch from single => single display, enabling mbus join.
> > + */
> > + if (new_num_active_pipes <= old_num_active_pipes)
> > intel_dbuf_mbus_update(state);
> >
> > gen9_dbuf_slices_update(i915,
> > old_dbuf_state->enabled_slices |
> > new_dbuf_state->enabled_slices);
> > +
> > + if (new_num_active_pipes <= old_num_active_pipes)
> > + intel_mbus_dbox_update(state);
> > }
> >
> > void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> > @@ -3608,13 +3616,59 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
> >
> > WARN_ON(!new_dbuf_state->base.changed);
> >
> > - if (hweight8(new_dbuf_state->active_pipes) > hweight8(old_dbuf_state->active_pipes))
> > - intel_dbuf_mbus_update(state);
> > -
> > gen9_dbuf_slices_update(i915,
> > new_dbuf_state->enabled_slices);
> > }
> >
> > +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)
> > +{
> > + const struct intel_dbuf_state *new_dbuf_state =
> > + intel_atomic_get_new_dbuf_state(state);
> > + const struct intel_dbuf_state *old_dbuf_state =
> > + intel_atomic_get_old_dbuf_state(state);
> > + enum pipe pipe;
> > + int new_num_active_pipes = 0;
> > + int old_num_active_pipes = 0;
> > +
> > + if (!new_dbuf_state ||
> > + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
> > + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
> > + return;
> > +
> > + pipe = ffs(new_dbuf_state->active_pipes) - 1;
> > + new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
> > +
> > + if (old_dbuf_state)
> > + old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
> > +
> > + WARN_ON(!new_dbuf_state->base.changed);
> > +
> > + /*
> > + * Switching from single to multiple display scenario
> > + */
> > + if (new_num_active_pipes > old_num_active_pipes) {
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *new_crtc_state;
> > + int i;
> > + intel_dbuf_mbus_update(state);
> > + intel_mbus_dbox_update(state);
> > +
> > + if (state->modeset)
> > + return;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + /*
> > + * According to BSpec we should wait vblank on single display,
> > + * before enabling additional displays
> > + */
> > + if (!new_crtc_state->hw.active || (crtc->pipe != pipe))
> > + continue;
> > +
> > + intel_crtc_wait_for_next_vblank(crtc);
>
> We should only need this when disabling mbus joining.
But this is exactly the case since this is called when we switch from single to
multiple displays.
>
> > + }
> > + }
> > +}
> > +
> > static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
> > {
> > switch (pipe) {
> > @@ -3638,8 +3692,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> > - const struct intel_crtc_state *new_crtc_state;
> > - const struct intel_crtc *crtc;
> > + const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > + struct intel_crtc *crtc;
> > u32 val = 0;
> > int i;
> >
> > @@ -3685,12 +3739,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> > val |= MBUS_DBOX_B_CREDIT(8);
> > }
> >
> > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > - u32 pipe_val = val;
> > + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > + u32 pipe_val = val, old_pipe_val;
> >
> > if (!new_crtc_state->hw.active)
> > continue;
> >
> > + old_pipe_val = intel_de_read(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe));
> > +
> > if (DISPLAY_VER(i915) >= 14) {
> > if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> > new_dbuf_state->active_pipes))
> > @@ -3700,6 +3756,14 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state)
> > }
> >
> > intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
> > +
> > + /*
> > + * BSpec instructs us to wait for vblank, if credits were changed.
> > + * However we need to do that here only if crtc was active prior to change.
> > + */
>
> Supposedly only needed when changing B credits, which we never do.
>
> If this is actually needed for other types of credits as well, then
> we're going to have to do things more carefully than this because
> the order in which the credits are increased vs. decreased actually
> matters.
Yep, this is artefact after my experimenting trying to figure out where FIFO underrun
was coming from. Can try removing it, hopefully won't harm.
>
> > + if (old_pipe_val != pipe_val &&
> > + old_crtc_state->hw.active && !state->modeset)
> > + intel_crtc_wait_for_next_vblank(crtc);
> > }
> > }
>
> The patch is pretty hard to follow. And I think in
> general that is because in the current code all the
> functions are doing way too many things. It's really
> hard to sequence anything correctly.
>
> I think we really need to chunk things up into more sensible pieces. Eg:
> mbus_dbox_ctl() -> calculate per-pipe PIPE_MBUS_DBOX_CTL value
> update_mbus_dbox() -> write PIPE_MBUS_DBOX_CTL, perhaps looping over all the pipes
> update_dbuf_min_tracker() -> update DBUF_CTL_S min tracker stuff
> mbus_update_pipe() -> determine the pipe for MBUS_CTL update
> update_mbus_ctl() -> write MBUS_CTL
>
> And then at the high level we should be able to just have something
> like:
>
> intel_mbus_pre_ddb_update() {
> if (!enabling_mbus_joining)
> return;
>
> pipe = mbus_update_pipe(new_dbuf_state)
> if (pipe != INVALID)
> return;
>
> update_mbus_ctl(pipe)
> update_mbus_dbox()
> update_dbuf_min_tracker()
> }
>
> intel_mbus_post_ddb_update() {
> if (disabling_mbus_joining)
> pipe = mbus_update_pipe(old_dbuf_state);
> else
> pipe = INVALID
>
> update_dbuf_min_tracker();
> update_mbus_dbox();
> update_mbus_ctl(pipe);
>
> if (pipe != INVALID)
> wait_for_vblank(pipe);
> }
Will do that. I was mostly concerned to make it _just work_ initially.
>
>
> Another dodgy thing I noticed is that active_pipes now affects
> PIPE_MBUS_DBOX_CTL BW credits on MTL+, but we're not taking that
> into account when calculating the state. So we don't necessarily
> serialize, nor do we necessarily add all the active crtcs into
> the state AFAICS, so we might not program PIPE_MBUS_DBOX_CTL for
> all pipes that need it. That could perhaps be fixed by the propsed
> update_mbus_dbox() just looping over all active pipes (based on
> dbuf_state->active_pipes), and not depend on having the crtcs in
> the state.
Considering our tight schedule I would go that way for now..
Stan
>
> I suppose another option would be to precompute the
> PIPE_MBUS_DBOX_CTL values and serialize/etc. based on those
> changing.
>
> Although the final solution for that is going to depend on
> whether we need to carefully sequence the non-B credit updates
> across multiple pipes or not.
>
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> > index e3d1d74a7b170..5a97556a68c2c 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> > @@ -73,6 +73,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
> > int intel_dbuf_init(struct drm_i915_private *i915);
> > void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
> > void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
> > +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
> > void intel_mbus_dbox_update(struct intel_atomic_state *state);
> >
> > #endif /* __SKL_WATERMARK_H__ */
> > --
> > 2.37.3
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-08 13:43 ` Lisovskiy, Stanislav
@ 2024-03-08 15:11 ` Ville Syrjälä
2024-03-11 9:41 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2024-03-08 15:11 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 08, 2024 at 03:43:35PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 08, 2024 at 12:07:19PM +0200, Ville Syrjälä wrote:
> > On Wed, Feb 28, 2024 at 10:02:13AM +0200, Stanislav Lisovskiy wrote:
> > > Currently we can't change MBUS join status without doing a modeset,
> > > because we are lacking mechanism to synchronize those with vblank.
> > > However then this means that we can't do a fastset, if there is a need
> > > to change MBUS join state. Fix that by implementing such change.
> > > We already call correspondent check and update at pre_plane dbuf update,
> > > so the only thing left is to have a non-modeset version of that.
> > > If active pipes stay the same then fastset is possible and only MBUS
> > > join state/ddb allocation updates would be committed.
> > >
> > > v2: Implement additional changes according to BSpec.
> > > Vblank wait is needed after MBus/Dbuf programming in case if
> > > no modeset is done and we are switching from single to multiple
> > > displays, i.e mbus join state switches from "joined" to "non-joined"
> > > state. Otherwise vblank wait is not needed according to spec.
> > >
> > > v3: Split mbus and dbox programming into to pre/post plane update parts,
> > > how it should be done according to BSpec.
> > >
> > > v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
> > > after DDB reallocation, but before crtc enabling(that is where is has
> > > to be according to spec).
> > > - Check if crtc is still active, not only the old state.
> > > - Do a vblank wait if MBUX DBOX register was modified.
> > > - And of course do vblank wait only if crtc was active.
> > > - Do vblank wait only if we are not doing a modeset, if we are doing
> > > something before *commit_modeset_enables, because all crtcs might be
> > > disabled at this moment, so we will get WARN if try waiting for vblank
> > > then.
> > > - Still getting FIFO underrun so try waiting for vblank in pre_plane update
> > > as well.
> > > - Write also pipe that we need to sync with to MBUS_CTL register.
> > >
> > > v5: - Do vblank wait only for the first pipe, if mbus is joined
> > > - Check also if new/old_dbuf_state is not NULL, before getting single pipe
> > > and active pipes.
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
> > > drivers/gpu/drm/i915/display/skl_watermark.c | 104 +++++++++++++++----
> > > drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> > > 3 files changed, 96 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 00ac65a140298..989818f5d342f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6906,6 +6906,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > > }
> > > }
> > >
> > > + /*
> > > + * Some MBUS/DBuf update scenarios(mbus join disable) require that
> > > + * changes are done _after_ DDB reallocation, but _before_ crtc enabling.
> > > + * Typically we are disabling resources in post_plane/crtc_enable hooks,
> > > + * however in that case BSpec explicitly states that this should be done
> > > + * before we enable additional displays.
> > > + * FIXME: Should we still call this also there(post_plane hook)
> > > + * for extra-safety? If so, how to make sure, we don't call it twice?
> > > + */
> > > + intel_dbuf_mbus_post_ddb_update(state);
> > > +
> > > update_pipes = modeset_pipes;
> > >
> > > /*
> > > @@ -7148,9 +7159,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > }
> > >
> > > intel_encoders_update_prepare(state);
> > > -
> > > intel_dbuf_pre_plane_update(state);
> > > - intel_mbus_dbox_update(state);
> > >
> > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > if (new_crtc_state->do_async_flip)
> > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > index 606b7ba9db9ce..f0604ede399f7 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > @@ -2628,13 +2628,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> > > if (ret)
> > > return ret;
> > >
> > > - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> > > - /* TODO: Implement vblank synchronized MBUS joining changes */
> > > - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> > > - if (ret)
> > > - return ret;
> > > - }
> > > -
> > > drm_dbg_kms(&i915->drm,
> > > "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> > > old_dbuf_state->enabled_slices,
> > > @@ -3539,8 +3532,9 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> > > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > u32 mbus_ctl, dbuf_min_tracker_val;
> > > enum dbuf_slice slice;
> > > - const struct intel_dbuf_state *dbuf_state =
> > > + const struct intel_dbuf_state *new_dbuf_state =
> > > intel_atomic_get_new_dbuf_state(state);
> > > + enum pipe pipe = ffs(new_dbuf_state->active_pipes) - 1;
> >
> > That pipe might not even be enabled at this point.
>
> Which scenario do you mean?
> intel_dbuf_mbus_update is called in two cases:
>
> 1) When switching from single display to multiple displays, according
> to spec we should program it before enabling additional displays,
> but after ddb allocation happens.
>
> 2) When switching from multiple displays to a single display,
> we program it after disabling all displays except one, but
> before ddb reallocation happens.
You seem to call it when the number of active pipes changes.
That doesn't necessarily mean anything for mbus joining.
> Probably you mean the case when its called from intel_dbuf_pre_plane_update,
> because commit_modeset_enables hasn't been yet called?
Yes, the pipe may still be off.
> That would be the case of switching from multiple displays to single one,
> for non-modeset at least shoudln't be a problem, as I understand.
I don't know what the hardware does in this case. Better not
to ask for trouble IMO in case it turns out the hardware won't
like it.
>
> But where should this be called then from?
>
> We always called this function from intel_dbuf_pre_plane_update.
As mentioned later in my mail, I think we just want a pre/post
ddb callsites for this stuff. Though the credit stuff (should we
need to account for those changing) might complicate things further...
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes
2024-03-08 15:11 ` Ville Syrjälä
@ 2024-03-11 9:41 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2024-03-11 9:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, jani.saarinen
On Fri, Mar 08, 2024 at 05:11:42PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 08, 2024 at 03:43:35PM +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Mar 08, 2024 at 12:07:19PM +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 28, 2024 at 10:02:13AM +0200, Stanislav Lisovskiy wrote:
> > > > Currently we can't change MBUS join status without doing a modeset,
> > > > because we are lacking mechanism to synchronize those with vblank.
> > > > However then this means that we can't do a fastset, if there is a need
> > > > to change MBUS join state. Fix that by implementing such change.
> > > > We already call correspondent check and update at pre_plane dbuf update,
> > > > so the only thing left is to have a non-modeset version of that.
> > > > If active pipes stay the same then fastset is possible and only MBUS
> > > > join state/ddb allocation updates would be committed.
> > > >
> > > > v2: Implement additional changes according to BSpec.
> > > > Vblank wait is needed after MBus/Dbuf programming in case if
> > > > no modeset is done and we are switching from single to multiple
> > > > displays, i.e mbus join state switches from "joined" to "non-joined"
> > > > state. Otherwise vblank wait is not needed according to spec.
> > > >
> > > > v3: Split mbus and dbox programming into to pre/post plane update parts,
> > > > how it should be done according to BSpec.
> > > >
> > > > v4: - Place "single display to multiple displays scenario" MBUS/DBOX programming
> > > > after DDB reallocation, but before crtc enabling(that is where is has
> > > > to be according to spec).
> > > > - Check if crtc is still active, not only the old state.
> > > > - Do a vblank wait if MBUX DBOX register was modified.
> > > > - And of course do vblank wait only if crtc was active.
> > > > - Do vblank wait only if we are not doing a modeset, if we are doing
> > > > something before *commit_modeset_enables, because all crtcs might be
> > > > disabled at this moment, so we will get WARN if try waiting for vblank
> > > > then.
> > > > - Still getting FIFO underrun so try waiting for vblank in pre_plane update
> > > > as well.
> > > > - Write also pipe that we need to sync with to MBUS_CTL register.
> > > >
> > > > v5: - Do vblank wait only for the first pipe, if mbus is joined
> > > > - Check also if new/old_dbuf_state is not NULL, before getting single pipe
> > > > and active pipes.
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 13 ++-
> > > > drivers/gpu/drm/i915/display/skl_watermark.c | 104 +++++++++++++++----
> > > > drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
> > > > 3 files changed, 96 insertions(+), 22 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 00ac65a140298..989818f5d342f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6906,6 +6906,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> > > > }
> > > > }
> > > >
> > > > + /*
> > > > + * Some MBUS/DBuf update scenarios(mbus join disable) require that
> > > > + * changes are done _after_ DDB reallocation, but _before_ crtc enabling.
> > > > + * Typically we are disabling resources in post_plane/crtc_enable hooks,
> > > > + * however in that case BSpec explicitly states that this should be done
> > > > + * before we enable additional displays.
> > > > + * FIXME: Should we still call this also there(post_plane hook)
> > > > + * for extra-safety? If so, how to make sure, we don't call it twice?
> > > > + */
> > > > + intel_dbuf_mbus_post_ddb_update(state);
> > > > +
> > > > update_pipes = modeset_pipes;
> > > >
> > > > /*
> > > > @@ -7148,9 +7159,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > > }
> > > >
> > > > intel_encoders_update_prepare(state);
> > > > -
> > > > intel_dbuf_pre_plane_update(state);
> > > > - intel_mbus_dbox_update(state);
> > > >
> > > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > > if (new_crtc_state->do_async_flip)
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > > index 606b7ba9db9ce..f0604ede399f7 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > > @@ -2628,13 +2628,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> > > > if (ret)
> > > > return ret;
> > > >
> > > > - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
> > > > - /* TODO: Implement vblank synchronized MBUS joining changes */
> > > > - ret = intel_modeset_all_pipes_late(state, "MBUS joining change");
> > > > - if (ret)
> > > > - return ret;
> > > > - }
> > > > -
> > > > drm_dbg_kms(&i915->drm,
> > > > "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
> > > > old_dbuf_state->enabled_slices,
> > > > @@ -3539,8 +3532,9 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state)
> > > > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > > u32 mbus_ctl, dbuf_min_tracker_val;
> > > > enum dbuf_slice slice;
> > > > - const struct intel_dbuf_state *dbuf_state =
> > > > + const struct intel_dbuf_state *new_dbuf_state =
> > > > intel_atomic_get_new_dbuf_state(state);
> > > > + enum pipe pipe = ffs(new_dbuf_state->active_pipes) - 1;
> > >
> > > That pipe might not even be enabled at this point.
> >
> > Which scenario do you mean?
> > intel_dbuf_mbus_update is called in two cases:
> >
> > 1) When switching from single display to multiple displays, according
> > to spec we should program it before enabling additional displays,
> > but after ddb allocation happens.
> >
> > 2) When switching from multiple displays to a single display,
> > we program it after disabling all displays except one, but
> > before ddb reallocation happens.
>
> You seem to call it when the number of active pipes changes.
> That doesn't necessarily mean anything for mbus joining.
From code here:
+ if (!new_dbuf_state ||
+ (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ return;
+
+ pipe = ffs(new_dbuf_state->active_pipes) - 1;
+ new_num_active_pipes = hweight8(new_dbuf_state->active_pipes);
+
+ if (old_dbuf_state)
+ old_num_active_pipes = hweight8(old_dbuf_state->active_pipes);
+
+ WARN_ON(!new_dbuf_state->base.changed);
+
+ /*
+ * Switching from single to multiple display scenario
+ */
+ if (new_num_active_pipes > old_num_active_pipes) {
We have a check above, so if we are at this point, means that either enabled_slices
had changed or joined_mbus state.
If for example new active pipe count is more than old active pipe count and
join_mbus state had changed, I think it for sure means single => multiple switch scenario,
since there are currently no other scenarios, when mbus_join changes and active pipe count
increases except that one.
For instance if old active pipe count was anything > 1 and it increases, there would have been
no mbus_join state change.
However enabled slice count may change, so I wonder if I need to may be add, some additional
check like if ((new_num_active_pipes > old_num_active_pipes) && old_num_active_pipes == 1) to be sure.
In fact I had it in one of previous revisions, but can't recall now, why I removed it.
>
> > Probably you mean the case when its called from intel_dbuf_pre_plane_update,
> > because commit_modeset_enables hasn't been yet called?
>
> Yes, the pipe may still be off.
>
> > That would be the case of switching from multiple displays to single one,
> > for non-modeset at least shoudln't be a problem, as I understand.
>
> I don't know what the hardware does in this case. Better not
> to ask for trouble IMO in case it turns out the hardware won't
> like it.
>
> >
> > But where should this be called then from?
> >
> > We always called this function from intel_dbuf_pre_plane_update.
>
> As mentioned later in my mail, I think we just want a pre/post
> ddb callsites for this stuff. Though the credit stuff (should we
> need to account for those changing) might complicate things further...
Okay, I already have post ddb call site, so means I need to do the same
for pre ddb callsite, the only thing I wonder if that change is going to
screw up something once again.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-03-11 9:42 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-28 8:02 [PATCH 0/2] Enable fastset for mbus_join state change Stanislav Lisovskiy
2024-02-28 8:02 ` [PATCH 1/2] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Stanislav Lisovskiy
2024-03-05 19:52 ` Paz Zcharya
2024-02-28 8:02 ` [PATCH 2/2] drm/i915: Implement vblank synchronized MBUS join changes Stanislav Lisovskiy
2024-03-05 19:54 ` Paz Zcharya
2024-03-08 10:07 ` Ville Syrjälä
2024-03-08 13:43 ` Lisovskiy, Stanislav
2024-03-08 15:11 ` Ville Syrjälä
2024-03-11 9:41 ` Lisovskiy, Stanislav
2024-02-28 8:45 ` ✗ Fi.CI.CHECKPATCH: warning for Enable fastset for mbus_join state change Patchwork
2024-02-28 8:56 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-28 23:21 ` ✓ Fi.CI.IGT: " Patchwork
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