[RFC 0/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[RFC 0/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[Hans de Goede]

Hi All,

Here is an alternative approach to fixing the p2sb_bar() caching
causing problems on an ASUS VivoBook D540NV-GQ065T.

This is untested, which is why this is marked as RFC. If this works
I believe that this is a better approach then the approach from:

"[PATCH v3] platform/x86: p2sb: Defer P2SB device scan when P2SB
device has func 0"

Regards,

Hans


Hans de Goede (1):
  platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

 drivers/platform/x86/p2sb.c | 23 ++++++++---------------
 1 file changed, 8 insertions(+), 15 deletions(-)

-- 
2.44.0

[RFC 1/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[Hans de Goede]

On Goldmont p2sb_bar() only ever gets called for 2 devices, the actual P2SB
devfn 13,0 and the SPI controller which is part of the P2SB, devfn 13,2.

But the current p2sb code tries to cache BAR0 info for all of
devfn 13,0 to 13,7 . This involves calling pci_scan_single_device()
for device 13 functions 0-7 and the hw does not seem to like
pci_scan_single_device() getting called for some of the other hidden
devices. E.g. on an ASUS VivoBook D540NV-GQ065T this leads to continuous
ACPI errors leading to high CPU usage.

Fix this by only caching BAR0 info and thus only calling
pci_scan_single_device() for the P2SB and the SPI controller.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=218531 [1]
Fixes: 5913320eb0b3 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/platform/x86/p2sb.c | 23 ++++++++---------------
 1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
index 6bd14d0132db..3d66e1d4eb1f 100644
--- a/drivers/platform/x86/p2sb.c
+++ b/drivers/platform/x86/p2sb.c
@@ -20,9 +20,11 @@
 #define P2SBC_HIDE		BIT(8)
 
 #define P2SB_DEVFN_DEFAULT	PCI_DEVFN(31, 1)
+#define P2SB_DEVFN_GOLDMONT	PCI_DEVFN(13, 0)
+#define SPI_DEVFN_GOLDMONT	PCI_DEVFN(13, 2)
 
 static const struct x86_cpu_id p2sb_cpu_ids[] = {
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	PCI_DEVFN(13, 0)),
+	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT),
 	{}
 };
 
@@ -98,21 +100,12 @@ static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn)
 
 static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
 {
-	unsigned int slot, fn;
+	/* Scan the P2SB device and cache its BAR0 */
+	p2sb_scan_and_cache_devfn(bus, devfn);
 
-	if (PCI_FUNC(devfn) == 0) {
-		/*
-		 * When function number of the P2SB device is zero, scan it and
-		 * other function numbers, and if devices are available, cache
-		 * their BAR0s.
-		 */
-		slot = PCI_SLOT(devfn);
-		for (fn = 0; fn < NR_P2SB_RES_CACHE; fn++)
-			p2sb_scan_and_cache_devfn(bus, PCI_DEVFN(slot, fn));
-	} else {
-		/* Scan the P2SB device and cache its BAR0 */
-		p2sb_scan_and_cache_devfn(bus, devfn);
-	}
+	/* On Goldmont p2sb_bar() also gets called for the SPI controller */
+	if (devfn == P2SB_DEVFN_GOLDMONT)
+		p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT);
 
 	if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res))
 		return -ENOENT;
-- 
2.44.0

Re: [RFC 1/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[Hans de Goede]

Hi All,

On 3/4/24 14:43, Hans de Goede wrote:
> On Goldmont p2sb_bar() only ever gets called for 2 devices, the actual P2SB
> devfn 13,0 and the SPI controller which is part of the P2SB, devfn 13,2.
> 
> But the current p2sb code tries to cache BAR0 info for all of
> devfn 13,0 to 13,7 . This involves calling pci_scan_single_device()
> for device 13 functions 0-7 and the hw does not seem to like
> pci_scan_single_device() getting called for some of the other hidden
> devices. E.g. on an ASUS VivoBook D540NV-GQ065T this leads to continuous
> ACPI errors leading to high CPU usage.
> 
> Fix this by only caching BAR0 info and thus only calling
> pci_scan_single_device() for the P2SB and the SPI controller.
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=218531 [1]
> Fixes: 5913320eb0b3 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe")
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Good news Danil Rybakov has just confirmed in bugzilla
that simple patch fixes things. So IMHO this is the way
to move forward to fix this.

Shin'ichiro, any objections from you against this fix ?

Danil, is it ok if I credit you for all your testing by adding:

Reported-by: Danil Rybakov <danilrybakov249@gmail.com>
Tested-by: Danil Rybakov <danilrybakov249@gmail.com>

to the commit message for the patch while merging it ?

Regards,

Hans






> ---
>  drivers/platform/x86/p2sb.c | 23 ++++++++---------------
>  1 file changed, 8 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/platform/x86/p2sb.c b/drivers/platform/x86/p2sb.c
> index 6bd14d0132db..3d66e1d4eb1f 100644
> --- a/drivers/platform/x86/p2sb.c
> +++ b/drivers/platform/x86/p2sb.c
> @@ -20,9 +20,11 @@
>  #define P2SBC_HIDE		BIT(8)
>  
>  #define P2SB_DEVFN_DEFAULT	PCI_DEVFN(31, 1)
> +#define P2SB_DEVFN_GOLDMONT	PCI_DEVFN(13, 0)
> +#define SPI_DEVFN_GOLDMONT	PCI_DEVFN(13, 2)
>  
>  static const struct x86_cpu_id p2sb_cpu_ids[] = {
> -	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	PCI_DEVFN(13, 0)),
> +	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT),
>  	{}
>  };
>  
> @@ -98,21 +100,12 @@ static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn)
>  
>  static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
>  {
> -	unsigned int slot, fn;
> +	/* Scan the P2SB device and cache its BAR0 */
> +	p2sb_scan_and_cache_devfn(bus, devfn);
>  
> -	if (PCI_FUNC(devfn) == 0) {
> -		/*
> -		 * When function number of the P2SB device is zero, scan it and
> -		 * other function numbers, and if devices are available, cache
> -		 * their BAR0s.
> -		 */
> -		slot = PCI_SLOT(devfn);
> -		for (fn = 0; fn < NR_P2SB_RES_CACHE; fn++)
> -			p2sb_scan_and_cache_devfn(bus, PCI_DEVFN(slot, fn));
> -	} else {
> -		/* Scan the P2SB device and cache its BAR0 */
> -		p2sb_scan_and_cache_devfn(bus, devfn);
> -	}
> +	/* On Goldmont p2sb_bar() also gets called for the SPI controller */
> +	if (devfn == P2SB_DEVFN_GOLDMONT)
> +		p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT);
>  
>  	if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res))
>  		return -ENOENT;

Re: [RFC 1/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[Shinichiro Kawasaki]

On Mar 04, 2024 / 17:47, Hans de Goede wrote:
> Hi All,
> 
> On 3/4/24 14:43, Hans de Goede wrote:
> > On Goldmont p2sb_bar() only ever gets called for 2 devices, the actual P2SB
> > devfn 13,0 and the SPI controller which is part of the P2SB, devfn 13,2.
> > 
> > But the current p2sb code tries to cache BAR0 info for all of
> > devfn 13,0 to 13,7 . This involves calling pci_scan_single_device()
> > for device 13 functions 0-7 and the hw does not seem to like
> > pci_scan_single_device() getting called for some of the other hidden
> > devices. E.g. on an ASUS VivoBook D540NV-GQ065T this leads to continuous
> > ACPI errors leading to high CPU usage.
> > 
> > Fix this by only caching BAR0 info and thus only calling
> > pci_scan_single_device() for the P2SB and the SPI controller.
> > 
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=218531 [1]
> > Fixes: 5913320eb0b3 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe")
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> 
> Good news Danil Rybakov has just confirmed in bugzilla
> that simple patch fixes things. So IMHO this is the way
> to move forward to fix this.

Agreed. This simpler fix is the better.

The functions other than 0 and 2 were totally in my blind spot.
Thank you very much for finding out the good solution.

> 
> Shin'ichiro, any objections from you against this fix ?

No objection!

> 
> Danil, is it ok if I credit you for all your testing by adding:
> 
> Reported-by: Danil Rybakov <danilrybakov249@gmail.com>
> Tested-by: Danil Rybakov <danilrybakov249@gmail.com>
> 
> to the commit message for the patch while merging it ?
> 
> Regards,
> 
> Hans

Re: [RFC 1/1] platform/x86: p2sb: On Goldmont only cache P2SB and SPI devfn BAR

[Hans de Goede]

Hi,

On 3/5/24 01:54, Shinichiro Kawasaki wrote:
> On Mar 04, 2024 / 17:47, Hans de Goede wrote:
>> Hi All,
>>
>> On 3/4/24 14:43, Hans de Goede wrote:
>>> On Goldmont p2sb_bar() only ever gets called for 2 devices, the actual P2SB
>>> devfn 13,0 and the SPI controller which is part of the P2SB, devfn 13,2.
>>>
>>> But the current p2sb code tries to cache BAR0 info for all of
>>> devfn 13,0 to 13,7 . This involves calling pci_scan_single_device()
>>> for device 13 functions 0-7 and the hw does not seem to like
>>> pci_scan_single_device() getting called for some of the other hidden
>>> devices. E.g. on an ASUS VivoBook D540NV-GQ065T this leads to continuous
>>> ACPI errors leading to high CPU usage.
>>>
>>> Fix this by only caching BAR0 info and thus only calling
>>> pci_scan_single_device() for the P2SB and the SPI controller.
>>>
>>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=218531 [1]
>>> Fixes: 5913320eb0b3 ("platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe")
>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>
>> Good news Danil Rybakov has just confirmed in bugzilla
>> that simple patch fixes things. So IMHO this is the way
>> to move forward to fix this.
> 
> Agreed. This simpler fix is the better.
> 
> The functions other than 0 and 2 were totally in my blind spot.
> Thank you very much for finding out the good solution.
> 
>>
>> Shin'ichiro, any objections from you against this fix ?
> 
> No objection!

Great I have merged this now and send a pull-request to Linus
with this fix:

https://lore.kernel.org/platform-driver-x86/cfc29d60-e11c-4d7f-9d9d-637ebde8f5fd@redhat.com/

Regards,

Hans