[arm-perf:for-next/perf 34/37] drivers/perf/starfive_starlink_pmu.c:169:17: error: implicit declaration of function 'writeq'; did you mean 'writel'?

* [arm-perf:for-next/perf 34/37] drivers/perf/starfive_starlink_pmu.c:169:17: error: implicit declaration of function 'writeq'; did you mean 'writel'?
@ 2024-03-05  5:30 kernel test robot
  2024-03-05  9:38 ` Will Deacon
  0 siblings, 1 reply; 3+ messages in thread
From: kernel test robot @ 2024-03-05  5:30 UTC (permalink / raw)
  To: Ji Sheng Teoh; +Cc: oe-kbuild-all, Will Deacon

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git for-next/perf
head:   b9f71ab2152e5b344c02eb3ff43637162aaf29e6
commit: c2b24812f7bc5fbd6f2f92af070856fbe4c37b40 [34/37] perf: starfive: Add StarLink PMU support
config: parisc-allmodconfig (https://download.01.org/0day-ci/archive/20240305/202403051305.36cANAVm-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240305/202403051305.36cANAVm-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403051305.36cANAVm-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/perf/starfive_starlink_pmu.c: In function 'starlink_pmu_set_event_period':
>> drivers/perf/starfive_starlink_pmu.c:169:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
     169 |                 writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CYCLE_COUNTER);
         |                 ^~~~~~
         |                 writel
   drivers/perf/starfive_starlink_pmu.c: In function 'starlink_pmu_counter_start':
>> drivers/perf/starfive_starlink_pmu.c:191:15: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
     191 |         val = readq(starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE);
         |               ^~~~~
         |               readl
   cc1: some warnings being treated as errors

vim +169 drivers/perf/starfive_starlink_pmu.c

   154	
   155	static void starlink_pmu_set_event_period(struct perf_event *event)
   156	{
   157		struct starlink_pmu *starlink_pmu = to_starlink_pmu(event->pmu);
   158		struct hw_perf_event *hwc = &event->hw;
   159		int idx = event->hw.idx;
   160	
   161		/*
   162		 * Program counter to half of it's max count to handle
   163		 * cases of extreme interrupt latency.
   164		 */
   165		u64 val = STARLINK_PMU_COUNTER_MASK >> 1;
   166	
   167		local64_set(&hwc->prev_count, val);
   168		if (hwc->config == STARLINK_CYCLES)
 > 169			writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_CYCLE_COUNTER);
   170		else
   171			writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_EVENT_COUNTER +
   172			       idx * sizeof(u64));
   173	}
   174	
   175	static void starlink_pmu_counter_start(struct perf_event *event,
   176					       struct starlink_pmu *starlink_pmu)
   177	{
   178		struct hw_perf_event *hwc = &event->hw;
   179		int idx = event->hw.idx;
   180		u64 val;
   181	
   182		/*
   183		 * Enable counter overflow interrupt[63:0],
   184		 * which is mapped as follow:
   185		 *
   186		 * event counter 0	- Bit [0]
   187		 * event counter 1	- Bit [1]
   188		 * ...
   189		 * cycle counter	- Bit [63]
   190		 */
 > 191		val = readq(starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE);
   192	
   193		if (hwc->config == STARLINK_CYCLES) {
   194			/*
   195			 * Cycle count has its dedicated register, and it starts
   196			 * counting as soon as STARLINK_PMU_GLOBAL_ENABLE is set.
   197			 */
   198			val |= STARLINK_PMU_CYCLE_OVERFLOW_MASK;
   199		} else {
   200			writeq(event->hw.config, starlink_pmu->pmu_base +
   201			       STARLINK_PMU_EVENT_SELECT + idx * sizeof(u64));
   202	
   203			val |= BIT_ULL(idx);
   204		}
   205	
   206		writeq(val, starlink_pmu->pmu_base + STARLINK_PMU_INTERRUPT_ENABLE);
   207	
   208		writeq(STARLINK_PMU_GLOBAL_ENABLE, starlink_pmu->pmu_base +
   209		       STARLINK_PMU_CONTROL);
   210	}
   211	

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