* [PULL 00/38] ppc-for-9.0-2 queue
@ 2024-03-12 16:58 Nicholas Piggin
2024-03-12 16:58 ` [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing Nicholas Piggin
` (39 more replies)
0 siblings, 40 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
The following changes since commit 35ac6831d98e18e2c78c85c93e3a6ca1f1ae3e58:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-03-12 13:42:57 +0000)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-2-20240313
for you to fetch changes up to e1617b845104032f0aaad9b91dcda56c7c437998:
spapr: nested: Introduce cap-nested-papr for Nested PAPR API (2024-03-13 02:47:04 +1000)
----------------------------------------------------------------
* PAPR nested hypervisor host implementation for spapr TCG
* excp_helper.c code cleanups and improvements
* Move more ops to decodetree
* Deprecate pseries-2.12 machines and P9 and P10 DD1.0 CPUs
* Document running Linux on AmigaNG
* Update dt feature advertising POWER CPUs.
* Add P10 PMU SPRs
* Improve pnv topology calculation for SMT8 CPUs.
* Various bug fixes.
----------------------------------------------------------------
BALATON Zoltan (8):
docs/system/ppc: Document running Linux on AmigaNG machines
target/ppc: Use env_cpu for cpu_abort in excp_helper
target/ppc: Readability improvements in exception handlers
target/ppc: Add gen_exception_err_nip() function
target/ppc: Clean up ifdefs in excp_helper.c, part 1
target/ppc: Clean up ifdefs in excp_helper.c, part 2
target/ppc: Clean up ifdefs in excp_helper.c, part 3
target/ppc: Remove interrupt handler wrapper functions
Benjamin Gray (1):
ppc/spapr: Add pa-features for POWER10 machines
Caleb Schlossin (1):
ppc/pnv: Improve pervasive topology calculation for big-core
Chinmay Rath (1):
target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree
Cédric Le Goater (1):
MAINTAINERS: Remove myself as reviewer from PPC
Harsh Prateek Bora (14):
spapr: nested: register nested-hv api hcalls only for cap-nested-hv
spapr: nested: move nested part of spapr_get_pate into spapr_nested.c
spapr: nested: Introduce SpaprMachineStateNested to store related info.
spapr: nested: keep nested-hv related code restricted to its API.
spapr: nested: Document Nested PAPR API
spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls.
spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls.
spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall.
spapr: nested: Extend nested_ppc_state for nested PAPR API
spapr: nested: Initialize the GSB elements lookup table.
spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
spapr: nested: Use correct source for parttbl info for nested PAPR API.
spapr: nested: Introduce H_GUEST_RUN_VCPU hcall.
spapr: nested: Introduce cap-nested-papr for Nested PAPR API
Madhavan Srinivasan (1):
target/ppc: Add power10 pmu SPRs
Nicholas Piggin (10):
target/ppc: Fix GDB SPR regnum indexing
target/ppc: Prevent supervisor from modifying MSR[ME]
spapr: set MSR[ME] and MSR[FP] on client entry
ppc: Drop support for POWER9 and POWER10 DD1 chips
target/ppc: POWER10 does not have transactional memory
ppc/spapr|pnv: Remove SAO from pa-features
ppc/spapr: Remove copy-paste from pa-features
ppc/spapr: Adjust ibm,pa-features for POWER9
ppc/pnv: Permit ibm,pa-features set per machine variant
ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits
Philippe Mathieu-Daudé (1):
docs: Deprecate the pseries-2.12 machines
MAINTAINERS | 4 +-
docs/about/deprecated.rst | 6 +-
docs/devel/nested-papr.txt | 119 +++
docs/system/ppc/amigang.rst | 161 +++
docs/system/target-ppc.rst | 1 +
hw/ppc/pnv.c | 175 +++-
hw/ppc/pnv_core.c | 8 +-
hw/ppc/ppc.c | 10 +
hw/ppc/spapr.c | 98 +-
hw/ppc/spapr_caps.c | 54 +
hw/ppc/spapr_cpu_core.c | 8 +-
hw/ppc/spapr_hcall.c | 24 +-
hw/ppc/spapr_nested.c | 1556 +++++++++++++++++++++++++++-
include/hw/ppc/pnv_chip.h | 2 +-
include/hw/ppc/pnv_core.h | 1 +
include/hw/ppc/spapr.h | 27 +-
include/hw/ppc/spapr_nested.h | 427 +++++++-
target/ppc/cpu-models.c | 4 -
target/ppc/cpu.h | 11 +
target/ppc/cpu_init.c | 46 +-
target/ppc/excp_helper.c | 418 +++-----
target/ppc/gdbstub.c | 7 +-
target/ppc/helper_regs.c | 5 +
target/ppc/insn32.decode | 26 +
target/ppc/kvm.c | 11 -
target/ppc/misc_helper.c | 3 -
target/ppc/translate.c | 164 +--
target/ppc/translate/fixedpoint-impl.c.inc | 70 ++
28 files changed, 2883 insertions(+), 563 deletions(-)
create mode 100644 docs/devel/nested-papr.txt
create mode 100644 docs/system/ppc/amigang.rst
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
` (38 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Akihiko Odaki
Fix an off by one bug.
Fixes: 1b53948ff8f70 ("target/ppc: Use GDBFeature for dynamic XML")
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/gdbstub.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 122ea9d0c0..80a2e7990b 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -324,6 +324,9 @@ static void gdb_gen_spr_feature(CPUState *cs)
continue;
}
+ gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
+ TARGET_LONG_BITS, num_regs,
+ "int", "spr");
/*
* GDB identifies registers based on the order they are
* presented in the XML. These ids will not match QEMU's
@@ -334,10 +337,6 @@ static void gdb_gen_spr_feature(CPUState *cs)
*/
spr->gdb_id = num_regs;
num_regs++;
-
- gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
- TARGET_LONG_BITS, num_regs,
- "int", "spr");
}
gdb_feature_builder_end(&builder);
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME]
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
2024-03-12 16:58 ` [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
` (37 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSR[ME] in privileged but non-hypervisor state
is ignored (i.e., the bit is not changed).
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/helper_regs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 410b39c231..25258986e3 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -264,6 +264,11 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
+ /* Attempt to modify MSR[ME] in guest state is ignored */
+ if (is_book3s_arch2x(env) && !(env->msr & MSR_HVB)) {
+ value &= ~(1 << MSR_ME);
+ value |= env->msr & (1 << MSR_ME);
+ }
if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
cpu_interrupt_exittb(cs);
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
2024-03-12 16:58 ` [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing Nicholas Piggin
2024-03-12 16:58 ` [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
` (36 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
The initial MSR state for the OpenFirmware binding specifies
MSR[ME] and MSR[FP] are set.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_cpu_core.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 40b7c52f7f..58cb992609 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -39,9 +39,13 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
/*
* "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
- * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
+ * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial
+ * Register Values". This can also be found in "LoPAPR 1.1" "C.9.2.1
+ * Initial Register Values".
*/
env->msr &= ~(1ULL << MSR_SF);
+ env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
+
env->spr[SPR_HIOR] = 0;
lpcr = env->spr[SPR_LPCR];
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (2 preceding siblings ...)
2024-03-12 16:58 ` [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 05/38] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
` (35 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4 ----
target/ppc/cpu_init.c | 7 ++-----
target/ppc/kvm.c | 11 -----------
4 files changed, 2 insertions(+), 22 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 58cb992609..e7c9edd033 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -398,10 +398,8 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
- DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 36e465b390..f2301b43f7 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -728,14 +728,10 @@
"POWER8 v2.0")
POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10, POWER8,
"POWER8NVL v1.0")
- POWERPC_DEF("power9_v1.0", CPU_POWERPC_POWER9_DD1, POWER9,
- "POWER9 v1.0")
POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
"POWER9 v2.0")
POWERPC_DEF("power9_v2.2", CPU_POWERPC_POWER9_DD22, POWER9,
"POWER9 v2.2")
- POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10,
- "POWER10 v1.0")
POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
"POWER10 v2.0")
#endif /* defined (TARGET_PPC64) */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1d3d1db7c3..572cbdf25f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6350,10 +6350,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
return false;
}
- if ((pvr & 0x0f00) == 0x100) {
- /* DD1.x always matches power9_v1.0 */
- return true;
- } else if ((pvr & 0x0f00) == 0x200) {
+ if ((pvr & 0x0f00) == 0x200) {
if ((pvr & 0xf) < 2) {
/* DD2.0, DD2.1 match power9_v2.0 */
if ((pcc->pvr & 0xf) == 0) {
@@ -6536,7 +6533,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
}
if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
- /* Major DD version matches to power10_v1.0 and power10_v2.0 */
+ /* Major DD version matches power10_v2.0 */
return true;
}
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index bcf30a5400..525fbe3892 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2369,17 +2369,6 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
#if defined(TARGET_PPC64)
pcc->radix_page_info = kvmppc_get_radix_page_info();
-
- if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
- /*
- * POWER9 DD1 has some bugs which make it not really ISA 3.00
- * compliant. More importantly, advertising ISA 3.00
- * architected mode may prevent guests from activating
- * necessary DD1 workarounds.
- */
- pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
- | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
- }
#endif /* defined(TARGET_PPC64) */
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 05/38] target/ppc: POWER10 does not have transactional memory
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (3 preceding siblings ...)
2024-03-12 16:58 ` [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
` (34 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu_init.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 572cbdf25f..b160926a93 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6573,11 +6573,10 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
+ PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
- (1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
(1ull << MSR_EE) |
@@ -6617,7 +6616,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
+ POWERPC_FLAG_VSX | POWERPC_FLAG_SCV;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (4 preceding siblings ...)
2024-03-12 16:58 ` [PULL 05/38] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 07/38] ppc/spapr: Remove copy-paste " Nicholas Piggin
` (33 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. This is an obscure feature that has been removed from
POWER10 ISA v3.1, there isn't much concern with removing it.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 14 ++++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b47b92baa..aa9786e970 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -150,7 +150,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 55263f0815..3108d7c532 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -233,17 +233,23 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
PowerPCCPU *cpu,
void *fdt, int offset)
{
+ /*
+ * SSO (SAO) ordering is supported on KVM and thread=single hosts,
+ * but not MTTCG, so disable it. To advertise it, a cap would have
+ * to be added, or support implemented for MTTCG.
+ */
+
uint8_t pa_features_206[] = { 6, 0,
- 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
+ 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
uint8_t pa_features_300[] = { 66, 0,
/* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
- /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
- 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
/* 6: DS207 */
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
/* 16: Vector */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 07/38] ppc/spapr: Remove copy-paste from pa-features
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (5 preceding siblings ...)
2024-03-12 16:58 ` [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
` (32 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3108d7c532..4192cd8d6c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -237,6 +237,10 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
* SSO (SAO) ordering is supported on KVM and thread=single hosts,
* but not MTTCG, so disable it. To advertise it, a cap would have
* to be added, or support implemented for MTTCG.
+ *
+ * Copy/paste is not supported by TCG, so it is not advertised. KVM
+ * can execute them but it has no accelerator drivers which are usable,
+ * so there isn't much need for it anyway.
*/
uint8_t pa_features_206[] = { 6, 0,
@@ -260,8 +264,8 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
/* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
- /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 36: SPR SO, 40: Radix MMU */
+ 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
/* 42: PM, 44: PC RA, 46: SC vec'd */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
/* 48: SIMD, 50: QP BFP, 52: String */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (6 preceding siblings ...)
2024-03-12 16:58 ` [PULL 07/38] ppc/spapr: Remove copy-paste " Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
` (31 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4192cd8d6c..5bbd0d7a04 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -258,14 +258,14 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
/* 16: Vector */
0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
- /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
/* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
- /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
- 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
- /* 36: SPR SO, 40: Radix MMU */
- 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
/* 42: PM, 44: PC RA, 46: SC vec'd */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
/* 48: SIMD, 50: QP BFP, 52: String */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (7 preceding siblings ...)
2024-03-12 16:58 ` [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant Nicholas Piggin
` (30 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Benjamin Gray
From: Benjamin Gray <bgray@linux.ibm.com>
Add POWER10 pa-features entry.
Notably DEXCR and [P]HASHST/[P]HASHCHK instruction support is
advertised. Each DEXCR aspect is allocated a bit in the device tree,
using the 68--71 byte range (inclusive). The functionality of the
[P]HASHST/[P]HASHCHK instructions is separately declared in byte 72,
bit 0 (BE).
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 5bbd0d7a04..a684e0d9dc 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -275,6 +275,36 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
/* 60: NM atomic, 62: RNG */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
};
+ /* 3.1 removes SAO, HTM support */
+ uint8_t pa_features_31[] = { 74, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+ /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+ 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+ /* 72: [P]HASHST/[P]HASHCHK */
+ 0x80, 0x00, /* 72 - 73 */
+ };
uint8_t *pa_features = NULL;
size_t pa_size;
@@ -290,6 +320,10 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
pa_features = pa_features_300;
pa_size = sizeof(pa_features_300);
}
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, cpu->compat_pvr)) {
+ pa_features = pa_features_31;
+ pa_size = sizeof(pa_features_31);
+ }
if (!pa_features) {
return;
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (8 preceding siblings ...)
2024-03-12 16:58 ` [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
` (29 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
This allows different pa-features for powernv8/9/10.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aa9786e970..52d964f77a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -133,7 +133,7 @@ static int get_cpus_node(void *fdt)
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
-static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
+static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
PowerPCCPU *cpu = pc->threads[0];
CPUState *cs = CPU(cpu);
@@ -149,11 +149,6 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
uint32_t cpufreq = 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
int offset;
char *nodename;
int cpus_offset = get_cpus_node(fdt);
@@ -236,15 +231,14 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
page_sizes_prop, page_sizes_prop_size)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features, sizeof(pa_features))));
-
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
servers_prop[i] = cpu_to_be32(pc->pir + i);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
+
+ return offset;
}
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
@@ -299,6 +293,17 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
return chip;
}
+/*
+ * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
+ * HTM is always enabled because TCG does implement HTM, it's just a
+ * degenerate implementation.
+ */
+static const uint8_t pa_features_207[] = { 24, 0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
+
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
@@ -311,8 +316,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
/* Interrupt Control Presenters (ICP). One per core. */
pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
@@ -335,8 +344,12 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
@@ -358,8 +371,12 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (9 preceding siblings ...)
2024-03-12 16:58 ` [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC Nicholas Piggin
` (28 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
hw/ppc/spapr.c | 1 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 52d964f77a..8a502dea90 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
}
}
+/*
+ * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
+ */
+static const uint8_t pa_features_300[] = { 66, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+};
+
static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
@@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
offset = pnv_dt_core(chip, pnv_core, fdt);
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features_207, sizeof(pa_features_207))));
+ pa_features_300, sizeof(pa_features_300))));
}
if (chip->ram_size) {
@@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
}
+/*
+ * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
+ * always disables copy/paste.
+ */
+static const uint8_t pa_features_31[] = { 74, 0,
+ /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+ /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+ /* 6: DS207 */
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+ /* 16: Vector */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+ /* 18: Vec. Scalar, 20: Vec. XOR */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+ /* 32: LE atomic, 34: EBB + ext EBB */
+ 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+ /* 40: Radix MMU */
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+ /* 42: PM, 44: PC RA, 46: SC vec'd */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+ /* 48: SIMD, 50: QP BFP, 52: String */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+ /* 54: DecFP, 56: DecI, 58: SHA */
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+ /* 60: NM atomic, 62: RNG */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+ /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+ 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+ /* 72: [P]HASHST/[P]HASHCHK */
+ 0x80, 0x00, /* 72 - 73 */
+};
+
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
@@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
offset = pnv_dt_core(chip, pnv_core, fdt);
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features_207, sizeof(pa_features_207))));
+ pa_features_31, sizeof(pa_features_31))));
}
if (chip->ram_size) {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a684e0d9dc..abd484023a 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -243,6 +243,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
* so there isn't much need for it anyway.
*/
+ /* These should be kept in sync with pnv */
uint8_t pa_features_206[] = { 6, 0,
0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (10 preceding siblings ...)
2024-03-12 16:58 ` [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 13/38] docs: Deprecate the pseries-2.12 machines Nicholas Piggin
` (27 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Cédric Le Goater
From: Cédric Le Goater <clg@kaod.org>
PPC maintainership has been a side activity for the last 2 years and
it is time to let go some of it now that Nick has taken over.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
MAINTAINERS | 3 ---
1 file changed, 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0087e4f1c7..fe8a7454ba 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -316,7 +316,6 @@ F: tests/tcg/openrisc/
PowerPC TCG CPUs
M: Nicholas Piggin <npiggin@gmail.com>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: target/ppc/
@@ -468,7 +467,6 @@ F: target/mips/sysemu/
PPC KVM CPUs
M: Nicholas Piggin <npiggin@gmail.com>
R: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
S: Odd Fixes
F: target/ppc/kvm.c
@@ -1508,7 +1506,6 @@ F: tests/avocado/ppc_prep_40p.py
sPAPR (pseries)
M: Nicholas Piggin <npiggin@gmail.com>
R: Daniel Henrique Barboza <danielhb413@gmail.com>
-R: Cédric Le Goater <clg@kaod.org>
R: David Gibson <david@gibson.dropbear.id.au>
R: Harsh Prateek Bora <harshpb@linux.ibm.com>
L: qemu-ppc@nongnu.org
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 13/38] docs: Deprecate the pseries-2.12 machines
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (11 preceding siblings ...)
2024-03-12 16:58 ` [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines Nicholas Piggin
` (26 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@linaro.org>
pSeries machines before 3.0 have complex migration back
compatibility code we'd like to get ride of. The last
one is 2.12, which is 6 years old. We just deprecated up
to the 2.11 machine in commit 1392617d35 ("spapr: Tag
pseries-2.1 - 2.11 machines as deprecated").
Take to opportunity to also deprecate the 2.12 machines.
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
docs/about/deprecated.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 4fb86608e4..7b548519b5 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -237,13 +237,13 @@ The Nios II architecture is orphan.
The machine is no longer in existence and has been long unmaintained
in QEMU. This also holds for the TC51828 16MiB flash that it uses.
-``pseries-2.1`` up to ``pseries-2.11`` (since 9.0)
+``pseries-2.1`` up to ``pseries-2.12`` (since 9.0)
''''''''''''''''''''''''''''''''''''''''''''''''''
-Older pseries machines before version 2.12 have undergone many changes
+Older pseries machines before version 3.0 have undergone many changes
to correct issues, mostly regarding migration compatibility. These are
no longer maintained and removing them will make the code easier to
-read and maintain. Use versions 2.12 and above as a replacement.
+read and maintain. Use versions 3.0 and above as a replacement.
Arm machines ``akita``, ``borzoi``, ``cheetah``, ``connex``, ``mainstone``, ``n800``, ``n810``, ``spitz``, ``terrier``, ``tosa``, ``verdex``, ``z2`` (since 9.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (12 preceding siblings ...)
2024-03-12 16:58 ` [PULL 13/38] docs: Deprecate the pseries-2.12 machines Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree Nicholas Piggin
` (25 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan, Bernhard Beschow
From: BALATON Zoltan <balaton@eik.bme.hu>
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently buried in the depths of the qemu-devel
mailing list and in the source code. Let's collect the information in
the QEMU handbook for a one stop solution.
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
MAINTAINERS | 1 +
docs/system/ppc/amigang.rst | 161 ++++++++++++++++++++++++++++++++++++
docs/system/target-ppc.rst | 1 +
3 files changed, 163 insertions(+)
create mode 100644 docs/system/ppc/amigang.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index fe8a7454ba..1f89e274d3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1572,6 +1572,7 @@ F: hw/rtc/m41t80.c
F: pc-bios/canyonlands.dt[sb]
F: pc-bios/u-boot-sam460ex-20100605.bin
F: roms/u-boot-sam460ex
+F: docs/system/ppc/amigang.rst
pegasos2
M: BALATON Zoltan <balaton@eik.bme.hu>
diff --git a/docs/system/ppc/amigang.rst b/docs/system/ppc/amigang.rst
new file mode 100644
index 0000000000..ba1a3d80b9
--- /dev/null
+++ b/docs/system/ppc/amigang.rst
@@ -0,0 +1,161 @@
+=========================================================
+AmigaNG boards (``amigaone``, ``pegasos2``, ``sam460ex``)
+=========================================================
+
+These PowerPC machines emulate boards that are primarily used for
+running Amiga like OSes (AmigaOS 4, MorphOS and AROS) but these can
+also run Linux which is what this section documents.
+
+Eyetech AmigaOne/Mai Logic Teron (``amigaone``)
+===============================================
+
+The ``amigaone`` machine emulates an AmigaOne XE mainboard by Eyetech
+which is a rebranded Mai Logic Teron board with modified U-Boot
+firmware to support AmigaOS 4.
+
+Emulated devices
+----------------
+
+ * PowerPC 7457 CPU (can also use``-cpu g3, 750cxe, 750fx`` or ``750gx``)
+ * Articia S north bridge
+ * VIA VT82C686B south bridge
+ * PCI VGA compatible card (guests may need other card instead)
+ * PS/2 keyboard and mouse
+
+Firmware
+--------
+
+A firmware binary is necessary for the boot process. It is a modified
+U-Boot under GPL but its source is lost so it cannot be included in
+QEMU. A binary is available at
+https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28.
+The ROM image is in the last 512kB which can be extracted with the
+following command:
+
+.. code-block:: bash
+
+ $ tail -c 524288 updater.image > u-boot-amigaone.bin
+
+The BIOS emulator in the firmware is unable to run QEMU‘s standard
+vgabios so ``VGABIOS-lgpl-latest.bin`` is needed instead which can be
+downloaded from http://www.nongnu.org/vgabios.
+
+Running Linux
+-------------
+
+There are some Linux images under the following link that work on the
+``amigaone`` machine:
+https://sourceforge.net/projects/amigaone-linux/files/debian-installer/.
+To boot the system run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine amigaone -bios u-boot-amigaone.bin \
+ -cdrom "A1 Linux Net Installer.iso" \
+ -device ati-vga,model=rv100,romfile=VGABIOS-lgpl-latest.bin
+
+From the firmware menu that appears select ``Boot sequence`` →
+``Amiga Multiboot Options`` and set ``Boot device 1`` to
+``Onboard VIA IDE CDROM``. Then hit escape until the main screen appears again,
+hit escape once more and from the exit menu that appears select either
+``Save settings and exit`` or ``Use settings for this session only``. It may
+take a long time loading the kernel into memory but eventually it boots and the
+installer becomes visible. The ``ati-vga`` RV100 emulation is not
+complete yet so only frame buffer works, DRM and 3D is not available.
+
+Genesi/bPlan Pegasos II (``pegasos2``)
+======================================
+
+The ``pegasos2`` machine emulates the Pegasos II sold by Genesi and
+designed by bPlan. Its schematics are available at
+https://www.powerdeveloper.org/platforms/pegasos/schematics.
+
+Emulated devices
+----------------
+
+ * PowerPC 7457 CPU (can also use``-cpu g3`` or ``750cxe``)
+ * Marvell MV64361 Discovery II north bridge
+ * VIA VT8231 south bridge
+ * PCI VGA compatible card (guests may need other card instead)
+ * PS/2 keyboard and mouse
+
+Firmware
+--------
+
+The Pegasos II board has an Open Firmware compliant ROM based on
+SmartFirmware with some changes that are not open-sourced therefore
+the ROM binary cannot be included in QEMU. An updater was available
+from bPlan, it can be found in the `Internet Archive
+<http://web.archive.org/web/20071021223056/http://www.bplan-gmbh.de/up050404/up050404>`_.
+The ROM image can be extracted from it with the following command:
+
+.. code-block:: bash
+
+ $ tail -c +85581 up050404 | head -c 524288 > pegasos2.rom
+
+Running Linux
+-------------
+
+The PowerPC version of Debian 8.11 supported Pegasos II. The BIOS
+emulator in the firmware binary is unable to run QEMU‘s standard
+vgabios so it needs to be disabled. To boot the system run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine pegasos2 -bios pegasos2.rom \
+ -cdrom debian-8.11.0-powerpc-netinst.iso \
+ -device VGA,romfile="" -serial stdio
+
+At the firmware ``ok`` prompt enter ``boot cd install/pegasos``.
+
+Alternatively, it is possible to boot the kernel directly without
+firmware ROM using the QEMU built-in minimal Virtual Open Firmware
+(VOF) emulation which is also supported on ``pegasos2``. For this,
+extract the kernel ``install/powerpc/vmlinuz-chrp.initrd`` from the CD
+image, then run:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine pegasos2 -serial stdio \
+ -kernel vmlinuz-chrp.initrd -append "---" \
+ -cdrom debian-8.11.0-powerpc-netinst.iso
+
+aCube Sam460ex (``sam460ex``)
+=============================
+
+The ``sam460ex`` machine emulates the Sam460ex board by aCube which is
+based on the AMCC PowerPC 460EX SoC (that despite its name has a
+PPC440 CPU core).
+
+Firmware
+--------
+
+The board has a firmware based on an older U-Boot version with
+modifications to support booting AmigaOS 4. The firmware ROM is
+included with QEMU.
+
+Emulated devices
+----------------
+
+ * PowerPC 460EX SoC
+ * M41T80 serial RTC chip
+ * Silicon Motion SM501 display parts (identical to SM502 on real board)
+ * Silicon Image SiI3112 2 port SATA controller
+ * USB keyboard and mouse
+
+Running Linux
+-------------
+
+The only Linux distro that supported Sam460ex out of box was CruxPPC
+2.x. It can be booted by running:
+
+.. code-block:: bash
+
+ $ qemu-system-ppc -machine sam460ex -serial stdio \
+ -drive if=none,id=cd,format=raw,file=crux-ppc-2.7a.iso \
+ -device ide-cd,drive=cd,bus=ide.1
+
+There are some other kernels and instructions for booting other
+distros on aCube's product page at
+https://www.acube-systems.biz/index.php?page=hardware&pid=5
+but those are untested.
diff --git a/docs/system/target-ppc.rst b/docs/system/target-ppc.rst
index 4f6eb93b17..87bf412ce5 100644
--- a/docs/system/target-ppc.rst
+++ b/docs/system/target-ppc.rst
@@ -17,6 +17,7 @@ help``.
.. toctree::
:maxdepth: 1
+ ppc/amigang
ppc/embedded
ppc/powermac
ppc/powernv
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (13 preceding siblings ...)
2024-03-12 16:58 ` [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 16/38] target/ppc: Add power10 pmu SPRs Nicholas Piggin
` (24 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Chinmay Rath, Richard Henderson
From: Chinmay Rath <rathc@linux.ibm.com>
This patch moves the below instructions to decodetree specification:
{add, subf}[c,e,me,ze][o][.] : XO-form
addic[.], subfic : D-form
addex : Z23-form
This patch introduces XO form instructions into decode tree
specification, for which all the four variations([o][.]) have been
handled with a single pattern. The changes were verified by validating
that the tcg ops generated by those instructions remain the same, which
were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/insn32.decode | 26 ++++
target/ppc/translate.c | 136 ---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 70 +++++++++++
3 files changed, 96 insertions(+), 136 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4fcf3af8d0..eada59f59f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -187,6 +187,12 @@
&X_a ra
@X_a ...... ra:3 .. ..... ..... .......... . &X_a
+&XO rt ra rb oe:bool rc:bool
+@XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
+
+&XO_ta rt ra oe:bool rc:bool
+@XO_ta ...... rt:5 ra:5 ..... oe:1 ......... rc:1 &XO_ta
+
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
@@ -322,10 +328,30 @@ CMPLI 001010 ... - . ..... ................ @D_bfu
### Fixed-Point Arithmetic Instructions
+ADD 011111 ..... ..... ..... . 100001010 . @XO
+ADDC 011111 ..... ..... ..... . 000001010 . @XO
+ADDE 011111 ..... ..... ..... . 010001010 . @XO
+
+# ADDEX is Z23-form, with CY=0; all other values for CY are reserved.
+# This works out the same as X-form.
+ADDEX 011111 ..... ..... ..... 00 10101010 - @X
+
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDIC 001100 ..... ..... ................ @D
+ADDIC_ 001101 ..... ..... ................ @D
ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+ADDME 011111 ..... ..... ----- . 011101010 . @XO_ta
+ADDZE 011111 ..... ..... ----- . 011001010 . @XO_ta
+
+SUBF 011111 ..... ..... ..... . 000101000 . @XO
+SUBFIC 001000 ..... ..... ................ @D
+SUBFC 011111 ..... ..... ..... . 000001000 . @XO
+SUBFE 011111 ..... ..... ..... . 010001000 . @XO
+
+SUBFME 011111 ..... ..... ----- . 011101000 . @XO_ta
+SUBFZE 011111 ..... ..... ----- . 011001000 . @XO_ta
## Fixed-Point Logical Instructions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 28fc7791af..4f6f7dcd89 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1735,61 +1735,6 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ret, t0);
}
}
-/* Add functions with two operands */
-#define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Add functions with one operand and one immediate */
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- ca, glue(ca, 32), \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-
-/* add add. addo addo. */
-GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
-/* addc addc. addco addco. */
-GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
-/* adde adde. addeo addeo. */
-GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
-/* addme addme. addmeo addmeo. */
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
-/* addex */
-GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
-/* addze addze. addzeo addzeo.*/
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addic addic.*/
-static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
-}
-
-static void gen_addic(DisasContext *ctx)
-{
- gen_op_addic(ctx, 0);
-}
-
-static void gen_addic_(DisasContext *ctx)
-{
- gen_op_addic(ctx, 1);
-}
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -2210,47 +2155,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ret, t0);
}
}
-/* Sub functions with Two operands functions */
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* Sub functions with one operand and one immediate */
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv t0 = tcg_constant_tl(const_val); \
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
- cpu_gpr[rA(ctx->opcode)], t0, \
- add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
-}
-/* subf subf. subfo subfo. */
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-/* subfc subfc. subfco subfco. */
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-/* subfe subfe. subfeo subfo. */
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-/* subfme subfme. subfmeo subfmeo. */
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-/* subfze subfze. subfzeo subfzeo.*/
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
-/* subfic */
-static void gen_subfic(DisasContext *ctx)
-{
- TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- c, 0, 1, 0, 0);
-}
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
@@ -6524,8 +6428,6 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
@@ -6536,7 +6438,6 @@ GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
#endif
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
-GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
@@ -6747,25 +6648,6 @@ GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
-#undef GEN_INT_ARITH_ADD
-#undef GEN_INT_ARITH_ADD_CONST
-#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
-GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
-GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
-GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
-GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
-GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_INT_ARITH_DIVW
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
@@ -6804,24 +6686,6 @@ GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
#endif
-#undef GEN_INT_ARITH_SUBF
-#undef GEN_INT_ARITH_SUBF_CONST
-#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
-#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
- add_ca, compute_ca, compute_ov) \
-GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
-GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
-GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
-GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
-GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
-GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
-GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
-GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
-GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
-
#undef GEN_LOGICAL1
#undef GEN_LOGICAL2
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 51c6fa7330..0c66465d96 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -325,6 +325,76 @@ static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
return true;
}
+static bool trans_ADDEX(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ov, cpu_ov32, true, true, false, false);
+ return true;
+}
+
+static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca,
+ bool compute_ov, bool compute_rc0)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), cpu_ca, cpu_ca32,
+ add_ca, compute_ca, compute_ov, compute_rc0);
+ return true;
+}
+
+static bool do_add_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_add_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_add(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ cpu_ca, cpu_ca32, add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(ADD, do_add_XO, false, false);
+TRANS(ADDC, do_add_XO, false, true);
+TRANS(ADDE, do_add_XO, true, true);
+TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), true, true);
+TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true);
+TRANS(ADDIC, do_add_D, false, true, false, false);
+TRANS(ADDIC_, do_add_D, false, true, false, true);
+
+static bool trans_SUBFIC(DisasContext *ctx, arg_D *a)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra],
+ tcg_constant_tl(a->si), false, true, false, false);
+ return true;
+}
+
+static bool do_subf_XO(DisasContext *ctx, arg_XO *a, bool add_ca,
+ bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+static bool do_subf_const_XO(DisasContext *ctx, arg_XO_ta *a, TCGv const_val,
+ bool add_ca, bool compute_ca)
+{
+ gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], const_val,
+ add_ca, compute_ca, a->oe, a->rc);
+ return true;
+}
+
+TRANS(SUBF, do_subf_XO, false, false)
+TRANS(SUBFC, do_subf_XO, false, true)
+TRANS(SUBFE, do_subf_XO, true, true)
+TRANS(SUBFME, do_subf_const_XO, tcg_constant_tl(-1LL), true, true)
+TRANS(SUBFZE, do_subf_const_XO, tcg_constant_tl(0), true, true)
+
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 16/38] target/ppc: Add power10 pmu SPRs
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (14 preceding siblings ...)
2024-03-12 16:58 ` [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core Nicholas Piggin
` (23 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Madhavan Srinivasan
From: Madhavan Srinivasan <maddy@linux.ibm.com>
Currently in tcg mode, when reading from power10 pmu spr like MMCR3,
qemu logs this message (when starting qemu with -d guest_errors)
Trying to read invalid spr 754 (0x2f2) at 0000000030056bb0
This is becuase, no read/write call-backs are registered for
these SPRs. Add support to register generic read/write
functions to these power10 pmu sprs to fix it.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 6 ++++++
target/ppc/cpu_init.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0133da4e07..ed04351f27 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1951,6 +1951,12 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_TLB2CFG (0x2B2)
#define SPR_BOOKE_TLB3CFG (0x2B3)
#define SPR_BOOKE_EPR (0x2BE)
+#define SPR_POWER_USIER2 (0x2E0)
+#define SPR_POWER_USIER3 (0x2E1)
+#define SPR_POWER_UMMCR3 (0x2E2)
+#define SPR_POWER_SIER2 (0x2F0)
+#define SPR_POWER_SIER3 (0x2F1)
+#define SPR_POWER_MMCR3 (0x2F2)
#define SPR_PERF0 (0x300)
#define SPR_RCPU_MI_RBA0 (0x300)
#define SPR_MPC_MI_CTR (0x300)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index b160926a93..df31490b07 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5308,6 +5308,38 @@ static void register_power8_pmu_user_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_power10_pmu_sup_sprs(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR3, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_SIER3, 0x00000000);
+}
+
+static void register_power10_pmu_user_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER2, "USIER2",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIER3, "USIER3",
+ &spr_read_generic, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void register_power5p_ear_sprs(CPUPPCState *env)
{
/* External access control */
@@ -6502,6 +6534,8 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
register_power10_dexcr_sprs(env);
+ register_power10_pmu_sup_sprs(env);
+ register_power10_pmu_user_sprs(env);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (15 preceding siblings ...)
2024-03-12 16:58 ` [PULL 16/38] target/ppc: Add power10 pmu SPRs Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 18/38] target/ppc: Use env_cpu for cpu_abort in excp_helper Nicholas Piggin
` (22 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Caleb Schlossin, Cédric Le Goater
From: Caleb Schlossin <calebs@linux.vnet.ibm.com>
Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 71 ++++++++++++++++++++++++++++-----------
hw/ppc/pnv_core.c | 8 ++---
include/hw/ppc/pnv_chip.h | 2 +-
include/hw/ppc/pnv_core.h | 1 +
target/ppc/misc_helper.c | 3 --
5 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8a502dea90..6fad628d9f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -141,8 +141,10 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
int smt_threads = CPU_CORE(pc)->nr_threads;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
+ PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip);
g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
int i;
+ uint32_t pir;
uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
0xffffffff, 0xffffffff};
uint32_t tbfreq = PNV_TIMEBASE_FREQ;
@@ -153,15 +155,17 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
char *nodename;
int cpus_offset = get_cpus_node(fdt);
- nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
+ pir = pnv_cc->chip_pir(chip, pc->hwid, 0);
+
+ nodename = g_strdup_printf("%s@%x", dc->fw_name, pir);
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
_FDT(offset);
g_free(nodename);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
- _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
- _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
+ _FDT((fdt_setprop_cell(fdt, offset, "reg", pir)));
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir)));
_FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
_FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
@@ -233,7 +237,7 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
- servers_prop[i] = cpu_to_be32(pc->pir + i);
+ servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i));
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
@@ -241,9 +245,11 @@ static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
return offset;
}
-static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
+static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid,
uint32_t nr_threads)
{
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ uint32_t pir = pcc->chip_pir(chip, hwid, 0);
uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
char *name;
const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
@@ -257,6 +263,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
rsize = sizeof(uint64_t) * 2 * nr_threads;
reg = g_malloc(rsize);
for (i = 0; i < nr_threads; i++) {
+ /* We know P8 PIR is linear with thread id */
reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
reg[i * 2 + 1] = cpu_to_be64(0x1000);
}
@@ -324,7 +331,7 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
pa_features_207, sizeof(pa_features_207))));
/* Interrupt Control Presenters (ICP). One per core. */
- pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
+ pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads);
}
if (chip->ram_size) {
@@ -1075,9 +1082,10 @@ static void pnv_init(MachineState *machine)
* 25:28 Core number
* 29:31 Thread ID
*/
-static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
+static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 7) | (core_id << 3);
+ return (chip->chip_id << 7) | (core_id << 3) | thread_id;
}
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@@ -1129,14 +1137,37 @@ static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
*
* We only care about the lower bits. uint32_t is fine for the moment.
*/
-static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
+static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 8) | (core_id << 2);
+ if (chip->nr_threads == 8) {
+ return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) |
+ (thread_id >> 1);
+ } else {
+ return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
}
-static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
+/*
+ * 0:48 Reserved - Read as zeroes
+ * 49:52 Node ID
+ * 53:55 Chip ID
+ * 56 Reserved - Read as zero
+ * 57:59 Quad ID
+ * 60 Core Chiplet Pair ID
+ * 61:63 Thread/Core Chiplet ID t0-t2
+ *
+ * We only care about the lower bits. uint32_t is fine for the moment.
+ */
+static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id,
+ uint32_t thread_id)
{
- return (chip->chip_id << 8) | (core_id << 2);
+ if (chip->nr_threads == 8) {
+ return (chip->chip_id << 8) | ((core_id / 4) << 4) |
+ ((core_id % 2) << 3) | thread_id;
+ } else {
+ return (chip->chip_id << 8) | (core_id << 2) | thread_id;
+ }
}
static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
@@ -1315,7 +1346,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
int core_hwid = CPU_CORE(pnv_core)->core_id;
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
- uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
+ uint32_t pir = pcc->chip_pir(chip, core_hwid, j);
PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
@@ -1428,7 +1459,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->num_phbs = 3;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1452,7 +1483,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1476,7 +1507,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 4;
- k->core_pir = pnv_chip_core_pir_p8;
+ k->chip_pir = pnv_chip_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->intc_reset = pnv_chip_power8_intc_reset;
k->intc_destroy = pnv_chip_power8_intc_destroy;
@@ -1749,7 +1780,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
- k->core_pir = pnv_chip_core_pir_p9;
+ k->chip_pir = pnv_chip_pir_p9;
k->intc_create = pnv_chip_power9_intc_create;
k->intc_reset = pnv_chip_power9_intc_reset;
k->intc_destroy = pnv_chip_power9_intc_destroy;
@@ -2061,7 +2092,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
k->cores_mask = POWER10_CORE_MASK;
- k->core_pir = pnv_chip_core_pir_p10;
+ k->chip_pir = pnv_chip_pir_p10;
k->intc_create = pnv_chip_power10_intc_create;
k->intc_reset = pnv_chip_power10_intc_reset;
k->intc_destroy = pnv_chip_power10_intc_destroy;
@@ -2151,8 +2182,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
chip->nr_threads, &error_fatal);
object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
core_hwid, &error_fatal);
- object_property_set_int(OBJECT(pnv_core), "pir",
- pcc->core_pir(chip, core_hwid), &error_fatal);
+ object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid,
+ &error_fatal);
object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
&error_fatal);
object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8c7afe037f..f40ab721d6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -226,7 +226,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
int thread_index)
{
CPUPPCState *env = &cpu->env;
- int core_pir;
+ int core_hwid;
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
Error *local_err = NULL;
@@ -242,10 +242,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
return;
}
- core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
+ core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort);
tir->default_value = thread_index;
- pir->default_value = core_pir + thread_index;
+ pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index);
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
@@ -342,7 +342,7 @@ static void pnv_core_unrealize(DeviceState *dev)
}
static Property pnv_core_properties[] = {
- DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
+ DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0),
DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
DEFINE_PROP_END_OF_LIST(),
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index af4cd7a8b8..8589f3291e 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -147,7 +147,7 @@ struct PnvChipClass {
DeviceRealize parent_realize;
- uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
+ uint32_t (*chip_pir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 4db21229a6..c6d62fd145 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -36,6 +36,7 @@ struct PnvCore {
/*< public >*/
PowerPCCPU **threads;
uint32_t pir;
+ uint32_t hwid;
uint64_t hrmor;
PnvChip *chip;
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index a9d41d2802..58e808dc96 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -49,9 +49,6 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
CPUState *cs = env_cpu(env);
CPUState *ccs;
uint32_t nr_threads = cs->nr_threads;
- uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1);
-
- assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]);
if (nr_threads == 1) {
env->spr[sprn] = val;
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 18/38] target/ppc: Use env_cpu for cpu_abort in excp_helper
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (16 preceding siblings ...)
2024-03-12 16:58 ` [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 19/38] target/ppc: Readability improvements in exception handlers Nicholas Piggin
` (21 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan, Philippe Mathieu-Daudé
From: BALATON Zoltan <balaton@eik.bme.hu>
Use the env_cpu function to get the CPUState for cpu_abort. These are
only needed in case of fatal errors so this allows to avoid casting
and storing CPUState in a local variable wnen not needed.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 118 +++++++++++++++++++++------------------
1 file changed, 63 insertions(+), 55 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 98952de267..56a5fe7f3b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -445,7 +445,6 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env)
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -473,8 +472,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -523,7 +522,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->spr[SPR_40x_ESR] = ESR_PTR;
break;
default:
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -550,11 +549,12 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
trace_ppc_excp_print("PIT");
break;
case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -569,7 +569,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -592,8 +591,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -653,7 +652,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -675,8 +674,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -703,11 +703,12 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -730,7 +731,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -753,8 +753,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -812,7 +812,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -854,8 +854,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset exception "
+ "%d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -875,11 +876,12 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -902,7 +904,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
@@ -925,8 +926,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -984,7 +985,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1026,7 +1027,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
@@ -1039,11 +1041,12 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1066,7 +1069,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1;
@@ -1103,8 +1105,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -1135,6 +1137,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
if (env->mpic_proxy) {
+ CPUState *cs = env_cpu(env);
/* IACK the IRQ on delivery */
env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
}
@@ -1173,7 +1176,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1214,7 +1217,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
/* DBSR already modified by caller */
} else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
+ cpu_abort(env_cpu(env),
+ "Debug exception triggered on unsupported model\n");
}
break;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
@@ -1228,17 +1232,19 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1376,7 +1382,6 @@ static bool is_prefix_insn_excp(PowerPCCPU *cpu, int excp)
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
@@ -1415,8 +1420,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
+ cpu_abort(env_cpu(env),
+ "Raised an exception without defined vector %d\n", excp);
}
vector |= env->excp_prefix;
@@ -1512,7 +1517,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
default:
/* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
+ cpu_abort(env_cpu(env), "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -1578,7 +1583,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
} else {
if (FIELD_EX64(env->msr, MSR, POW)) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
+ cpu_abort(env_cpu(env),
+ "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
}
@@ -1650,11 +1656,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_VPUA: /* Vector assist exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
- cpu_abort(cs, "%s exception not implemented\n",
+ cpu_abort(env_cpu(env), "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
break;
}
@@ -1687,8 +1694,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
+ cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR) %d "
+ "with no HV support\n", excp);
}
/* This can update new_msr and vector if AIL applies */
@@ -1706,11 +1713,11 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(env_cpu(env), "Invalid PowerPC exception %d. Aborting\n",
+ excp);
}
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
@@ -2244,7 +2251,6 @@ void ppc_maybe_interrupt(CPUPPCState *env)
static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2288,14 +2294,14 @@ static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
static void p8_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_MCK: /* Machine check exception */
@@ -2359,7 +2365,8 @@ static void p8_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
@@ -2438,7 +2445,8 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
#endif
@@ -2446,7 +2454,6 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
switch (interrupt) {
case PPC_INTERRUPT_RESET: /* External reset */
@@ -2543,7 +2550,8 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
assert(!env->resume_as_sreset);
break;
default:
- cpu_abort(cs, "Invalid PowerPC interrupt %d. Aborting\n", interrupt);
+ cpu_abort(env_cpu(env), "Invalid PowerPC interrupt %d. Aborting\n",
+ interrupt);
}
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 19/38] target/ppc: Readability improvements in exception handlers
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (17 preceding siblings ...)
2024-03-12 16:58 ` [PULL 18/38] target/ppc: Use env_cpu for cpu_abort in excp_helper Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 20/38] target/ppc: Add gen_exception_err_nip() function Nicholas Piggin
` (20 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 1 +
target/ppc/excp_helper.c | 179 +++++++--------------------------------
2 files changed, 33 insertions(+), 147 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ed04351f27..7c48b2eadb 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2954,6 +2954,7 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
}
#if !defined(CONFIG_USER_ONLY)
+/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 56a5fe7f3b..c15cd904d1 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -403,9 +403,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector,
* We don't use hreg_store_msr here as already have treated any
* special case that could occur. Just store MSR and update hflags
*
- * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
- * will prevent setting of the HV bit which some exceptions might need
- * to do.
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it will
+ * prevent setting of the HV bit which some exceptions might need to do.
*/
env->nip = vector;
env->msr = msr;
@@ -447,25 +446,15 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden.
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & (((target_ulong)1 << MSR_ME));
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -475,7 +464,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -487,7 +475,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
srr0 = SPR_40x_SRR2;
srr1 = SPR_40x_SRR3;
break;
@@ -558,12 +545,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
}
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -575,16 +558,10 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -594,7 +571,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -604,7 +580,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -632,11 +607,9 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -712,20 +685,11 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -737,16 +701,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -756,7 +714,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -764,7 +721,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -792,11 +748,9 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -865,12 +819,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
ppc_excp_debug_sw_tlb(env, excp);
-
msr |= env->crf[0] << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
-
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */
@@ -885,20 +837,11 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -910,16 +853,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
- /*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
- */
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -929,7 +866,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -937,7 +873,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
powerpc_mcheck_checkstop(env);
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
-
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
@@ -965,11 +900,9 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -1050,20 +983,11 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
- /* Save PC */
env->spr[SPR_SRR0] = env->nip;
-
- /* Save MSR */
env->spr[SPR_SRR1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -1071,24 +995,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
-
- msr = env->msr;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
/*
- * new interrupt handler msr preserves existing ME unless
- * explicitly overridden
+ * Book E does not play games with certain bits of xSRR1 being MSR save
+ * bits and others being error status. xSRR1 is the old MSR, period.
*/
- new_msr = env->msr & ((target_ulong)1 << MSR_ME);
+ msr = env->msr;
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
+ /* new interrupt handler msr preserves ME unless explicitly overridden */
+ new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later.
- */
+ /* HV emu assistance interrupt only exists on server arch 2.05 or later */
if (excp == POWERPC_EXCP_HV_EMU) {
excp = POWERPC_EXCP_PROGRAM;
}
@@ -1108,7 +1026,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
switch (excp) {
@@ -1152,11 +1069,9 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
env->spr[SPR_BOOKE_ESR] = ESR_FP;
@@ -1257,12 +1172,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
#endif
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
@@ -1384,21 +1295,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
+ int srr0 = SPR_SRR0, srr1 = SPR_SRR1, lev = -1;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
/*
- * new interrupt handler msr preserves existing HV and ME unless
- * explicitly overridden
+ * new interrupt handler msr preserves HV and ME unless explicitly
+ * overridden
*/
new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
* P7/P8/P9
@@ -1423,7 +1330,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
cpu_abort(env_cpu(env),
"Raised an exception without defined vector %d\n", excp);
}
-
vector |= env->excp_prefix;
if (is_prefix_insn_excp(cpu, excp)) {
@@ -1440,7 +1346,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
*/
new_msr |= (target_ulong)MSR_HVB;
}
-
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
@@ -1458,23 +1363,17 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
bool lpes0;
- /*
- * LPES0 is only taken into consideration if we support HV
- * mode for this CPU.
- */
+ /* LPES0 is only taken into consideration if we support HV mode */
if (!env->has_hv_mode) {
break;
}
-
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-
if (!lpes0) {
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
}
-
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
@@ -1497,11 +1396,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
powerpc_reset_excp_state(cpu);
return;
}
-
/*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
+ * NIP always points to the faulting instruction for FP exceptions,
+ * so always use store_next and claim we are precise in the MSR.
*/
msr |= 0x00100000;
break;
@@ -1665,21 +1562,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
}
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
new_msr |= (target_ulong)1 << MSR_LE;
}
-
new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
env->spr[srr0] = env->nip;
-
- /* Save MSR */
env->spr[srr1] = msr;
}
@@ -1688,19 +1577,15 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
/* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
vhc->deliver_hv_excp(cpu, excp);
-
powerpc_reset_excp_state(cpu);
-
} else {
/* Sanity check */
if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
cpu_abort(env_cpu(env), "Trying to deliver HV exception (HSRR) %d "
"with no HV support\n", excp);
}
-
/* This can update new_msr and vector if AIL applies */
ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
-
powerpc_set_excp_state(cpu, vector, new_msr);
}
}
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 20/38] target/ppc: Add gen_exception_err_nip() function
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (18 preceding siblings ...)
2024-03-12 16:58 ` [PULL 19/38] target/ppc: Readability improvements in exception handlers Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1 Nicholas Piggin
` (19 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
Add gen_exception_err_nip() that does the same as gen_exception_err()
but takes the nip as a parameter to allow specifying it instead of
using the current instruction address then change gen_exception_err()
to use it.
The gen_exception() and gen_exception_nip() functions are similar so
remove code duplication from those too while at it.
Suggested-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/translate.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4f6f7dcd89..93ffec787c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -296,33 +296,26 @@ static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
tcg_gen_movi_tl(cpu_nip, nip);
}
-static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
+static void gen_exception_err_nip(DisasContext *ctx, uint32_t excp,
+ uint32_t error, target_ulong nip)
{
TCGv_i32 t0, t1;
- /*
- * These are all synchronous exceptions, we set the PC back to the
- * faulting instruction
- */
- gen_update_nip(ctx, ctx->cia);
+ gen_update_nip(ctx, nip);
t0 = tcg_constant_i32(excp);
t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(tcg_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception(DisasContext *ctx, uint32_t excp)
+static inline void gen_exception_err(DisasContext *ctx, uint32_t excp,
+ uint32_t error)
{
- TCGv_i32 t0;
-
/*
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- gen_update_nip(ctx, ctx->cia);
- t0 = tcg_constant_i32(excp);
- gen_helper_raise_exception(tcg_env, t0);
- ctx->base.is_jmp = DISAS_NORETURN;
+ gen_exception_err_nip(ctx, excp, error, ctx->cia);
}
static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
@@ -336,6 +329,15 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
ctx->base.is_jmp = DISAS_NORETURN;
}
+static inline void gen_exception(DisasContext *ctx, uint32_t excp)
+{
+ /*
+ * These are all synchronous exceptions, we set the PC back to the
+ * faulting instruction
+ */
+ gen_exception_nip(ctx, excp, ctx->cia);
+}
+
#if !defined(CONFIG_USER_ONLY)
static void gen_ppc_maybe_interrupt(DisasContext *ctx)
{
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (19 preceding siblings ...)
2024-03-12 16:58 ` [PULL 20/38] target/ppc: Add gen_exception_err_nip() function Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 22/38] target/ppc: Clean up ifdefs in excp_helper.c, part 2 Nicholas Piggin
` (18 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
Use #ifdef, #ifndef for brevity and add comments to #endif that are
more than a few lines apart for clarity.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 49 ++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index c15cd904d1..32337c67f4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -35,7 +35,7 @@
/*****************************************************************************/
/* Exception processing */
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
static const char *powerpc_excp_name(int excp)
{
@@ -186,7 +186,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
env->error_code);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static int powerpc_reset_wakeup(CPUPPCState *env, int excp, target_ulong *msr)
{
/* We no longer are in a PM state */
@@ -380,7 +380,7 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
}
}
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_reset_excp_state(PowerPCCPU *cpu)
{
@@ -1163,7 +1163,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
new_msr |= (target_ulong)1 << MSR_CM;
@@ -1594,7 +1594,7 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
g_assert_not_reached();
}
-#endif
+#endif /* TARGET_PPC64 */
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
@@ -1645,7 +1645,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
powerpc_excp(cpu, cs->exception_index);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
#define P7_UNUSED_INTERRUPTS \
(PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \
PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
@@ -1976,7 +1976,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
return 0;
}
-#endif
+#endif /* TARGET_PPC64 */
static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
{
@@ -2093,7 +2093,7 @@ static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
switch (env->excp_model) {
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
case POWERPC_EXCP_POWER7:
return p7_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER8:
@@ -2132,7 +2132,7 @@ void ppc_maybe_interrupt(CPUPPCState *env)
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
static void p7_deliver_interrupt(CPUPPCState *env, int interrupt)
{
PowerPCCPU *cpu = env_archcpu(env);
@@ -2334,7 +2334,7 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
interrupt);
}
}
-#endif
+#endif /* TARGET_PPC64 */
static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
{
@@ -2443,7 +2443,7 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
{
switch (env->excp_model) {
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
case POWERPC_EXCP_POWER7:
p7_deliver_interrupt(env, interrupt);
break;
@@ -2553,9 +2553,9 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
{
raise_exception_err_ra(env, exception, 0, 0);
}
-#endif
+#endif /* CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
+#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
@@ -2572,7 +2572,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env)
ppc_maybe_interrupt(env);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_scv(CPUPPCState *env, uint32_t lev)
{
if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
@@ -2600,7 +2600,7 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn)
ppc_maybe_interrupt(env);
}
-#endif /* defined(TARGET_PPC64) */
+#endif /* TARGET_PPC64 */
static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
@@ -2611,7 +2611,7 @@ static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
if (env->flags & POWERPC_FLAG_TGPR)
msr &= ~(1ULL << MSR_TGPR);
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
/* Switching to 32-bit ? Crop the nip */
if (!msr_is_64bit(env, msr)) {
nip = (uint32_t)nip;
@@ -2640,7 +2640,7 @@ void helper_rfi(CPUPPCState *env)
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_rfid(CPUPPCState *env)
{
/*
@@ -2661,7 +2661,7 @@ void helper_hrfid(CPUPPCState *env)
{
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
-#endif
+#endif /* TARGET_PPC64 */
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
void helper_rfebb(CPUPPCState *env, target_ulong s)
@@ -2738,7 +2738,7 @@ void raise_ebb_perfm_exception(CPUPPCState *env)
do_ebb(env, POWERPC_EXCP_PERFM_EBB);
}
-#endif
+#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
@@ -2780,7 +2780,7 @@ void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
}
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2793,8 +2793,8 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
POWERPC_EXCP_TRAP, GETPC());
}
}
-#endif
-#endif
+#endif /* TARGET_PPC64 */
+#endif /* CONFIG_TCG */
#ifdef CONFIG_TCG
static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
@@ -2909,8 +2909,7 @@ HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
#endif /* CONFIG_TCG */
-#if !defined(CONFIG_USER_ONLY)
-
+#ifndef CONFIG_USER_ONLY
#ifdef CONFIG_TCG
/* Embedded.Processor Control */
@@ -3019,7 +3018,7 @@ void helper_book3s_msgsnd(target_ulong rb)
book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL);
}
-#if defined(TARGET_PPC64)
+#ifdef TARGET_PPC64
void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
{
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 22/38] target/ppc: Clean up ifdefs in excp_helper.c, part 2
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (20 preceding siblings ...)
2024-03-12 16:58 ` [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1 Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 23/38] target/ppc: Clean up ifdefs in excp_helper.c, part 3 Nicholas Piggin
` (17 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
Remove check for !defined(CONFIG_USER_ONLY) as this is already within
an #ifndef CONFIG_USER_ONLY block.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 32337c67f4..148b0c3a19 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2663,7 +2663,7 @@ void helper_hrfid(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+#ifdef TARGET_PPC64
void helper_rfebb(CPUPPCState *env, target_ulong s)
{
target_ulong msr = env->msr;
@@ -2738,7 +2738,7 @@ void raise_ebb_perfm_exception(CPUPPCState *env)
do_ebb(env, POWERPC_EXCP_PERFM_EBB);
}
-#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
+#endif /* TARGET_PPC64 */
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 23/38] target/ppc: Clean up ifdefs in excp_helper.c, part 3
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (21 preceding siblings ...)
2024-03-12 16:58 ` [PULL 22/38] target/ppc: Clean up ifdefs in excp_helper.c, part 2 Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 24/38] target/ppc: Remove interrupt handler wrapper functions Nicholas Piggin
` (16 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
Concatenate #if blocks that are ending then beginning on the next line
again.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 148b0c3a19..a9efda7626 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2553,10 +2553,8 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
{
raise_exception_err_ra(env, exception, 0, 0);
}
-#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
-#ifdef CONFIG_TCG
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
uint32_t excp = hreg_store_msr(env, val, 0);
@@ -2661,9 +2659,7 @@ void helper_hrfid(CPUPPCState *env)
{
do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
-#endif /* TARGET_PPC64 */
-#ifdef TARGET_PPC64
void helper_rfebb(CPUPPCState *env, target_ulong s)
{
target_ulong msr = env->msr;
@@ -2763,10 +2759,8 @@ void helper_rfmci(CPUPPCState *env)
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
}
-#endif /* CONFIG_TCG */
-#endif /* !defined(CONFIG_USER_ONLY) */
+#endif /* !CONFIG_USER_ONLY */
-#ifdef CONFIG_TCG
void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags)
{
@@ -2794,9 +2788,7 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
}
}
#endif /* TARGET_PPC64 */
-#endif /* CONFIG_TCG */
-#ifdef CONFIG_TCG
static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
{
const uint16_t c = 0xfffc;
@@ -2907,11 +2899,8 @@ HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
-#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
-#ifdef CONFIG_TCG
-
/* Embedded.Processor Control */
static int dbell2irq(target_ulong rb)
{
@@ -3258,5 +3247,5 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return false;
}
-#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 24/38] target/ppc: Remove interrupt handler wrapper functions
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (22 preceding siblings ...)
2024-03-12 16:58 ` [PULL 23/38] target/ppc: Clean up ifdefs in excp_helper.c, part 3 Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 25/38] spapr: nested: register nested-hv api hcalls only for cap-nested-hv Nicholas Piggin
` (15 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, BALATON Zoltan
From: BALATON Zoltan <balaton@eik.bme.hu>
These wrappers call out to handle POWER7 and newer in separate
functions but reduce to the generic case when TARGET_PPC64 is not
defined. It is easy enough to include the switch in the beginning of
the generic functions to branch out to the specific functions and get
rid of these wrappers. This avoids one indirection and entirely
compiles out the switch without TARGET_PPC64.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 67 +++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a9efda7626..ded488fcd8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1978,8 +1978,21 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
+static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER8:
+ return p8_next_unmasked_interrupt(env);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_next_unmasked_interrupt(env);
+ default:
+ break;
+ }
+#endif
bool async_deliver;
/* External reset */
@@ -2090,23 +2103,6 @@ static int ppc_next_unmasked_interrupt_generic(CPUPPCState *env)
return 0;
}
-static int ppc_next_unmasked_interrupt(CPUPPCState *env)
-{
- switch (env->excp_model) {
-#ifdef TARGET_PPC64
- case POWERPC_EXCP_POWER7:
- return p7_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER8:
- return p8_next_unmasked_interrupt(env);
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- return p9_next_unmasked_interrupt(env);
-#endif
- default:
- return ppc_next_unmasked_interrupt_generic(env);
- }
-}
-
/*
* Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be
* delivered and clears CPU_INTERRUPT_HARD otherwise.
@@ -2336,8 +2332,21 @@ static void p9_deliver_interrupt(CPUPPCState *env, int interrupt)
}
#endif /* TARGET_PPC64 */
-static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
+static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
{
+#ifdef TARGET_PPC64
+ switch (env->excp_model) {
+ case POWERPC_EXCP_POWER7:
+ return p7_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER8:
+ return p8_deliver_interrupt(env, interrupt);
+ case POWERPC_EXCP_POWER9:
+ case POWERPC_EXCP_POWER10:
+ return p9_deliver_interrupt(env, interrupt);
+ default:
+ break;
+ }
+#endif
PowerPCCPU *cpu = env_archcpu(env);
switch (interrupt) {
@@ -2440,26 +2449,6 @@ static void ppc_deliver_interrupt_generic(CPUPPCState *env, int interrupt)
}
}
-static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt)
-{
- switch (env->excp_model) {
-#ifdef TARGET_PPC64
- case POWERPC_EXCP_POWER7:
- p7_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER8:
- p8_deliver_interrupt(env, interrupt);
- break;
- case POWERPC_EXCP_POWER9:
- case POWERPC_EXCP_POWER10:
- p9_deliver_interrupt(env, interrupt);
- break;
-#endif
- default:
- ppc_deliver_interrupt_generic(env, interrupt);
- }
-}
-
void ppc_cpu_do_system_reset(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 25/38] spapr: nested: register nested-hv api hcalls only for cap-nested-hv
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (23 preceding siblings ...)
2024-03-12 16:58 ` [PULL 24/38] target/ppc: Remove interrupt handler wrapper functions Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 26/38] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c Nicholas Piggin
` (14 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Since cap-nested-hv is an optional capability, it makes sense to register
api specfic hcalls only when respective capability is enabled. This
requires to introduce a new API to unregister hypercalls to maintain
sanity across guest reboot since caps are re-applied across reboots and
re-registeration of hypercalls would hit assert otherwise.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_hcall.c | 24 ++++++++++++++++++++++--
hw/ppc/spapr_nested.c | 25 +++++++++++++++++++++++--
include/hw/ppc/spapr.h | 4 ++++
include/hw/ppc/spapr_nested.h | 1 -
5 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index abd484023a..7321c35174 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1734,6 +1734,7 @@ static void spapr_machine_reset(MachineState *machine, ShutdownCause reason)
pef_kvm_reset(machine->cgs, &error_fatal);
spapr_caps_apply(spapr);
+ spapr_nested_reset(spapr);
first_ppc_cpu = POWERPC_CPU(first_cpu);
if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 75c2d12978..5e1d020e3d 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1525,6 +1525,28 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
*slot = fn;
}
+void spapr_unregister_hypercall(target_ulong opcode)
+{
+ spapr_hcall_fn *slot;
+
+ if (opcode <= MAX_HCALL_OPCODE) {
+ assert((opcode & 0x3) == 0);
+
+ slot = &papr_hypercall_table[opcode / 4];
+ } else if (opcode >= SVM_HCALL_BASE && opcode <= SVM_HCALL_MAX) {
+ /* we only have SVM-related hcall numbers assigned in multiples of 4 */
+ assert((opcode & 0x3) == 0);
+
+ slot = &svm_hypercall_table[(opcode - SVM_HCALL_BASE) / 4];
+ } else {
+ assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
+
+ slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
+ }
+
+ *slot = NULL;
+}
+
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args)
{
@@ -1638,8 +1660,6 @@ static void hypercall_register_types(void)
spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
-
- spapr_register_nested();
}
type_init(hypercall_register_types)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 121aa96ddc..8e0ee0d22f 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -7,6 +7,14 @@
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_nested.h"
+void spapr_nested_reset(SpaprMachineState *spapr)
+{
+ if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
+ spapr_unregister_nested_hv();
+ spapr_register_nested_hv();
+ }
+}
+
#ifdef CONFIG_TCG
#define PRTS_MASK 0x1f
@@ -375,20 +383,33 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
address_space_unmap(CPU(cpu)->as, regs, len, len, true);
}
-void spapr_register_nested(void)
+void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
}
+
+void spapr_unregister_nested_hv(void)
+{
+ spapr_unregister_hypercall(KVMPPC_H_SET_PARTITION_TABLE);
+ spapr_unregister_hypercall(KVMPPC_H_ENTER_NESTED);
+ spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE);
+ spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST);
+}
#else
void spapr_exit_nested(PowerPCCPU *cpu, int excp)
{
g_assert_not_reached();
}
-void spapr_register_nested(void)
+void spapr_register_nested_hv(void)
+{
+ /* DO NOTHING */
+}
+
+void spapr_unregister_nested_hv(void)
{
/* DO NOTHING */
}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 5b5ba9ef77..78a736297b 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -631,6 +631,7 @@ typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
target_ulong *args);
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
+void spapr_unregister_hypercall(target_ulong opcode);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
@@ -1028,5 +1029,8 @@ void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt);
/* H_WATCHDOG */
void spapr_watchdog_init(SpaprMachineState *spapr);
+void spapr_register_nested_hv(void);
+void spapr_unregister_nested_hv(void);
+void spapr_nested_reset(SpaprMachineState *spapr);
#endif /* HW_SPAPR_H */
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index d312a5d61d..09d95182b2 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -95,7 +95,6 @@ struct nested_ppc_state {
int64_t tb_offset;
};
-void spapr_register_nested(void);
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 26/38] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (24 preceding siblings ...)
2024-03-12 16:58 ` [PULL 25/38] spapr: nested: register nested-hv api hcalls only for cap-nested-hv Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 27/38] spapr: nested: Introduce SpaprMachineStateNested to store related info Nicholas Piggin
` (13 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Most of the nested code has already been moved to spapr_nested.c
This logic inside spapr_get_pate is related to nested guests and
better suited for spapr_nested.c, hence moving there.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 28 ++-------------------------
hw/ppc/spapr_nested.c | 36 +++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr_nested.h | 3 ++-
3 files changed, 40 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 7321c35174..ff429d0ffe 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1407,7 +1407,6 @@ void spapr_init_all_lpcrs(target_ulong value, target_ulong mask)
}
}
-
static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry)
{
@@ -1420,33 +1419,10 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
/* Copy PATE1:GR into PATE0:HR */
entry->dw0 = spapr->patb_entry & PATE0_HR;
entry->dw1 = spapr->patb_entry;
-
+ return true;
} else {
- uint64_t patb, pats;
-
- assert(lpid != 0);
-
- patb = spapr->nested_ptcr & PTCR_PATB;
- pats = spapr->nested_ptcr & PTCR_PATS;
-
- /* Check if partition table is properly aligned */
- if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
- return false;
- }
-
- /* Calculate number of entries */
- pats = 1ull << (pats + 12 - 4);
- if (pats <= lpid) {
- return false;
- }
-
- /* Grab entry */
- patb += 16 * lpid;
- entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
- entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
}
-
- return true;
}
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 8e0ee0d22f..f7888ca8bd 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -6,6 +6,7 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_nested.h"
+#include "mmu-book3s-v3.h"
void spapr_nested_reset(SpaprMachineState *spapr)
{
@@ -16,6 +17,35 @@ void spapr_nested_reset(SpaprMachineState *spapr)
}
#ifdef CONFIG_TCG
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ uint64_t patb, pats;
+
+ assert(lpid != 0);
+
+ patb = spapr->nested_ptcr & PTCR_PATB;
+ pats = spapr->nested_ptcr & PTCR_PATS;
+
+ /* Check if partition table is properly aligned */
+ if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
+ return false;
+ }
+
+ /* Calculate number of entries */
+ pats = 1ull << (pats + 12 - 4);
+ if (pats <= lpid) {
+ return false;
+ }
+
+ /* Grab entry */
+ patb += 16 * lpid;
+ entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
+ entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return true;
+}
+
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -413,4 +443,10 @@ void spapr_unregister_nested_hv(void)
{
/* DO NOTHING */
}
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ return false;
+}
#endif
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 09d95182b2..1df1ce14f6 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -96,5 +96,6 @@ struct nested_ppc_state {
};
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
-
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 27/38] spapr: nested: Introduce SpaprMachineStateNested to store related info.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (25 preceding siblings ...)
2024-03-12 16:58 ` [PULL 26/38] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 28/38] spapr: nested: keep nested-hv related code restricted to its API Nicholas Piggin
` (12 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Currently, nested_ptcr is being used by existing nested-hv API to store
nested guest related info. This need to be organised to extend support
for the nested PAPR API which would need to store additional info
related to nested guests in next series of patches.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 8 ++++----
include/hw/ppc/spapr.h | 3 ++-
include/hw/ppc/spapr_nested.h | 5 +++++
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index f7888ca8bd..c2a33fc3a9 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -25,8 +25,8 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
assert(lpid != 0);
- patb = spapr->nested_ptcr & PTCR_PATB;
- pats = spapr->nested_ptcr & PTCR_PATS;
+ patb = spapr->nested.ptcr & PTCR_PATB;
+ pats = spapr->nested.ptcr & PTCR_PATS;
/* Check if partition table is properly aligned */
if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
@@ -63,7 +63,7 @@ static target_ulong h_set_ptbl(PowerPCCPU *cpu,
return H_PARAMETER;
}
- spapr->nested_ptcr = ptcr; /* Save new partition table */
+ spapr->nested.ptcr = ptcr; /* Save new partition table */
return H_SUCCESS;
}
@@ -195,7 +195,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
struct kvmppc_pt_regs *regs;
hwaddr len;
- if (spapr->nested_ptcr == 0) {
+ if (spapr->nested.ptcr == 0) {
return H_NOT_AVAILABLE;
}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 78a736297b..0eb01ea6fd 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -12,6 +12,7 @@
#include "hw/ppc/spapr_xive.h" /* For SpaprXive */
#include "hw/ppc/xics.h" /* For ICSState */
#include "hw/ppc/spapr_tpm_proxy.h"
+#include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */
struct SpaprVioBus;
struct SpaprPhbState;
@@ -213,7 +214,7 @@ struct SpaprMachineState {
uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
/* Nested HV support (TCG only) */
- uint64_t nested_ptcr;
+ SpaprMachineStateNested nested;
Notifier epow_notifier;
QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 1df1ce14f6..2488ea98da 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -3,6 +3,10 @@
#include "target/ppc/cpu.h"
+typedef struct SpaprMachineStateNested {
+ uint64_t ptcr;
+} SpaprMachineStateNested;
+
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
* New member must be added at the end.
@@ -96,6 +100,7 @@ struct nested_ppc_state {
};
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
+typedef struct SpaprMachineState SpaprMachineState;
bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 28/38] spapr: nested: keep nested-hv related code restricted to its API.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (26 preceding siblings ...)
2024-03-12 16:58 ` [PULL 27/38] spapr: nested: Introduce SpaprMachineStateNested to store related info Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 29/38] spapr: nested: Document Nested PAPR API Nicholas Piggin
` (11 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
spapr_exit_nested and spapr_get_pate_nested_hv contains code which
is specific to nested-hv API. Isolating code flows based on API
helps extending it to be used with different API as well.
Suggested-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 6 +++++-
hw/ppc/spapr_nested.c | 25 ++++++++++++++++++++++---
include/hw/ppc/spapr_nested.h | 3 +++
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index ff429d0ffe..e001ffe06f 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1421,7 +1421,11 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
entry->dw1 = spapr->patb_entry;
return true;
} else {
- return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
+ assert(spapr_nested_api(spapr));
+ if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
+ }
+ return false;
}
}
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index c2a33fc3a9..12fdbe2aba 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -11,11 +11,19 @@
void spapr_nested_reset(SpaprMachineState *spapr)
{
if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
+ spapr->nested.api = NESTED_API_KVM_HV;
spapr_unregister_nested_hv();
spapr_register_nested_hv();
+ } else {
+ spapr->nested.api = 0;
}
}
+uint8_t spapr_nested_api(SpaprMachineState *spapr)
+{
+ return spapr->nested.api;
+}
+
#ifdef CONFIG_TCG
bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
@@ -310,7 +318,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
return env->gpr[3];
}
-void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
@@ -322,8 +330,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
struct kvmppc_pt_regs *regs;
hwaddr len;
- assert(spapr_cpu->in_nested);
-
nested_save_state(&l2_state, cpu);
hsrr0 = env->spr[SPR_HSRR0];
hsrr1 = env->spr[SPR_HSRR1];
@@ -413,6 +419,19 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
address_space_unmap(CPU(cpu)->as, regs, len, len, true);
}
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+
+ assert(spapr_cpu->in_nested);
+ if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ spapr_exit_nested_hv(cpu, excp);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 2488ea98da..bf3a7b8d89 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -5,6 +5,8 @@
typedef struct SpaprMachineStateNested {
uint64_t ptcr;
+ uint8_t api;
+#define NESTED_API_KVM_HV 1
} SpaprMachineStateNested;
/*
@@ -103,4 +105,5 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp);
typedef struct SpaprMachineState SpaprMachineState;
bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry);
+uint8_t spapr_nested_api(SpaprMachineState *spapr);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 29/38] spapr: nested: Document Nested PAPR API
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (27 preceding siblings ...)
2024-03-12 16:58 ` [PULL 28/38] spapr: nested: keep nested-hv related code restricted to its API Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 30/38] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls Nicholas Piggin
` (10 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Adding initial documentation about Nested PAPR API to describe the set
of APIs and its usage. Also talks about the Guest State Buffer elements
and it's format which is used between L0/L1 to communicate L2 state.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
docs/devel/nested-papr.txt | 119 +++++++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
create mode 100644 docs/devel/nested-papr.txt
diff --git a/docs/devel/nested-papr.txt b/docs/devel/nested-papr.txt
new file mode 100644
index 0000000000..90943650db
--- /dev/null
+++ b/docs/devel/nested-papr.txt
@@ -0,0 +1,119 @@
+Nested PAPR API (aka KVM on PowerVM)
+====================================
+
+This API aims at providing support to enable nested virtualization with
+KVM on PowerVM. While the existing support for nested KVM on PowerNV was
+introduced with cap-nested-hv option, however, with a slight design change,
+to enable this on papr/pseries, a new cap-nested-papr option is added. eg:
+
+ qemu-system-ppc64 -cpu POWER10 -machine pseries,cap-nested-papr=true ...
+
+Work by:
+ Michael Neuling <mikey@neuling.org>
+ Vaibhav Jain <vaibhav@linux.ibm.com>
+ Jordan Niethe <jniethe5@gmail.com>
+ Harsh Prateek Bora <harshpb@linux.ibm.com>
+ Shivaprasad G Bhat <sbhat@linux.ibm.com>
+ Kautuk Consul <kconsul@linux.vnet.ibm.com>
+
+Below taken from the kernel documentation:
+
+Introduction
+============
+
+This document explains how a guest operating system can act as a
+hypervisor and run nested guests through the use of hypercalls, if the
+hypervisor has implemented them. The terms L0, L1, and L2 are used to
+refer to different software entities. L0 is the hypervisor mode entity
+that would normally be called the "host" or "hypervisor". L1 is a
+guest virtual machine that is directly run under L0 and is initiated
+and controlled by L0. L2 is a guest virtual machine that is initiated
+and controlled by L1 acting as a hypervisor. A significant design change
+wrt existing API is that now the entire L2 state is maintained within L0.
+
+Existing Nested-HV API
+======================
+
+Linux/KVM has had support for Nesting as an L0 or L1 since 2018
+
+The L0 code was added::
+
+ commit 8e3f5fc1045dc49fd175b978c5457f5f51e7a2ce
+ Author: Paul Mackerras <paulus@ozlabs.org>
+ Date: Mon Oct 8 16:31:03 2018 +1100
+ KVM: PPC: Book3S HV: Framework and hcall stubs for nested virtualization
+
+The L1 code was added::
+
+ commit 360cae313702cdd0b90f82c261a8302fecef030a
+ Author: Paul Mackerras <paulus@ozlabs.org>
+ Date: Mon Oct 8 16:31:04 2018 +1100
+ KVM: PPC: Book3S HV: Nested guest entry via hypercall
+
+This API works primarily using a signal hcall h_enter_nested(). This
+call made by the L1 to tell the L0 to start an L2 vCPU with the given
+state. The L0 then starts this L2 and runs until an L2 exit condition
+is reached. Once the L2 exits, the state of the L2 is given back to
+the L1 by the L0. The full L2 vCPU state is always transferred from
+and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
+vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
+-> L1 exit).
+
+The only state kept by the L0 is the partition table. The L1 registers
+it's partition table using the h_set_partition_table() hcall. All
+other state held by the L0 about the L2s is cached state (such as
+shadow page tables).
+
+The L1 may run any L2 or vCPU without first informing the L0. It
+simply starts the vCPU using h_enter_nested(). The creation of L2s and
+vCPUs is done implicitly whenever h_enter_nested() is called.
+
+In this document, we call this existing API the v1 API.
+
+New PAPR API
+===============
+
+The new PAPR API changes from the v1 API such that the creating L2 and
+associated vCPUs is explicit. In this document, we call this the v2
+API.
+
+h_enter_nested() is replaced with H_GUEST_VCPU_RUN(). Before this can
+be called the L1 must explicitly create the L2 using h_guest_create()
+and any associated vCPUs() created with h_guest_create_vCPU(). Getting
+and setting vCPU state can also be performed using h_guest_{g|s}et
+hcall.
+
+The basic execution flow is for an L1 to create an L2, run it, and
+delete it is:
+
+- L1 and L0 negotiate capabilities with H_GUEST_{G,S}ET_CAPABILITIES()
+ (normally at L1 boot time).
+
+- L1 requests the L0 to create an L2 with H_GUEST_CREATE() and receives a token
+
+- L1 requests the L0 to create an L2 vCPU with H_GUEST_CREATE_VCPU()
+
+- L1 and L0 communicate the vCPU state using the H_GUEST_{G,S}ET() hcall
+
+- L1 requests the L0 to run the vCPU using H_GUEST_RUN_VCPU() hcall
+
+- L1 deletes L2 with H_GUEST_DELETE()
+
+For more details, please refer:
+
+[1] Linux Kernel documentation (upstream documentation commit):
+
+commit 476652297f94a2e5e5ef29e734b0da37ade94110
+Author: Michael Neuling <mikey@neuling.org>
+Date: Thu Sep 14 13:06:00 2023 +1000
+
+ docs: powerpc: Document nested KVM on POWER
+
+ Document support for nested KVM on POWER using the existing API as well
+ as the new PAPR API. This includes the new HCALL interface and how it
+ used by KVM.
+
+ Signed-off-by: Michael Neuling <mikey@neuling.org>
+ Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
+ Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+ Link: https://msgid.link/20230914030600.16993-12-jniethe5@gmail.com
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 30/38] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (28 preceding siblings ...)
2024-03-12 16:58 ` [PULL 29/38] spapr: nested: Document Nested PAPR API Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 31/38] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls Nicholas Piggin
` (9 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling, Amit Machhiwal
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Introduce the nested PAPR hcalls:
- H_GUEST_GET_CAPABILITIES which is used to query the capabilities
of the API and the L2 guests it provides.
- H_GUEST_SET_CAPABILITIES which is used to set the Guest API
capabilities that the Host Partition supports and may use.
[amachhiw: support for p9 compat mode and return register bug fixes]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Amit Machhiwal <amachhiw@linux.vnet.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 115 ++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 7 ++-
include/hw/ppc/spapr_nested.h | 12 ++++
3 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 12fdbe2aba..c35acee51f 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -7,6 +7,7 @@
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_nested.h"
#include "mmu-book3s-v3.h"
+#include "cpu-models.h"
void spapr_nested_reset(SpaprMachineState *spapr)
{
@@ -16,6 +17,7 @@ void spapr_nested_reset(SpaprMachineState *spapr)
spapr_register_nested_hv();
} else {
spapr->nested.api = 0;
+ spapr->nested.capabilities_set = false;
}
}
@@ -432,6 +434,93 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
}
}
+static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+
+ if (flags) { /* don't handle any flags capabilities for now */
+ return H_PARAMETER;
+ }
+
+ /* P10 capabilities */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[4] |= H_GUEST_CAPABILITIES_P10_MODE;
+ }
+
+ /* P9 capabilities */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[4] |= H_GUEST_CAPABILITIES_P9_MODE;
+ }
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong capabilities = args[1];
+ env->gpr[4] = 0;
+
+ if (flags) { /* don't handle any flags capabilities for now */
+ return H_PARAMETER;
+ }
+
+ if (capabilities & H_GUEST_CAPABILITIES_COPY_MEM) {
+ env->gpr[4] = 1;
+ return H_P2; /* isn't supported */
+ }
+
+ /*
+ * If there are no capabilities configured, set the R5 to the index of
+ * the first supported Power Processor Mode
+ */
+ if (!capabilities) {
+ env->gpr[4] = 1;
+
+ /* set R5 to the first supported Power Processor Mode */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP;
+ } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[5] = H_GUEST_CAP_P9_MODE_BMAP;
+ }
+
+ return H_P2;
+ }
+
+ /*
+ * If an invalid capability is set, R5 should contain the index of the
+ * invalid capability bit
+ */
+ if (capabilities & ~H_GUEST_CAP_VALID_MASK) {
+ env->gpr[4] = 1;
+
+ /* Set R5 to the index of the invalid capability */
+ env->gpr[5] = 63 - ctz64(capabilities);
+
+ return H_P2;
+ }
+
+ if (!spapr->nested.capabilities_set) {
+ spapr->nested.capabilities_set = true;
+ spapr->nested.pvr_base = env->spr[SPR_PVR];
+ return H_SUCCESS;
+ } else {
+ return H_STATE;
+ }
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
@@ -447,6 +536,21 @@ void spapr_unregister_nested_hv(void)
spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE);
spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST);
}
+
+void spapr_register_nested_papr(void)
+{
+ spapr_register_hypercall(H_GUEST_GET_CAPABILITIES,
+ h_guest_get_capabilities);
+ spapr_register_hypercall(H_GUEST_SET_CAPABILITIES,
+ h_guest_set_capabilities);
+}
+
+void spapr_unregister_nested_papr(void)
+{
+ spapr_unregister_hypercall(H_GUEST_GET_CAPABILITIES);
+ spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES);
+}
+
#else
void spapr_exit_nested(PowerPCCPU *cpu, int excp)
{
@@ -468,4 +572,15 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
{
return false;
}
+
+void spapr_register_nested_papr(void)
+{
+ /* DO NOTHING */
+}
+
+void spapr_unregister_nested_papr(void)
+{
+ /* DO NOTHING */
+}
+
#endif
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 0eb01ea6fd..2906d59137 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -364,6 +364,7 @@ struct SpaprMachineState {
#define H_NOOP -63
#define H_UNSUPPORTED -67
#define H_OVERLAP -68
+#define H_STATE -75
#define H_UNSUPPORTED_FLAG -256
#define H_MULTI_THREADS_ACTIVE -9005
@@ -583,8 +584,10 @@ struct SpaprMachineState {
#define H_RPT_INVALIDATE 0x448
#define H_SCM_FLUSH 0x44C
#define H_WATCHDOG 0x45C
+#define H_GUEST_GET_CAPABILITIES 0x460
+#define H_GUEST_SET_CAPABILITIES 0x464
-#define MAX_HCALL_OPCODE H_WATCHDOG
+#define MAX_HCALL_OPCODE H_GUEST_SET_CAPABILITIES
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
@@ -1033,5 +1036,7 @@ void spapr_watchdog_init(SpaprMachineState *spapr);
void spapr_register_nested_hv(void);
void spapr_unregister_nested_hv(void);
void spapr_nested_reset(SpaprMachineState *spapr);
+void spapr_register_nested_papr(void);
+void spapr_unregister_nested_papr(void);
#endif /* HW_SPAPR_H */
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index bf3a7b8d89..73687e03e4 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -7,8 +7,20 @@ typedef struct SpaprMachineStateNested {
uint64_t ptcr;
uint8_t api;
#define NESTED_API_KVM_HV 1
+ bool capabilities_set;
+ uint32_t pvr_base;
} SpaprMachineStateNested;
+/* Nested PAPR API related macros */
+#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
+#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
+#define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
+#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \
+ H_GUEST_CAPABILITIES_P9_MODE)
+#define H_GUEST_CAP_COPY_MEM_BMAP 0
+#define H_GUEST_CAP_P9_MODE_BMAP 1
+#define H_GUEST_CAP_P10_MODE_BMAP 2
+
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
* New member must be added at the end.
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 31/38] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (29 preceding siblings ...)
2024-03-12 16:58 ` [PULL 30/38] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 32/38] spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall Nicholas Piggin
` (8 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Introduce the nested PAPR hcalls:
- H_GUEST_CREATE which is used to create and allocate resources for
nested guest being created.
- H_GUEST_DELETE which is used to delete and deallocate resources
for the nested guest being deleted. It also supports deleting all nested
guests at once using a deleteAll flag.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 103 ++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 4 +-
include/hw/ppc/spapr_nested.h | 7 +++
3 files changed, 113 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index c35acee51f..1f6eb68b93 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -521,6 +521,105 @@ static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu,
}
}
+static void
+destroy_guest_helper(gpointer value)
+{
+ struct SpaprMachineStateNestedGuest *guest = value;
+ g_free(guest);
+}
+
+static target_ulong h_guest_create(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong continue_token = args[1];
+ uint64_t guestid;
+ int nguests = 0;
+ struct SpaprMachineStateNestedGuest *guest;
+
+ if (flags) { /* don't handle any flags for now */
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ if (continue_token != -1) {
+ return H_P2;
+ }
+
+ if (!spapr->nested.capabilities_set) {
+ return H_STATE;
+ }
+
+ if (!spapr->nested.guests) {
+ spapr->nested.guests = g_hash_table_new_full(NULL,
+ NULL,
+ NULL,
+ destroy_guest_helper);
+ }
+
+ nguests = g_hash_table_size(spapr->nested.guests);
+
+ if (nguests == PAPR_NESTED_GUEST_MAX) {
+ return H_NO_MEM;
+ }
+
+ /* Lookup for available guestid */
+ for (guestid = 1; guestid < PAPR_NESTED_GUEST_MAX; guestid++) {
+ if (!(g_hash_table_lookup(spapr->nested.guests,
+ GINT_TO_POINTER(guestid)))) {
+ break;
+ }
+ }
+
+ if (guestid == PAPR_NESTED_GUEST_MAX) {
+ return H_NO_MEM;
+ }
+
+ guest = g_try_new0(struct SpaprMachineStateNestedGuest, 1);
+ if (!guest) {
+ return H_NO_MEM;
+ }
+
+ guest->pvr_logical = spapr->nested.pvr_base;
+ g_hash_table_insert(spapr->nested.guests, GINT_TO_POINTER(guestid), guest);
+ env->gpr[4] = guestid;
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_guest_delete(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong guestid = args[1];
+ struct SpaprMachineStateNestedGuest *guest;
+
+ /*
+ * handle flag deleteAllGuests, if set:
+ * guestid is ignored and all guests are deleted
+ *
+ */
+ if (flags & ~H_GUEST_DELETE_ALL_FLAG) {
+ return H_UNSUPPORTED_FLAG; /* other flag bits reserved */
+ } else if (flags & H_GUEST_DELETE_ALL_FLAG) {
+ g_hash_table_destroy(spapr->nested.guests);
+ return H_SUCCESS;
+ }
+
+ guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
+ if (!guest) {
+ return H_P2;
+ }
+
+ g_hash_table_remove(spapr->nested.guests, GINT_TO_POINTER(guestid));
+
+ return H_SUCCESS;
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
@@ -543,12 +642,16 @@ void spapr_register_nested_papr(void)
h_guest_get_capabilities);
spapr_register_hypercall(H_GUEST_SET_CAPABILITIES,
h_guest_set_capabilities);
+ spapr_register_hypercall(H_GUEST_CREATE, h_guest_create);
+ spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete);
}
void spapr_unregister_nested_papr(void)
{
spapr_unregister_hypercall(H_GUEST_GET_CAPABILITIES);
spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES);
+ spapr_unregister_hypercall(H_GUEST_CREATE);
+ spapr_unregister_hypercall(H_GUEST_DELETE);
}
#else
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 2906d59137..13416fc3d7 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -586,8 +586,10 @@ struct SpaprMachineState {
#define H_WATCHDOG 0x45C
#define H_GUEST_GET_CAPABILITIES 0x460
#define H_GUEST_SET_CAPABILITIES 0x464
+#define H_GUEST_CREATE 0x470
+#define H_GUEST_DELETE 0x488
-#define MAX_HCALL_OPCODE H_GUEST_SET_CAPABILITIES
+#define MAX_HCALL_OPCODE H_GUEST_DELETE
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 73687e03e4..56d43e540b 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -9,8 +9,13 @@ typedef struct SpaprMachineStateNested {
#define NESTED_API_KVM_HV 1
bool capabilities_set;
uint32_t pvr_base;
+ GHashTable *guests;
} SpaprMachineStateNested;
+typedef struct SpaprMachineStateNestedGuest {
+ uint32_t pvr_logical;
+} SpaprMachineStateNestedGuest;
+
/* Nested PAPR API related macros */
#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
@@ -20,6 +25,8 @@ typedef struct SpaprMachineStateNested {
#define H_GUEST_CAP_COPY_MEM_BMAP 0
#define H_GUEST_CAP_P9_MODE_BMAP 1
#define H_GUEST_CAP_P10_MODE_BMAP 2
+#define PAPR_NESTED_GUEST_MAX 4096
+#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 32/38] spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (30 preceding siblings ...)
2024-03-12 16:58 ` [PULL 31/38] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 33/38] spapr: nested: Extend nested_ppc_state for nested PAPR API Nicholas Piggin
` (7 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to
create and initialize the specified VCPU resource for the previously
created guest. Each guest can have multiple VCPUs upto max 2048.
All VCPUs for a guest gets deallocated on guest delete.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 62 +++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 2 ++
include/hw/ppc/spapr_nested.h | 8 +++++
3 files changed, 72 insertions(+)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 1f6eb68b93..72bf3dc6d4 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -8,6 +8,7 @@
#include "hw/ppc/spapr_nested.h"
#include "mmu-book3s-v3.h"
#include "cpu-models.h"
+#include "qemu/log.h"
void spapr_nested_reset(SpaprMachineState *spapr)
{
@@ -434,6 +435,16 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
}
}
+static
+SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
+ target_ulong guestid)
+{
+ SpaprMachineStateNestedGuest *guest;
+
+ guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
+ return guest;
+}
+
static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong opcode,
@@ -525,6 +536,7 @@ static void
destroy_guest_helper(gpointer value)
{
struct SpaprMachineStateNestedGuest *guest = value;
+ g_free(guest->vcpus);
g_free(guest);
}
@@ -620,6 +632,54 @@ static target_ulong h_guest_delete(PowerPCCPU *cpu,
return H_SUCCESS;
}
+static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ target_ulong flags = args[0];
+ target_ulong guestid = args[1];
+ target_ulong vcpuid = args[2];
+ SpaprMachineStateNestedGuest *guest;
+
+ if (flags) { /* don't handle any flags for now */
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ guest = spapr_get_nested_guest(spapr, guestid);
+ if (!guest) {
+ return H_P2;
+ }
+
+ if (vcpuid < guest->nr_vcpus) {
+ qemu_log_mask(LOG_UNIMP, "vcpuid " TARGET_FMT_ld " already in use.",
+ vcpuid);
+ return H_IN_USE;
+ }
+ /* linear vcpuid allocation only */
+ assert(vcpuid == guest->nr_vcpus);
+
+ if (guest->nr_vcpus >= PAPR_NESTED_GUEST_VCPU_MAX) {
+ return H_P3;
+ }
+
+ SpaprMachineStateNestedGuestVcpu *vcpus, *curr_vcpu;
+ vcpus = g_try_renew(struct SpaprMachineStateNestedGuestVcpu,
+ guest->vcpus,
+ guest->nr_vcpus + 1);
+ if (!vcpus) {
+ return H_NO_MEM;
+ }
+ guest->vcpus = vcpus;
+ curr_vcpu = &vcpus[guest->nr_vcpus];
+ memset(curr_vcpu, 0, sizeof(SpaprMachineStateNestedGuestVcpu));
+
+ curr_vcpu->enabled = true;
+ guest->nr_vcpus++;
+
+ return H_SUCCESS;
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
@@ -644,6 +704,7 @@ void spapr_register_nested_papr(void)
h_guest_set_capabilities);
spapr_register_hypercall(H_GUEST_CREATE, h_guest_create);
spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete);
+ spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu);
}
void spapr_unregister_nested_papr(void)
@@ -652,6 +713,7 @@ void spapr_unregister_nested_papr(void)
spapr_unregister_hypercall(H_GUEST_SET_CAPABILITIES);
spapr_unregister_hypercall(H_GUEST_CREATE);
spapr_unregister_hypercall(H_GUEST_DELETE);
+ spapr_unregister_hypercall(H_GUEST_CREATE_VCPU);
}
#else
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 13416fc3d7..070135793a 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -365,6 +365,7 @@ struct SpaprMachineState {
#define H_UNSUPPORTED -67
#define H_OVERLAP -68
#define H_STATE -75
+#define H_IN_USE -77
#define H_UNSUPPORTED_FLAG -256
#define H_MULTI_THREADS_ACTIVE -9005
@@ -587,6 +588,7 @@ struct SpaprMachineState {
#define H_GUEST_GET_CAPABILITIES 0x460
#define H_GUEST_SET_CAPABILITIES 0x464
#define H_GUEST_CREATE 0x470
+#define H_GUEST_CREATE_VCPU 0x474
#define H_GUEST_DELETE 0x488
#define MAX_HCALL_OPCODE H_GUEST_DELETE
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 56d43e540b..2ac3076fac 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -14,6 +14,8 @@ typedef struct SpaprMachineStateNested {
typedef struct SpaprMachineStateNestedGuest {
uint32_t pvr_logical;
+ unsigned long nr_vcpus;
+ struct SpaprMachineStateNestedGuestVcpu *vcpus;
} SpaprMachineStateNestedGuest;
/* Nested PAPR API related macros */
@@ -27,6 +29,7 @@ typedef struct SpaprMachineStateNestedGuest {
#define H_GUEST_CAP_P10_MODE_BMAP 2
#define PAPR_NESTED_GUEST_MAX 4096
#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
+#define PAPR_NESTED_GUEST_VCPU_MAX 2048
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
@@ -120,6 +123,11 @@ struct nested_ppc_state {
int64_t tb_offset;
};
+typedef struct SpaprMachineStateNestedGuestVcpu {
+ bool enabled;
+ struct nested_ppc_state state;
+} SpaprMachineStateNestedGuestVcpu;
+
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
typedef struct SpaprMachineState SpaprMachineState;
bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 33/38] spapr: nested: Extend nested_ppc_state for nested PAPR API
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (31 preceding siblings ...)
2024-03-12 16:58 ` [PULL 32/38] spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 34/38] spapr: nested: Initialize the GSB elements lookup table Nicholas Piggin
` (6 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Currently, nested_ppc_state stores a certain set of registers and works
with nested_[load|save]_state() for state transfer as reqd for nested-hv API.
Extending these with additional registers state as reqd for nested PAPR API.
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Suggested-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 106 ++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr_nested.h | 50 ++++++++++++++++
target/ppc/cpu.h | 2 +
3 files changed, 158 insertions(+)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 72bf3dc6d4..6a2ff963c6 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -108,6 +108,7 @@ static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu,
static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
memcpy(save->gpr, env->gpr, sizeof(save->gpr));
@@ -134,6 +135,58 @@ static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
save->pidr = env->spr[SPR_BOOKS_PID];
save->ppr = env->spr[SPR_PPR];
+ if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ save->pvr = env->spr[SPR_PVR];
+ save->amor = env->spr[SPR_AMOR];
+ save->dawr0 = env->spr[SPR_DAWR0];
+ save->dawrx0 = env->spr[SPR_DAWRX0];
+ save->ciabr = env->spr[SPR_CIABR];
+ save->purr = env->spr[SPR_PURR];
+ save->spurr = env->spr[SPR_SPURR];
+ save->ic = env->spr[SPR_IC];
+ save->vtb = env->spr[SPR_VTB];
+ save->hdar = env->spr[SPR_HDAR];
+ save->hdsisr = env->spr[SPR_HDSISR];
+ save->heir = env->spr[SPR_HEIR];
+ save->asdr = env->spr[SPR_ASDR];
+ save->dawr1 = env->spr[SPR_DAWR1];
+ save->dawrx1 = env->spr[SPR_DAWRX1];
+ save->dexcr = env->spr[SPR_DEXCR];
+ save->hdexcr = env->spr[SPR_HDEXCR];
+ save->hashkeyr = env->spr[SPR_HASHKEYR];
+ save->hashpkeyr = env->spr[SPR_HASHPKEYR];
+ memcpy(save->vsr, env->vsr, sizeof(save->vsr));
+ save->ebbhr = env->spr[SPR_EBBHR];
+ save->tar = env->spr[SPR_TAR];
+ save->ebbrr = env->spr[SPR_EBBRR];
+ save->bescr = env->spr[SPR_BESCR];
+ save->iamr = env->spr[SPR_IAMR];
+ save->amr = env->spr[SPR_AMR];
+ save->uamor = env->spr[SPR_UAMOR];
+ save->dscr = env->spr[SPR_DSCR];
+ save->fscr = env->spr[SPR_FSCR];
+ save->pspb = env->spr[SPR_PSPB];
+ save->ctrl = env->spr[SPR_CTRL];
+ save->vrsave = env->spr[SPR_VRSAVE];
+ save->dar = env->spr[SPR_DAR];
+ save->dsisr = env->spr[SPR_DSISR];
+ save->pmc1 = env->spr[SPR_POWER_PMC1];
+ save->pmc2 = env->spr[SPR_POWER_PMC2];
+ save->pmc3 = env->spr[SPR_POWER_PMC3];
+ save->pmc4 = env->spr[SPR_POWER_PMC4];
+ save->pmc5 = env->spr[SPR_POWER_PMC5];
+ save->pmc6 = env->spr[SPR_POWER_PMC6];
+ save->mmcr0 = env->spr[SPR_POWER_MMCR0];
+ save->mmcr1 = env->spr[SPR_POWER_MMCR1];
+ save->mmcr2 = env->spr[SPR_POWER_MMCR2];
+ save->mmcra = env->spr[SPR_POWER_MMCRA];
+ save->sdar = env->spr[SPR_POWER_SDAR];
+ save->siar = env->spr[SPR_POWER_SIAR];
+ save->sier = env->spr[SPR_POWER_SIER];
+ save->vscr = ppc_get_vscr(env);
+ save->fpscr = env->fpscr;
+ }
+
save->tb_offset = env->tb_env->tb_offset;
}
@@ -141,6 +194,7 @@ static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
memcpy(env->gpr, load->gpr, sizeof(env->gpr));
@@ -167,6 +221,58 @@ static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
env->spr[SPR_BOOKS_PID] = load->pidr;
env->spr[SPR_PPR] = load->ppr;
+ if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ env->spr[SPR_PVR] = load->pvr;
+ env->spr[SPR_AMOR] = load->amor;
+ env->spr[SPR_DAWR0] = load->dawr0;
+ env->spr[SPR_DAWRX0] = load->dawrx0;
+ env->spr[SPR_CIABR] = load->ciabr;
+ env->spr[SPR_PURR] = load->purr;
+ env->spr[SPR_SPURR] = load->purr;
+ env->spr[SPR_IC] = load->ic;
+ env->spr[SPR_VTB] = load->vtb;
+ env->spr[SPR_HDAR] = load->hdar;
+ env->spr[SPR_HDSISR] = load->hdsisr;
+ env->spr[SPR_HEIR] = load->heir;
+ env->spr[SPR_ASDR] = load->asdr;
+ env->spr[SPR_DAWR1] = load->dawr1;
+ env->spr[SPR_DAWRX1] = load->dawrx1;
+ env->spr[SPR_DEXCR] = load->dexcr;
+ env->spr[SPR_HDEXCR] = load->hdexcr;
+ env->spr[SPR_HASHKEYR] = load->hashkeyr;
+ env->spr[SPR_HASHPKEYR] = load->hashpkeyr;
+ memcpy(env->vsr, load->vsr, sizeof(env->vsr));
+ env->spr[SPR_EBBHR] = load->ebbhr;
+ env->spr[SPR_TAR] = load->tar;
+ env->spr[SPR_EBBRR] = load->ebbrr;
+ env->spr[SPR_BESCR] = load->bescr;
+ env->spr[SPR_IAMR] = load->iamr;
+ env->spr[SPR_AMR] = load->amr;
+ env->spr[SPR_UAMOR] = load->uamor;
+ env->spr[SPR_DSCR] = load->dscr;
+ env->spr[SPR_FSCR] = load->fscr;
+ env->spr[SPR_PSPB] = load->pspb;
+ env->spr[SPR_CTRL] = load->ctrl;
+ env->spr[SPR_VRSAVE] = load->vrsave;
+ env->spr[SPR_DAR] = load->dar;
+ env->spr[SPR_DSISR] = load->dsisr;
+ env->spr[SPR_POWER_PMC1] = load->pmc1;
+ env->spr[SPR_POWER_PMC2] = load->pmc2;
+ env->spr[SPR_POWER_PMC3] = load->pmc3;
+ env->spr[SPR_POWER_PMC4] = load->pmc4;
+ env->spr[SPR_POWER_PMC5] = load->pmc5;
+ env->spr[SPR_POWER_PMC6] = load->pmc6;
+ env->spr[SPR_POWER_MMCR0] = load->mmcr0;
+ env->spr[SPR_POWER_MMCR1] = load->mmcr1;
+ env->spr[SPR_POWER_MMCR2] = load->mmcr2;
+ env->spr[SPR_POWER_MMCRA] = load->mmcra;
+ env->spr[SPR_POWER_SDAR] = load->sdar;
+ env->spr[SPR_POWER_SIAR] = load->siar;
+ env->spr[SPR_POWER_SIER] = load->sier;
+ ppc_store_vscr(env, load->vscr);
+ ppc_store_fpscr(env, load->fpscr);
+ }
+
env->tb_env->tb_offset = load->tb_offset;
/*
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 2ac3076fac..d232014ccb 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -7,6 +7,7 @@ typedef struct SpaprMachineStateNested {
uint64_t ptcr;
uint8_t api;
#define NESTED_API_KVM_HV 1
+#define NESTED_API_PAPR 2
bool capabilities_set;
uint32_t pvr_base;
GHashTable *guests;
@@ -121,6 +122,55 @@ struct nested_ppc_state {
uint64_t ppr;
int64_t tb_offset;
+ /* Nested PAPR API */
+ uint64_t amor;
+ uint64_t dawr0;
+ uint64_t dawrx0;
+ uint64_t ciabr;
+ uint64_t purr;
+ uint64_t spurr;
+ uint64_t ic;
+ uint64_t vtb;
+ uint64_t hdar;
+ uint64_t hdsisr;
+ uint64_t heir;
+ uint64_t asdr;
+ uint64_t dawr1;
+ uint64_t dawrx1;
+ uint64_t dexcr;
+ uint64_t hdexcr;
+ uint64_t hashkeyr;
+ uint64_t hashpkeyr;
+ ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
+ uint64_t ebbhr;
+ uint64_t tar;
+ uint64_t ebbrr;
+ uint64_t bescr;
+ uint64_t iamr;
+ uint64_t amr;
+ uint64_t uamor;
+ uint64_t dscr;
+ uint64_t fscr;
+ uint64_t pspb;
+ uint64_t ctrl;
+ uint64_t vrsave;
+ uint64_t dar;
+ uint64_t dsisr;
+ uint64_t pmc1;
+ uint64_t pmc2;
+ uint64_t pmc3;
+ uint64_t pmc4;
+ uint64_t pmc5;
+ uint64_t pmc6;
+ uint64_t mmcr0;
+ uint64_t mmcr1;
+ uint64_t mmcr2;
+ uint64_t mmcra;
+ uint64_t sdar;
+ uint64_t siar;
+ uint64_t sier;
+ uint32_t vscr;
+ uint64_t fpscr;
};
typedef struct SpaprMachineStateNestedGuestVcpu {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7c48b2eadb..be5f74a7cd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1755,9 +1755,11 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_PSPB (0x09F)
#define SPR_DPDES (0x0B0)
#define SPR_DAWR0 (0x0B4)
+#define SPR_DAWR1 (0x0B5)
#define SPR_RPR (0x0BA)
#define SPR_CIABR (0x0BB)
#define SPR_DAWRX0 (0x0BC)
+#define SPR_DAWRX1 (0x0BD)
#define SPR_HFSCR (0x0BE)
#define SPR_VRSAVE (0x100)
#define SPR_USPRG0 (0x100)
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 34/38] spapr: nested: Initialize the GSB elements lookup table.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (32 preceding siblings ...)
2024-03-12 16:58 ` [PULL 33/38] spapr: nested: Extend nested_ppc_state for nested PAPR API Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls Nicholas Piggin
` (5 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling, Shivaprasad G Bhat,
Amit Machhiwal
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Nested PAPR API provides a standard Guest State Buffer (GSB) format
with unique IDs for each guest state element for which get/set state is
supported by the API. Some of the elements are read-only and/or guest-wide.
Introducing additional required GSB elements and helper routines for state
exchange of each of the nested guest state elements for which get/set state
should be supported by the API.
[amachhiw: set the PCR whenever logical PVR is set]
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Signed-off-by: Amit Machhiwal <amachhiw@linux.vnet.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 487 +++++++++++++++++++++++++++++++++-
include/hw/ppc/spapr_nested.h | 313 ++++++++++++++++++++++
2 files changed, 798 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 6a2ff963c6..cd7fa90350 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -19,6 +19,7 @@ void spapr_nested_reset(SpaprMachineState *spapr)
} else {
spapr->nested.api = 0;
spapr->nested.capabilities_set = false;
+ spapr_nested_gsb_init();
}
}
@@ -136,7 +137,6 @@ static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
save->ppr = env->spr[SPR_PPR];
if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
- save->pvr = env->spr[SPR_PVR];
save->amor = env->spr[SPR_AMOR];
save->dawr0 = env->spr[SPR_DAWR0];
save->dawrx0 = env->spr[SPR_DAWRX0];
@@ -222,7 +222,6 @@ static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
env->spr[SPR_PPR] = load->ppr;
if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
- env->spr[SPR_PVR] = load->pvr;
env->spr[SPR_AMOR] = load->amor;
env->spr[SPR_DAWR0] = load->dawr0;
env->spr[SPR_DAWRX0] = load->dawrx0;
@@ -551,6 +550,485 @@ SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
return guest;
}
+static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid, bool inoutbuf)
+{
+ struct SpaprMachineStateNestedGuestVcpu *vcpu;
+ /*
+ * Perform sanity checks for the provided vcpuid of a guest.
+ * For now, ensure its valid, allocated and enabled for use.
+ */
+
+ if (vcpuid >= PAPR_NESTED_GUEST_VCPU_MAX) {
+ return false;
+ }
+
+ if (!(vcpuid < guest->nr_vcpus)) {
+ return false;
+ }
+
+ vcpu = &guest->vcpus[vcpuid];
+ if (!vcpu->enabled) {
+ return false;
+ }
+
+ if (!inoutbuf) {
+ return true;
+ }
+
+ /* Check to see if the in/out buffers are registered */
+ if (vcpu->runbufin.addr && vcpu->runbufout.addr) {
+ return true;
+ }
+
+ return false;
+}
+
+static void *get_vcpu_state_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ assert(spapr_nested_vcpu_check(guest, vcpuid, false));
+ return &guest->vcpus[vcpuid].state;
+}
+
+static void *get_vcpu_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ assert(spapr_nested_vcpu_check(guest, vcpuid, false));
+ return &guest->vcpus[vcpuid];
+}
+
+static void *get_guest_ptr(SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid)
+{
+ return guest; /* for GSBE_NESTED */
+}
+
+/*
+ * set=1 means the L1 is trying to set some state
+ * set=0 means the L1 is trying to get some state
+ */
+static void copy_state_8to8(void *a, void *b, bool set)
+{
+ /* set takes from the Big endian element_buf and sets internal buffer */
+
+ if (set) {
+ *(uint64_t *)a = be64_to_cpu(*(uint64_t *)b);
+ } else {
+ *(uint64_t *)b = cpu_to_be64(*(uint64_t *)a);
+ }
+}
+
+static void copy_state_4to4(void *a, void *b, bool set)
+{
+ if (set) {
+ *(uint32_t *)a = be32_to_cpu(*(uint32_t *)b);
+ } else {
+ *(uint32_t *)b = cpu_to_be32(*((uint32_t *)a));
+ }
+}
+
+static void copy_state_16to16(void *a, void *b, bool set)
+{
+ uint64_t *src, *dst;
+
+ if (set) {
+ src = b;
+ dst = a;
+
+ dst[1] = be64_to_cpu(src[0]);
+ dst[0] = be64_to_cpu(src[1]);
+ } else {
+ src = a;
+ dst = b;
+
+ dst[1] = cpu_to_be64(src[0]);
+ dst[0] = cpu_to_be64(src[1]);
+ }
+}
+
+static void copy_state_4to8(void *a, void *b, bool set)
+{
+ if (set) {
+ *(uint64_t *)a = (uint64_t) be32_to_cpu(*(uint32_t *)b);
+ } else {
+ *(uint32_t *)b = cpu_to_be32((uint32_t) (*((uint64_t *)a)));
+ }
+}
+
+static void copy_state_pagetbl(void *a, void *b, bool set)
+{
+ uint64_t *pagetbl;
+ uint64_t *buf; /* 3 double words */
+ uint64_t rts;
+
+ assert(set);
+
+ pagetbl = a;
+ buf = b;
+
+ *pagetbl = be64_to_cpu(buf[0]);
+ /* as per ISA section 6.7.6.1 */
+ *pagetbl |= PATE0_HR; /* Host Radix bit is 1 */
+
+ /* RTS */
+ rts = be64_to_cpu(buf[1]);
+ assert(rts == 52);
+ rts = rts - 31; /* since radix tree size = 2^(RTS+31) */
+ *pagetbl |= ((rts & 0x7) << 5); /* RTS2 is bit 56:58 */
+ *pagetbl |= (((rts >> 3) & 0x3) << 61); /* RTS1 is bit 1:2 */
+
+ /* RPDS {Size = 2^(RPDS+3) , RPDS >=5} */
+ *pagetbl |= 63 - clz64(be64_to_cpu(buf[2])) - 3;
+}
+
+static void copy_state_proctbl(void *a, void *b, bool set)
+{
+ uint64_t *proctbl;
+ uint64_t *buf; /* 2 double words */
+
+ assert(set);
+
+ proctbl = a;
+ buf = b;
+ /* PRTB: Process Table Base */
+ *proctbl = be64_to_cpu(buf[0]);
+ /* PRTS: Process Table Size = 2^(12+PRTS) */
+ if (be64_to_cpu(buf[1]) == (1ULL << 12)) {
+ *proctbl |= 0;
+ } else if (be64_to_cpu(buf[1]) == (1ULL << 24)) {
+ *proctbl |= 12;
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void copy_state_runbuf(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 2 double words */
+ struct SpaprMachineStateNestedGuestVcpuRunBuf *runbuf;
+
+ assert(set);
+
+ runbuf = a;
+ buf = b;
+
+ runbuf->addr = be64_to_cpu(buf[0]);
+ assert(runbuf->addr);
+
+ /* per spec */
+ assert(be64_to_cpu(buf[1]) <= 16384);
+
+ /*
+ * This will also hit in the input buffer but should be fine for
+ * now. If not we can split this function.
+ */
+ assert(be64_to_cpu(buf[1]) >= VCPU_OUT_BUF_MIN_SZ);
+
+ runbuf->size = be64_to_cpu(buf[1]);
+}
+
+/* tell the L1 how big we want the output vcpu run buffer */
+static void out_buf_min_size(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 1 double word */
+
+ assert(!set);
+
+ buf = b;
+
+ buf[0] = cpu_to_be64(VCPU_OUT_BUF_MIN_SZ);
+}
+
+static void copy_logical_pvr(void *a, void *b, bool set)
+{
+ SpaprMachineStateNestedGuest *guest;
+ uint32_t *buf; /* 1 word */
+ uint32_t *pvr_logical_ptr;
+ uint32_t pvr_logical;
+ target_ulong pcr = 0;
+
+ pvr_logical_ptr = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be32(*pvr_logical_ptr);
+ return;
+ }
+
+ pvr_logical = be32_to_cpu(buf[0]);
+
+ *pvr_logical_ptr = pvr_logical;
+
+ if (*pvr_logical_ptr) {
+ switch (*pvr_logical_ptr) {
+ case CPU_POWERPC_LOGICAL_3_10:
+ pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00;
+ break;
+ case CPU_POWERPC_LOGICAL_3_00:
+ pcr = PCR_COMPAT_3_00;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Could not set PCR for LPVR=0x%08x\n",
+ *pvr_logical_ptr);
+ return;
+ }
+ }
+
+ guest = container_of(pvr_logical_ptr,
+ struct SpaprMachineStateNestedGuest,
+ pvr_logical);
+ for (int i = 0; i < guest->nr_vcpus; i++) {
+ guest->vcpus[i].state.pcr = ~pcr | HVMASK_PCR;
+ }
+}
+
+static void copy_tb_offset(void *a, void *b, bool set)
+{
+ SpaprMachineStateNestedGuest *guest;
+ uint64_t *buf; /* 1 double word */
+ uint64_t *tb_offset_ptr;
+ uint64_t tb_offset;
+
+ tb_offset_ptr = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be64(*tb_offset_ptr);
+ return;
+ }
+
+ tb_offset = be64_to_cpu(buf[0]);
+ /* need to copy this to the individual tb_offset for each vcpu */
+ guest = container_of(tb_offset_ptr,
+ struct SpaprMachineStateNestedGuest,
+ tb_offset);
+ for (int i = 0; i < guest->nr_vcpus; i++) {
+ guest->vcpus[i].tb_offset = tb_offset;
+ }
+}
+
+static void copy_state_hdecr(void *a, void *b, bool set)
+{
+ uint64_t *buf; /* 1 double word */
+ uint64_t *hdecr_expiry_tb;
+
+ hdecr_expiry_tb = a;
+ buf = b;
+
+ if (!set) {
+ buf[0] = cpu_to_be64(*hdecr_expiry_tb);
+ return;
+ }
+
+ *hdecr_expiry_tb = be64_to_cpu(buf[0]);
+}
+
+struct guest_state_element_type guest_state_element_types[] = {
+ GUEST_STATE_ELEMENT_NOP(GSB_HV_VCPU_IGNORED_ID, 0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR0, gpr[0]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR1, gpr[1]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR2, gpr[2]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR3, gpr[3]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR4, gpr[4]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR5, gpr[5]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR6, gpr[6]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR7, gpr[7]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR8, gpr[8]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR9, gpr[9]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR10, gpr[10]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR11, gpr[11]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR12, gpr[12]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR13, gpr[13]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR14, gpr[14]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR15, gpr[15]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR16, gpr[16]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR17, gpr[17]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR18, gpr[18]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR19, gpr[19]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR20, gpr[20]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR21, gpr[21]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR22, gpr[22]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR23, gpr[23]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR24, gpr[24]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR25, gpr[25]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR26, gpr[26]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR27, gpr[27]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR28, gpr[28]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR29, gpr[29]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR30, gpr[30]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR31, gpr[31]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_NIA, nip),
+ GSE_ENV_DWM(GSB_VCPU_SPR_MSR, msr, HVMASK_MSR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTR, ctr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_LR, lr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_XER, xer),
+ GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_CR, cr),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_MMCR3),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER2),
+ GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER3),
+ GUEST_STATE_ELEMENT_NOP_W(GSB_VCPU_SPR_WORT),
+ GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMOR, amor),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HFSCR, hfscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR0, dawr0),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX0, dawrx0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CIABR, ciabr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PURR, purr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPURR, spurr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IC, ic),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_VTB, vtb),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HDAR, hdar),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HDSISR, hdsisr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HEIR, heir),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_ASDR, asdr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR0, srr0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR1, srr1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG0, sprg0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG1, sprg1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG2, sprg2),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG3, sprg3),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PIDR, pidr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CFAR, cfar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PPR, ppr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR1, dawr1),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX1, dawrx1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DEXCR, dexcr),
+ GSE_ENV_DWM(GSB_VCPU_SPR_HDEXCR, hdexcr, HVMASK_HDEXCR),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHKEYR, hashkeyr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHPKEYR, hashpkeyr),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR0, vsr[0]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR1, vsr[1]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR2, vsr[2]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR3, vsr[3]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR4, vsr[4]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR5, vsr[5]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR6, vsr[6]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR7, vsr[7]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR8, vsr[8]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR9, vsr[9]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR10, vsr[10]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR11, vsr[11]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR12, vsr[12]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR13, vsr[13]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR14, vsr[14]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR15, vsr[15]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR16, vsr[16]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR17, vsr[17]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR18, vsr[18]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR19, vsr[19]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR20, vsr[20]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR21, vsr[21]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR22, vsr[22]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR23, vsr[23]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR24, vsr[24]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR25, vsr[25]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR26, vsr[26]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR27, vsr[27]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR28, vsr[28]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR29, vsr[29]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR30, vsr[30]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR31, vsr[31]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR32, vsr[32]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR33, vsr[33]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR34, vsr[34]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR35, vsr[35]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR36, vsr[36]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR37, vsr[37]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR38, vsr[38]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR39, vsr[39]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR40, vsr[40]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR41, vsr[41]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR42, vsr[42]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR43, vsr[43]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR44, vsr[44]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR45, vsr[45]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR46, vsr[46]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR47, vsr[47]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR48, vsr[48]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR49, vsr[49]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR50, vsr[50]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR51, vsr[51]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR52, vsr[52]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR53, vsr[53]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR54, vsr[54]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR55, vsr[55]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR56, vsr[56]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR57, vsr[57]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR58, vsr[58]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR59, vsr[59]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR60, vsr[60]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR61, vsr[61]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR62, vsr[62]),
+ GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR63, vsr[63]),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBHR, ebbhr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_TAR, tar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBRR, ebbrr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_BESCR, bescr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IAMR, iamr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_UAMOR, uamor),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DSCR, dscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC1, pmc1),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC2, pmc2),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC3, pmc3),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC4, pmc4),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC5, pmc5),
+ GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC6, pmc6),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR0, mmcr0),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR1, mmcr1),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR2, mmcr2),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCRA, mmcra),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SDAR , sdar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIAR , siar),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIER , sier),
+ GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_VSCR, vscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr),
+ GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_DEC_EXPIRE_TB, dec_expiry_tb),
+ GSBE_NESTED(GSB_PART_SCOPED_PAGETBL, 0x18, parttbl[0], copy_state_pagetbl),
+ GSBE_NESTED(GSB_PROCESS_TBL, 0x10, parttbl[1], copy_state_proctbl),
+ GSBE_NESTED(GSB_VCPU_LPVR, 0x4, pvr_logical, copy_logical_pvr),
+ GSBE_NESTED_MSK(GSB_TB_OFFSET, 0x8, tb_offset, copy_tb_offset,
+ HVMASK_TB_OFFSET),
+ GSBE_NESTED_VCPU(GSB_VCPU_IN_BUFFER, 0x10, runbufin, copy_state_runbuf),
+ GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUFFER, 0x10, runbufout, copy_state_runbuf),
+ GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUF_MIN_SZ, 0x8, runbufout, out_buf_min_size),
+ GSBE_NESTED_VCPU(GSB_VCPU_HDEC_EXPIRY_TB, 0x8, hdecr_expiry_tb,
+ copy_state_hdecr)
+};
+
+void spapr_nested_gsb_init(void)
+{
+ struct guest_state_element_type *type;
+
+ /* Init the guest state elements lookup table, flags for now */
+ for (int i = 0; i < ARRAY_SIZE(guest_state_element_types); i++) {
+ type = &guest_state_element_types[i];
+
+ assert(type->id <= GSB_LAST);
+ if (type->id >= GSB_VCPU_SPR_HDAR)
+ /* 0xf000 - 0xf005 Thread + RO */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY;
+ else if (type->id >= GSB_VCPU_IN_BUFFER)
+ /* 0x0c00 - 0xf000 Thread + RW */
+ type->flags = 0;
+ else if (type->id >= GSB_VCPU_LPVR)
+ /* 0x0003 - 0x0bff Guest + RW */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
+ else if (type->id >= GSB_HV_VCPU_STATE_SIZE)
+ /* 0x0001 - 0x0002 Guest + RO */
+ type->flags = GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY |
+ GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE;
+ }
+}
+
static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong opcode,
@@ -854,4 +1332,9 @@ void spapr_unregister_nested_papr(void)
/* DO NOTHING */
}
+void spapr_nested_gsb_init(void)
+{
+ /* DO NOTHING */
+}
+
#endif
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index d232014ccb..3da02df7bb 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -3,6 +3,191 @@
#include "target/ppc/cpu.h"
+/* Guest State Buffer Element IDs */
+#define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
+#define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
+#define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
+#define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
+#define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
+#define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
+#define GSB_PROCESS_TBL 0x0006 /* Process Table */
+ /* RESERVED 0x0007 - 0x0BFF */
+#define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */
+#define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */
+#define GSB_VCPU_VPA 0x0C02 /* HRA to Guest VCPU VPA */
+ /* RESERVED 0x0C03 - 0x0FFF */
+#define GSB_VCPU_GPR0 0x1000
+#define GSB_VCPU_GPR1 0x1001
+#define GSB_VCPU_GPR2 0x1002
+#define GSB_VCPU_GPR3 0x1003
+#define GSB_VCPU_GPR4 0x1004
+#define GSB_VCPU_GPR5 0x1005
+#define GSB_VCPU_GPR6 0x1006
+#define GSB_VCPU_GPR7 0x1007
+#define GSB_VCPU_GPR8 0x1008
+#define GSB_VCPU_GPR9 0x1009
+#define GSB_VCPU_GPR10 0x100A
+#define GSB_VCPU_GPR11 0x100B
+#define GSB_VCPU_GPR12 0x100C
+#define GSB_VCPU_GPR13 0x100D
+#define GSB_VCPU_GPR14 0x100E
+#define GSB_VCPU_GPR15 0x100F
+#define GSB_VCPU_GPR16 0x1010
+#define GSB_VCPU_GPR17 0x1011
+#define GSB_VCPU_GPR18 0x1012
+#define GSB_VCPU_GPR19 0x1013
+#define GSB_VCPU_GPR20 0x1014
+#define GSB_VCPU_GPR21 0x1015
+#define GSB_VCPU_GPR22 0x1016
+#define GSB_VCPU_GPR23 0x1017
+#define GSB_VCPU_GPR24 0x1018
+#define GSB_VCPU_GPR25 0x1019
+#define GSB_VCPU_GPR26 0x101A
+#define GSB_VCPU_GPR27 0x101B
+#define GSB_VCPU_GPR28 0x101C
+#define GSB_VCPU_GPR29 0x101D
+#define GSB_VCPU_GPR30 0x101E
+#define GSB_VCPU_GPR31 0x101F
+#define GSB_VCPU_HDEC_EXPIRY_TB 0x1020
+#define GSB_VCPU_SPR_NIA 0x1021
+#define GSB_VCPU_SPR_MSR 0x1022
+#define GSB_VCPU_SPR_LR 0x1023
+#define GSB_VCPU_SPR_XER 0x1024
+#define GSB_VCPU_SPR_CTR 0x1025
+#define GSB_VCPU_SPR_CFAR 0x1026
+#define GSB_VCPU_SPR_SRR0 0x1027
+#define GSB_VCPU_SPR_SRR1 0x1028
+#define GSB_VCPU_SPR_DAR 0x1029
+#define GSB_VCPU_DEC_EXPIRE_TB 0x102A
+#define GSB_VCPU_SPR_VTB 0x102B
+#define GSB_VCPU_SPR_LPCR 0x102C
+#define GSB_VCPU_SPR_HFSCR 0x102D
+#define GSB_VCPU_SPR_FSCR 0x102E
+#define GSB_VCPU_SPR_FPSCR 0x102F
+#define GSB_VCPU_SPR_DAWR0 0x1030
+#define GSB_VCPU_SPR_DAWR1 0x1031
+#define GSB_VCPU_SPR_CIABR 0x1032
+#define GSB_VCPU_SPR_PURR 0x1033
+#define GSB_VCPU_SPR_SPURR 0x1034
+#define GSB_VCPU_SPR_IC 0x1035
+#define GSB_VCPU_SPR_SPRG0 0x1036
+#define GSB_VCPU_SPR_SPRG1 0x1037
+#define GSB_VCPU_SPR_SPRG2 0x1038
+#define GSB_VCPU_SPR_SPRG3 0x1039
+#define GSB_VCPU_SPR_PPR 0x103A
+#define GSB_VCPU_SPR_MMCR0 0x103B
+#define GSB_VCPU_SPR_MMCR1 0x103C
+#define GSB_VCPU_SPR_MMCR2 0x103D
+#define GSB_VCPU_SPR_MMCR3 0x103E
+#define GSB_VCPU_SPR_MMCRA 0x103F
+#define GSB_VCPU_SPR_SIER 0x1040
+#define GSB_VCPU_SPR_SIER2 0x1041
+#define GSB_VCPU_SPR_SIER3 0x1042
+#define GSB_VCPU_SPR_BESCR 0x1043
+#define GSB_VCPU_SPR_EBBHR 0x1044
+#define GSB_VCPU_SPR_EBBRR 0x1045
+#define GSB_VCPU_SPR_AMR 0x1046
+#define GSB_VCPU_SPR_IAMR 0x1047
+#define GSB_VCPU_SPR_AMOR 0x1048
+#define GSB_VCPU_SPR_UAMOR 0x1049
+#define GSB_VCPU_SPR_SDAR 0x104A
+#define GSB_VCPU_SPR_SIAR 0x104B
+#define GSB_VCPU_SPR_DSCR 0x104C
+#define GSB_VCPU_SPR_TAR 0x104D
+#define GSB_VCPU_SPR_DEXCR 0x104E
+#define GSB_VCPU_SPR_HDEXCR 0x104F
+#define GSB_VCPU_SPR_HASHKEYR 0x1050
+#define GSB_VCPU_SPR_HASHPKEYR 0x1051
+#define GSB_VCPU_SPR_CTRL 0x1052
+ /* RESERVED 0x1053 - 0x1FFF */
+#define GSB_VCPU_SPR_CR 0x2000
+#define GSB_VCPU_SPR_PIDR 0x2001
+#define GSB_VCPU_SPR_DSISR 0x2002
+#define GSB_VCPU_SPR_VSCR 0x2003
+#define GSB_VCPU_SPR_VRSAVE 0x2004
+#define GSB_VCPU_SPR_DAWRX0 0x2005
+#define GSB_VCPU_SPR_DAWRX1 0x2006
+#define GSB_VCPU_SPR_PMC1 0x2007
+#define GSB_VCPU_SPR_PMC2 0x2008
+#define GSB_VCPU_SPR_PMC3 0x2009
+#define GSB_VCPU_SPR_PMC4 0x200A
+#define GSB_VCPU_SPR_PMC5 0x200B
+#define GSB_VCPU_SPR_PMC6 0x200C
+#define GSB_VCPU_SPR_WORT 0x200D
+#define GSB_VCPU_SPR_PSPB 0x200E
+ /* RESERVED 0x200F - 0x2FFF */
+#define GSB_VCPU_SPR_VSR0 0x3000
+#define GSB_VCPU_SPR_VSR1 0x3001
+#define GSB_VCPU_SPR_VSR2 0x3002
+#define GSB_VCPU_SPR_VSR3 0x3003
+#define GSB_VCPU_SPR_VSR4 0x3004
+#define GSB_VCPU_SPR_VSR5 0x3005
+#define GSB_VCPU_SPR_VSR6 0x3006
+#define GSB_VCPU_SPR_VSR7 0x3007
+#define GSB_VCPU_SPR_VSR8 0x3008
+#define GSB_VCPU_SPR_VSR9 0x3009
+#define GSB_VCPU_SPR_VSR10 0x300A
+#define GSB_VCPU_SPR_VSR11 0x300B
+#define GSB_VCPU_SPR_VSR12 0x300C
+#define GSB_VCPU_SPR_VSR13 0x300D
+#define GSB_VCPU_SPR_VSR14 0x300E
+#define GSB_VCPU_SPR_VSR15 0x300F
+#define GSB_VCPU_SPR_VSR16 0x3010
+#define GSB_VCPU_SPR_VSR17 0x3011
+#define GSB_VCPU_SPR_VSR18 0x3012
+#define GSB_VCPU_SPR_VSR19 0x3013
+#define GSB_VCPU_SPR_VSR20 0x3014
+#define GSB_VCPU_SPR_VSR21 0x3015
+#define GSB_VCPU_SPR_VSR22 0x3016
+#define GSB_VCPU_SPR_VSR23 0x3017
+#define GSB_VCPU_SPR_VSR24 0x3018
+#define GSB_VCPU_SPR_VSR25 0x3019
+#define GSB_VCPU_SPR_VSR26 0x301A
+#define GSB_VCPU_SPR_VSR27 0x301B
+#define GSB_VCPU_SPR_VSR28 0x301C
+#define GSB_VCPU_SPR_VSR29 0x301D
+#define GSB_VCPU_SPR_VSR30 0x301E
+#define GSB_VCPU_SPR_VSR31 0x301F
+#define GSB_VCPU_SPR_VSR32 0x3020
+#define GSB_VCPU_SPR_VSR33 0x3021
+#define GSB_VCPU_SPR_VSR34 0x3022
+#define GSB_VCPU_SPR_VSR35 0x3023
+#define GSB_VCPU_SPR_VSR36 0x3024
+#define GSB_VCPU_SPR_VSR37 0x3025
+#define GSB_VCPU_SPR_VSR38 0x3026
+#define GSB_VCPU_SPR_VSR39 0x3027
+#define GSB_VCPU_SPR_VSR40 0x3028
+#define GSB_VCPU_SPR_VSR41 0x3029
+#define GSB_VCPU_SPR_VSR42 0x302A
+#define GSB_VCPU_SPR_VSR43 0x302B
+#define GSB_VCPU_SPR_VSR44 0x302C
+#define GSB_VCPU_SPR_VSR45 0x302D
+#define GSB_VCPU_SPR_VSR46 0x302E
+#define GSB_VCPU_SPR_VSR47 0x302F
+#define GSB_VCPU_SPR_VSR48 0x3030
+#define GSB_VCPU_SPR_VSR49 0x3031
+#define GSB_VCPU_SPR_VSR50 0x3032
+#define GSB_VCPU_SPR_VSR51 0x3033
+#define GSB_VCPU_SPR_VSR52 0x3034
+#define GSB_VCPU_SPR_VSR53 0x3035
+#define GSB_VCPU_SPR_VSR54 0x3036
+#define GSB_VCPU_SPR_VSR55 0x3037
+#define GSB_VCPU_SPR_VSR56 0x3038
+#define GSB_VCPU_SPR_VSR57 0x3039
+#define GSB_VCPU_SPR_VSR58 0x303A
+#define GSB_VCPU_SPR_VSR59 0x303B
+#define GSB_VCPU_SPR_VSR60 0x303C
+#define GSB_VCPU_SPR_VSR61 0x303D
+#define GSB_VCPU_SPR_VSR62 0x303E
+#define GSB_VCPU_SPR_VSR63 0x303F
+ /* RESERVED 0x3040 - 0xEFFF */
+#define GSB_VCPU_SPR_HDAR 0xF000
+#define GSB_VCPU_SPR_HDSISR 0xF001
+#define GSB_VCPU_SPR_HEIR 0xF002
+#define GSB_VCPU_SPR_ASDR 0xF003
+/* End of list of Guest State Buffer Element IDs */
+#define GSB_LAST GSB_VCPU_SPR_ASDR
+
typedef struct SpaprMachineStateNested {
uint64_t ptcr;
uint8_t api;
@@ -16,6 +201,8 @@ typedef struct SpaprMachineStateNested {
typedef struct SpaprMachineStateNestedGuest {
uint32_t pvr_logical;
unsigned long nr_vcpus;
+ uint64_t parttbl[2];
+ uint64_t tb_offset;
struct SpaprMachineStateNestedGuestVcpu *vcpus;
} SpaprMachineStateNestedGuest;
@@ -31,6 +218,109 @@ typedef struct SpaprMachineStateNestedGuest {
#define PAPR_NESTED_GUEST_MAX 4096
#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
#define PAPR_NESTED_GUEST_VCPU_MAX 2048
+#define VCPU_OUT_BUF_MIN_SZ 0x80ULL
+#define HVMASK_DEFAULT 0xffffffffffffffff
+#define HVMASK_LPCR 0x0070000003820800
+#define HVMASK_MSR 0xEBFFFFFFFFBFEFFF
+#define HVMASK_HDEXCR 0x00000000FFFFFFFF
+#define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF
+
+/*
+ * As per ISA v3.1B, following bits are reserved:
+ * 0:2
+ * 4:57 (ISA mentions bit 58 as well but it should be used for P10)
+ * 61:63 (hence, haven't included PCR bits for v2.06 and v2.05
+ * in LOW BITS)
+ */
+#define PCR_LOW_BITS (PCR_COMPAT_3_10 | PCR_COMPAT_3_00)
+#define HVMASK_PCR (~PCR_LOW_BITS)
+
+#define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = ptr, \
+ .offset = offsetof(struct s, f), \
+ .copy = (c) \
+}
+
+#define GSBE_NESTED(i, sz, f, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_guest_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GSBE_NESTED_MSK(i, sz, f, c, m) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_guest_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
+ .copy = (c), \
+ .mask = (m) \
+}
+
+#define GSBE_NESTED_VCPU(i, sz, f, c) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = get_vcpu_ptr, \
+ .offset = offsetof(struct SpaprMachineStateNestedGuestVcpu, f),\
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GUEST_STATE_ELEMENT_NOP(i, sz) { \
+ .id = (i), \
+ .size = (sz), \
+ .location = NULL, \
+ .offset = 0, \
+ .copy = NULL, \
+ .mask = HVMASK_DEFAULT \
+}
+
+#define GUEST_STATE_ELEMENT_NOP_DW(i) \
+ GUEST_STATE_ELEMENT_NOP(i, 8)
+#define GUEST_STATE_ELEMENT_NOP_W(i) \
+ GUEST_STATE_ELEMENT_NOP(i, 4)
+
+#define GUEST_STATE_ELEMENT_BASE(i, s, c) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = 0, \
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+ }
+
+#define GUEST_STATE_ELEMENT_OFF(i, s, f, c) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = offsetof(struct nested_ppc_state, f), \
+ .copy = (c), \
+ .mask = HVMASK_DEFAULT \
+ }
+
+#define GUEST_STATE_ELEMENT_MSK(i, s, f, c, m) { \
+ .id = (i), \
+ .size = (s), \
+ .location = get_vcpu_state_ptr, \
+ .offset = offsetof(struct nested_ppc_state, f), \
+ .copy = (c), \
+ .mask = (m) \
+ }
+
+#define GUEST_STATE_ELEMENT_ENV_QW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 16, f, copy_state_16to16)
+#define GUEST_STATE_ELEMENT_ENV_DW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 8, f, copy_state_8to8)
+#define GUEST_STATE_ELEMENT_ENV_W(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to8)
+#define GUEST_STATE_ELEMENT_ENV_WW(i, f) \
+ GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to4)
+#define GSE_ENV_DWM(i, f, m) \
+ GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m)
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
@@ -171,16 +461,39 @@ struct nested_ppc_state {
uint64_t sier;
uint32_t vscr;
uint64_t fpscr;
+ int64_t dec_expiry_tb;
+};
+
+struct SpaprMachineStateNestedGuestVcpuRunBuf {
+ uint64_t addr;
+ uint64_t size;
};
typedef struct SpaprMachineStateNestedGuestVcpu {
bool enabled;
struct nested_ppc_state state;
+ struct SpaprMachineStateNestedGuestVcpuRunBuf runbufin;
+ struct SpaprMachineStateNestedGuestVcpuRunBuf runbufout;
+ int64_t tb_offset;
+ uint64_t hdecr_expiry_tb;
} SpaprMachineStateNestedGuestVcpu;
+struct guest_state_element_type {
+ uint16_t id;
+ int size;
+#define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1
+#define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x2
+ uint16_t flags;
+ void *(*location)(SpaprMachineStateNestedGuest *, target_ulong);
+ size_t offset;
+ void (*copy)(void *, void *, bool);
+ uint64_t mask;
+};
+
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
typedef struct SpaprMachineState SpaprMachineState;
bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry);
uint8_t spapr_nested_api(SpaprMachineState *spapr);
+void spapr_nested_gsb_init(void);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (33 preceding siblings ...)
2024-03-12 16:58 ` [PULL 34/38] spapr: nested: Initialize the GSB elements lookup table Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-26 16:02 ` Peter Maydell
2024-03-12 16:58 ` [PULL 36/38] spapr: nested: Use correct source for parttbl info for nested PAPR API Nicholas Piggin
` (4 subsequent siblings)
39 siblings, 1 reply; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which is used to get state of a nested guest or
a guest VCPU. The value field for each element in the request is
destination to be updated to reflect current state on success.
- H_GUEST_SET_STATE which is used to modify the state of a guest or
a guest VCPU. On success, guest (or its VCPU) state shall be
updated as per the value field for the requested element(s).
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 268 ++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 3 +
include/hw/ppc/spapr_nested.h | 23 +++
3 files changed, 294 insertions(+)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index cd7fa90350..cea282926f 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -1029,6 +1029,140 @@ void spapr_nested_gsb_init(void)
}
}
+static struct guest_state_element *guest_state_element_next(
+ struct guest_state_element *element,
+ int64_t *len,
+ int64_t *num_elements)
+{
+ uint16_t size;
+
+ /* size is of element->value[] only. Not whole guest_state_element */
+ size = be16_to_cpu(element->size);
+
+ if (len) {
+ *len -= size + offsetof(struct guest_state_element, value);
+ }
+
+ if (num_elements) {
+ *num_elements -= 1;
+ }
+
+ return (struct guest_state_element *)(element->value + size);
+}
+
+static
+struct guest_state_element_type *guest_state_element_type_find(uint16_t id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(guest_state_element_types); i++)
+ if (id == guest_state_element_types[i].id) {
+ return &guest_state_element_types[i];
+ }
+
+ return NULL;
+}
+
+static void log_element(struct guest_state_element *element,
+ struct guest_state_request *gsr)
+{
+ qemu_log_mask(LOG_GUEST_ERROR, "h_guest_%s_state id:0x%04x size:0x%04x",
+ gsr->flags & GUEST_STATE_REQUEST_SET ? "set" : "get",
+ be16_to_cpu(element->id), be16_to_cpu(element->size));
+ qemu_log_mask(LOG_GUEST_ERROR, "buf:0x%016"PRIx64" ...\n",
+ be64_to_cpu(*(uint64_t *)element->value));
+}
+
+static bool guest_state_request_check(struct guest_state_request *gsr)
+{
+ int64_t num_elements, len = gsr->len;
+ struct guest_state_buffer *gsb = gsr->gsb;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ uint16_t id, size;
+
+ /* gsb->num_elements = 0 == 32 bits long */
+ assert(len >= 4);
+
+ num_elements = be32_to_cpu(gsb->num_elements);
+ element = gsb->elements;
+ len -= sizeof(gsb->num_elements);
+
+ /* Walk the buffer to validate the length */
+ while (num_elements) {
+
+ id = be16_to_cpu(element->id);
+ size = be16_to_cpu(element->size);
+
+ if (false) {
+ log_element(element, gsr);
+ }
+ /* buffer size too small */
+ if (len < 0) {
+ return false;
+ }
+
+ type = guest_state_element_type_find(id);
+ if (!type) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Element ID %04x unknown\n", id);
+ log_element(element, gsr);
+ return false;
+ }
+
+ if (id == GSB_HV_VCPU_IGNORED_ID) {
+ goto next_element;
+ }
+
+ if (size != type->size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Size mismatch. Element ID:%04x."
+ "Size Exp:%i Got:%i\n", id, type->size, size);
+ log_element(element, gsr);
+ return false;
+ }
+
+ if ((type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY) &&
+ (gsr->flags & GUEST_STATE_REQUEST_SET)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Trying to set a read-only Element "
+ "ID:%04x.\n", id);
+ return false;
+ }
+
+ if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE) {
+ /* guest wide element type */
+ if (!(gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "trying to set a guest wide "
+ "Element ID:%04x.\n", id);
+ return false;
+ }
+ } else {
+ /* thread wide element type */
+ if (gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE) {
+ qemu_log_mask(LOG_GUEST_ERROR, "trying to set a thread wide "
+ "Element ID:%04x.\n", id);
+ return false;
+ }
+ }
+next_element:
+ element = guest_state_element_next(element, &len, &num_elements);
+
+ }
+ return true;
+}
+
+static bool is_gsr_invalid(struct guest_state_request *gsr,
+ struct guest_state_element *element,
+ struct guest_state_element_type *type)
+{
+ if ((gsr->flags & GUEST_STATE_REQUEST_SET) &&
+ (*(uint64_t *)(element->value) & ~(type->mask))) {
+ log_element(element, gsr);
+ qemu_log_mask(LOG_GUEST_ERROR, "L1 can't set reserved bits "
+ "(allowed mask: 0x%08"PRIx64")\n", type->mask);
+ return true;
+ }
+ return false;
+}
+
static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu,
SpaprMachineState *spapr,
target_ulong opcode,
@@ -1264,6 +1398,136 @@ static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu,
return H_SUCCESS;
}
+static target_ulong getset_state(SpaprMachineStateNestedGuest *guest,
+ uint64_t vcpuid,
+ struct guest_state_request *gsr)
+{
+ void *ptr;
+ uint16_t id;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ int64_t lenleft, num_elements;
+
+ lenleft = gsr->len;
+
+ if (!guest_state_request_check(gsr)) {
+ return H_P3;
+ }
+
+ num_elements = be32_to_cpu(gsr->gsb->num_elements);
+ element = gsr->gsb->elements;
+ /* Process the elements */
+ while (num_elements) {
+ type = NULL;
+ /* log_element(element, gsr); */
+
+ id = be16_to_cpu(element->id);
+ if (id == GSB_HV_VCPU_IGNORED_ID) {
+ goto next_element;
+ }
+
+ type = guest_state_element_type_find(id);
+ assert(type);
+
+ /* Get pointer to guest data to get/set */
+ if (type->location && type->copy) {
+ ptr = type->location(guest, vcpuid);
+ assert(ptr);
+ if (!~(type->mask) && is_gsr_invalid(gsr, element, type)) {
+ return H_INVALID_ELEMENT_VALUE;
+ }
+ type->copy(ptr + type->offset, element->value,
+ gsr->flags & GUEST_STATE_REQUEST_SET ? true : false);
+ }
+
+next_element:
+ element = guest_state_element_next(element, &lenleft, &num_elements);
+ }
+
+ return H_SUCCESS;
+}
+
+static target_ulong map_and_getset_state(PowerPCCPU *cpu,
+ SpaprMachineStateNestedGuest *guest,
+ uint64_t vcpuid,
+ struct guest_state_request *gsr)
+{
+ target_ulong rc;
+ int64_t len;
+ bool is_write;
+
+ len = gsr->len;
+ /* only get_state would require write access to the provided buffer */
+ is_write = (gsr->flags & GUEST_STATE_REQUEST_SET) ? false : true;
+ gsr->gsb = address_space_map(CPU(cpu)->as, gsr->buf, (uint64_t *)&len,
+ is_write, MEMTXATTRS_UNSPECIFIED);
+ if (!gsr->gsb) {
+ rc = H_P3;
+ goto out1;
+ }
+
+ if (len != gsr->len) {
+ rc = H_P3;
+ goto out1;
+ }
+
+ rc = getset_state(guest, vcpuid, gsr);
+
+out1:
+ address_space_unmap(CPU(cpu)->as, gsr->gsb, len, is_write, len);
+ return rc;
+}
+
+static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong *args,
+ bool set)
+{
+ target_ulong flags = args[0];
+ target_ulong lpid = args[1];
+ target_ulong vcpuid = args[2];
+ target_ulong buf = args[3];
+ target_ulong buflen = args[4];
+ struct guest_state_request gsr;
+ SpaprMachineStateNestedGuest *guest;
+
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return H_P2;
+ }
+ gsr.buf = buf;
+ assert(buflen <= GSB_MAX_BUF_SIZE);
+ gsr.len = buflen;
+ gsr.flags = 0;
+ if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
+ gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
+ }
+ if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
+ return H_PARAMETER; /* flag not supported yet */
+ }
+
+ if (set) {
+ gsr.flags |= GUEST_STATE_REQUEST_SET;
+ }
+ return map_and_getset_state(cpu, guest, vcpuid, &gsr);
+}
+
+static target_ulong h_guest_set_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ return h_guest_getset_state(cpu, spapr, args, true);
+}
+
+static target_ulong h_guest_get_state(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ return h_guest_getset_state(cpu, spapr, args, false);
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
@@ -1289,6 +1553,8 @@ void spapr_register_nested_papr(void)
spapr_register_hypercall(H_GUEST_CREATE, h_guest_create);
spapr_register_hypercall(H_GUEST_DELETE, h_guest_delete);
spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu);
+ spapr_register_hypercall(H_GUEST_SET_STATE, h_guest_set_state);
+ spapr_register_hypercall(H_GUEST_GET_STATE, h_guest_get_state);
}
void spapr_unregister_nested_papr(void)
@@ -1298,6 +1564,8 @@ void spapr_unregister_nested_papr(void)
spapr_unregister_hypercall(H_GUEST_CREATE);
spapr_unregister_hypercall(H_GUEST_DELETE);
spapr_unregister_hypercall(H_GUEST_CREATE_VCPU);
+ spapr_unregister_hypercall(H_GUEST_SET_STATE);
+ spapr_unregister_hypercall(H_GUEST_GET_STATE);
}
#else
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 070135793a..6223873641 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -366,6 +366,7 @@ struct SpaprMachineState {
#define H_OVERLAP -68
#define H_STATE -75
#define H_IN_USE -77
+#define H_INVALID_ELEMENT_VALUE -81
#define H_UNSUPPORTED_FLAG -256
#define H_MULTI_THREADS_ACTIVE -9005
@@ -589,6 +590,8 @@ struct SpaprMachineState {
#define H_GUEST_SET_CAPABILITIES 0x464
#define H_GUEST_CREATE 0x470
#define H_GUEST_CREATE_VCPU 0x474
+#define H_GUEST_GET_STATE 0x478
+#define H_GUEST_SET_STATE 0x47C
#define H_GUEST_DELETE 0x488
#define MAX_HCALL_OPCODE H_GUEST_DELETE
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 3da02df7bb..bf9b258c29 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -224,6 +224,10 @@ typedef struct SpaprMachineStateNestedGuest {
#define HVMASK_MSR 0xEBFFFFFFFFBFEFFF
#define HVMASK_HDEXCR 0x00000000FFFFFFFF
#define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF
+#define GSB_MAX_BUF_SIZE (1024 * 1024)
+#define H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE 0x8000000000000000
+#define GUEST_STATE_REQUEST_GUEST_WIDE 0x1
+#define GUEST_STATE_REQUEST_SET 0x2
/*
* As per ISA v3.1B, following bits are reserved:
@@ -322,6 +326,25 @@ typedef struct SpaprMachineStateNestedGuest {
#define GSE_ENV_DWM(i, f, m) \
GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m)
+struct guest_state_element {
+ uint16_t id;
+ uint16_t size;
+ uint8_t value[];
+} QEMU_PACKED;
+
+struct guest_state_buffer {
+ uint32_t num_elements;
+ struct guest_state_element elements[];
+} QEMU_PACKED;
+
+/* Actual buffer plus some metadata about the request */
+struct guest_state_request {
+ struct guest_state_buffer *gsb;
+ int64_t buf;
+ int64_t len;
+ uint16_t flags;
+};
+
/*
* Register state for entering a nested guest with H_ENTER_NESTED.
* New member must be added at the end.
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 36/38] spapr: nested: Use correct source for parttbl info for nested PAPR API.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (34 preceding siblings ...)
2024-03-12 16:58 ` [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 37/38] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall Nicholas Piggin
` (3 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() via
helper.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 6 +++--
hw/ppc/spapr_nested.c | 41 ++++++++++++++++++++++++++---------
include/hw/ppc/spapr_nested.h | 2 ++
3 files changed, 37 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e001ffe06f..aaf73781b0 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1421,11 +1421,13 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
entry->dw1 = spapr->patb_entry;
return true;
} else {
- assert(spapr_nested_api(spapr));
if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
+ } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry);
+ } else {
+ g_assert_not_reached();
}
- return false;
}
}
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index cea282926f..1a5cb254c9 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -58,6 +58,31 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
return true;
}
+static
+SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
+ target_ulong guestid)
+{
+ SpaprMachineStateNestedGuest *guest;
+
+ guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
+ return guest;
+}
+
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ SpaprMachineStateNestedGuest *guest;
+ assert(lpid != 0);
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return false;
+ }
+
+ entry->dw0 = guest->parttbl[0];
+ entry->dw1 = guest->parttbl[1];
+ return true;
+}
+
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -540,16 +565,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp)
}
}
-static
-SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *spapr,
- target_ulong guestid)
-{
- SpaprMachineStateNestedGuest *guest;
-
- guest = g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(guestid));
- return guest;
-}
-
static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest,
target_ulong vcpuid, bool inoutbuf)
{
@@ -1590,6 +1605,12 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
return false;
}
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ return false;
+}
+
void spapr_register_nested_papr(void)
{
/* DO NOTHING */
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index bf9b258c29..93ef14adcc 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -519,4 +519,6 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry);
uint8_t spapr_nested_api(SpaprMachineState *spapr);
void spapr_nested_gsb_init(void);
+bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
#endif /* HW_SPAPR_NESTED_H */
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 37/38] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall.
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (35 preceding siblings ...)
2024-03-12 16:58 ` [PULL 36/38] spapr: nested: Use correct source for parttbl info for nested PAPR API Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 16:58 ` [PULL 38/38] spapr: nested: Introduce cap-nested-papr for Nested PAPR API Nicholas Piggin
` (2 subsequent siblings)
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
The H_GUEST_RUN_VCPU hcall is used to start execution of a Guest VCPU.
The Hypervisor will update the state of the Guest VCPU based on the
input buffer, restore the saved Guest VCPU state, and start its
execution.
The Guest VCPU can stop running for numerous reasons including HCALLs,
hypervisor exceptions, or an outstanding Host Partition Interrupt.
The reason that the Guest VCPU stopped running is communicated through
R4 and the output buffer will be filled in with any relevant state.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/ppc.c | 10 ++
hw/ppc/spapr_nested.c | 334 ++++++++++++++++++++++++++++++++++++++----
target/ppc/cpu.h | 2 +
3 files changed, 316 insertions(+), 30 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index fadb8f5239..e6fa5580c0 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -633,6 +633,16 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
((uint64_t)value << 32) | tb);
}
+void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset)
+{
+ env->tb_env->tb_offset += offset;
+}
+
+void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset)
+{
+ env->tb_env->tb_offset -= offset;
+}
+
uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 1a5cb254c9..ce3490bcf2 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -210,14 +210,28 @@ static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu)
save->sier = env->spr[SPR_POWER_SIER];
save->vscr = ppc_get_vscr(env);
save->fpscr = env->fpscr;
+ } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ save->tb_offset = env->tb_env->tb_offset;
}
+}
- save->tb_offset = env->tb_env->tb_offset;
+static void nested_post_load_state(CPUPPCState *env, CPUState *cs)
+{
+ /*
+ * compute hflags and possible interrupts.
+ */
+ hreg_compute_hflags(env);
+ ppc_maybe_interrupt(env);
+ /*
+ * Nested HV does not tag TLB entries between L1 and L2, so must
+ * flush on transition.
+ */
+ tlb_flush(cs);
+ env->reserve_addr = -1; /* Reset the reservation */
}
static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
{
- CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
@@ -295,22 +309,9 @@ static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load)
env->spr[SPR_POWER_SIER] = load->sier;
ppc_store_vscr(env, load->vscr);
ppc_store_fpscr(env, load->fpscr);
+ } else if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ env->tb_env->tb_offset = load->tb_offset;
}
-
- env->tb_env->tb_offset = load->tb_offset;
-
- /*
- * MSR updated, compute hflags and possible interrupts.
- */
- hreg_compute_hflags(env);
- ppc_maybe_interrupt(env);
-
- /*
- * Nested HV does not tag TLB entries between L1 and L2, so must
- * flush on transition.
- */
- tlb_flush(cs);
- env->reserve_addr = -1; /* Reset the reservation */
}
/*
@@ -325,6 +326,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
struct nested_ppc_state l2_state;
target_ulong hv_ptr = args[0];
@@ -423,6 +425,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
* Switch to the nested guest environment and start the "hdec" timer.
*/
nested_load_state(cpu, &l2_state);
+ nested_post_load_state(env, cs);
hdec = hv_state.hdec_expiry - now;
cpu_ppc_hdecr_init(env);
@@ -454,6 +457,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
struct nested_ppc_state l2_state;
target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4];
@@ -475,6 +479,7 @@ static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
*/
assert(env->spr[SPR_LPIDR] != 0);
nested_load_state(cpu, spapr_cpu->nested_host_state);
+ nested_post_load_state(env, cs);
env->gpr[3] = env->excp_vectors[excp]; /* hcall return value */
cpu_ppc_hdecr_exit(env);
@@ -552,19 +557,6 @@ static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp)
address_space_unmap(CPU(cpu)->as, regs, len, len, true);
}
-void spapr_exit_nested(PowerPCCPU *cpu, int excp)
-{
- SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
-
- assert(spapr_cpu->in_nested);
- if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
- spapr_exit_nested_hv(cpu, excp);
- } else {
- g_assert_not_reached();
- }
-}
-
static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest,
target_ulong vcpuid, bool inoutbuf)
{
@@ -1543,6 +1535,286 @@ static target_ulong h_guest_get_state(PowerPCCPU *cpu,
return h_guest_getset_state(cpu, spapr, args, false);
}
+static void exit_nested_store_l2(PowerPCCPU *cpu, int excp,
+ SpaprMachineStateNestedGuestVcpu *vcpu)
+{
+ CPUPPCState *env = &cpu->env;
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong now, hdar, hdsisr, asdr;
+
+ assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr)); /* sanity check */
+
+ now = cpu_ppc_load_tbl(env); /* L2 timebase */
+ now -= vcpu->tb_offset; /* L1 timebase */
+ vcpu->state.dec_expiry_tb = now - cpu_ppc_load_decr(env);
+ cpu_ppc_store_decr(env, spapr_cpu->nested_host_state->dec_expiry_tb - now);
+ /* backup hdar, hdsisr, asdr if reqd later below */
+ hdar = vcpu->state.hdar;
+ hdsisr = vcpu->state.hdsisr;
+ asdr = vcpu->state.asdr;
+
+ nested_save_state(&vcpu->state, cpu);
+
+ if (excp == POWERPC_EXCP_MCHECK ||
+ excp == POWERPC_EXCP_RESET ||
+ excp == POWERPC_EXCP_SYSCALL) {
+ vcpu->state.nip = env->spr[SPR_SRR0];
+ vcpu->state.msr = env->spr[SPR_SRR1] & env->msr_mask;
+ } else {
+ vcpu->state.nip = env->spr[SPR_HSRR0];
+ vcpu->state.msr = env->spr[SPR_HSRR1] & env->msr_mask;
+ }
+
+ /* hdar, hdsisr, asdr should be retained unless certain exceptions */
+ if ((excp != POWERPC_EXCP_HDSI) && (excp != POWERPC_EXCP_HISI)) {
+ vcpu->state.asdr = asdr;
+ } else if (excp != POWERPC_EXCP_HDSI) {
+ vcpu->state.hdar = hdar;
+ vcpu->state.hdsisr = hdsisr;
+ }
+}
+
+static int get_exit_ids(uint64_t srr0, uint16_t ids[16])
+{
+ int nr;
+
+ switch (srr0) {
+ case 0xc00:
+ nr = 10;
+ ids[0] = GSB_VCPU_GPR3;
+ ids[1] = GSB_VCPU_GPR4;
+ ids[2] = GSB_VCPU_GPR5;
+ ids[3] = GSB_VCPU_GPR6;
+ ids[4] = GSB_VCPU_GPR7;
+ ids[5] = GSB_VCPU_GPR8;
+ ids[6] = GSB_VCPU_GPR9;
+ ids[7] = GSB_VCPU_GPR10;
+ ids[8] = GSB_VCPU_GPR11;
+ ids[9] = GSB_VCPU_GPR12;
+ break;
+ case 0xe00:
+ nr = 5;
+ ids[0] = GSB_VCPU_SPR_HDAR;
+ ids[1] = GSB_VCPU_SPR_HDSISR;
+ ids[2] = GSB_VCPU_SPR_ASDR;
+ ids[3] = GSB_VCPU_SPR_NIA;
+ ids[4] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xe20:
+ nr = 4;
+ ids[0] = GSB_VCPU_SPR_HDAR;
+ ids[1] = GSB_VCPU_SPR_ASDR;
+ ids[2] = GSB_VCPU_SPR_NIA;
+ ids[3] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xe40:
+ nr = 3;
+ ids[0] = GSB_VCPU_SPR_HEIR;
+ ids[1] = GSB_VCPU_SPR_NIA;
+ ids[2] = GSB_VCPU_SPR_MSR;
+ break;
+ case 0xf80:
+ nr = 3;
+ ids[0] = GSB_VCPU_SPR_HFSCR;
+ ids[1] = GSB_VCPU_SPR_NIA;
+ ids[2] = GSB_VCPU_SPR_MSR;
+ break;
+ default:
+ nr = 0;
+ break;
+ }
+
+ return nr;
+}
+
+static void exit_process_output_buffer(PowerPCCPU *cpu,
+ SpaprMachineStateNestedGuest *guest,
+ target_ulong vcpuid,
+ target_ulong *r3)
+{
+ SpaprMachineStateNestedGuestVcpu *vcpu = &guest->vcpus[vcpuid];
+ struct guest_state_request gsr;
+ struct guest_state_buffer *gsb;
+ struct guest_state_element *element;
+ struct guest_state_element_type *type;
+ int exit_id_count = 0;
+ uint16_t exit_cause_ids[16];
+ hwaddr len;
+
+ len = vcpu->runbufout.size;
+ gsb = address_space_map(CPU(cpu)->as, vcpu->runbufout.addr, &len, true,
+ MEMTXATTRS_UNSPECIFIED);
+ if (!gsb || len != vcpu->runbufout.size) {
+ address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
+ *r3 = H_P2;
+ return;
+ }
+
+ exit_id_count = get_exit_ids(*r3, exit_cause_ids);
+
+ /* Create a buffer of elements to send back */
+ gsb->num_elements = cpu_to_be32(exit_id_count);
+ element = gsb->elements;
+ for (int i = 0; i < exit_id_count; i++) {
+ type = guest_state_element_type_find(exit_cause_ids[i]);
+ assert(type);
+ element->id = cpu_to_be16(exit_cause_ids[i]);
+ element->size = cpu_to_be16(type->size);
+ element = guest_state_element_next(element, NULL, NULL);
+ }
+ gsr.gsb = gsb;
+ gsr.len = VCPU_OUT_BUF_MIN_SZ;
+ gsr.flags = 0; /* get + never guest wide */
+ getset_state(guest, vcpuid, &gsr);
+
+ address_space_unmap(CPU(cpu)->as, gsb, len, true, len);
+ return;
+}
+
+static
+void spapr_exit_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, int excp)
+{
+ CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */
+ target_ulong lpid = 0, vcpuid = 0;
+ struct SpaprMachineStateNestedGuestVcpu *vcpu = NULL;
+ struct SpaprMachineStateNestedGuest *guest = NULL;
+
+ lpid = spapr_cpu->nested_host_state->gpr[5];
+ vcpuid = spapr_cpu->nested_host_state->gpr[6];
+ guest = spapr_get_nested_guest(spapr, lpid);
+ assert(guest);
+ spapr_nested_vcpu_check(guest, vcpuid, false);
+ vcpu = &guest->vcpus[vcpuid];
+
+ exit_nested_store_l2(cpu, excp, vcpu);
+ /* do the output buffer for run_vcpu*/
+ exit_process_output_buffer(cpu, guest, vcpuid, &r3_return);
+
+ assert(env->spr[SPR_LPIDR] != 0);
+ nested_load_state(cpu, spapr_cpu->nested_host_state);
+ cpu_ppc_decrease_tb_by_offset(env, vcpu->tb_offset);
+ env->gpr[3] = H_SUCCESS;
+ env->gpr[4] = r3_return;
+ nested_post_load_state(env, cs);
+ cpu_ppc_hdecr_exit(env);
+
+ spapr_cpu->in_nested = false;
+ g_free(spapr_cpu->nested_host_state);
+ spapr_cpu->nested_host_state = NULL;
+}
+
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+
+ assert(spapr_cpu->in_nested);
+ if (spapr_nested_api(spapr) == NESTED_API_KVM_HV) {
+ spapr_exit_nested_hv(cpu, excp);
+ } else if (spapr_nested_api(spapr) == NESTED_API_PAPR) {
+ spapr_exit_nested_papr(spapr, cpu, excp);
+ } else {
+ g_assert_not_reached();
+ }
+}
+
+static void nested_papr_load_l2(PowerPCCPU *cpu,
+ CPUPPCState *env,
+ SpaprMachineStateNestedGuestVcpu *vcpu,
+ target_ulong now)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ target_ulong lpcr, lpcr_mask, hdec;
+ lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
+
+ assert(vcpu);
+ assert(sizeof(env->gpr) == sizeof(vcpu->state.gpr));
+ nested_load_state(cpu, &vcpu->state);
+ lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) |
+ (vcpu->state.lpcr & lpcr_mask);
+ lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
+ lpcr &= ~LPCR_LPES0;
+ env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask;
+
+ hdec = vcpu->hdecr_expiry_tb - now;
+ cpu_ppc_store_decr(env, vcpu->state.dec_expiry_tb - now);
+ cpu_ppc_hdecr_init(env);
+ cpu_ppc_store_hdecr(env, hdec);
+
+ cpu_ppc_increase_tb_by_offset(env, vcpu->tb_offset);
+}
+
+static void nested_papr_run_vcpu(PowerPCCPU *cpu,
+ uint64_t lpid,
+ SpaprMachineStateNestedGuestVcpu *vcpu)
+{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+ CPUPPCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong now = cpu_ppc_load_tbl(env);
+
+ assert(env->spr[SPR_LPIDR] == 0);
+ assert(spapr->nested.api); /* ensure API version is initialized */
+ spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1);
+ assert(spapr_cpu->nested_host_state);
+ nested_save_state(spapr_cpu->nested_host_state, cpu);
+ spapr_cpu->nested_host_state->dec_expiry_tb = now - cpu_ppc_load_decr(env);
+ nested_papr_load_l2(cpu, env, vcpu, now);
+ env->spr[SPR_LPIDR] = lpid; /* post load l2 */
+
+ spapr_cpu->in_nested = true;
+ nested_post_load_state(env, cs);
+}
+
+static target_ulong h_guest_run_vcpu(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong flags = args[0];
+ target_ulong lpid = args[1];
+ target_ulong vcpuid = args[2];
+ struct SpaprMachineStateNestedGuestVcpu *vcpu;
+ struct guest_state_request gsr;
+ SpaprMachineStateNestedGuest *guest;
+ target_ulong rc;
+
+ if (flags) /* don't handle any flags for now */
+ return H_PARAMETER;
+
+ guest = spapr_get_nested_guest(spapr, lpid);
+ if (!guest) {
+ return H_P2;
+ }
+ if (!spapr_nested_vcpu_check(guest, vcpuid, true)) {
+ return H_P3;
+ }
+
+ if (guest->parttbl[0] == 0) {
+ /* At least need a partition scoped radix tree */
+ return H_NOT_AVAILABLE;
+ }
+
+ vcpu = &guest->vcpus[vcpuid];
+
+ /* Read run_vcpu input buffer to update state */
+ gsr.buf = vcpu->runbufin.addr;
+ gsr.len = vcpu->runbufin.size;
+ gsr.flags = GUEST_STATE_REQUEST_SET; /* Thread wide + writing */
+ rc = map_and_getset_state(cpu, guest, vcpuid, &gsr);
+ if (rc == H_SUCCESS) {
+ nested_papr_run_vcpu(cpu, lpid, vcpu);
+ } else {
+ env->gpr[3] = rc;
+ }
+ return env->gpr[3];
+}
+
void spapr_register_nested_hv(void)
{
spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
@@ -1570,6 +1842,7 @@ void spapr_register_nested_papr(void)
spapr_register_hypercall(H_GUEST_CREATE_VCPU, h_guest_create_vcpu);
spapr_register_hypercall(H_GUEST_SET_STATE, h_guest_set_state);
spapr_register_hypercall(H_GUEST_GET_STATE, h_guest_get_state);
+ spapr_register_hypercall(H_GUEST_RUN_VCPU, h_guest_run_vcpu);
}
void spapr_unregister_nested_papr(void)
@@ -1581,6 +1854,7 @@ void spapr_unregister_nested_papr(void)
spapr_unregister_hypercall(H_GUEST_CREATE_VCPU);
spapr_unregister_hypercall(H_GUEST_SET_STATE);
spapr_unregister_hypercall(H_GUEST_GET_STATE);
+ spapr_unregister_hypercall(H_GUEST_RUN_VCPU);
}
#else
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index be5f74a7cd..67e6b2effd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1584,6 +1584,8 @@ uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
+void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
+void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
bool ppc_decr_clear_on_delivery(CPUPPCState *env);
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PULL 38/38] spapr: nested: Introduce cap-nested-papr for Nested PAPR API
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (36 preceding siblings ...)
2024-03-12 16:58 ` [PULL 37/38] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall Nicholas Piggin
@ 2024-03-12 16:58 ` Nicholas Piggin
2024-03-12 19:29 ` [PULL 00/38] ppc-for-9.0-2 queue Bernhard Beschow
2024-03-13 15:10 ` Peter Maydell
39 siblings, 0 replies; 46+ messages in thread
From: Nicholas Piggin @ 2024-03-12 16:58 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API for nested guests. This new API is to enable support for KVM on PowerVM
and the support in Linux kernel has already merged upstream.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 2 ++
hw/ppc/spapr_caps.c | 54 ++++++++++++++++++++++++++++++++++++++++++
hw/ppc/spapr_nested.c | 8 ++++---
include/hw/ppc/spapr.h | 6 ++++-
4 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index aaf73781b0..99d3fcb185 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2166,6 +2166,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_cap_fwnmi,
&vmstate_spapr_fwnmi,
&vmstate_spapr_cap_rpt_invalidate,
+ &vmstate_spapr_cap_nested_papr,
NULL
}
};
@@ -4732,6 +4733,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
+ smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index e889244e52..62abf1ba9d 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -487,6 +487,50 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
error_append_hint(errp, "Try appending -machine cap-nested-hv=off "
"or use threads=1 with -smp\n");
}
+ if (spapr_nested_api(spapr) &&
+ spapr_nested_api(spapr) != NESTED_API_KVM_HV) {
+ error_setg(errp, "Nested-HV APIs are mutually exclusive");
+ error_append_hint(errp, "Please use either cap-nested-hv or "
+ "cap-nested-papr to proceed.\n");
+ return;
+ } else {
+ spapr->nested.api = NESTED_API_KVM_HV;
+ }
+ }
+}
+
+static void cap_nested_papr_apply(SpaprMachineState *spapr,
+ uint8_t val, Error **errp)
+{
+ ERRP_GUARD();
+ PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ CPUPPCState *env = &cpu->env;
+
+ if (!val) {
+ /* capability disabled by default */
+ return;
+ }
+
+ if (tcg_enabled()) {
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ error_setg(errp, "Nested-PAPR only supported on POWER9 and later");
+ error_append_hint(errp,
+ "Try appending -machine cap-nested-papr=off\n");
+ return;
+ }
+ if (spapr_nested_api(spapr) &&
+ spapr_nested_api(spapr) != NESTED_API_PAPR) {
+ error_setg(errp, "Nested-HV APIs are mutually exclusive");
+ error_append_hint(errp, "Please use either cap-nested-hv or "
+ "cap-nested-papr to proceed.\n");
+ return;
+ } else {
+ spapr->nested.api = NESTED_API_PAPR;
+ }
+ } else if (kvm_enabled()) {
+ error_setg(errp, "KVM implementation does not support Nested-PAPR");
+ error_append_hint(errp,
+ "Try appending -machine cap-nested-papr=off\n");
}
}
@@ -735,6 +779,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
.type = "bool",
.apply = cap_nested_kvm_hv_apply,
},
+ [SPAPR_CAP_NESTED_PAPR] = {
+ .name = "nested-papr",
+ .description = "Allow Nested HV (PAPR API)",
+ .index = SPAPR_CAP_NESTED_PAPR,
+ .get = spapr_cap_get_bool,
+ .set = spapr_cap_set_bool,
+ .type = "bool",
+ .apply = cap_nested_papr_apply,
+ },
[SPAPR_CAP_LARGE_DECREMENTER] = {
.name = "large-decr",
.description = "Allow Large Decrementer",
@@ -919,6 +972,7 @@ SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE);
SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
+SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR);
SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index ce3490bcf2..936659b4c0 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -13,13 +13,15 @@
void spapr_nested_reset(SpaprMachineState *spapr)
{
if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
- spapr->nested.api = NESTED_API_KVM_HV;
spapr_unregister_nested_hv();
spapr_register_nested_hv();
- } else {
- spapr->nested.api = 0;
+ } else if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_PAPR)) {
spapr->nested.capabilities_set = false;
+ spapr_unregister_nested_papr();
+ spapr_register_nested_papr();
spapr_nested_gsb_init();
+ } else {
+ spapr->nested.api = 0;
}
}
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 6223873641..4aaf23d28f 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -81,8 +81,10 @@ typedef enum {
#define SPAPR_CAP_RPT_INVALIDATE 0x0B
/* Support for AIL modes */
#define SPAPR_CAP_AIL_MODE_3 0x0C
+/* Nested PAPR */
+#define SPAPR_CAP_NESTED_PAPR 0x0D
/* Num Caps */
-#define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1)
+#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_PAPR + 1)
/*
* Capability Values
@@ -592,6 +594,7 @@ struct SpaprMachineState {
#define H_GUEST_CREATE_VCPU 0x474
#define H_GUEST_GET_STATE 0x478
#define H_GUEST_SET_STATE 0x47C
+#define H_GUEST_RUN_VCPU 0x480
#define H_GUEST_DELETE 0x488
#define MAX_HCALL_OPCODE H_GUEST_DELETE
@@ -996,6 +999,7 @@ extern const VMStateDescription vmstate_spapr_cap_sbbc;
extern const VMStateDescription vmstate_spapr_cap_ibs;
extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
+extern const VMStateDescription vmstate_spapr_cap_nested_papr;
extern const VMStateDescription vmstate_spapr_cap_large_decr;
extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
extern const VMStateDescription vmstate_spapr_cap_fwnmi;
--
2.42.0
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [PULL 00/38] ppc-for-9.0-2 queue
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (37 preceding siblings ...)
2024-03-12 16:58 ` [PULL 38/38] spapr: nested: Introduce cap-nested-papr for Nested PAPR API Nicholas Piggin
@ 2024-03-12 19:29 ` Bernhard Beschow
2024-03-13 15:10 ` Peter Maydell
39 siblings, 0 replies; 46+ messages in thread
From: Bernhard Beschow @ 2024-03-12 19:29 UTC (permalink / raw)
To: qemu-devel, Nicholas Piggin
Cc: qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
Am 12. März 2024 16:58:11 UTC schrieb Nicholas Piggin <npiggin@gmail.com>:
>The following changes since commit 35ac6831d98e18e2c78c85c93e3a6ca1f1ae3e58:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-03-12 13:42:57 +0000)
>
>are available in the Git repository at:
>
> https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-2-20240313
>
>for you to fetch changes up to e1617b845104032f0aaad9b91dcda56c7c437998:
>
> spapr: nested: Introduce cap-nested-papr for Nested PAPR API (2024-03-13 02:47:04 +1000)
>
>----------------------------------------------------------------
>* PAPR nested hypervisor host implementation for spapr TCG
>* excp_helper.c code cleanups and improvements
>* Move more ops to decodetree
>* Deprecate pseries-2.12 machines and P9 and P10 DD1.0 CPUs
>* Document running Linux on AmigaNG
>* Update dt feature advertising POWER CPUs.
>* Add P10 PMU SPRs
>* Improve pnv topology calculation for SMT8 CPUs.
>* Various bug fixes.
>
>----------------------------------------------------------------
>BALATON Zoltan (8):
> docs/system/ppc: Document running Linux on AmigaNG machines
Thanks, Nicholas!
Best regards,
Bernhard
> target/ppc: Use env_cpu for cpu_abort in excp_helper
> target/ppc: Readability improvements in exception handlers
> target/ppc: Add gen_exception_err_nip() function
> target/ppc: Clean up ifdefs in excp_helper.c, part 1
> target/ppc: Clean up ifdefs in excp_helper.c, part 2
> target/ppc: Clean up ifdefs in excp_helper.c, part 3
> target/ppc: Remove interrupt handler wrapper functions
>
>Benjamin Gray (1):
> ppc/spapr: Add pa-features for POWER10 machines
>
>Caleb Schlossin (1):
> ppc/pnv: Improve pervasive topology calculation for big-core
>
>Chinmay Rath (1):
> target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree
>
>Cédric Le Goater (1):
> MAINTAINERS: Remove myself as reviewer from PPC
>
>Harsh Prateek Bora (14):
> spapr: nested: register nested-hv api hcalls only for cap-nested-hv
> spapr: nested: move nested part of spapr_get_pate into spapr_nested.c
> spapr: nested: Introduce SpaprMachineStateNested to store related info.
> spapr: nested: keep nested-hv related code restricted to its API.
> spapr: nested: Document Nested PAPR API
> spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls.
> spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls.
> spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall.
> spapr: nested: Extend nested_ppc_state for nested PAPR API
> spapr: nested: Initialize the GSB elements lookup table.
> spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
> spapr: nested: Use correct source for parttbl info for nested PAPR API.
> spapr: nested: Introduce H_GUEST_RUN_VCPU hcall.
> spapr: nested: Introduce cap-nested-papr for Nested PAPR API
>
>Madhavan Srinivasan (1):
> target/ppc: Add power10 pmu SPRs
>
>Nicholas Piggin (10):
> target/ppc: Fix GDB SPR regnum indexing
> target/ppc: Prevent supervisor from modifying MSR[ME]
> spapr: set MSR[ME] and MSR[FP] on client entry
> ppc: Drop support for POWER9 and POWER10 DD1 chips
> target/ppc: POWER10 does not have transactional memory
> ppc/spapr|pnv: Remove SAO from pa-features
> ppc/spapr: Remove copy-paste from pa-features
> ppc/spapr: Adjust ibm,pa-features for POWER9
> ppc/pnv: Permit ibm,pa-features set per machine variant
> ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits
>
>Philippe Mathieu-Daudé (1):
> docs: Deprecate the pseries-2.12 machines
>
> MAINTAINERS | 4 +-
> docs/about/deprecated.rst | 6 +-
> docs/devel/nested-papr.txt | 119 +++
> docs/system/ppc/amigang.rst | 161 +++
> docs/system/target-ppc.rst | 1 +
> hw/ppc/pnv.c | 175 +++-
> hw/ppc/pnv_core.c | 8 +-
> hw/ppc/ppc.c | 10 +
> hw/ppc/spapr.c | 98 +-
> hw/ppc/spapr_caps.c | 54 +
> hw/ppc/spapr_cpu_core.c | 8 +-
> hw/ppc/spapr_hcall.c | 24 +-
> hw/ppc/spapr_nested.c | 1556 +++++++++++++++++++++++++++-
> include/hw/ppc/pnv_chip.h | 2 +-
> include/hw/ppc/pnv_core.h | 1 +
> include/hw/ppc/spapr.h | 27 +-
> include/hw/ppc/spapr_nested.h | 427 +++++++-
> target/ppc/cpu-models.c | 4 -
> target/ppc/cpu.h | 11 +
> target/ppc/cpu_init.c | 46 +-
> target/ppc/excp_helper.c | 418 +++-----
> target/ppc/gdbstub.c | 7 +-
> target/ppc/helper_regs.c | 5 +
> target/ppc/insn32.decode | 26 +
> target/ppc/kvm.c | 11 -
> target/ppc/misc_helper.c | 3 -
> target/ppc/translate.c | 164 +--
> target/ppc/translate/fixedpoint-impl.c.inc | 70 ++
> 28 files changed, 2883 insertions(+), 563 deletions(-)
> create mode 100644 docs/devel/nested-papr.txt
> create mode 100644 docs/system/ppc/amigang.rst
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 00/38] ppc-for-9.0-2 queue
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
` (38 preceding siblings ...)
2024-03-12 19:29 ` [PULL 00/38] ppc-for-9.0-2 queue Bernhard Beschow
@ 2024-03-13 15:10 ` Peter Maydell
39 siblings, 0 replies; 46+ messages in thread
From: Peter Maydell @ 2024-03-13 15:10 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Harsh Prateek Bora
On Tue, 12 Mar 2024 at 16:59, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> The following changes since commit 35ac6831d98e18e2c78c85c93e3a6ca1f1ae3e58:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-03-12 13:42:57 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.0-2-20240313
>
> for you to fetch changes up to e1617b845104032f0aaad9b91dcda56c7c437998:
>
> spapr: nested: Introduce cap-nested-papr for Nested PAPR API (2024-03-13 02:47:04 +1000)
>
> ----------------------------------------------------------------
> * PAPR nested hypervisor host implementation for spapr TCG
> * excp_helper.c code cleanups and improvements
> * Move more ops to decodetree
> * Deprecate pseries-2.12 machines and P9 and P10 DD1.0 CPUs
> * Document running Linux on AmigaNG
> * Update dt feature advertising POWER CPUs.
> * Add P10 PMU SPRs
> * Improve pnv topology calculation for SMT8 CPUs.
> * Various bug fixes.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-12 16:58 ` [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls Nicholas Piggin
@ 2024-03-26 16:02 ` Peter Maydell
2024-03-27 5:41 ` Harsh Prateek Bora
0 siblings, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2024-03-26 16:02 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza,
Harsh Prateek Bora, Michael Neuling
On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> From: Harsh Prateek Bora <harshpb@linux.ibm.com>
>
> Introduce the nested PAPR hcalls:
> - H_GUEST_GET_STATE which is used to get state of a nested guest or
> a guest VCPU. The value field for each element in the request is
> destination to be updated to reflect current state on success.
> - H_GUEST_SET_STATE which is used to modify the state of a guest or
> a guest VCPU. On success, guest (or its VCPU) state shall be
> updated as per the value field for the requested element(s).
>
> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Hi; Coverity points out a problem with this code (CID 1540008, 1540009):
> +static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
> + SpaprMachineState *spapr,
> + target_ulong *args,
> + bool set)
> +{
> + target_ulong flags = args[0];
> + target_ulong lpid = args[1];
> + target_ulong vcpuid = args[2];
> + target_ulong buf = args[3];
> + target_ulong buflen = args[4];
> + struct guest_state_request gsr;
> + SpaprMachineStateNestedGuest *guest;
> +
> + guest = spapr_get_nested_guest(spapr, lpid);
> + if (!guest) {
> + return H_P2;
> + }
> + gsr.buf = buf;
> + assert(buflen <= GSB_MAX_BUF_SIZE);
> + gsr.len = buflen;
> + gsr.flags = 0;
> + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
flags is a target_ulong, which means it might only be 32 bits.
But H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE has a bit set in the
upper 32 bits only. So Coverity complains about this condition
being always-zero and the body of the if being dead code.
What was the intention here?
> + gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
> + }
> + if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
> + return H_PARAMETER; /* flag not supported yet */
> + }
> +
> + if (set) {
> + gsr.flags |= GUEST_STATE_REQUEST_SET;
> + }
> + return map_and_getset_state(cpu, guest, vcpuid, &gsr);
> +}
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-26 16:02 ` Peter Maydell
@ 2024-03-27 5:41 ` Harsh Prateek Bora
2024-03-27 8:05 ` Thomas Huth
2024-03-28 15:25 ` Peter Maydell
0 siblings, 2 replies; 46+ messages in thread
From: Harsh Prateek Bora @ 2024-03-27 5:41 UTC (permalink / raw)
To: Peter Maydell, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Michael Neuling
On 3/26/24 21:32, Peter Maydell wrote:
> On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> From: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>
>> Introduce the nested PAPR hcalls:
>> - H_GUEST_GET_STATE which is used to get state of a nested guest or
>> a guest VCPU. The value field for each element in the request is
>> destination to be updated to reflect current state on success.
>> - H_GUEST_SET_STATE which is used to modify the state of a guest or
>> a guest VCPU. On success, guest (or its VCPU) state shall be
>> updated as per the value field for the requested element(s).
>>
>> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>> Signed-off-by: Michael Neuling <mikey@neuling.org>
>> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
> Hi; Coverity points out a problem with this code (CID 1540008, 1540009):
>
>
>
>> +static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
>> + SpaprMachineState *spapr,
>> + target_ulong *args,
>> + bool set)
>> +{
>> + target_ulong flags = args[0];
>> + target_ulong lpid = args[1];
>> + target_ulong vcpuid = args[2];
>> + target_ulong buf = args[3];
>> + target_ulong buflen = args[4];
>> + struct guest_state_request gsr;
>> + SpaprMachineStateNestedGuest *guest;
>> +
>> + guest = spapr_get_nested_guest(spapr, lpid);
>> + if (!guest) {
>> + return H_P2;
>> + }
>> + gsr.buf = buf;
>> + assert(buflen <= GSB_MAX_BUF_SIZE);
>> + gsr.len = buflen;
>> + gsr.flags = 0;
>> + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
>
> flags is a target_ulong, which means it might only be 32 bits.
> But H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE has a bit set in the
> upper 32 bits only. So Coverity complains about this condition
> being always-zero and the body of the if being dead code.
>
> What was the intention here?
Hi Peter,
Ideally this is intended to be running on a ppc64 where target_ulong
should be uint64_t. I guess same holds true for existing nested-hv code
as well.
Hi Nick,
Do you think keeping both nested APIs (i.e. entire spapr_nested.c)
within #ifdef TARGET_PPC64 would be a better choice here?
regards,
Harsh
>
>> + gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
>> + }
>> + if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
>> + return H_PARAMETER; /* flag not supported yet */
>> + }
>> +
>> + if (set) {
>> + gsr.flags |= GUEST_STATE_REQUEST_SET;
>> + }
>> + return map_and_getset_state(cpu, guest, vcpuid, &gsr);
>> +}
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-27 5:41 ` Harsh Prateek Bora
@ 2024-03-27 8:05 ` Thomas Huth
2024-03-28 15:25 ` Peter Maydell
1 sibling, 0 replies; 46+ messages in thread
From: Thomas Huth @ 2024-03-27 8:05 UTC (permalink / raw)
To: Harsh Prateek Bora, Peter Maydell, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Michael Neuling
On 27/03/2024 06.41, Harsh Prateek Bora wrote:
>
>
> On 3/26/24 21:32, Peter Maydell wrote:
>> On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin <npiggin@gmail.com> wrote:
>>>
>>> From: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>>
>>> Introduce the nested PAPR hcalls:
>>> - H_GUEST_GET_STATE which is used to get state of a nested guest or
>>> a guest VCPU. The value field for each element in the request is
>>> destination to be updated to reflect current state on success.
>>> - H_GUEST_SET_STATE which is used to modify the state of a guest or
>>> a guest VCPU. On success, guest (or its VCPU) state shall be
>>> updated as per the value field for the requested element(s).
>>>
>>> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>>> Signed-off-by: Michael Neuling <mikey@neuling.org>
>>> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>>
>> Hi; Coverity points out a problem with this code (CID 1540008, 1540009):
>>
>>
>>
>>> +static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
>>> + SpaprMachineState *spapr,
>>> + target_ulong *args,
>>> + bool set)
>>> +{
>>> + target_ulong flags = args[0];
>>> + target_ulong lpid = args[1];
>>> + target_ulong vcpuid = args[2];
>>> + target_ulong buf = args[3];
>>> + target_ulong buflen = args[4];
>>> + struct guest_state_request gsr;
>>> + SpaprMachineStateNestedGuest *guest;
>>> +
>>> + guest = spapr_get_nested_guest(spapr, lpid);
>>> + if (!guest) {
>>> + return H_P2;
>>> + }
>>> + gsr.buf = buf;
>>> + assert(buflen <= GSB_MAX_BUF_SIZE);
>>> + gsr.len = buflen;
>>> + gsr.flags = 0;
>>> + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
>>
>> flags is a target_ulong, which means it might only be 32 bits.
>> But H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE has a bit set in the
>> upper 32 bits only. So Coverity complains about this condition
>> being always-zero and the body of the if being dead code.
>>
>> What was the intention here?
>
> Hi Peter,
> Ideally this is intended to be running on a ppc64 where target_ulong
> should be uint64_t. I guess same holds true for existing nested-hv code
> as well.
>
> Hi Nick,
> Do you think keeping both nested APIs (i.e. entire spapr_nested.c)
> within #ifdef TARGET_PPC64 would be a better choice here?
spapr_numa.c is only included with CONFIG_PSERIES in hw/ppc/meson.build, so
that should already take care that this code is only compiled with a 64-bit
target ... Can we somehow teach Coverity to take that into consideration?
Thomas
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-27 5:41 ` Harsh Prateek Bora
2024-03-27 8:05 ` Thomas Huth
@ 2024-03-28 15:25 ` Peter Maydell
2024-03-29 3:53 ` Harsh Prateek Bora
1 sibling, 1 reply; 46+ messages in thread
From: Peter Maydell @ 2024-03-28 15:25 UTC (permalink / raw)
To: Harsh Prateek Bora
Cc: Nicholas Piggin, qemu-devel, qemu-ppc, Daniel Henrique Barboza,
Michael Neuling
On Wed, 27 Mar 2024 at 05:41, Harsh Prateek Bora <harshpb@linux.ibm.com> wrote:
>
>
>
> On 3/26/24 21:32, Peter Maydell wrote:
> > On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin <npiggin@gmail.com> wrote:
> >>
> >> From: Harsh Prateek Bora <harshpb@linux.ibm.com>
> >>
> >> Introduce the nested PAPR hcalls:
> >> - H_GUEST_GET_STATE which is used to get state of a nested guest or
> >> a guest VCPU. The value field for each element in the request is
> >> destination to be updated to reflect current state on success.
> >> - H_GUEST_SET_STATE which is used to modify the state of a guest or
> >> a guest VCPU. On success, guest (or its VCPU) state shall be
> >> updated as per the value field for the requested element(s).
> >>
> >> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
> >> Signed-off-by: Michael Neuling <mikey@neuling.org>
> >> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> >
> > Hi; Coverity points out a problem with this code (CID 1540008, 1540009):
> >
> >
> >
> >> +static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
> >> + SpaprMachineState *spapr,
> >> + target_ulong *args,
> >> + bool set)
> >> +{
> >> + target_ulong flags = args[0];
> >> + target_ulong lpid = args[1];
> >> + target_ulong vcpuid = args[2];
> >> + target_ulong buf = args[3];
> >> + target_ulong buflen = args[4];
> >> + struct guest_state_request gsr;
> >> + SpaprMachineStateNestedGuest *guest;
> >> +
> >> + guest = spapr_get_nested_guest(spapr, lpid);
> >> + if (!guest) {
> >> + return H_P2;
> >> + }
> >> + gsr.buf = buf;
> >> + assert(buflen <= GSB_MAX_BUF_SIZE);
> >> + gsr.len = buflen;
> >> + gsr.flags = 0;
> >> + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
> >
> > flags is a target_ulong, which means it might only be 32 bits.
> > But H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE has a bit set in the
> > upper 32 bits only. So Coverity complains about this condition
> > being always-zero and the body of the if being dead code.
> >
> > What was the intention here?
>
> Hi Peter,
> Ideally this is intended to be running on a ppc64 where target_ulong
> should be uint64_t. I guess same holds true for existing nested-hv code
> as well.
Sorry, I'm afraid I misread the Coverity report here;
sorry for the confusion. The 32-vs-64 bits question is a red
herring.
What Coverity is actually pointing out is in this next bit:
> >> + gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
> >> + }
> >> + if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
The C operator ! is the logical-NOT operator; since
H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE is a non-zero value
that means that !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE is 0;
so we're testing (flags & 0), which is always false, and this
is the if() body which is dead-code as a result.
Should this be the bitwise-NOT ~ (ie "if any flag other
than this one is set"), or should this be an else clause
to the previous if() (ie "if this flag is not set") ?
> >> + return H_PARAMETER; /* flag not supported yet */
> >> + }
> >> +
> >> + if (set) {
> >> + gsr.flags |= GUEST_STATE_REQUEST_SET;
> >> + }
> >> + return map_and_getset_state(cpu, guest, vcpuid, &gsr);
> >> +}
> >
thanks
-- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls.
2024-03-28 15:25 ` Peter Maydell
@ 2024-03-29 3:53 ` Harsh Prateek Bora
0 siblings, 0 replies; 46+ messages in thread
From: Harsh Prateek Bora @ 2024-03-29 3:53 UTC (permalink / raw)
To: Peter Maydell
Cc: Nicholas Piggin, qemu-devel, qemu-ppc, Daniel Henrique Barboza,
Michael Neuling
On 3/28/24 20:55, Peter Maydell wrote:
> On Wed, 27 Mar 2024 at 05:41, Harsh Prateek Bora <harshpb@linux.ibm.com> wrote:
>>
>>
>>
>> On 3/26/24 21:32, Peter Maydell wrote:
>>> On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin <npiggin@gmail.com> wrote:
>>>>
>>>> From: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>>>
>>>> Introduce the nested PAPR hcalls:
>>>> - H_GUEST_GET_STATE which is used to get state of a nested guest or
>>>> a guest VCPU. The value field for each element in the request is
>>>> destination to be updated to reflect current state on success.
>>>> - H_GUEST_SET_STATE which is used to modify the state of a guest or
>>>> a guest VCPU. On success, guest (or its VCPU) state shall be
>>>> updated as per the value field for the requested element(s).
>>>>
>>>> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>>>> Signed-off-by: Michael Neuling <mikey@neuling.org>
>>>> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>>>
>>> Hi; Coverity points out a problem with this code (CID 1540008, 1540009):
>>>
>>>
>>>
>>>> +static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
>>>> + SpaprMachineState *spapr,
>>>> + target_ulong *args,
>>>> + bool set)
>>>> +{
>>>> + target_ulong flags = args[0];
>>>> + target_ulong lpid = args[1];
>>>> + target_ulong vcpuid = args[2];
>>>> + target_ulong buf = args[3];
>>>> + target_ulong buflen = args[4];
>>>> + struct guest_state_request gsr;
>>>> + SpaprMachineStateNestedGuest *guest;
>>>> +
>>>> + guest = spapr_get_nested_guest(spapr, lpid);
>>>> + if (!guest) {
>>>> + return H_P2;
>>>> + }
>>>> + gsr.buf = buf;
>>>> + assert(buflen <= GSB_MAX_BUF_SIZE);
>>>> + gsr.len = buflen;
>>>> + gsr.flags = 0;
>>>> + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
>>>
>>> flags is a target_ulong, which means it might only be 32 bits.
>>> But H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE has a bit set in the
>>> upper 32 bits only. So Coverity complains about this condition
>>> being always-zero and the body of the if being dead code.
>>>
>>> What was the intention here?
>>
>> Hi Peter,
>> Ideally this is intended to be running on a ppc64 where target_ulong
>> should be uint64_t. I guess same holds true for existing nested-hv code
>> as well.
>
> Sorry, I'm afraid I misread the Coverity report here;
> sorry for the confusion. The 32-vs-64 bits question is a red
> herring.
>
> What Coverity is actually pointing out is in this next bit:
>
>>>> + gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
>>>> + }
>>>> + if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
>
> The C operator ! is the logical-NOT operator; since
> H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE is a non-zero value
> that means that !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE is 0;
> so we're testing (flags & 0), which is always false, and this
> is the if() body which is dead-code as a result.
>
> Should this be the bitwise-NOT ~ (ie "if any flag other
> than this one is set"), or should this be an else clause
> to the previous if() (ie "if this flag is not set") ?
Oh, this should have been bitwise-NOT, I shall send a follow-up patch
for the fix.
regards,
Harsh
>
>>>> + return H_PARAMETER; /* flag not supported yet */
>>>> + }
>>>> +
>>>> + if (set) {
>>>> + gsr.flags |= GUEST_STATE_REQUEST_SET;
>>>> + }
>>>> + return map_and_getset_state(cpu, guest, vcpuid, &gsr);
>>>> +}
>>>
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2024-03-29 3:55 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-12 16:58 [PULL 00/38] ppc-for-9.0-2 queue Nicholas Piggin
2024-03-12 16:58 ` [PULL 01/38] target/ppc: Fix GDB SPR regnum indexing Nicholas Piggin
2024-03-12 16:58 ` [PULL 02/38] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-03-12 16:58 ` [PULL 03/38] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
2024-03-12 16:58 ` [PULL 04/38] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
2024-03-12 16:58 ` [PULL 05/38] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-03-12 16:58 ` [PULL 06/38] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
2024-03-12 16:58 ` [PULL 07/38] ppc/spapr: Remove copy-paste " Nicholas Piggin
2024-03-12 16:58 ` [PULL 08/38] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-03-12 16:58 ` [PULL 09/38] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-03-12 16:58 ` [PULL 10/38] ppc/pnv: Permit ibm,pa-features set per machine variant Nicholas Piggin
2024-03-12 16:58 ` [PULL 11/38] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-03-12 16:58 ` [PULL 12/38] MAINTAINERS: Remove myself as reviewer from PPC Nicholas Piggin
2024-03-12 16:58 ` [PULL 13/38] docs: Deprecate the pseries-2.12 machines Nicholas Piggin
2024-03-12 16:58 ` [PULL 14/38] docs/system/ppc: Document running Linux on AmigaNG machines Nicholas Piggin
2024-03-12 16:58 ` [PULL 15/38] target/ppc: Move add and subf type fixed-point arithmetic instructions to decodetree Nicholas Piggin
2024-03-12 16:58 ` [PULL 16/38] target/ppc: Add power10 pmu SPRs Nicholas Piggin
2024-03-12 16:58 ` [PULL 17/38] ppc/pnv: Improve pervasive topology calculation for big-core Nicholas Piggin
2024-03-12 16:58 ` [PULL 18/38] target/ppc: Use env_cpu for cpu_abort in excp_helper Nicholas Piggin
2024-03-12 16:58 ` [PULL 19/38] target/ppc: Readability improvements in exception handlers Nicholas Piggin
2024-03-12 16:58 ` [PULL 20/38] target/ppc: Add gen_exception_err_nip() function Nicholas Piggin
2024-03-12 16:58 ` [PULL 21/38] target/ppc: Clean up ifdefs in excp_helper.c, part 1 Nicholas Piggin
2024-03-12 16:58 ` [PULL 22/38] target/ppc: Clean up ifdefs in excp_helper.c, part 2 Nicholas Piggin
2024-03-12 16:58 ` [PULL 23/38] target/ppc: Clean up ifdefs in excp_helper.c, part 3 Nicholas Piggin
2024-03-12 16:58 ` [PULL 24/38] target/ppc: Remove interrupt handler wrapper functions Nicholas Piggin
2024-03-12 16:58 ` [PULL 25/38] spapr: nested: register nested-hv api hcalls only for cap-nested-hv Nicholas Piggin
2024-03-12 16:58 ` [PULL 26/38] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c Nicholas Piggin
2024-03-12 16:58 ` [PULL 27/38] spapr: nested: Introduce SpaprMachineStateNested to store related info Nicholas Piggin
2024-03-12 16:58 ` [PULL 28/38] spapr: nested: keep nested-hv related code restricted to its API Nicholas Piggin
2024-03-12 16:58 ` [PULL 29/38] spapr: nested: Document Nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 30/38] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls Nicholas Piggin
2024-03-12 16:58 ` [PULL 31/38] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls Nicholas Piggin
2024-03-12 16:58 ` [PULL 32/38] spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall Nicholas Piggin
2024-03-12 16:58 ` [PULL 33/38] spapr: nested: Extend nested_ppc_state for nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 34/38] spapr: nested: Initialize the GSB elements lookup table Nicholas Piggin
2024-03-12 16:58 ` [PULL 35/38] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls Nicholas Piggin
2024-03-26 16:02 ` Peter Maydell
2024-03-27 5:41 ` Harsh Prateek Bora
2024-03-27 8:05 ` Thomas Huth
2024-03-28 15:25 ` Peter Maydell
2024-03-29 3:53 ` Harsh Prateek Bora
2024-03-12 16:58 ` [PULL 36/38] spapr: nested: Use correct source for parttbl info for nested PAPR API Nicholas Piggin
2024-03-12 16:58 ` [PULL 37/38] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall Nicholas Piggin
2024-03-12 16:58 ` [PULL 38/38] spapr: nested: Introduce cap-nested-papr for Nested PAPR API Nicholas Piggin
2024-03-12 19:29 ` [PULL 00/38] ppc-for-9.0-2 queue Bernhard Beschow
2024-03-13 15:10 ` Peter Maydell
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