* [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN}
@ 2024-03-15 17:03 Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 1/3] memory: renesas-rpc-if: Clear HS bit during hardware initialization Lad Prabhakar
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Lad Prabhakar @ 2024-03-15 17:03 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
Hi All,
This patch series adds RPC-IF support for RZ/G2{EHMN} SoCs. Note by
default the RPC-IF is not enabled on the boards as the hyperflash is
locked by TF-A. To unlock the hyperflash one must build TF-A with
"RCAR_RPC_HYPERFLASH_LOCKED=0" flag and enable it in the board DTS.
Note: All the patches have been cherry picked from upstream kernel.
Cheers,
Prabhakar
Adam Ford (1):
arm64: dts: renesas: rzg2: Add RPC-IF Support
Cong Dang (2):
memory: renesas-rpc-if: Clear HS bit during hardware initialization
memory: renesas-rpc-if: Remove redundant division of dummy
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 17 +++++++++++++++++
drivers/memory/renesas-rpc-if.c | 6 ++++--
5 files changed, 72 insertions(+), 2 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5.10.y-cip 1/3] memory: renesas-rpc-if: Clear HS bit during hardware initialization
2024-03-15 17:03 [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Lad Prabhakar
@ 2024-03-15 17:03 ` Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 2/3] memory: renesas-rpc-if: Remove redundant division of dummy Lad Prabhakar
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Lad Prabhakar @ 2024-03-15 17:03 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Cong Dang <cong.dang.xn@renesas.com>
commit 5192481f908e576be42bd39ec12979b79e11f7e0 upstream.
According to the datasheet, HS bit should be specified to 1 when using
DMA transfer. As DMA transfer is not supported, it should be cleared to
0.
Previously, the driver relied on the HS bit being cleared by prior
firmware but this is not always the case.
Fix this by ensuring the bit is cleared during hardware initialization.
Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/08d9fb10b3051decebf871267a6e2e7cb2d4faf9.1665583089.git.geert+renesas@glider.be
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/memory/renesas-rpc-if.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 6a096a033651..598180b2adaf 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -318,6 +318,9 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
+ /* DMA Transfer is not supported */
+ regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
+
if (rpc->type == RPCIF_RCAR_GEN3)
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5.10.y-cip 2/3] memory: renesas-rpc-if: Remove redundant division of dummy
2024-03-15 17:03 [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 1/3] memory: renesas-rpc-if: Clear HS bit during hardware initialization Lad Prabhakar
@ 2024-03-15 17:03 ` Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 3/3] arm64: dts: renesas: rzg2: Add RPC-IF Support Lad Prabhakar
2024-03-18 11:39 ` [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Pavel Machek
3 siblings, 0 replies; 6+ messages in thread
From: Lad Prabhakar @ 2024-03-15 17:03 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Cong Dang <cong.dang.xn@renesas.com>
commit 637581ce60403a27712c657453a210c8fd17cc66 upstream.
The dummy cycles value was wrongly calculated if dummy.buswidth > 1,
which affects QSPI, OSPI, HyperFlash on various SoCs. We're lucky in
Single SPI case since its dummy.buswidth equals to 1, so the result of
the division is unchanged
This issue can be reproduced using something like the following commands
A. QSPI mode: Mount device with jffs2 format
jffs2: CLEANMARKER node found at 0x00000004, not first node in block (0x00000000)
B. QSPI mode: Write data to mtd10, where mtd10 is a parition on SPI Flash
storage, defined properly in a device tree
[Correct fragment, read from SPI Flash]
root@v3x:~# echo "hello" > /dev/mtd10
root@v3x:~# hexdump -C -n100 /dev/mtd10
00000000 68 65 6c 6c 6f 0a ff ff ff ff ff ff ff ff ff ff |hello...........|
00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
[Incorrect read of the same fragment: see the difference at offsets 0-3]
root@v3x:~# echo "hello" > /dev/mtd10
root@v3x:~# hexdump -C -n100 /dev/mtd10
00000000 00 00 00 00 68 65 6c 6c 6f 0a ff ff ff ff ff ff |....hello.......|
00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
As seen from the result, 4 NULL bytes were inserted before the test data.
Wrong calculation in rpcif_prepare() led to miss of some dummy cycle. A
division by bus width is redundant because it had been performed already
in spi-rpc-if.c::rpcif_spi_mem_prepare()
Fix this by removing the redundant division.
Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver")
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20230112090655.43367-1-wsa+renesas@sang-engineering.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230207173051.449151-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/memory/renesas-rpc-if.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 598180b2adaf..2e5a0117585f 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -427,8 +427,7 @@ void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
if (op->dummy.buswidth) {
rpc->enable |= RPCIF_SMENR_DME;
- rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
- op->dummy.buswidth);
+ rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles);
}
if (op->option.buswidth) {
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5.10.y-cip 3/3] arm64: dts: renesas: rzg2: Add RPC-IF Support
2024-03-15 17:03 [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 1/3] memory: renesas-rpc-if: Clear HS bit during hardware initialization Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 2/3] memory: renesas-rpc-if: Remove redundant division of dummy Lad Prabhakar
@ 2024-03-15 17:03 ` Lad Prabhakar
2024-03-18 11:39 ` [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Pavel Machek
3 siblings, 0 replies; 6+ messages in thread
From: Lad Prabhakar @ 2024-03-15 17:03 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
From: Adam Ford <aford173@gmail.com>
commit 8811955d0a6d0abfa3e1c0cee30090fda0015069 upstream.
The RZ/G2 series contain the SPI Multi I/O Bus Controller (RPC-IF).
Add the nodes, but make them disabled by default.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20210102115412.3402059-4-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 17 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 17 +++++++++++++++++
4 files changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index a5ebe574fbac..2e427f21130d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2318,6 +2318,23 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774a1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 20003a41a706..5b05474dc272 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2175,6 +2175,23 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774b1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sata: sata@ee300000 {
compatible = "renesas,sata-r8a774b1",
"renesas,rcar-gen3-sata";
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index c4a6dfae93aa..36e80e781352 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1651,6 +1651,23 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774c0-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 2e6c12a46daf..8eb006cbd9af 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -2408,6 +2408,23 @@ sdhi3: mmc@ee160000 {
status = "disabled";
};
+ rpc: spi@ee200000 {
+ compatible = "renesas,r8a774e1-rpc-if",
+ "renesas,rcar-gen3-rpc-if";
+ reg = <0 0xee200000 0 0x200>,
+ <0 0x08000000 0 0x4000000>,
+ <0 0xee208000 0 0x100>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sata: sata@ee300000 {
compatible = "renesas,sata-r8a774e1",
"renesas,rcar-gen3-sata";
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN}
2024-03-15 17:03 [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Lad Prabhakar
` (2 preceding siblings ...)
2024-03-15 17:03 ` [PATCH 5.10.y-cip 3/3] arm64: dts: renesas: rzg2: Add RPC-IF Support Lad Prabhakar
@ 2024-03-18 11:39 ` Pavel Machek
2024-03-19 11:10 ` Pavel Machek
3 siblings, 1 reply; 6+ messages in thread
From: Pavel Machek @ 2024-03-18 11:39 UTC (permalink / raw)
To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 723 bytes --]
Hi!
> This patch series adds RPC-IF support for RZ/G2{EHMN} SoCs. Note by
> default the RPC-IF is not enabled on the boards as the hyperflash is
> locked by TF-A. To unlock the hyperflash one must build TF-A with
> "RCAR_RPC_HYPERFLASH_LOCKED=0" flag and enable it in the board DTS.
>
> Note: All the patches have been cherry picked from upstream kernel.
The series looks ok to me, thank you. I can apply it if it passes
testing and if there are no other comments. I guess this should be
applied before corresponding 4.19 patch.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN}
2024-03-18 11:39 ` [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Pavel Machek
@ 2024-03-19 11:10 ` Pavel Machek
0 siblings, 0 replies; 6+ messages in thread
From: Pavel Machek @ 2024-03-19 11:10 UTC (permalink / raw)
To: Pavel Machek; +Cc: Lad Prabhakar, cip-dev, Nobuhiro Iwamatsu, Biju Das
[-- Attachment #1: Type: text/plain, Size: 766 bytes --]
Hi!
> > This patch series adds RPC-IF support for RZ/G2{EHMN} SoCs. Note by
> > default the RPC-IF is not enabled on the boards as the hyperflash is
> > locked by TF-A. To unlock the hyperflash one must build TF-A with
> > "RCAR_RPC_HYPERFLASH_LOCKED=0" flag and enable it in the board DTS.
> >
> > Note: All the patches have been cherry picked from upstream kernel.
>
> The series looks ok to me, thank you. I can apply it if it passes
> testing and if there are no other comments. I guess this should be
> applied before corresponding 4.19 patch.
Thank you, applied.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-03-19 11:10 UTC | newest]
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2024-03-15 17:03 [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 1/3] memory: renesas-rpc-if: Clear HS bit during hardware initialization Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 2/3] memory: renesas-rpc-if: Remove redundant division of dummy Lad Prabhakar
2024-03-15 17:03 ` [PATCH 5.10.y-cip 3/3] arm64: dts: renesas: rzg2: Add RPC-IF Support Lad Prabhakar
2024-03-18 11:39 ` [PATCH 5.10.y-cip 0/3] Add RPC-IF support for RZ/G2{EHMN} Pavel Machek
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