* [PATCH 00/12] Use clksel for more clocks for dra7
@ 2024-03-27 7:38 Tony Lindgren
2024-03-27 7:38 ` [PATCH 01/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE Tony Lindgren
` (12 more replies)
0 siblings, 13 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
Hi all,
This series of patches updates dra7 to use more clksel clocks.
This simplifies things for dealing with the remaining make W=1
dtbs unique_unit_address warnings.
After this series, dra7 is left with the following clocks that
should be updated:
- DPLL output related clksel registers that should be updated
to use clksel clocks to get rid of the remaining warnings
for unique_unit_address
- Read-only clkctrl clocks still mapped as composite clocks
and should be updated to use the clkctrl binding to drop
the use of the custom ti,bit-shift property
The DPLL output clocks are problematic at this point as the
clock driver makes assumptions based on no reg property in
_register_dpll_x2() for the ti,omap4-dpll-x2-clock. After
the driver issues are solved, the DPLL output related clocks
can also use the clksel binding.
Regards,
Tony
Tony Lindgren (12):
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB
ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0
arch/arm/boot/dts/ti/omap/dra76x.dtsi | 63 +++--
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 270 +++++++++++++------
2 files changed, 220 insertions(+), 113 deletions(-)
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 01/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 02/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP Tony Lindgren
` (11 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -285,13 +285,21 @@ dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
ti,invert-autoidle-bit;
};
- dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_core_byp_mux";
- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x012c>;
+ /* CM_CLKSEL_DPLL_CORE */
+ clock@12c {
+ compatible = "ti,clksel";
+ reg = <0x12c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_core_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_core_byp_mux";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ #clock-cells = <0>;
+ };
};
dpll_core_ck: clock@120 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 02/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
2024-03-27 7:38 ` [PATCH 01/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 03/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA Tony Lindgren
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -376,13 +376,21 @@ dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
clock-div = <1>;
};
- dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_dsp_byp_mux";
- clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x0240>;
+ /* CM_CLKSEL_DPLL_DSP */
+ clock@240 {
+ compatible = "ti,clksel";
+ reg = <0x240>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_dsp_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_dsp_byp_mux";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ #clock-cells = <0>;
+ };
};
dpll_dsp_ck: clock@234 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 03/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
2024-03-27 7:38 ` [PATCH 01/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE Tony Lindgren
2024-03-27 7:38 ` [PATCH 02/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 04/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU Tony Lindgren
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -426,13 +426,21 @@ iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
clock-div = <1>;
};
- dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_iva_byp_mux";
- clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x01ac>;
+ /* CM_CLKSEL_DPLL_IVA */
+ clock@1ac {
+ compatible = "ti,clksel";
+ reg = <0x1ac>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_iva_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_iva_byp_mux";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ #clock-cells = <0>;
+ };
};
dpll_iva_ck: clock@1a0 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 04/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (2 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 03/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 05/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR Tony Lindgren
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -476,13 +476,21 @@ iva_dclk: clock-iva-dclk {
clock-div = <1>;
};
- dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_gpu_byp_mux";
- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x02e4>;
+ /* CM_CLKSEL_DPLL_GPU */
+ clock@2e4 {
+ compatible = "ti,clksel";
+ reg = <0x2e4>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_gpu_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gpu_byp_mux";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ #clock-cells = <0>;
+ };
};
dpll_gpu_ck: clock@2d8 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 05/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (3 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 04/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 06/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC Tony Lindgren
` (7 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -538,13 +538,21 @@ core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
clock-div = <1>;
};
- dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_ddr_byp_mux";
- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x021c>;
+ /* CM_CLKSEL_DPLL_DDR */
+ clock@21c {
+ compatible = "ti,clksel";
+ reg = <0x21c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_ddr_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_ddr_byp_mux";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ #clock-cells = <0>;
+ };
};
dpll_ddr_ck: clock@210 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 06/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (4 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 05/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 07/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE Tony Lindgren
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -575,13 +575,21 @@ dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
ti,invert-autoidle-bit;
};
- dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_gmac_byp_mux";
- clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x02b4>;
+ /* CM_CLKSEL_DPLL_GMAC */
+ clock@2b4 {
+ compatible = "ti,clksel";
+ reg = <0x2b4>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_gmac_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_gmac_byp_mux";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ #clock-cells = <0>;
+ };
};
dpll_gmac_ck: clock@2a8 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 07/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (5 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 06/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 08/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE Tony Lindgren
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -666,13 +666,21 @@ eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
clock-div = <1>;
};
- dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_eve_byp_mux";
- clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x0290>;
+ /* CM_CLKSEL_DPLL_EVE */
+ clock@290 {
+ compatible = "ti,clksel";
+ reg = <0x290>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_eve_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_eve_byp_mux";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ #clock-cells = <0>;
+ };
};
dpll_eve_ck: clock@284 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 08/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (6 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 07/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 09/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS Tony Lindgren
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 26 +++++++++++++-------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -894,15 +894,23 @@ hdmi_div_clk: clock-hdmi-div {
clock-div = <1>;
};
- l3_iclk_div: clock-l3-iclk-div-4@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "l3_iclk_div";
- ti,max-div = <2>;
- ti,bit-shift = <4>;
- reg = <0x0100>;
- clocks = <&dpll_core_h12x2_ck>;
- ti,index-power-of-two;
+ /* CM_CLKSEL_CORE */
+ clock@100 {
+ compatible = "ti,clksel";
+ reg = <0x100>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ l3_iclk_div: clock@4 {
+ reg = <4>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "l3_iclk_div";
+ ti,max-div = <2>;
+ clocks = <&dpll_core_h12x2_ck>;
+ ti,index-power-of-two;
+ #clock-cells = <0>;
+ };
};
l4_root_clk_div: clock-l4-root-clk-div {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (7 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 08/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 10/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER Tony Lindgren
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 21 ++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -975,12 +975,21 @@ sys_clkin1: clock-sys-clkin1@110 {
ti,index-starts-at-one;
};
- abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "abe_dpll_sys_clk_mux";
- clocks = <&sys_clkin1>, <&sys_clkin2>;
- reg = <0x0118>;
+ /* CM_CLKSEL_ABE_PLL_SYS */
+ clock@118 {
+ compatible = "ti,clksel";
+ reg = <0x118>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ abe_dpll_sys_clk_mux: clock@0 {
+ reg = <0>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "abe_dpll_sys_clk_mux";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ #clock-cells = <0>;
+ };
};
abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 10/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (8 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 09/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 11/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB Tony Lindgren
` (2 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -1399,13 +1399,21 @@ apll_pcie_m2_ck: clock-apll-pcie-m2 {
clock-div = <1>;
};
- dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_per_byp_mux";
- clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x014c>;
+ /* CM_CLKSEL_DPLL_PER */
+ clock@14c {
+ compatible = "ti,clksel";
+ reg = <0x14c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_per_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_per_byp_mux";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ #clock-cells = <0>;
+ };
};
dpll_per_ck: clock@140 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 11/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (9 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 10/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-27 7:38 ` [PATCH 12/12] ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 Tony Lindgren
2024-03-28 11:31 ` [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 47 +++++++++++++-------
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -1091,14 +1091,23 @@ per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
ti,index-power-of-two;
};
- dsp_gclk_div: clock-dsp-gclk-div@18c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "dsp_gclk_div";
- clocks = <&dpll_dsp_m2_ck>;
- ti,max-div = <64>;
- reg = <0x018c>;
- ti,index-power-of-two;
+ /* CM_CLKSEL_DPLL_USB */
+ clock@18c {
+ compatible = "ti,clksel";
+ reg = <0x18c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsp_gclk_div: clock@0 {
+ reg = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dsp_gclk_div";
+ clocks = <&dpll_dsp_m2_ck>;
+ ti,max-div = <64>;
+ ti,index-power-of-two;
+ #clock-cells = <0>;
+ };
};
gpu_dclk: clock-gpu-dclk@1a0 {
@@ -1445,13 +1454,21 @@ func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
clock-div = <1>;
};
- dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clock-output-names = "dpll_usb_byp_mux";
- clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x018c>;
+ /* CM_CLKSEL_DPLL_USB */
+ clock@18c {
+ compatible = "ti,clksel";
+ reg = <0x18c>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_usb_byp_mux: clock@23 {
+ reg = <23>;
+ compatible = "ti,mux-clock";
+ clock-output-names = "dpll_usb_byp_mux";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ #clock-cells = <0>;
+ };
};
dpll_usb_ck: clock@180 {
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 12/12] ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (10 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 11/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB Tony Lindgren
@ 2024-03-27 7:38 ` Tony Lindgren
2024-03-28 11:31 ` [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
12 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-03-27 7:38 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
On dra76x, most dpll_gmac output clksel clocks are in registers from
CM_CLKSEL_DPLL_GMAC to CM_DIV_H13_DPLL_GMAC. In addition to that, there
are there more clocks in the CTRL_CORE_SMA_SW_0 register.
Let's group the CTRL_CORE_SMA_SW_0 clocks using the clksel binding to
reduce make W=1 dtbs unique_unit_address warnings, and stop using the
custom the ti,bit-shift property in favor of the standard reg property.
Let's also add a comment for the CTRL_CORE_SMA_SW_0 clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/ti/omap/dra76x.dtsi | 63 +++++++++++++++------------
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra76x.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra76x.dtsi
@@ -84,35 +84,44 @@ csi2_1: port@1 {
};
&scm_conf_clocks {
- dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_gmac_x2_ck>;
- ti,max-div = <63>;
- reg = <0x03fc>;
- ti,bit-shift = <20>;
- ti,latch-bit = <26>;
- assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
- assigned-clock-rates = <80000000>;
- };
-
- dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+ /* CTRL_CORE_SMA_SW_0 */
+ clock@3fc {
+ compatible = "ti,clksel";
reg = <0x3fc>;
- ti,bit-shift = <29>;
- ti,latch-bit = <26>;
- assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
- assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
- };
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- mcan_clk: mcan_clk@3fc {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
- ti,bit-shift = <27>;
- reg = <0x3fc>;
+ dpll_gmac_h14x2_ctrl_ck: clock@20 {
+ reg = <20>;
+ clock-output-names = "dpll_gmac_h14x2_ctrl_ck";
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,latch-bit = <26>;
+ assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
+ assigned-clock-rates = <80000000>;
+ #clock-cells = <0>;
+ };
+
+ mcan_clk: clock@27 {
+ reg = <27>;
+ clock-output-names = "mcan_clk";
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+ #clock-cells = <0>;
+ };
+
+ dpll_gmac_h14x2_ctrl_mux_ck: clock@29 {
+ reg = <29>;
+ clock-output-names = "dpll_gmac_h14x2_ctrl_mux_ck";
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+ ti,latch-bit = <26>;
+ assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+ assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
+ #clock-cells = <0>;
+ };
};
};
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/12] Use clksel for more clocks for dra7
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
` (11 preceding siblings ...)
2024-03-27 7:38 ` [PATCH 12/12] ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 Tony Lindgren
@ 2024-03-28 11:31 ` Tony Lindgren
2024-04-03 8:43 ` Tony Lindgren
12 siblings, 1 reply; 15+ messages in thread
From: Tony Lindgren @ 2024-03-28 11:31 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
* Tony Lindgren <tony@atomide.com> [240327 09:39]:
> The DPLL output clocks are problematic at this point as the
> clock driver makes assumptions based on no reg property in
> _register_dpll_x2() for the ti,omap4-dpll-x2-clock. After
> the driver issues are solved, the DPLL output related clocks
> can also use the clksel binding.
Actually the driver needs changes only for clocks where there's no
reg entry. For the clocks with a reg entry like dpll_per m2 outputs,
the following seems to work based on light testing.
Regards,
Tony
8< -----------------
diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -1425,6 +1425,7 @@ dpll_per_byp_mux: clock@23 {
};
};
+ /* CM_CLKSEL_DPLL_PER */
dpll_per_ck: clock@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
@@ -1433,16 +1434,43 @@ dpll_per_ck: clock@140 {
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
- dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "dpll_per_m2_ck";
- clocks = <&dpll_per_ck>;
- ti,max-div = <31>;
- ti,autoidle-shift = <8>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- ti,invert-autoidle-bit;
+ /* CM_DIV_M2_DPLL_PER */
+ clock@150 {
+ compatible = "ti,clksel";
+ reg = <0x150>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpll_per_m2x2_ck: clock@0 {
+ reg = <0>;
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clock-output-names = "dpll_per_m2x2_ck";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m2_ck: clock@8 {
+ compatible = "fixed-factor-clock";
+ reg = <8>;
+ #clock-cells = <0>;
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "dpll_per_m2_ck";
+ };
+
+ dpll_per_x2_ck: clock@10 {
+ reg = <10>;
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clock-output-names = "dpll_per_x2_ck";
+ clocks = <&dpll_per_ck>;
+ };
};
func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
@@ -1503,13 +1531,6 @@ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
ti,invert-autoidle-bit;
};
- dpll_per_x2_ck: clock-dpll-per-x2 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clock-output-names = "dpll_per_x2_ck";
- clocks = <&dpll_per_ck>;
- };
-
dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1558,18 +1579,6 @@ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
ti,invert-autoidle-bit;
};
- dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clock-output-names = "dpll_per_m2x2_ck";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- ti,autoidle-shift = <8>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- ti,invert-autoidle-bit;
- };
-
dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
--
2.44.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/12] Use clksel for more clocks for dra7
2024-03-28 11:31 ` [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
@ 2024-04-03 8:43 ` Tony Lindgren
0 siblings, 0 replies; 15+ messages in thread
From: Tony Lindgren @ 2024-04-03 8:43 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree
* Tony Lindgren <tony@atomide.com> [240328 11:31]:
> * Tony Lindgren <tony@atomide.com> [240327 09:39]:
> > The DPLL output clocks are problematic at this point as the
> > clock driver makes assumptions based on no reg property in
> > _register_dpll_x2() for the ti,omap4-dpll-x2-clock. After
> > the driver issues are solved, the DPLL output related clocks
> > can also use the clksel binding.
>
> Actually the driver needs changes only for clocks where there's no
> reg entry. For the clocks with a reg entry like dpll_per m2 outputs,
> the following seems to work based on light testing.
Oh but below dpll_per_x2_ck has no reg yet we now add the reg property.
Likely the additional patch below can't be used without driver changes
for _register_dpll_x2().
Regards,
Tony
> 8< -----------------
> diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
> --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
> @@ -1425,6 +1425,7 @@ dpll_per_byp_mux: clock@23 {
> };
> };
>
> + /* CM_CLKSEL_DPLL_PER */
> dpll_per_ck: clock@140 {
> #clock-cells = <0>;
> compatible = "ti,omap4-dpll-clock";
> @@ -1433,16 +1434,43 @@ dpll_per_ck: clock@140 {
> reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
> };
>
> - dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clock-output-names = "dpll_per_m2_ck";
> - clocks = <&dpll_per_ck>;
> - ti,max-div = <31>;
> - ti,autoidle-shift = <8>;
> - reg = <0x0150>;
> - ti,index-starts-at-one;
> - ti,invert-autoidle-bit;
> + /* CM_DIV_M2_DPLL_PER */
> + clock@150 {
> + compatible = "ti,clksel";
> + reg = <0x150>;
> + #clock-cells = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpll_per_m2x2_ck: clock@0 {
> + reg = <0>;
> + #clock-cells = <0>;
> + compatible = "ti,divider-clock";
> + clock-output-names = "dpll_per_m2x2_ck";
> + clocks = <&dpll_per_x2_ck>;
> + ti,max-div = <31>;
> + ti,autoidle-shift = <8>;
> + ti,index-starts-at-one;
> + ti,invert-autoidle-bit;
> + };
> +
> + dpll_per_m2_ck: clock@8 {
> + compatible = "fixed-factor-clock";
> + reg = <8>;
> + #clock-cells = <0>;
> + clocks = <&dpll_per_m2x2_ck>;
> + clock-mult = <1>;
> + clock-div = <2>;
> + clock-output-names = "dpll_per_m2_ck";
> + };
> +
> + dpll_per_x2_ck: clock@10 {
> + reg = <10>;
> + #clock-cells = <0>;
> + compatible = "ti,omap4-dpll-x2-clock";
> + clock-output-names = "dpll_per_x2_ck";
> + clocks = <&dpll_per_ck>;
> + };
> };
>
> func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
> @@ -1503,13 +1531,6 @@ dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
> ti,invert-autoidle-bit;
> };
>
> - dpll_per_x2_ck: clock-dpll-per-x2 {
> - #clock-cells = <0>;
> - compatible = "ti,omap4-dpll-x2-clock";
> - clock-output-names = "dpll_per_x2_ck";
> - clocks = <&dpll_per_ck>;
> - };
> -
> dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
> #clock-cells = <0>;
> compatible = "ti,divider-clock";
> @@ -1558,18 +1579,6 @@ dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
> ti,invert-autoidle-bit;
> };
>
> - dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
> - #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clock-output-names = "dpll_per_m2x2_ck";
> - clocks = <&dpll_per_x2_ck>;
> - ti,max-div = <31>;
> - ti,autoidle-shift = <8>;
> - reg = <0x0150>;
> - ti,index-starts-at-one;
> - ti,invert-autoidle-bit;
> - };
> -
> dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> --
> 2.44.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2024-04-03 8:43 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-27 7:38 [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
2024-03-27 7:38 ` [PATCH 01/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE Tony Lindgren
2024-03-27 7:38 ` [PATCH 02/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP Tony Lindgren
2024-03-27 7:38 ` [PATCH 03/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA Tony Lindgren
2024-03-27 7:38 ` [PATCH 04/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU Tony Lindgren
2024-03-27 7:38 ` [PATCH 05/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR Tony Lindgren
2024-03-27 7:38 ` [PATCH 06/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC Tony Lindgren
2024-03-27 7:38 ` [PATCH 07/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE Tony Lindgren
2024-03-27 7:38 ` [PATCH 08/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE Tony Lindgren
2024-03-27 7:38 ` [PATCH 09/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS Tony Lindgren
2024-03-27 7:38 ` [PATCH 10/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER Tony Lindgren
2024-03-27 7:38 ` [PATCH 11/12] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB Tony Lindgren
2024-03-27 7:38 ` [PATCH 12/12] ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 Tony Lindgren
2024-03-28 11:31 ` [PATCH 00/12] Use clksel for more clocks for dra7 Tony Lindgren
2024-04-03 8:43 ` Tony Lindgren
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