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* [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems
@ 2024-03-27 16:23 Alex Hung
  2024-03-27 16:23 ` [PATCH 2/3] lib/amd: Return false if dp_fec or dp_dsc is not supported Alex Hung
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Alex Hung @ 2024-03-27 16:23 UTC (permalink / raw)
  To: igt-dev
  Cc: rodrigo.siqueira, harry.wentland, hersenxs.wu, Alex Hung, Hersen Wu

Use "indent -linux" to fix code styles such as idententation and spaces.
Some manual fixes were also applied for consistency.

There are no funtional changes.

Reviewed-by: Hersen Wu <Hersenxs.Wu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
V2:
- Change "igt_output_t * output" to "igt_output_t *output"
- Limit lines to 100

 tests/amdgpu/amd_dp_dsc.c | 170 ++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 82 deletions(-)

diff --git a/tests/amdgpu/amd_dp_dsc.c b/tests/amdgpu/amd_dp_dsc.c
index e782ce84a..900182443 100644
--- a/tests/amdgpu/amd_dp_dsc.c
+++ b/tests/amdgpu/amd_dp_dsc.c
@@ -79,19 +79,19 @@ static void test_init(data_t *data)
 
 		/* Only allow physically connected displays for the tests. */
 		if (!igt_output_is_connected(output))
-				continue;
+			continue;
 
-		/* Ensure that outpus are DP, DSC & FEC capable*/
+		/* Ensure that outpus are DP, DSC & FEC capable */
 		if (!(is_dp_fec_supported(data->fd, output->name) &&
-			is_dp_dsc_supported(data->fd, output->name)))
+		      is_dp_dsc_supported(data->fd, output->name)))
 			continue;
 
-		if (output->config.connector->connector_type !=
-			DRM_MODE_CONNECTOR_DisplayPort)
+		if (output->config.connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 			continue;
 
-		igt_assert(kmstest_get_connector_default_mode(
-				data->fd, output->config.connector, &data->mode[n]));
+		igt_assert(kmstest_get_connector_default_mode(data->fd,
+							      output->config.connector,
+							      &data->mode[n]));
 
 		n += 1;
 	}
@@ -117,11 +117,11 @@ static void test_dsc_enable(data_t *data)
 			continue;
 
 		igt_create_pattern_fb(data->fd,
-					data->mode[i].hdisplay,
-					data->mode[i].vdisplay,
-					DRM_FORMAT_XRGB8888,
-					0,
-					&ref_fb);
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
@@ -144,11 +144,11 @@ static void test_dsc_enable(data_t *data)
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_OFF);
 
 		igt_plane_set_fb(data->primary[i], &ref_fb);
-		igt_display_commit_atomic(display,DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
 		dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
 
-		/* Revert DSC back to automatic mechanism by disabling state overwrites*/
+		/* Revert DSC back to automatic mechanism by disabling state overwrites */
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
@@ -166,13 +166,17 @@ static void test_dsc_enable(data_t *data)
 	igt_skip_on(test_conn_cnt == 0);
 }
 
-static bool update_slice_height(data_t *data, int v_addressable,
-					  int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+static bool update_slice_height(data_t *data,
+				int v_addressable,
+				int *num_slices,
+				igt_output_t *output,
+				int conn_idx,
+				igt_fb_t ref_fb)
 {
 	int i;
 	bool pass = true;
 
-	for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+	for (i = 0; i < NUM_SLICE_SLOTS; i++) {
 		int act_slice_height;
 		int slice_height = v_addressable / num_slices[i] + (v_addressable % num_slices[i]);
 
@@ -200,13 +204,17 @@ static bool update_slice_height(data_t *data, int v_addressable,
 	return pass;
 }
 
-static bool update_slice_width(data_t *data, int h_addressable,
-					  int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+static bool update_slice_width(data_t *data,
+			       int h_addressable,
+			       int *num_slices,
+			       igt_output_t *output,
+			       int conn_idx,
+			       igt_fb_t ref_fb)
 {
 	int i;
 	bool pass = true;
 
-	for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+	for (i = 0; i < NUM_SLICE_SLOTS; i++) {
 		int act_slice_width;
 		int slice_width = h_addressable / num_slices[i] + (h_addressable % num_slices[i]);
 
@@ -240,9 +248,9 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 	igt_output_t *output;
 	igt_display_t *display = &data->display;
 	igt_fb_t ref_fb;
-	int num_slices [] = { 1, 2, 4, 8 };
+	int num_slices[] = { 1, 2, 4, 8 };
 	int h_addressable, v_addressable;
-	bool ret_slice_height= false, ret_slice_width = false;
+	bool ret_slice_height = false, ret_slice_width = false;
 	int i, test_conn_cnt = 0;
 
 	test_init(data);
@@ -255,11 +263,11 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 			continue;
 
 		igt_create_pattern_fb(data->fd,
-					data->mode[i].hdisplay,
-					data->mode[i].vdisplay,
-					DRM_FORMAT_XRGB8888,
-					0,
-					&ref_fb);
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
@@ -296,7 +304,7 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 
 		dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
 
-		/* Revert DSC back to automatic mechanism by disabling state overwrites*/
+		/* Revert DSC back to automatic mechanism by disabling state overwrites */
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
@@ -321,43 +329,41 @@ static void test_dsc_link_settings(data_t *data)
 	igt_output_t *output;
 	igt_fb_t ref_fb[MAX_PIPES];
 	igt_crc_t ref_crc[MAX_PIPES], new_crc[MAX_PIPES];
-    int lane_count[4], link_rate[4], link_spread[4];
+	int lane_count[4], link_rate[4], link_spread[4];
 	igt_display_t *display = &data->display;
 	int i, lc, lr;
-    bool dsc_on;
-	const enum dc_lane_count lane_count_vals[] =
-	{
+	bool dsc_on;
+	const enum dc_lane_count lane_count_vals[] = {
 		LANE_COUNT_TWO,
 		LANE_COUNT_FOUR
 	};
-	const enum dc_link_rate link_rate_vals[] =
-	{
+	const enum dc_link_rate link_rate_vals[] = {
 		LINK_RATE_LOW,
 		LINK_RATE_HIGH,
 		LINK_RATE_HIGH2,
 		LINK_RATE_HIGH3
 	};
 
-    test_init(data);
+	test_init(data);
 
-    /* Setup all outputs */
+	/* Setup all outputs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
 		if (!output || !igt_output_is_connected(output))
 			continue;
 
-        igt_create_pattern_fb(data->fd,
-                    data->mode[i].hdisplay,
-                    data->mode[i].vdisplay,
-                    DRM_FORMAT_XRGB8888,
-                    0,
-                    &ref_fb[i]);
+		igt_create_pattern_fb(data->fd,
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb[i]);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb[i]);
 	}
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
 
-    /* Collect reference CRCs */
+	/* Collect reference CRCs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
 		if (!output || !igt_output_is_connected(output))
@@ -376,11 +382,11 @@ static void test_dsc_link_settings(data_t *data)
 
 				/* Write lower link settings */
 				igt_info("Applying lane count: %d, link rate 0x%02x, on default training\n",
-						lane_count_vals[lc], link_rate_vals[lr]);
+					 lane_count_vals[lc], link_rate_vals[lr]);
 				igt_amd_write_link_settings(data->fd, output->name,
-							lane_count_vals[lc],
-							link_rate_vals[lr],
-							LINK_TRAINING_DEFAULT);
+							    lane_count_vals[lc],
+							    link_rate_vals[lr],
+							    LINK_TRAINING_DEFAULT);
 				usleep(500 * MSEC_PER_SEC);
 			}
 
@@ -393,10 +399,11 @@ static void test_dsc_link_settings(data_t *data)
 					continue;
 
 				/* Verify lower link settings */
-				igt_amd_read_link_settings(data->fd, output->name,
-							lane_count,
-							link_rate,
-							link_spread);
+				igt_amd_read_link_settings(data->fd,
+							   output->name,
+							   lane_count,
+							   link_rate,
+							   link_spread);
 
 				igt_assert_f(lane_count[0] == lane_count_vals[lc], "Lowering lane count settings failed\n");
 				igt_assert_f(link_rate[0] == link_rate_vals[lr], "Lowering link rate settings failed\n");
@@ -404,10 +411,10 @@ static void test_dsc_link_settings(data_t *data)
 				/* Log current mode and DSC status */
 				dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
 				igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
-							data->mode[i].hdisplay,
-							data->mode[i].vdisplay,
-							data->mode[i].vrefresh,
-							dsc_on ? "ON" : "OFF");
+					 data->mode[i].hdisplay,
+					 data->mode[i].vdisplay,
+					 data->mode[i].vrefresh,
+					 dsc_on ? "ON" : "OFF");
 
 				igt_pipe_crc_collect_crc(data->pipe_crc[i], &new_crc[i]);
 				igt_assert_crc_equal(&ref_crc[i], &new_crc[i]);
@@ -423,7 +430,7 @@ static void test_dsc_link_settings(data_t *data)
 		igt_remove_fb(data->fd, &ref_fb[i]);
 	}
 
-    test_fini(data);
+	test_fini(data);
 }
 
 static void test_dsc_bpc(data_t *data)
@@ -433,10 +440,10 @@ static void test_dsc_bpc(data_t *data)
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
 	int i, bpc, max_supported_bpc[MAX_PIPES];
-    bool dsc_on;
-	const int bpc_vals[] = {12, 10, 8};
+	bool dsc_on;
+	const int bpc_vals[] = { 12, 10, 8 };
 
-    test_init(data);
+	test_init(data);
 
 	/* Find max supported bpc */
 	for_each_pipe(&data->display, i) {
@@ -447,7 +454,7 @@ static void test_dsc_bpc(data_t *data)
 		max_supported_bpc[i] = igt_get_output_max_bpc(data->fd, output->name);
 	}
 
-    /* Setup all outputs */
+	/* Setup all outputs */
 	for (bpc = 0; bpc < ARRAY_SIZE(bpc_vals); bpc++) {
 		igt_info("Testing bpc = %d\n", bpc_vals[bpc]);
 
@@ -463,11 +470,11 @@ static void test_dsc_bpc(data_t *data)
 			igt_info("Setting bpc = %d\n", bpc_vals[bpc]);
 			igt_output_set_prop_value(output, IGT_CONNECTOR_MAX_BPC, bpc_vals[bpc]);
 			igt_create_pattern_fb(data->fd,
-						data->mode[i].hdisplay,
-						data->mode[i].vdisplay,
-						DRM_FORMAT_XRGB8888,
-						0,
-						&ref_fb[i]);
+					      data->mode[i].hdisplay,
+					      data->mode[i].vdisplay,
+					      DRM_FORMAT_XRGB8888,
+					      0,
+					      &ref_fb[i]);
 			igt_output_set_pipe(output, data->pipe_id[i]);
 			igt_plane_set_fb(data->primary[i], &ref_fb[i]);
 		}
@@ -488,16 +495,18 @@ static void test_dsc_bpc(data_t *data)
 
 			/* Check current bpc */
 			igt_info("Verifying display %s has correct bpc\n", output->name);
-			igt_assert_output_bpc_equal(data->fd, data->pipe_id[i],
-						    output->name, bpc_vals[bpc]);
+			igt_assert_output_bpc_equal(data->fd,
+						    data->pipe_id[i],
+						    output->name,
+						    bpc_vals[bpc]);
 
 			/* Log current mode and DSC status */
 			dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
 			igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
-						data->mode[i].hdisplay,
-						data->mode[i].vdisplay,
-						data->mode[i].vrefresh,
-						dsc_on ? "ON" : "OFF");
+				 data->mode[i].hdisplay,
+				 data->mode[i].vdisplay,
+				 data->mode[i].vrefresh,
+				 dsc_on ? "ON" : "OFF");
 		}
 
 		/* Cleanup all fbs */
@@ -513,17 +522,15 @@ static void test_dsc_bpc(data_t *data)
 		}
 	}
 
-    test_fini(data);
+	test_fini(data);
 }
 
-igt_main
-{
+igt_main {
 	data_t data = { 0 };
 
 	igt_skip_on_simulation();
 
-	igt_fixture
-	{
+	igt_fixture {
 		data.fd = drm_open_driver_master(DRIVER_ANY);
 
 		igt_display_require(&data.display, data.fd);
@@ -536,22 +543,21 @@ igt_main
 
 	igt_describe("Forces DSC on/off & ensures it is reset properly");
 	igt_subtest("dsc-enable-basic")
-		    test_dsc_enable(&data);
+	    test_dsc_enable(&data);
 
 	igt_describe("Tests various DSC slice dimensions");
 	igt_subtest("dsc-slice-dimensions-change")
-		    test_dsc_slice_dimensions_change(&data);
+	    test_dsc_slice_dimensions_change(&data);
 
 	igt_describe("Tests various combinations of link_rate + lane_count and logs if DSC enabled/disabled");
 	igt_subtest("dsc-link-settings")
-		    test_dsc_link_settings(&data);
+	    test_dsc_link_settings(&data);
 
 	igt_describe("Tests different bpc settings and logs if DSC is enabled/disabled");
 	igt_subtest("dsc-bpc")
-			test_dsc_bpc(&data);
+	    test_dsc_bpc(&data);
 
-	igt_fixture
-	{
+	igt_fixture {
 		igt_reset_connectors();
 		igt_display_fini(&data.display);
 	}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 2/3] lib/amd: Return false if dp_fec or dp_dsc is not supported
  2024-03-27 16:23 [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Alex Hung
@ 2024-03-27 16:23 ` Alex Hung
  2024-03-27 16:23 ` [PATCH 3/3] tests/amdgpu/amd_dp_dsc: Check connector's dsc capability Alex Hung
  2024-03-27 17:57 ` ✓ CI.xeBAT: success for series starting with [1/3,V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Alex Hung @ 2024-03-27 16:23 UTC (permalink / raw)
  To: igt-dev
  Cc: rodrigo.siqueira, harry.wentland, hersenxs.wu, Alex Hung, Hersen Wu

Stop assertion but return accordingly when dp_fec or dp_dsc is
not supported.

Reviewed-by: Hersen Wu <Hersenxs.Wu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
V2: - Limit lines to 100

 lib/igt_amd.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/lib/igt_amd.c b/lib/igt_amd.c
index 623883dbc..c0c4dfc67 100644
--- a/lib/igt_amd.c
+++ b/lib/igt_amd.c
@@ -353,10 +353,11 @@ bool is_dp_dsc_supported(int drm_fd, char *connector_name)
 	}
 
 	ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_FEC_SUPPORT, buf, sizeof(buf));
-	close(fd);
+	if (ret < 0)
+		igt_info("Reading %s for connector %s failed.\n",
+			 DEBUGFS_DSC_FEC_SUPPORT, connector_name);
 
-	igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
-		     DEBUGFS_DSC_FEC_SUPPORT, connector_name);
+	close(fd);
 
 	return strstr(buf, "DSC_Sink_Support: yes");
 }
@@ -380,10 +381,11 @@ bool is_dp_fec_supported(int drm_fd, char *connector_name)
 	}
 
 	ret = igt_debugfs_simple_read(fd, DEBUGFS_DSC_FEC_SUPPORT, buf, sizeof(buf));
-	close(fd);
+	if (ret < 0)
+		igt_info("Reading %s for connector %s failed.\n",
+			 DEBUGFS_DSC_FEC_SUPPORT, connector_name);
 
-	igt_assert_f(ret >= 0, "Reading %s for connector %s failed.\n",
-		     DEBUGFS_DSC_FEC_SUPPORT, connector_name);
+	close(fd);
 
 	return strstr(buf, "FEC_Sink_Support: yes");
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 3/3] tests/amdgpu/amd_dp_dsc: Check connector's dsc capability
  2024-03-27 16:23 [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Alex Hung
  2024-03-27 16:23 ` [PATCH 2/3] lib/amd: Return false if dp_fec or dp_dsc is not supported Alex Hung
@ 2024-03-27 16:23 ` Alex Hung
  2024-03-27 17:57 ` ✓ CI.xeBAT: success for series starting with [1/3,V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Alex Hung @ 2024-03-27 16:23 UTC (permalink / raw)
  To: igt-dev
  Cc: rodrigo.siqueira, harry.wentland, hersenxs.wu, Alex Hung, Hersen Wu

test_init() only sets data->mode when an output is DSC capable. As a
result, it is necessary to check it before running each subtest.

Reviewed-by: Hersen Wu <Hersenxs.Wu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
V2: Limit lines to 100

 tests/amdgpu/amd_dp_dsc.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/tests/amdgpu/amd_dp_dsc.c b/tests/amdgpu/amd_dp_dsc.c
index 900182443..13c4452da 100644
--- a/tests/amdgpu/amd_dp_dsc.c
+++ b/tests/amdgpu/amd_dp_dsc.c
@@ -99,6 +99,15 @@ static void test_init(data_t *data)
 	igt_display_reset(display);
 }
 
+static bool is_dsc_capable(drmModeModeInfo *mode)
+{
+	/* mode is not set in test_init() if it is dsc capable */
+	if (mode->hdisplay == 0 || mode->vdisplay == 0)
+		return false;
+
+	return true;
+}
+
 static void test_dsc_enable(data_t *data)
 {
 	bool dsc_on, dsc_after, dsc_before;
@@ -113,7 +122,7 @@ static void test_dsc_enable(data_t *data)
 	for_each_pipe(&data->display, i) {
 		/* Setup the output */
 		output = data->output[i];
-		if (!output || !igt_output_is_connected(output))
+		if (!output || !igt_output_is_connected(output) || !is_dsc_capable(&data->mode[i]))
 			continue;
 
 		igt_create_pattern_fb(data->fd,
@@ -259,7 +268,7 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 	for_each_pipe(&data->display, i) {
 		/* Setup the output */
 		output = data->output[i];
-		if (!output || !igt_output_is_connected(output))
+		if (!output || !igt_output_is_connected(output) || !is_dsc_capable(&data->mode[i]))
 			continue;
 
 		igt_create_pattern_fb(data->fd,
@@ -349,7 +358,7 @@ static void test_dsc_link_settings(data_t *data)
 	/* Setup all outputs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
-		if (!output || !igt_output_is_connected(output))
+		if (!output || !igt_output_is_connected(output) || !is_dsc_capable(&data->mode[i]))
 			continue;
 
 		igt_create_pattern_fb(data->fd,
@@ -366,7 +375,7 @@ static void test_dsc_link_settings(data_t *data)
 	/* Collect reference CRCs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
-		if (!output || !igt_output_is_connected(output))
+		if (!output || !igt_output_is_connected(output) || !is_dsc_capable(&data->mode[i]))
 			continue;
 
 		igt_pipe_crc_collect_crc(data->pipe_crc[i], &ref_crc[i]);
@@ -377,7 +386,8 @@ static void test_dsc_link_settings(data_t *data)
 			/* Write new link_settings */
 			for_each_pipe(&data->display, i) {
 				output = data->output[i];
-				if (!output || !igt_output_is_connected(output))
+				if (!output || !igt_output_is_connected(output) ||
+				    !is_dsc_capable(&data->mode[i]))
 					continue;
 
 				/* Write lower link settings */
@@ -395,7 +405,8 @@ static void test_dsc_link_settings(data_t *data)
 
 			for_each_pipe(&data->display, i) {
 				output = data->output[i];
-				if (!output || !igt_output_is_connected(output))
+				if (!output || !igt_output_is_connected(output) ||
+				    !is_dsc_capable(&data->mode[i]))
 					continue;
 
 				/* Verify lower link settings */
@@ -425,8 +436,9 @@ static void test_dsc_link_settings(data_t *data)
 	/* Cleanup all fbs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
-		if (!output || !igt_output_is_connected(output))
+		if (!output || !igt_output_is_connected(output) || !is_dsc_capable(&data->mode[i]))
 			continue;
+
 		igt_remove_fb(data->fd, &ref_fb[i]);
 	}
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* ✓ CI.xeBAT: success for series starting with [1/3,V2] tests/amdgpu/amd_dp_dsc: Correct code style problems
  2024-03-27 16:23 [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Alex Hung
  2024-03-27 16:23 ` [PATCH 2/3] lib/amd: Return false if dp_fec or dp_dsc is not supported Alex Hung
  2024-03-27 16:23 ` [PATCH 3/3] tests/amdgpu/amd_dp_dsc: Check connector's dsc capability Alex Hung
@ 2024-03-27 17:57 ` Patchwork
  2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2024-03-27 17:57 UTC (permalink / raw)
  To: Alex Hung; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 3891 bytes --]

== Series Details ==

Series: series starting with [1/3,V2] tests/amdgpu/amd_dp_dsc: Correct code style problems
URL   : https://patchwork.freedesktop.org/series/131696/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_7786_BAT -> XEIGTPW_10931_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (5 -> 4)
------------------------------

  Missing    (1): bat-lnl-1 

Known issues
------------

  Here are the changes found in XEIGTPW_10931_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_evict@evict-beng-small-external:
    - bat-dg2-oem2:       [SKIP][1] ([Intel XE#1130]) -> [PASS][2] +13 other tests pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_evict@evict-beng-small-external.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_evict@evict-beng-small-external.html

  * igt@xe_module_load@load:
    - bat-dg2-oem2:       [FAIL][3] ([Intel XE#1132]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@xe_evict@evict-beng-mixed-threads-small-multi-vm:
    - bat-dg2-oem2:       [SKIP][5] ([Intel XE#1130]) -> [TIMEOUT][6] ([Intel XE#1027] / [Intel XE#1088])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_evict@evict-beng-mixed-threads-small-multi-vm.html

  * igt@xe_evict@evict-beng-small:
    - bat-dg2-oem2:       [SKIP][7] ([Intel XE#1130]) -> [DMESG-WARN][8] ([Intel XE#1373])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_evict@evict-beng-small.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_evict@evict-beng-small.html

  * igt@xe_evict@evict-cm-threads-small:
    - bat-dg2-oem2:       [SKIP][9] ([Intel XE#1130]) -> [INCOMPLETE][10] ([Intel XE#1027] / [Intel XE#804])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_evict@evict-cm-threads-small.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_evict@evict-cm-threads-small.html

  * igt@xe_evict@evict-mixed-threads-small:
    - bat-dg2-oem2:       [SKIP][11] ([Intel XE#1130]) -> [INCOMPLETE][12] ([Intel XE#804])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7786/bat-dg2-oem2/igt@xe_evict@evict-mixed-threads-small.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/bat-dg2-oem2/igt@xe_evict@evict-mixed-threads-small.html

  
  [Intel XE#1027]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1027
  [Intel XE#1088]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1088
  [Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
  [Intel XE#1132]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1132
  [Intel XE#1373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1373
  [Intel XE#804]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/804


Build changes
-------------

  * IGT: IGT_7786 -> IGTPW_10931
  * Linux: xe-998-f9c56f1a03b5c35488671e4ffe61e28b12ffe163 -> xe-1001-0a8fdcee5ce9a43e8411ea096c7361f8ec7829ca

  IGTPW_10931: 10931
  IGT_7786: 1e4a3cd0a4bb3419fb70ed3e01259485b056dcfd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-1001-0a8fdcee5ce9a43e8411ea096c7361f8ec7829ca: 0a8fdcee5ce9a43e8411ea096c7361f8ec7829ca
  xe-998-f9c56f1a03b5c35488671e4ffe61e28b12ffe163: f9c56f1a03b5c35488671e4ffe61e28b12ffe163

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_10931/index.html

[-- Attachment #2: Type: text/html, Size: 5015 bytes --]

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems
@ 2024-03-27 16:27 Alex Hung
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Hung @ 2024-03-27 16:27 UTC (permalink / raw)
  To: igt-dev
  Cc: rodrigo.siqueira, harry.wentland, hersenxs.wu, Alex Hung, Hersen Wu

Use "indent -linux" to fix code styles such as idententation and spaces.
Some manual fixes were also applied for consistency.

There are no funtional changes.

Reviewed-by: Hersen Wu <Hersenxs.Wu@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
V2:
- Change "igt_output_t * output" to "igt_output_t *output"
- Limit lines to 100

 tests/amdgpu/amd_dp_dsc.c | 170 ++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 82 deletions(-)

diff --git a/tests/amdgpu/amd_dp_dsc.c b/tests/amdgpu/amd_dp_dsc.c
index e782ce84a..900182443 100644
--- a/tests/amdgpu/amd_dp_dsc.c
+++ b/tests/amdgpu/amd_dp_dsc.c
@@ -79,19 +79,19 @@ static void test_init(data_t *data)
 
 		/* Only allow physically connected displays for the tests. */
 		if (!igt_output_is_connected(output))
-				continue;
+			continue;
 
-		/* Ensure that outpus are DP, DSC & FEC capable*/
+		/* Ensure that outpus are DP, DSC & FEC capable */
 		if (!(is_dp_fec_supported(data->fd, output->name) &&
-			is_dp_dsc_supported(data->fd, output->name)))
+		      is_dp_dsc_supported(data->fd, output->name)))
 			continue;
 
-		if (output->config.connector->connector_type !=
-			DRM_MODE_CONNECTOR_DisplayPort)
+		if (output->config.connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 			continue;
 
-		igt_assert(kmstest_get_connector_default_mode(
-				data->fd, output->config.connector, &data->mode[n]));
+		igt_assert(kmstest_get_connector_default_mode(data->fd,
+							      output->config.connector,
+							      &data->mode[n]));
 
 		n += 1;
 	}
@@ -117,11 +117,11 @@ static void test_dsc_enable(data_t *data)
 			continue;
 
 		igt_create_pattern_fb(data->fd,
-					data->mode[i].hdisplay,
-					data->mode[i].vdisplay,
-					DRM_FORMAT_XRGB8888,
-					0,
-					&ref_fb);
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
@@ -144,11 +144,11 @@ static void test_dsc_enable(data_t *data)
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_FORCE_OFF);
 
 		igt_plane_set_fb(data->primary[i], &ref_fb);
-		igt_display_commit_atomic(display,DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
+		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
 
 		dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
 
-		/* Revert DSC back to automatic mechanism by disabling state overwrites*/
+		/* Revert DSC back to automatic mechanism by disabling state overwrites */
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
@@ -166,13 +166,17 @@ static void test_dsc_enable(data_t *data)
 	igt_skip_on(test_conn_cnt == 0);
 }
 
-static bool update_slice_height(data_t *data, int v_addressable,
-					  int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+static bool update_slice_height(data_t *data,
+				int v_addressable,
+				int *num_slices,
+				igt_output_t *output,
+				int conn_idx,
+				igt_fb_t ref_fb)
 {
 	int i;
 	bool pass = true;
 
-	for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+	for (i = 0; i < NUM_SLICE_SLOTS; i++) {
 		int act_slice_height;
 		int slice_height = v_addressable / num_slices[i] + (v_addressable % num_slices[i]);
 
@@ -200,13 +204,17 @@ static bool update_slice_height(data_t *data, int v_addressable,
 	return pass;
 }
 
-static bool update_slice_width(data_t *data, int h_addressable,
-					  int *num_slices, igt_output_t *output, int conn_idx, igt_fb_t ref_fb)
+static bool update_slice_width(data_t *data,
+			       int h_addressable,
+			       int *num_slices,
+			       igt_output_t *output,
+			       int conn_idx,
+			       igt_fb_t ref_fb)
 {
 	int i;
 	bool pass = true;
 
-	for(i = 0; i < NUM_SLICE_SLOTS; i++) {
+	for (i = 0; i < NUM_SLICE_SLOTS; i++) {
 		int act_slice_width;
 		int slice_width = h_addressable / num_slices[i] + (h_addressable % num_slices[i]);
 
@@ -240,9 +248,9 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 	igt_output_t *output;
 	igt_display_t *display = &data->display;
 	igt_fb_t ref_fb;
-	int num_slices [] = { 1, 2, 4, 8 };
+	int num_slices[] = { 1, 2, 4, 8 };
 	int h_addressable, v_addressable;
-	bool ret_slice_height= false, ret_slice_width = false;
+	bool ret_slice_height = false, ret_slice_width = false;
 	int i, test_conn_cnt = 0;
 
 	test_init(data);
@@ -255,11 +263,11 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 			continue;
 
 		igt_create_pattern_fb(data->fd,
-					data->mode[i].hdisplay,
-					data->mode[i].vdisplay,
-					DRM_FORMAT_XRGB8888,
-					0,
-					&ref_fb);
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 		igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
@@ -296,7 +304,7 @@ static void test_dsc_slice_dimensions_change(data_t *data)
 
 		dsc_after = igt_amd_read_dsc_clock_status(data->fd, output->name);
 
-		/* Revert DSC back to automatic mechanism by disabling state overwrites*/
+		/* Revert DSC back to automatic mechanism by disabling state overwrites */
 		igt_plane_set_fb(data->primary[i], &ref_fb);
 
 		igt_amd_write_dsc_clock_en(data->fd, output->name, DSC_AUTOMATIC);
@@ -321,43 +329,41 @@ static void test_dsc_link_settings(data_t *data)
 	igt_output_t *output;
 	igt_fb_t ref_fb[MAX_PIPES];
 	igt_crc_t ref_crc[MAX_PIPES], new_crc[MAX_PIPES];
-    int lane_count[4], link_rate[4], link_spread[4];
+	int lane_count[4], link_rate[4], link_spread[4];
 	igt_display_t *display = &data->display;
 	int i, lc, lr;
-    bool dsc_on;
-	const enum dc_lane_count lane_count_vals[] =
-	{
+	bool dsc_on;
+	const enum dc_lane_count lane_count_vals[] = {
 		LANE_COUNT_TWO,
 		LANE_COUNT_FOUR
 	};
-	const enum dc_link_rate link_rate_vals[] =
-	{
+	const enum dc_link_rate link_rate_vals[] = {
 		LINK_RATE_LOW,
 		LINK_RATE_HIGH,
 		LINK_RATE_HIGH2,
 		LINK_RATE_HIGH3
 	};
 
-    test_init(data);
+	test_init(data);
 
-    /* Setup all outputs */
+	/* Setup all outputs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
 		if (!output || !igt_output_is_connected(output))
 			continue;
 
-        igt_create_pattern_fb(data->fd,
-                    data->mode[i].hdisplay,
-                    data->mode[i].vdisplay,
-                    DRM_FORMAT_XRGB8888,
-                    0,
-                    &ref_fb[i]);
+		igt_create_pattern_fb(data->fd,
+				      data->mode[i].hdisplay,
+				      data->mode[i].vdisplay,
+				      DRM_FORMAT_XRGB8888,
+				      0,
+				      &ref_fb[i]);
 		igt_output_set_pipe(output, data->pipe_id[i]);
 		igt_plane_set_fb(data->primary[i], &ref_fb[i]);
 	}
 	igt_display_commit_atomic(display, DRM_MODE_ATOMIC_ALLOW_MODESET, 0);
 
-    /* Collect reference CRCs */
+	/* Collect reference CRCs */
 	for_each_pipe(&data->display, i) {
 		output = data->output[i];
 		if (!output || !igt_output_is_connected(output))
@@ -376,11 +382,11 @@ static void test_dsc_link_settings(data_t *data)
 
 				/* Write lower link settings */
 				igt_info("Applying lane count: %d, link rate 0x%02x, on default training\n",
-						lane_count_vals[lc], link_rate_vals[lr]);
+					 lane_count_vals[lc], link_rate_vals[lr]);
 				igt_amd_write_link_settings(data->fd, output->name,
-							lane_count_vals[lc],
-							link_rate_vals[lr],
-							LINK_TRAINING_DEFAULT);
+							    lane_count_vals[lc],
+							    link_rate_vals[lr],
+							    LINK_TRAINING_DEFAULT);
 				usleep(500 * MSEC_PER_SEC);
 			}
 
@@ -393,10 +399,11 @@ static void test_dsc_link_settings(data_t *data)
 					continue;
 
 				/* Verify lower link settings */
-				igt_amd_read_link_settings(data->fd, output->name,
-							lane_count,
-							link_rate,
-							link_spread);
+				igt_amd_read_link_settings(data->fd,
+							   output->name,
+							   lane_count,
+							   link_rate,
+							   link_spread);
 
 				igt_assert_f(lane_count[0] == lane_count_vals[lc], "Lowering lane count settings failed\n");
 				igt_assert_f(link_rate[0] == link_rate_vals[lr], "Lowering link rate settings failed\n");
@@ -404,10 +411,10 @@ static void test_dsc_link_settings(data_t *data)
 				/* Log current mode and DSC status */
 				dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
 				igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
-							data->mode[i].hdisplay,
-							data->mode[i].vdisplay,
-							data->mode[i].vrefresh,
-							dsc_on ? "ON" : "OFF");
+					 data->mode[i].hdisplay,
+					 data->mode[i].vdisplay,
+					 data->mode[i].vrefresh,
+					 dsc_on ? "ON" : "OFF");
 
 				igt_pipe_crc_collect_crc(data->pipe_crc[i], &new_crc[i]);
 				igt_assert_crc_equal(&ref_crc[i], &new_crc[i]);
@@ -423,7 +430,7 @@ static void test_dsc_link_settings(data_t *data)
 		igt_remove_fb(data->fd, &ref_fb[i]);
 	}
 
-    test_fini(data);
+	test_fini(data);
 }
 
 static void test_dsc_bpc(data_t *data)
@@ -433,10 +440,10 @@ static void test_dsc_bpc(data_t *data)
 	igt_crc_t test_crc;
 	igt_display_t *display = &data->display;
 	int i, bpc, max_supported_bpc[MAX_PIPES];
-    bool dsc_on;
-	const int bpc_vals[] = {12, 10, 8};
+	bool dsc_on;
+	const int bpc_vals[] = { 12, 10, 8 };
 
-    test_init(data);
+	test_init(data);
 
 	/* Find max supported bpc */
 	for_each_pipe(&data->display, i) {
@@ -447,7 +454,7 @@ static void test_dsc_bpc(data_t *data)
 		max_supported_bpc[i] = igt_get_output_max_bpc(data->fd, output->name);
 	}
 
-    /* Setup all outputs */
+	/* Setup all outputs */
 	for (bpc = 0; bpc < ARRAY_SIZE(bpc_vals); bpc++) {
 		igt_info("Testing bpc = %d\n", bpc_vals[bpc]);
 
@@ -463,11 +470,11 @@ static void test_dsc_bpc(data_t *data)
 			igt_info("Setting bpc = %d\n", bpc_vals[bpc]);
 			igt_output_set_prop_value(output, IGT_CONNECTOR_MAX_BPC, bpc_vals[bpc]);
 			igt_create_pattern_fb(data->fd,
-						data->mode[i].hdisplay,
-						data->mode[i].vdisplay,
-						DRM_FORMAT_XRGB8888,
-						0,
-						&ref_fb[i]);
+					      data->mode[i].hdisplay,
+					      data->mode[i].vdisplay,
+					      DRM_FORMAT_XRGB8888,
+					      0,
+					      &ref_fb[i]);
 			igt_output_set_pipe(output, data->pipe_id[i]);
 			igt_plane_set_fb(data->primary[i], &ref_fb[i]);
 		}
@@ -488,16 +495,18 @@ static void test_dsc_bpc(data_t *data)
 
 			/* Check current bpc */
 			igt_info("Verifying display %s has correct bpc\n", output->name);
-			igt_assert_output_bpc_equal(data->fd, data->pipe_id[i],
-						    output->name, bpc_vals[bpc]);
+			igt_assert_output_bpc_equal(data->fd,
+						    data->pipe_id[i],
+						    output->name,
+						    bpc_vals[bpc]);
 
 			/* Log current mode and DSC status */
 			dsc_on = igt_amd_read_dsc_clock_status(data->fd, output->name) == 1;
 			igt_info("Current mode is: %dx%d @%dHz -- DSC is: %s\n",
-						data->mode[i].hdisplay,
-						data->mode[i].vdisplay,
-						data->mode[i].vrefresh,
-						dsc_on ? "ON" : "OFF");
+				 data->mode[i].hdisplay,
+				 data->mode[i].vdisplay,
+				 data->mode[i].vrefresh,
+				 dsc_on ? "ON" : "OFF");
 		}
 
 		/* Cleanup all fbs */
@@ -513,17 +522,15 @@ static void test_dsc_bpc(data_t *data)
 		}
 	}
 
-    test_fini(data);
+	test_fini(data);
 }
 
-igt_main
-{
+igt_main {
 	data_t data = { 0 };
 
 	igt_skip_on_simulation();
 
-	igt_fixture
-	{
+	igt_fixture {
 		data.fd = drm_open_driver_master(DRIVER_ANY);
 
 		igt_display_require(&data.display, data.fd);
@@ -536,22 +543,21 @@ igt_main
 
 	igt_describe("Forces DSC on/off & ensures it is reset properly");
 	igt_subtest("dsc-enable-basic")
-		    test_dsc_enable(&data);
+	    test_dsc_enable(&data);
 
 	igt_describe("Tests various DSC slice dimensions");
 	igt_subtest("dsc-slice-dimensions-change")
-		    test_dsc_slice_dimensions_change(&data);
+	    test_dsc_slice_dimensions_change(&data);
 
 	igt_describe("Tests various combinations of link_rate + lane_count and logs if DSC enabled/disabled");
 	igt_subtest("dsc-link-settings")
-		    test_dsc_link_settings(&data);
+	    test_dsc_link_settings(&data);
 
 	igt_describe("Tests different bpc settings and logs if DSC is enabled/disabled");
 	igt_subtest("dsc-bpc")
-			test_dsc_bpc(&data);
+	    test_dsc_bpc(&data);
 
-	igt_fixture
-	{
+	igt_fixture {
 		igt_reset_connectors();
 		igt_display_fini(&data.display);
 	}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-03-27 17:57 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-27 16:23 [PATCH 1/3][V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Alex Hung
2024-03-27 16:23 ` [PATCH 2/3] lib/amd: Return false if dp_fec or dp_dsc is not supported Alex Hung
2024-03-27 16:23 ` [PATCH 3/3] tests/amdgpu/amd_dp_dsc: Check connector's dsc capability Alex Hung
2024-03-27 17:57 ` ✓ CI.xeBAT: success for series starting with [1/3,V2] tests/amdgpu/amd_dp_dsc: Correct code style problems Patchwork
2024-03-27 16:27 [PATCH 1/3][V2] " Alex Hung

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