* [PATCH 00/13] spi: add driver for Intel discrete graphics
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Add driver for access to Intel discrete graphics card
internal SPI device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide spi driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
series with connection to the Xe driver and splitting
the spi driver part to separate module in spi subsystem.
Alexander Usyskin (13):
spi: add auxiliary device for intel dg spi
drm/i915/spi: add spi device for discrete graphics
drm/i915/spi: add intel_spi_region map
drm/i915/spi: add support for access mode
spi: add driver for intel graphics on-die spi device
spi: intel-dg: implement region enumeration
spi: intel-dg: implement spi access functions
spi: intel-dg: spi register with mtd
spi: intel-dg: implement mtd access handlers
spi: intel-dg: align 64bit read and write
spi: intel-dg: wake card on operations
drm/xe/spi: add on-die spi device
drm/xe/spi: add support for access mode
drivers/gpu/drm/i915/Makefile | 4 +
drivers/gpu/drm/i915/i915_driver.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 97 +++
drivers/gpu/drm/i915/spi/intel_spi.h | 15 +
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5 +
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 5 +
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +-
drivers/gpu/drm/xe/xe_spi.c | 107 ++++
drivers/gpu/drm/xe/xe_spi.h | 15 +
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-intel-dg.c | 867 ++++++++++++++++++++++++++
include/linux/intel_dg_spi_aux.h | 27 +
17 files changed, 1170 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
create mode 100644 drivers/gpu/drm/xe/xe_spi.c
create mode 100644 drivers/gpu/drm/xe/xe_spi.h
create mode 100644 drivers/spi/spi-intel-dg.c
create mode 100644 include/linux/intel_dg_spi_aux.h
--
2.34.1
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 00/13] spi: add driver for Intel discrete graphics
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Add driver for access to Intel discrete graphics card
internal SPI device.
Expose device on auxiliary bus by i915 and Xe drivers and
provide spi driver to register this device with MTD framework.
This is a rewrite of "drm/i915/spi: spi access for discrete graphics"
series with connection to the Xe driver and splitting
the spi driver part to separate module in spi subsystem.
Alexander Usyskin (13):
spi: add auxiliary device for intel dg spi
drm/i915/spi: add spi device for discrete graphics
drm/i915/spi: add intel_spi_region map
drm/i915/spi: add support for access mode
spi: add driver for intel graphics on-die spi device
spi: intel-dg: implement region enumeration
spi: intel-dg: implement spi access functions
spi: intel-dg: spi register with mtd
spi: intel-dg: implement mtd access handlers
spi: intel-dg: align 64bit read and write
spi: intel-dg: wake card on operations
drm/xe/spi: add on-die spi device
drm/xe/spi: add support for access mode
drivers/gpu/drm/i915/Makefile | 4 +
drivers/gpu/drm/i915/i915_driver.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 97 +++
drivers/gpu/drm/i915/spi/intel_spi.h | 15 +
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5 +
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 5 +
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +-
drivers/gpu/drm/xe/xe_spi.c | 107 ++++
drivers/gpu/drm/xe/xe_spi.h | 15 +
drivers/spi/Kconfig | 11 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-intel-dg.c | 867 ++++++++++++++++++++++++++
include/linux/intel_dg_spi_aux.h | 27 +
17 files changed, 1170 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
create mode 100644 drivers/gpu/drm/xe/xe_spi.c
create mode 100644 drivers/gpu/drm/xe/xe_spi.h
create mode 100644 drivers/spi/spi-intel-dg.c
create mode 100644 include/linux/intel_dg_spi_aux.h
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 01/13] spi: add auxiliary device for intel dg spi
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Add auxilary bus device structure for
Intel Discrete Graphics SPI device.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 include/linux/intel_dg_spi_aux.h
diff --git a/include/linux/intel_dg_spi_aux.h b/include/linux/intel_dg_spi_aux.h
new file mode 100644
index 000000000000..d4c3830d56d6
--- /dev/null
+++ b/include/linux/intel_dg_spi_aux.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_DG_SPI_AUX_H__
+#define __INTEL_DG_SPI_AUX_H__
+
+#include <linux/auxiliary_bus.h>
+
+#define INTEL_DG_SPI_REGIONS 13
+
+struct intel_dg_spi_region {
+ const char *name;
+};
+
+struct intel_dg_spi_dev {
+ struct auxiliary_device aux_dev;
+ bool writeable_override;
+ struct resource bar;
+ const struct intel_dg_spi_region *regions;
+};
+
+#define auxiliary_dev_to_intel_dg_spi_dev(auxiliary_dev) \
+ container_of(auxiliary_dev, struct intel_dg_spi_dev, aux_dev)
+
+#endif /* __INTEL_DG_SPI_AUX_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 01/13] spi: add auxiliary device for intel dg spi
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Add auxilary bus device structure for
Intel Discrete Graphics SPI device.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 include/linux/intel_dg_spi_aux.h
diff --git a/include/linux/intel_dg_spi_aux.h b/include/linux/intel_dg_spi_aux.h
new file mode 100644
index 000000000000..d4c3830d56d6
--- /dev/null
+++ b/include/linux/intel_dg_spi_aux.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_DG_SPI_AUX_H__
+#define __INTEL_DG_SPI_AUX_H__
+
+#include <linux/auxiliary_bus.h>
+
+#define INTEL_DG_SPI_REGIONS 13
+
+struct intel_dg_spi_region {
+ const char *name;
+};
+
+struct intel_dg_spi_dev {
+ struct auxiliary_device aux_dev;
+ bool writeable_override;
+ struct resource bar;
+ const struct intel_dg_spi_region *regions;
+};
+
+#define auxiliary_dev_to_intel_dg_spi_dev(auxiliary_dev) \
+ container_of(auxiliary_dev, struct intel_dg_spi_dev, aux_dev)
+
+#endif /* __INTEL_DG_SPI_AUX_H__ */
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 02/13] drm/i915/spi: add spi device for discrete graphics
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Enable access to internal spi on DGFX devices via a child device.
The spi child device is exposed via auxiliary bus.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/i915_driver.c | 6 +++
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 64 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/spi/intel_spi.h | 15 +++++++
6 files changed, 94 insertions(+)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e777686190ca..2bd481862a48 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -239,6 +239,10 @@ i915-y += \
i915-y += \
gt/intel_gsc.o
+# graphics spi device (DGFX) support
+i915-y += \
+ spi/intel_spi.o
+
# graphics hardware monitoring (HWMON) support
i915-$(CONFIG_HWMON) += \
i915_hwmon.o
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c7d7c3b7ecc6..716fa20c52ce 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -81,6 +81,8 @@
#include "soc/intel_dram.h"
#include "soc/intel_gmch.h"
+#include "spi/intel_spi.h"
+
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drm_client.h"
@@ -619,6 +621,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
/* Depends on sysfs having been initialized */
i915_perf_register(dev_priv);
+ intel_spi_init(dev_priv);
+
for_each_gt(gt, dev_priv, i)
intel_gt_driver_register(gt);
@@ -662,6 +666,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
i915_hwmon_unregister(dev_priv);
+ intel_spi_fini(dev_priv);
+
i915_perf_unregister(dev_priv);
i915_pmu_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 861567362abd..e8e0d9ff4e66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -34,6 +34,8 @@
#include <linux/pm_qos.h>
+#include <linux/intel_dg_spi_aux.h>
+
#include <drm/ttm/ttm_device.h>
#include "display/intel_display_limits.h"
@@ -330,6 +332,8 @@ struct drm_i915_private {
struct i915_perf perf;
+ struct intel_dg_spi_dev spi;
+
struct i915_hwmon *hwmon;
struct intel_gt *gt[I915_MAX_GT];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..8b2935e384e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -928,6 +928,7 @@
#define DG2_GSC_HECI2_BASE 0x00374000
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
+#define GEN12_GUNIT_SPI_BASE 0x00102040
#define HECI_H_CSR(base) _MMIO((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
new file mode 100644
index 000000000000..17e4c7861ef5
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/irq.h>
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "spi/intel_spi.h"
+
+#define GEN12_GUNIT_SPI_SIZE 0x80
+
+static void i915_spi_release_dev(struct device *dev)
+{
+}
+
+void intel_spi_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_dg_spi_dev *spi = &dev_priv->spi;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(dev_priv))
+ return;
+
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = i915_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+}
+
+void intel_spi_fini(struct drm_i915_private *dev_priv)
+{
+ struct intel_dg_spi_dev *spi = &dev_priv->spi;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+
+ dev_dbg(&pdev->dev, "removing i915-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h b/drivers/gpu/drm/i915/spi/intel_spi.h
new file mode 100644
index 000000000000..ed4153401f5d
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_SPI_H__
+#define __INTEL_SPI_H__
+
+struct drm_i915_private;
+
+void intel_spi_init(struct drm_i915_private *i915);
+
+void intel_spi_fini(struct drm_i915_private *i915);
+
+#endif /* __INTEL_SPI_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 02/13] drm/i915/spi: add spi device for discrete graphics
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Enable access to internal spi on DGFX devices via a child device.
The spi child device is exposed via auxiliary bus.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/i915_driver.c | 6 +++
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/spi/intel_spi.c | 64 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/spi/intel_spi.h | 15 +++++++
6 files changed, 94 insertions(+)
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e777686190ca..2bd481862a48 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -239,6 +239,10 @@ i915-y += \
i915-y += \
gt/intel_gsc.o
+# graphics spi device (DGFX) support
+i915-y += \
+ spi/intel_spi.o
+
# graphics hardware monitoring (HWMON) support
i915-$(CONFIG_HWMON) += \
i915_hwmon.o
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c7d7c3b7ecc6..716fa20c52ce 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -81,6 +81,8 @@
#include "soc/intel_dram.h"
#include "soc/intel_gmch.h"
+#include "spi/intel_spi.h"
+
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drm_client.h"
@@ -619,6 +621,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
/* Depends on sysfs having been initialized */
i915_perf_register(dev_priv);
+ intel_spi_init(dev_priv);
+
for_each_gt(gt, dev_priv, i)
intel_gt_driver_register(gt);
@@ -662,6 +666,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
i915_hwmon_unregister(dev_priv);
+ intel_spi_fini(dev_priv);
+
i915_perf_unregister(dev_priv);
i915_pmu_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 861567362abd..e8e0d9ff4e66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -34,6 +34,8 @@
#include <linux/pm_qos.h>
+#include <linux/intel_dg_spi_aux.h>
+
#include <drm/ttm/ttm_device.h>
#include "display/intel_display_limits.h"
@@ -330,6 +332,8 @@ struct drm_i915_private {
struct i915_perf perf;
+ struct intel_dg_spi_dev spi;
+
struct i915_hwmon *hwmon;
struct intel_gt *gt[I915_MAX_GT];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27dc903f0553..8b2935e384e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -928,6 +928,7 @@
#define DG2_GSC_HECI2_BASE 0x00374000
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
+#define GEN12_GUNIT_SPI_BASE 0x00102040
#define HECI_H_CSR(base) _MMIO((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
new file mode 100644
index 000000000000..17e4c7861ef5
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/irq.h>
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "spi/intel_spi.h"
+
+#define GEN12_GUNIT_SPI_SIZE 0x80
+
+static void i915_spi_release_dev(struct device *dev)
+{
+}
+
+void intel_spi_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_dg_spi_dev *spi = &dev_priv->spi;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(dev_priv))
+ return;
+
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = i915_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "i915-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+}
+
+void intel_spi_fini(struct drm_i915_private *dev_priv)
+{
+ struct intel_dg_spi_dev *spi = &dev_priv->spi;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+
+ dev_dbg(&pdev->dev, "removing i915-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.h b/drivers/gpu/drm/i915/spi/intel_spi.h
new file mode 100644
index 000000000000..ed4153401f5d
--- /dev/null
+++ b/drivers/gpu/drm/i915/spi/intel_spi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_SPI_H__
+#define __INTEL_SPI_H__
+
+struct drm_i915_private;
+
+void intel_spi_init(struct drm_i915_private *i915);
+
+void intel_spi_fini(struct drm_i915_private *i915);
+
+#endif /* __INTEL_SPI_H__ */
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/13] drm/i915/spi: add intel_spi_region map
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Add the dGFX spi region map and convey it via auxiliary device
to the spi child device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 17e4c7861ef5..8dd4065551e2 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -11,6 +11,13 @@
#define GEN12_GUNIT_SPI_SIZE 0x80
+static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
static void i915_spi_release_dev(struct device *dev)
{
}
@@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv)
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
spi->bar.flags = IORESOURCE_MEM;
spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
aux_dev->name = "spi";
aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/13] drm/i915/spi: add intel_spi_region map
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Add the dGFX spi region map and convey it via auxiliary device
to the spi child device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 17e4c7861ef5..8dd4065551e2 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -11,6 +11,13 @@
#define GEN12_GUNIT_SPI_SIZE 0x80
+static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
static void i915_spi_release_dev(struct device *dev)
{
}
@@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv)
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
spi->bar.flags = IORESOURCE_MEM;
spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
aux_dev->name = "spi";
aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/13] drm/i915/spi: add support for access mode
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 8dd4065551e2..747e43313c6f 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -10,6 +10,7 @@
#include "spi/intel_spi.h"
#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
[0] = { .name = "DESCRIPTOR", },
@@ -22,6 +23,29 @@ static void i915_spi_release_dev(struct device *dev)
{
}
+static bool i915_spi_writeable_override(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ resource_size_t base;
+ bool writeable_override;
+
+ if (IS_DG1(dev_priv)) {
+ base = DG1_GSC_HECI2_BASE;
+ } else if (IS_DG2(dev_priv)) {
+ base = DG2_GSC_HECI2_BASE;
+ } else {
+ dev_err(&pdev->dev, "Unknown platform\n");
+ return true;
+ }
+
+ writeable_override =
+ !(intel_uncore_read(&dev_priv->uncore, HECI_FWSTS(base, 2)) &
+ HECI_FW_STATUS_2_SPI_ACCESS_MODE);
+ if (writeable_override)
+ dev_info(&pdev->dev, "SPI access overridden by jumper\n");
+ return writeable_override;
+}
+
void intel_spi_init(struct drm_i915_private *dev_priv)
{
struct intel_dg_spi_dev *spi = &dev_priv->spi;
@@ -33,6 +57,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv)
if (!IS_DGFX(dev_priv))
return;
+ spi->writeable_override = i915_spi_writeable_override(dev_priv);
spi->bar.parent = &pdev->resource[0];
spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/13] drm/i915/spi: add support for access mode
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c
index 8dd4065551e2..747e43313c6f 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi.c
@@ -10,6 +10,7 @@
#include "spi/intel_spi.h"
#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
[0] = { .name = "DESCRIPTOR", },
@@ -22,6 +23,29 @@ static void i915_spi_release_dev(struct device *dev)
{
}
+static bool i915_spi_writeable_override(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ resource_size_t base;
+ bool writeable_override;
+
+ if (IS_DG1(dev_priv)) {
+ base = DG1_GSC_HECI2_BASE;
+ } else if (IS_DG2(dev_priv)) {
+ base = DG2_GSC_HECI2_BASE;
+ } else {
+ dev_err(&pdev->dev, "Unknown platform\n");
+ return true;
+ }
+
+ writeable_override =
+ !(intel_uncore_read(&dev_priv->uncore, HECI_FWSTS(base, 2)) &
+ HECI_FW_STATUS_2_SPI_ACCESS_MODE);
+ if (writeable_override)
+ dev_info(&pdev->dev, "SPI access overridden by jumper\n");
+ return writeable_override;
+}
+
void intel_spi_init(struct drm_i915_private *dev_priv)
{
struct intel_dg_spi_dev *spi = &dev_priv->spi;
@@ -33,6 +57,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv)
if (!IS_DGFX(dev_priv))
return;
+ spi->writeable_override = i915_spi_writeable_override(dev_priv);
spi->bar.parent = &pdev->resource[0];
spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/13] spi: add driver for intel graphics on-die spi device
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
Add auxiliary driver for intel discrete graphics
on-die spi device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/Kconfig | 11 +++
drivers/spi/Makefile | 1 +
drivers/spi/spi-intel-dg.c | 146 +++++++++++++++++++++++++++++++++++++
3 files changed, 158 insertions(+)
create mode 100644 drivers/spi/spi-intel-dg.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ddae0fde798e..d84896e6e7a0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -507,6 +507,17 @@ config SPI_INTEL_PLATFORM
To compile this driver as a module, choose M here: the module
will be called spi-intel-platform.
+config SPI_INTEL_DG
+ tristate "Intel Discrete Graphic SPI flash driver"
+ depends on AUXILIARY_BUS || COMPILE_TEST
+ depends on MTD
+ help
+ This enables support for Intel Discrete Graphic SPI
+ auxiliary device.
+
+ To compile this driver as a module, choose M here: the module
+ will be called spi-intel-dg.
+
config SPI_JCORE
tristate "J-Core SPI Master"
depends on OF && (SUPERH || COMPILE_TEST)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e158761d6844 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_SPI_INGENIC) += spi-ingenic.o
obj-$(CONFIG_SPI_INTEL) += spi-intel.o
obj-$(CONFIG_SPI_INTEL_PCI) += spi-intel-pci.o
obj-$(CONFIG_SPI_INTEL_PLATFORM) += spi-intel-platform.o
+obj-$(CONFIG_SPI_INTEL_DG) += spi-intel-dg.o
obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
obj-$(CONFIG_SPI_LJCA) += spi-ljca.o
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
new file mode 100644
index 000000000000..8dc5448fc901
--- /dev/null
+++ b/drivers/spi/spi-intel-dg.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/device.h>
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+struct intel_dg_spi {
+ struct kref refcnt;
+ void __iomem *base;
+ size_t size;
+ unsigned int nregions;
+ struct {
+ const char *name;
+ u8 id;
+ u64 offset;
+ u64 size;
+ } regions[];
+};
+
+static void intel_dg_spi_release(struct kref *kref)
+{
+ struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
+ int i;
+
+ pr_debug("freeing spi memory\n");
+ for (i = 0; i < spi->nregions; i++)
+ kfree(spi->regions[i].name);
+ kfree(spi);
+}
+
+static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
+ const struct auxiliary_device_id *aux_dev_id)
+{
+ struct intel_dg_spi_dev *ispi = auxiliary_dev_to_intel_dg_spi_dev(aux_dev);
+ struct device *device;
+ struct intel_dg_spi *spi;
+ unsigned int nregions;
+ unsigned int i, n;
+ size_t size;
+ char *name;
+ size_t name_size;
+ int ret;
+
+ device = &aux_dev->dev;
+
+ /* count available regions */
+ for (nregions = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name)
+ nregions++;
+ }
+
+ if (!nregions) {
+ dev_err(device, "no regions defined\n");
+ return -ENODEV;
+ }
+
+ size = sizeof(*spi) + sizeof(spi->regions[0]) * nregions;
+ spi = kzalloc(size, GFP_KERNEL);
+ if (!spi)
+ return -ENOMEM;
+
+ kref_init(&spi->refcnt);
+
+ spi->nregions = nregions;
+ for (n = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name) {
+ name_size = strlen(dev_name(&aux_dev->dev)) +
+ strlen(ispi->regions[i].name) + 2; /* for point */
+ name = kzalloc(name_size, GFP_KERNEL);
+ if (!name)
+ continue;
+ snprintf(name, name_size, "%s.%s",
+ dev_name(&aux_dev->dev), ispi->regions[i].name);
+ spi->regions[n].name = name;
+ spi->regions[n].id = i;
+ n++;
+ }
+ }
+
+ spi->base = devm_ioremap_resource(device, &ispi->bar);
+ if (IS_ERR(spi->base)) {
+ dev_err(device, "mmio not mapped\n");
+ ret = PTR_ERR(spi->base);
+ goto err;
+ }
+
+ dev_set_drvdata(&aux_dev->dev, spi);
+
+ dev_dbg(device, "bound\n");
+
+ return 0;
+
+err:
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+ return ret;
+}
+
+static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
+{
+ struct intel_dg_spi *spi = dev_get_drvdata(&aux_dev->dev);
+
+ if (!spi)
+ return;
+
+ dev_set_drvdata(&aux_dev->dev, NULL);
+
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+}
+
+static const struct auxiliary_device_id intel_dg_spi_id_table[] = {
+ {
+ .name = "i915.spi",
+ },
+ {
+ .name = "xe.spi",
+ },
+ {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table);
+
+static struct auxiliary_driver intel_dg_spi_driver = {
+ .probe = intel_dg_spi_probe,
+ .remove = intel_dg_spi_remove,
+ .driver = {
+ /* auxiliary_driver_register() sets .name to be the modname */
+ },
+ .id_table = intel_dg_spi_id_table
+};
+
+module_auxiliary_driver(intel_dg_spi_driver);
+
+MODULE_ALIAS("auxiliary:i915.spi");
+MODULE_ALIAS("auxiliary:xe.spi");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("Intel DGFX SPI driver");
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 05/13] spi: add driver for intel graphics on-die spi device
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Tomas Winkler, Lucas De Marchi
Add auxiliary driver for intel discrete graphics
on-die spi device.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/Kconfig | 11 +++
drivers/spi/Makefile | 1 +
drivers/spi/spi-intel-dg.c | 146 +++++++++++++++++++++++++++++++++++++
3 files changed, 158 insertions(+)
create mode 100644 drivers/spi/spi-intel-dg.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ddae0fde798e..d84896e6e7a0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -507,6 +507,17 @@ config SPI_INTEL_PLATFORM
To compile this driver as a module, choose M here: the module
will be called spi-intel-platform.
+config SPI_INTEL_DG
+ tristate "Intel Discrete Graphic SPI flash driver"
+ depends on AUXILIARY_BUS || COMPILE_TEST
+ depends on MTD
+ help
+ This enables support for Intel Discrete Graphic SPI
+ auxiliary device.
+
+ To compile this driver as a module, choose M here: the module
+ will be called spi-intel-dg.
+
config SPI_JCORE
tristate "J-Core SPI Master"
depends on OF && (SUPERH || COMPILE_TEST)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..e158761d6844 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_SPI_INGENIC) += spi-ingenic.o
obj-$(CONFIG_SPI_INTEL) += spi-intel.o
obj-$(CONFIG_SPI_INTEL_PCI) += spi-intel-pci.o
obj-$(CONFIG_SPI_INTEL_PLATFORM) += spi-intel-platform.o
+obj-$(CONFIG_SPI_INTEL_DG) += spi-intel-dg.o
obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
obj-$(CONFIG_SPI_LJCA) += spi-ljca.o
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
new file mode 100644
index 000000000000..8dc5448fc901
--- /dev/null
+++ b/drivers/spi/spi-intel-dg.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/device.h>
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+struct intel_dg_spi {
+ struct kref refcnt;
+ void __iomem *base;
+ size_t size;
+ unsigned int nregions;
+ struct {
+ const char *name;
+ u8 id;
+ u64 offset;
+ u64 size;
+ } regions[];
+};
+
+static void intel_dg_spi_release(struct kref *kref)
+{
+ struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
+ int i;
+
+ pr_debug("freeing spi memory\n");
+ for (i = 0; i < spi->nregions; i++)
+ kfree(spi->regions[i].name);
+ kfree(spi);
+}
+
+static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
+ const struct auxiliary_device_id *aux_dev_id)
+{
+ struct intel_dg_spi_dev *ispi = auxiliary_dev_to_intel_dg_spi_dev(aux_dev);
+ struct device *device;
+ struct intel_dg_spi *spi;
+ unsigned int nregions;
+ unsigned int i, n;
+ size_t size;
+ char *name;
+ size_t name_size;
+ int ret;
+
+ device = &aux_dev->dev;
+
+ /* count available regions */
+ for (nregions = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name)
+ nregions++;
+ }
+
+ if (!nregions) {
+ dev_err(device, "no regions defined\n");
+ return -ENODEV;
+ }
+
+ size = sizeof(*spi) + sizeof(spi->regions[0]) * nregions;
+ spi = kzalloc(size, GFP_KERNEL);
+ if (!spi)
+ return -ENOMEM;
+
+ kref_init(&spi->refcnt);
+
+ spi->nregions = nregions;
+ for (n = 0, i = 0; i < INTEL_DG_SPI_REGIONS; i++) {
+ if (ispi->regions[i].name) {
+ name_size = strlen(dev_name(&aux_dev->dev)) +
+ strlen(ispi->regions[i].name) + 2; /* for point */
+ name = kzalloc(name_size, GFP_KERNEL);
+ if (!name)
+ continue;
+ snprintf(name, name_size, "%s.%s",
+ dev_name(&aux_dev->dev), ispi->regions[i].name);
+ spi->regions[n].name = name;
+ spi->regions[n].id = i;
+ n++;
+ }
+ }
+
+ spi->base = devm_ioremap_resource(device, &ispi->bar);
+ if (IS_ERR(spi->base)) {
+ dev_err(device, "mmio not mapped\n");
+ ret = PTR_ERR(spi->base);
+ goto err;
+ }
+
+ dev_set_drvdata(&aux_dev->dev, spi);
+
+ dev_dbg(device, "bound\n");
+
+ return 0;
+
+err:
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+ return ret;
+}
+
+static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
+{
+ struct intel_dg_spi *spi = dev_get_drvdata(&aux_dev->dev);
+
+ if (!spi)
+ return;
+
+ dev_set_drvdata(&aux_dev->dev, NULL);
+
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+}
+
+static const struct auxiliary_device_id intel_dg_spi_id_table[] = {
+ {
+ .name = "i915.spi",
+ },
+ {
+ .name = "xe.spi",
+ },
+ {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table);
+
+static struct auxiliary_driver intel_dg_spi_driver = {
+ .probe = intel_dg_spi_probe,
+ .remove = intel_dg_spi_remove,
+ .driver = {
+ /* auxiliary_driver_register() sets .name to be the modname */
+ },
+ .id_table = intel_dg_spi_id_table
+};
+
+module_auxiliary_driver(intel_dg_spi_driver);
+
+MODULE_ALIAS("auxiliary:i915.spi");
+MODULE_ALIAS("auxiliary:xe.spi");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("Intel DGFX SPI driver");
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/13] spi: intel-dg: implement region enumeration
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
In intel-dg spi, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 190 +++++++++++++++++++++++++++++++++++++
1 file changed, 190 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 8dc5448fc901..8ef9dccc9062 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -17,14 +17,197 @@ struct intel_dg_spi {
void __iomem *base;
size_t size;
unsigned int nregions;
+ u32 access_map;
struct {
const char *name;
u8 id;
u64 offset;
u64 size;
+ unsigned int is_readable:1;
+ unsigned int is_writable:1;
} regions[];
};
+#define SPI_TRIGGER_REG 0x00000000
+#define SPI_VALSIG_REG 0x00000010
+#define SPI_ADDRESS_REG 0x00000040
+#define SPI_REGION_ID_REG 0x00000044
+/*
+ * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
+ * [23:16]-Reserved
+ * [31:24]-Erase SPI RegionID
+ */
+#define SPI_ERASE_REG 0x00000048
+#define SPI_ACCESS_ERROR_REG 0x00000070
+#define SPI_ADDRESS_ERROR_REG 0x00000074
+
+/* Flash Valid Signature */
+#define SPI_FLVALSIG 0x0FF0A55A
+
+#define SPI_MAP_ADDR_MASK 0x000000FF
+#define SPI_MAP_ADDR_SHIFT 0x00000004
+
+#define REGION_ID_DESCRIPTOR 0
+/* Flash Region Base Address */
+#define FRBA 0x40
+/* Flash Region __n - Flash Descriptor Record */
+#define FLREG(__n) (FRBA + ((__n) * 4))
+/* Flash Map 1 Register */
+#define FLMAP1_REG 0x18
+#define FLMSTR4_OFFSET 0x00C
+
+#define SPI_ACCESS_ERROR_PCIE_MASK 0x7
+
+static inline void spi_set_region_id(struct intel_dg_spi *spi, u8 region)
+{
+ iowrite32((u32)region, spi->base + SPI_REGION_ID_REG);
+}
+
+static inline u32 spi_error(struct intel_dg_spi *spi)
+{
+ u32 reg = ioread32(spi->base + SPI_ACCESS_ERROR_REG) &
+ SPI_ACCESS_ERROR_PCIE_MASK;
+
+ /* reset error bits */
+ if (reg)
+ iowrite32(reg, spi->base + SPI_ACCESS_ERROR_REG);
+
+ return reg;
+}
+
+static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return ioread32(base + SPI_TRIGGER_REG);
+}
+
+static int spi_get_access_map(struct intel_dg_spi *spi)
+{
+ u32 flmap1;
+ u32 fmba;
+ u32 fmstr4;
+ u32 fmstr4_addr;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ flmap1 = spi_read32(spi, FLMAP1_REG);
+ if (spi_error(spi))
+ return -EIO;
+ /* Get Flash Master Baser Address (FMBA) */
+ fmba = ((flmap1 & SPI_MAP_ADDR_MASK) << SPI_MAP_ADDR_SHIFT);
+ fmstr4_addr = fmba + FLMSTR4_OFFSET;
+
+ fmstr4 = spi_read32(spi, fmstr4_addr);
+ if (spi_error(spi))
+ return -EIO;
+
+ spi->access_map = fmstr4;
+ return 0;
+}
+
+static bool spi_region_readable(struct intel_dg_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 8)); /* [19:8] */
+ else
+ return spi->access_map & (1 << (region - 12)); /* [3:0] */
+}
+
+static bool spi_region_writeable(struct intel_dg_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 20)); /* [31:20] */
+ else
+ return spi->access_map & (1 << (region - 8)); /* [7:4] */
+}
+
+static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
+{
+ u32 is_valid;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ is_valid = spi_read32(spi, SPI_VALSIG_REG);
+ if (spi_error(spi))
+ return -EIO;
+
+ if (is_valid != SPI_FLVALSIG)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
+{
+ int ret;
+ unsigned int i, n;
+
+ /* clean error register, previous errors are ignored */
+ spi_error(spi);
+
+ ret = intel_dg_spi_is_valid(spi);
+ if (ret) {
+ dev_err(device, "The SPI is not valid %d\n", ret);
+ return ret;
+ }
+
+ if (spi_get_access_map(spi))
+ return -EIO;
+
+ for (i = 0, n = 0; i < spi->nregions; i++) {
+ u32 address, base, limit, region;
+ u8 id = spi->regions[i].id;
+
+ address = FLREG(id);
+ region = spi_read32(spi, address);
+
+ base = (region & 0x0000FFFF) << 12;
+ limit = (((region & 0xFFFF0000) >> 16) << 12) | 0xFFF;
+
+ dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n",
+ id, spi->regions[i].name, region, base, limit);
+
+ if (base >= limit || (i > 0 && limit == 0)) {
+ dev_dbg(device, "[%d] %s: disabled\n",
+ id, spi->regions[i].name);
+ spi->regions[i].is_readable = 0;
+ continue;
+ }
+
+ if (spi->size < limit)
+ spi->size = limit;
+
+ spi->regions[i].offset = base;
+ spi->regions[i].size = limit - base + 1;
+ /* No write access to descriptor; mask it out*/
+ spi->regions[i].is_writable = spi_region_writeable(spi, id);
+
+ spi->regions[i].is_readable = spi_region_readable(spi, id);
+ dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n",
+ spi->regions[i].name,
+ spi->regions[i].id,
+ spi->regions[i].offset,
+ spi->regions[i].size,
+ spi->regions[i].is_readable,
+ spi->regions[i].is_writable);
+
+ if (spi->regions[i].is_readable)
+ n++;
+ }
+
+ dev_dbg(device, "Registered %d regions\n", n);
+
+ /* Need to add 1 to the amount of memory
+ * so it is reported as an even block
+ */
+ spi->size += 1;
+
+ return n;
+}
+
static void intel_dg_spi_release(struct kref *kref)
{
struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
@@ -92,6 +275,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = intel_dg_spi_init(spi, device);
+ if (ret < 0) {
+ dev_err(device, "cannot initialize spi\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "bound\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 06/13] spi: intel-dg: implement region enumeration
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
In intel-dg spi, there is no access to the spi controller,
the information is extracted from the descriptor region.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 190 +++++++++++++++++++++++++++++++++++++
1 file changed, 190 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 8dc5448fc901..8ef9dccc9062 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -17,14 +17,197 @@ struct intel_dg_spi {
void __iomem *base;
size_t size;
unsigned int nregions;
+ u32 access_map;
struct {
const char *name;
u8 id;
u64 offset;
u64 size;
+ unsigned int is_readable:1;
+ unsigned int is_writable:1;
} regions[];
};
+#define SPI_TRIGGER_REG 0x00000000
+#define SPI_VALSIG_REG 0x00000010
+#define SPI_ADDRESS_REG 0x00000040
+#define SPI_REGION_ID_REG 0x00000044
+/*
+ * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K
+ * [23:16]-Reserved
+ * [31:24]-Erase SPI RegionID
+ */
+#define SPI_ERASE_REG 0x00000048
+#define SPI_ACCESS_ERROR_REG 0x00000070
+#define SPI_ADDRESS_ERROR_REG 0x00000074
+
+/* Flash Valid Signature */
+#define SPI_FLVALSIG 0x0FF0A55A
+
+#define SPI_MAP_ADDR_MASK 0x000000FF
+#define SPI_MAP_ADDR_SHIFT 0x00000004
+
+#define REGION_ID_DESCRIPTOR 0
+/* Flash Region Base Address */
+#define FRBA 0x40
+/* Flash Region __n - Flash Descriptor Record */
+#define FLREG(__n) (FRBA + ((__n) * 4))
+/* Flash Map 1 Register */
+#define FLMAP1_REG 0x18
+#define FLMSTR4_OFFSET 0x00C
+
+#define SPI_ACCESS_ERROR_PCIE_MASK 0x7
+
+static inline void spi_set_region_id(struct intel_dg_spi *spi, u8 region)
+{
+ iowrite32((u32)region, spi->base + SPI_REGION_ID_REG);
+}
+
+static inline u32 spi_error(struct intel_dg_spi *spi)
+{
+ u32 reg = ioread32(spi->base + SPI_ACCESS_ERROR_REG) &
+ SPI_ACCESS_ERROR_PCIE_MASK;
+
+ /* reset error bits */
+ if (reg)
+ iowrite32(reg, spi->base + SPI_ACCESS_ERROR_REG);
+
+ return reg;
+}
+
+static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return ioread32(base + SPI_TRIGGER_REG);
+}
+
+static int spi_get_access_map(struct intel_dg_spi *spi)
+{
+ u32 flmap1;
+ u32 fmba;
+ u32 fmstr4;
+ u32 fmstr4_addr;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ flmap1 = spi_read32(spi, FLMAP1_REG);
+ if (spi_error(spi))
+ return -EIO;
+ /* Get Flash Master Baser Address (FMBA) */
+ fmba = ((flmap1 & SPI_MAP_ADDR_MASK) << SPI_MAP_ADDR_SHIFT);
+ fmstr4_addr = fmba + FLMSTR4_OFFSET;
+
+ fmstr4 = spi_read32(spi, fmstr4_addr);
+ if (spi_error(spi))
+ return -EIO;
+
+ spi->access_map = fmstr4;
+ return 0;
+}
+
+static bool spi_region_readable(struct intel_dg_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 8)); /* [19:8] */
+ else
+ return spi->access_map & (1 << (region - 12)); /* [3:0] */
+}
+
+static bool spi_region_writeable(struct intel_dg_spi *spi, u8 region)
+{
+ if (region < 12)
+ return spi->access_map & (1 << (region + 20)); /* [31:20] */
+ else
+ return spi->access_map & (1 << (region - 8)); /* [7:4] */
+}
+
+static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
+{
+ u32 is_valid;
+
+ spi_set_region_id(spi, REGION_ID_DESCRIPTOR);
+
+ is_valid = spi_read32(spi, SPI_VALSIG_REG);
+ if (spi_error(spi))
+ return -EIO;
+
+ if (is_valid != SPI_FLVALSIG)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
+{
+ int ret;
+ unsigned int i, n;
+
+ /* clean error register, previous errors are ignored */
+ spi_error(spi);
+
+ ret = intel_dg_spi_is_valid(spi);
+ if (ret) {
+ dev_err(device, "The SPI is not valid %d\n", ret);
+ return ret;
+ }
+
+ if (spi_get_access_map(spi))
+ return -EIO;
+
+ for (i = 0, n = 0; i < spi->nregions; i++) {
+ u32 address, base, limit, region;
+ u8 id = spi->regions[i].id;
+
+ address = FLREG(id);
+ region = spi_read32(spi, address);
+
+ base = (region & 0x0000FFFF) << 12;
+ limit = (((region & 0xFFFF0000) >> 16) << 12) | 0xFFF;
+
+ dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n",
+ id, spi->regions[i].name, region, base, limit);
+
+ if (base >= limit || (i > 0 && limit == 0)) {
+ dev_dbg(device, "[%d] %s: disabled\n",
+ id, spi->regions[i].name);
+ spi->regions[i].is_readable = 0;
+ continue;
+ }
+
+ if (spi->size < limit)
+ spi->size = limit;
+
+ spi->regions[i].offset = base;
+ spi->regions[i].size = limit - base + 1;
+ /* No write access to descriptor; mask it out*/
+ spi->regions[i].is_writable = spi_region_writeable(spi, id);
+
+ spi->regions[i].is_readable = spi_region_readable(spi, id);
+ dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n",
+ spi->regions[i].name,
+ spi->regions[i].id,
+ spi->regions[i].offset,
+ spi->regions[i].size,
+ spi->regions[i].is_readable,
+ spi->regions[i].is_writable);
+
+ if (spi->regions[i].is_readable)
+ n++;
+ }
+
+ dev_dbg(device, "Registered %d regions\n", n);
+
+ /* Need to add 1 to the amount of memory
+ * so it is reported as an even block
+ */
+ spi->size += 1;
+
+ return n;
+}
+
static void intel_dg_spi_release(struct kref *kref)
{
struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
@@ -92,6 +275,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = intel_dg_spi_init(spi, device);
+ if (ret < 0) {
+ dev_err(device, "cannot initialize spi\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "bound\n");
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/13] spi: intel-dg: implement spi access functions
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Implement spi_read(), spi_erase() and spi_write() functions.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
---
drivers/spi/spi-intel-dg.c | 199 +++++++++++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 8ef9dccc9062..af65101456a4 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -3,13 +3,16 @@
* Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/intel_dg_spi_aux.h>
#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
+#include <linux/sizes.h>
#include <linux/types.h>
struct intel_dg_spi {
@@ -84,6 +87,33 @@ static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address)
return ioread32(base + SPI_TRIGGER_REG);
}
+static inline u64 spi_read64(struct intel_dg_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return readq(base + SPI_TRIGGER_REG);
+}
+
+static void spi_write32(struct intel_dg_spi *spi, u32 address, u32 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ iowrite32(data, base + SPI_TRIGGER_REG);
+}
+
+static void spi_write64(struct intel_dg_spi *spi, u32 address, u64 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ writeq(data, base + SPI_TRIGGER_REG);
+}
+
static int spi_get_access_map(struct intel_dg_spi *spi)
{
u32 flmap1;
@@ -140,6 +170,175 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
return 0;
}
+__maybe_unused
+static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from)
+{
+ unsigned int i;
+
+ for (i = 0; i < spi->nregions; i++) {
+ if ((spi->regions[i].offset + spi->regions[i].size - 1) > from &&
+ spi->regions[i].offset <= from &&
+ spi->regions[i].size != 0)
+ break;
+ }
+
+ return i;
+}
+
+static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to,
+ loff_t offset, size_t len, const u32 *newdata)
+{
+ u32 data = spi_read32(spi, to);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy((u8 *)&data + offset, newdata, len);
+
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
+ loff_t to, size_t len, const unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t to4;
+ size_t to_shift;
+ size_t len_s = len;
+ ssize_t ret;
+
+ spi_set_region_id(spi, region);
+
+ to4 = ALIGN_DOWN(to, sizeof(u32));
+ to_shift = min(sizeof(u32) - ((size_t)to - to4), len);
+ if (to - to4) {
+ ret = spi_rewrite_partial(spi, to4, to - to4, to_shift,
+ (uint32_t *)&buf[0]);
+ if (ret < 0)
+ return ret;
+
+ buf += to_shift;
+ to += to_shift;
+ len_s -= to_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data;
+
+ memcpy(&data, &buf[i], sizeof(u64));
+ spi_write64(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data;
+
+ memcpy(&data, &buf[i], sizeof(u32));
+ spi_write32(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ ret = spi_rewrite_partial(spi, to + i, 0, len4,
+ (uint32_t *)&buf[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
+ loff_t from, size_t len, unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t from4;
+ size_t from_shift;
+ size_t len_s = len;
+
+ spi_set_region_id(spi, region);
+
+ from4 = ALIGN_DOWN(from, sizeof(u32));
+ from_shift = min(sizeof(u32) - ((size_t)from - from4), len);
+
+ if (from - from4) {
+ u32 data = spi_read32(spi, from4);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);
+ len_s -= from_shift;
+ buf += from_shift;
+ from += from_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data = spi_read64(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy(&buf[i], &data, sizeof(data));
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, sizeof(data));
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, len4);
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t
+spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
+{
+ u64 i;
+ const u32 block = 0x10;
+ void __iomem *base = spi->base;
+
+ for (i = 0; i < len; i += SZ_4K) {
+ iowrite32(from + i, base + SPI_ADDRESS_REG);
+ iowrite32(region << 24 | block, base + SPI_ERASE_REG);
+ /* Since the writes are via sguint
+ * we cannot do back to back erases.
+ */
+ msleep(50);
+ }
+ return len;
+}
+
static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
{
int ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 07/13] spi: intel-dg: implement spi access functions
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Implement spi_read(), spi_erase() and spi_write() functions.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
---
drivers/spi/spi-intel-dg.c | 199 +++++++++++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 8ef9dccc9062..af65101456a4 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -3,13 +3,16 @@
* Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/intel_dg_spi_aux.h>
#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
+#include <linux/sizes.h>
#include <linux/types.h>
struct intel_dg_spi {
@@ -84,6 +87,33 @@ static inline u32 spi_read32(struct intel_dg_spi *spi, u32 address)
return ioread32(base + SPI_TRIGGER_REG);
}
+static inline u64 spi_read64(struct intel_dg_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return readq(base + SPI_TRIGGER_REG);
+}
+
+static void spi_write32(struct intel_dg_spi *spi, u32 address, u32 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ iowrite32(data, base + SPI_TRIGGER_REG);
+}
+
+static void spi_write64(struct intel_dg_spi *spi, u32 address, u64 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ writeq(data, base + SPI_TRIGGER_REG);
+}
+
static int spi_get_access_map(struct intel_dg_spi *spi)
{
u32 flmap1;
@@ -140,6 +170,175 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
return 0;
}
+__maybe_unused
+static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from)
+{
+ unsigned int i;
+
+ for (i = 0; i < spi->nregions; i++) {
+ if ((spi->regions[i].offset + spi->regions[i].size - 1) > from &&
+ spi->regions[i].offset <= from &&
+ spi->regions[i].size != 0)
+ break;
+ }
+
+ return i;
+}
+
+static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to,
+ loff_t offset, size_t len, const u32 *newdata)
+{
+ u32 data = spi_read32(spi, to);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy((u8 *)&data + offset, newdata, len);
+
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
+ loff_t to, size_t len, const unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t to4;
+ size_t to_shift;
+ size_t len_s = len;
+ ssize_t ret;
+
+ spi_set_region_id(spi, region);
+
+ to4 = ALIGN_DOWN(to, sizeof(u32));
+ to_shift = min(sizeof(u32) - ((size_t)to - to4), len);
+ if (to - to4) {
+ ret = spi_rewrite_partial(spi, to4, to - to4, to_shift,
+ (uint32_t *)&buf[0]);
+ if (ret < 0)
+ return ret;
+
+ buf += to_shift;
+ to += to_shift;
+ len_s -= to_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data;
+
+ memcpy(&data, &buf[i], sizeof(u64));
+ spi_write64(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data;
+
+ memcpy(&data, &buf[i], sizeof(u32));
+ spi_write32(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ ret = spi_rewrite_partial(spi, to + i, 0, len4,
+ (uint32_t *)&buf[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
+ loff_t from, size_t len, unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+ size_t from4;
+ size_t from_shift;
+ size_t len_s = len;
+
+ spi_set_region_id(spi, region);
+
+ from4 = ALIGN_DOWN(from, sizeof(u32));
+ from_shift = min(sizeof(u32) - ((size_t)from - from4), len);
+
+ if (from - from4) {
+ u32 data = spi_read32(spi, from4);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift);
+ len_s -= from_shift;
+ buf += from_shift;
+ from += from_shift;
+ }
+
+ len8 = ALIGN_DOWN(len_s, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data = spi_read64(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy(&buf[i], &data, sizeof(data));
+ }
+
+ len4 = len_s - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, sizeof(data));
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, len4);
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t
+spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
+{
+ u64 i;
+ const u32 block = 0x10;
+ void __iomem *base = spi->base;
+
+ for (i = 0; i < len; i += SZ_4K) {
+ iowrite32(from + i, base + SPI_ADDRESS_REG);
+ iowrite32(region << 24 | block, base + SPI_ERASE_REG);
+ /* Since the writes are via sguint
+ * we cannot do back to back erases.
+ */
+ msleep(50);
+ }
+ return len;
+}
+
static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
{
int ret;
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/13] spi: intel-dg: spi register with mtd
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Register the on-die spi device with the mtd subsystem.
Refcount spi object on _get and _put mtd callbacks.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 111 +++++++++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index af65101456a4..4af8a2314fc7 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -10,6 +10,8 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/sizes.h>
@@ -17,6 +19,8 @@
struct intel_dg_spi {
struct kref refcnt;
+ struct mtd_info mtd;
+ struct mutex lock; /* region access lock */
void __iomem *base;
size_t size;
unsigned int nregions;
@@ -407,6 +411,23 @@ static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
return n;
}
+static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
+{
+ return 0;
+}
+
+static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ return 0;
+}
+
+static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ return 0;
+}
+
static void intel_dg_spi_release(struct kref *kref)
{
struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
@@ -415,9 +436,90 @@ static void intel_dg_spi_release(struct kref *kref)
pr_debug("freeing spi memory\n");
for (i = 0; i < spi->nregions; i++)
kfree(spi->regions[i].name);
+ mutex_destroy(&spi->lock);
kfree(spi);
}
+static int intel_dg_spi_get_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct intel_dg_spi *spi;
+
+ if (!mtd)
+ return -ENODEV;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+ pr_debug("get spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_get(&spi->refcnt);
+
+ return 0;
+}
+
+static void intel_dg_spi_put_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct intel_dg_spi *spi;
+
+ if (!mtd)
+ return;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return;
+ pr_debug("put spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+}
+
+static int intel_dg_spi_init_mtd(struct intel_dg_spi *spi, struct device *device,
+ unsigned int nparts, bool writeable_override)
+{
+ unsigned int i;
+ unsigned int n;
+ struct mtd_partition *parts = NULL;
+ int ret;
+
+ dev_dbg(device, "registering with mtd\n");
+
+ spi->mtd.owner = THIS_MODULE;
+ spi->mtd.dev.parent = device;
+ spi->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
+ spi->mtd.type = MTD_DATAFLASH;
+ spi->mtd.priv = spi;
+ spi->mtd._write = intel_dg_spi_write;
+ spi->mtd._read = intel_dg_spi_read;
+ spi->mtd._erase = intel_dg_spi_erase;
+ spi->mtd._get_device = intel_dg_spi_get_device;
+ spi->mtd._put_device = intel_dg_spi_put_device;
+ spi->mtd.writesize = SZ_1; /* 1 byte granularity */
+ spi->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
+ spi->mtd.size = spi->size;
+
+ parts = kcalloc(spi->nregions, sizeof(*parts), GFP_KERNEL);
+ if (!parts)
+ return -ENOMEM;
+
+ for (i = 0, n = 0; i < spi->nregions && n < nparts; i++) {
+ if (!spi->regions[i].is_readable)
+ continue;
+ parts[n].name = spi->regions[i].name;
+ parts[n].offset = spi->regions[i].offset;
+ parts[n].size = spi->regions[i].size;
+ if (!spi->regions[i].is_writable && !writeable_override)
+ parts[n].mask_flags = MTD_WRITEABLE;
+ n++;
+ }
+
+ ret = mtd_device_register(&spi->mtd, parts, n);
+
+ kfree(parts);
+
+ return ret;
+}
+
static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -449,6 +551,7 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
if (!spi)
return -ENOMEM;
+ mutex_init(&spi->lock);
kref_init(&spi->refcnt);
spi->nregions = nregions;
@@ -481,6 +584,12 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = intel_dg_spi_init_mtd(spi, device, ret, ispi->writeable_override);
+ if (ret) {
+ dev_err(device, "failed init mtd %d\n", ret);
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "bound\n");
@@ -499,6 +608,8 @@ static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ mtd_device_unregister(&spi->mtd);
+
dev_set_drvdata(&aux_dev->dev, NULL);
kref_put(&spi->refcnt, intel_dg_spi_release);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 08/13] spi: intel-dg: spi register with mtd
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Register the on-die spi device with the mtd subsystem.
Refcount spi object on _get and _put mtd callbacks.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 111 +++++++++++++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index af65101456a4..4af8a2314fc7 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -10,6 +10,8 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/sizes.h>
@@ -17,6 +19,8 @@
struct intel_dg_spi {
struct kref refcnt;
+ struct mtd_info mtd;
+ struct mutex lock; /* region access lock */
void __iomem *base;
size_t size;
unsigned int nregions;
@@ -407,6 +411,23 @@ static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
return n;
}
+static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
+{
+ return 0;
+}
+
+static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ return 0;
+}
+
+static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ return 0;
+}
+
static void intel_dg_spi_release(struct kref *kref)
{
struct intel_dg_spi *spi = container_of(kref, struct intel_dg_spi, refcnt);
@@ -415,9 +436,90 @@ static void intel_dg_spi_release(struct kref *kref)
pr_debug("freeing spi memory\n");
for (i = 0; i < spi->nregions; i++)
kfree(spi->regions[i].name);
+ mutex_destroy(&spi->lock);
kfree(spi);
}
+static int intel_dg_spi_get_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct intel_dg_spi *spi;
+
+ if (!mtd)
+ return -ENODEV;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+ pr_debug("get spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_get(&spi->refcnt);
+
+ return 0;
+}
+
+static void intel_dg_spi_put_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master;
+ struct intel_dg_spi *spi;
+
+ if (!mtd)
+ return;
+
+ master = mtd_get_master(mtd);
+ spi = master->priv;
+ if (WARN_ON(!spi))
+ return;
+ pr_debug("put spi %s %d\n", mtd->name, kref_read(&spi->refcnt));
+ kref_put(&spi->refcnt, intel_dg_spi_release);
+}
+
+static int intel_dg_spi_init_mtd(struct intel_dg_spi *spi, struct device *device,
+ unsigned int nparts, bool writeable_override)
+{
+ unsigned int i;
+ unsigned int n;
+ struct mtd_partition *parts = NULL;
+ int ret;
+
+ dev_dbg(device, "registering with mtd\n");
+
+ spi->mtd.owner = THIS_MODULE;
+ spi->mtd.dev.parent = device;
+ spi->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
+ spi->mtd.type = MTD_DATAFLASH;
+ spi->mtd.priv = spi;
+ spi->mtd._write = intel_dg_spi_write;
+ spi->mtd._read = intel_dg_spi_read;
+ spi->mtd._erase = intel_dg_spi_erase;
+ spi->mtd._get_device = intel_dg_spi_get_device;
+ spi->mtd._put_device = intel_dg_spi_put_device;
+ spi->mtd.writesize = SZ_1; /* 1 byte granularity */
+ spi->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
+ spi->mtd.size = spi->size;
+
+ parts = kcalloc(spi->nregions, sizeof(*parts), GFP_KERNEL);
+ if (!parts)
+ return -ENOMEM;
+
+ for (i = 0, n = 0; i < spi->nregions && n < nparts; i++) {
+ if (!spi->regions[i].is_readable)
+ continue;
+ parts[n].name = spi->regions[i].name;
+ parts[n].offset = spi->regions[i].offset;
+ parts[n].size = spi->regions[i].size;
+ if (!spi->regions[i].is_writable && !writeable_override)
+ parts[n].mask_flags = MTD_WRITEABLE;
+ n++;
+ }
+
+ ret = mtd_device_register(&spi->mtd, parts, n);
+
+ kfree(parts);
+
+ return ret;
+}
+
static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -449,6 +551,7 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
if (!spi)
return -ENOMEM;
+ mutex_init(&spi->lock);
kref_init(&spi->refcnt);
spi->nregions = nregions;
@@ -481,6 +584,12 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
goto err;
}
+ ret = intel_dg_spi_init_mtd(spi, device, ret, ispi->writeable_override);
+ if (ret) {
+ dev_err(device, "failed init mtd %d\n", ret);
+ goto err;
+ }
+
dev_set_drvdata(&aux_dev->dev, spi);
dev_dbg(device, "bound\n");
@@ -499,6 +608,8 @@ static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ mtd_device_unregister(&spi->mtd);
+
dev_set_drvdata(&aux_dev->dev, NULL);
kref_put(&spi->refcnt, intel_dg_spi_release);
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/13] spi: intel-dg: implement mtd access handlers
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 152 +++++++++++++++++++++++++++++++++++--
1 file changed, 147 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 4af8a2314fc7..9e8be7713f1a 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -174,7 +174,6 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
return 0;
}
-__maybe_unused
static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from)
{
unsigned int i;
@@ -206,7 +205,6 @@ static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to,
return len;
}
-__maybe_unused
static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
loff_t to, size_t len, const unsigned char *buf)
{
@@ -265,7 +263,6 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
loff_t from, size_t len, unsigned char *buf)
{
@@ -324,7 +321,6 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t
spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
{
@@ -413,18 +409,164 @@ static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
{
- return 0;
+ struct intel_dg_spi *spi;
+ unsigned int idx;
+ u8 region;
+ u64 addr;
+ ssize_t bytes;
+ loff_t from;
+ size_t len;
+ size_t total_len;
+ int ret = 0;
+
+ if (!mtd || !info)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %llx\n",
+ info->addr, info->len);
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EINVAL;
+ }
+
+ total_len = info->len;
+ addr = info->addr;
+
+ mutex_lock(&spi->lock);
+
+ while (total_len > 0) {
+ if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
+ info->fail_addr = addr;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ idx = spi_get_region(spi, addr);
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ from = addr - spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ len = total_len;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n",
+ region, spi->regions[idx].name, from, len);
+
+ bytes = spi_erase(spi, region, from, len, &info->fail_addr);
+ if (bytes < 0) {
+ dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
+ info->fail_addr += spi->regions[idx].offset;
+ ret = bytes;
+ goto out;
+ }
+
+ addr += len;
+ total_len -= len;
+ }
+
+out:
+ mutex_unlock(&spi->lock);
+ return ret;
}
static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
+ struct intel_dg_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, from);
+
+ dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, from, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of ragnge");
+ return -ERANGE;
+ }
+
+ from -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_read(spi, region, from, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
+ struct intel_dg_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, to);
+
+ dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, to, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ return -ERANGE;
+ }
+
+ to -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - to)
+ len = spi->regions[idx].size - to;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_write(spi, region, to, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 09/13] spi: intel-dg: implement mtd access handlers
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx,
Lucas De Marchi, Tomas Winkler
Implement mtd read, erase, and write handlers.
For erase operation address and size should be 4K aligned.
For write operation address and size has to be 4bytes aligned.
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 152 +++++++++++++++++++++++++++++++++++--
1 file changed, 147 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 4af8a2314fc7..9e8be7713f1a 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -174,7 +174,6 @@ static int intel_dg_spi_is_valid(struct intel_dg_spi *spi)
return 0;
}
-__maybe_unused
static unsigned int spi_get_region(const struct intel_dg_spi *spi, loff_t from)
{
unsigned int i;
@@ -206,7 +205,6 @@ static ssize_t spi_rewrite_partial(struct intel_dg_spi *spi, loff_t to,
return len;
}
-__maybe_unused
static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
loff_t to, size_t len, const unsigned char *buf)
{
@@ -265,7 +263,6 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
loff_t from, size_t len, unsigned char *buf)
{
@@ -324,7 +321,6 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
return len;
}
-__maybe_unused
static ssize_t
spi_erase(struct intel_dg_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr)
{
@@ -413,18 +409,164 @@ static int intel_dg_spi_init(struct intel_dg_spi *spi, struct device *device)
static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
{
- return 0;
+ struct intel_dg_spi *spi;
+ unsigned int idx;
+ u8 region;
+ u64 addr;
+ ssize_t bytes;
+ loff_t from;
+ size_t len;
+ size_t total_len;
+ int ret = 0;
+
+ if (!mtd || !info)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %llx\n",
+ info->addr, info->len);
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EINVAL;
+ }
+
+ total_len = info->len;
+ addr = info->addr;
+
+ mutex_lock(&spi->lock);
+
+ while (total_len > 0) {
+ if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) {
+ dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len);
+ info->fail_addr = addr;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ idx = spi_get_region(spi, addr);
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ info->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ ret = -ERANGE;
+ goto out;
+ }
+
+ from = addr - spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ len = total_len;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n",
+ region, spi->regions[idx].name, from, len);
+
+ bytes = spi_erase(spi, region, from, len, &info->fail_addr);
+ if (bytes < 0) {
+ dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes);
+ info->fail_addr += spi->regions[idx].offset;
+ ret = bytes;
+ goto out;
+ }
+
+ addr += len;
+ total_len -= len;
+ }
+
+out:
+ mutex_unlock(&spi->lock);
+ return ret;
}
static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
+ struct intel_dg_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, from);
+
+ dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, from, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of ragnge");
+ return -ERANGE;
+ }
+
+ from -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - from)
+ len = spi->regions[idx].size - from;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_read(spi, region, from, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "read failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
+ struct intel_dg_spi *spi;
+ ssize_t ret;
+ unsigned int idx;
+ u8 region;
+
+ if (!mtd)
+ return -EINVAL;
+
+ spi = mtd->priv;
+ if (WARN_ON(!spi))
+ return -EINVAL;
+
+ idx = spi_get_region(spi, to);
+
+ dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n",
+ spi->regions[idx].id, spi->regions[idx].name, to, len);
+
+ if (idx >= spi->nregions) {
+ dev_err(&mtd->dev, "out of range");
+ return -ERANGE;
+ }
+
+ to -= spi->regions[idx].offset;
+ region = spi->regions[idx].id;
+ if (len > spi->regions[idx].size - to)
+ len = spi->regions[idx].size - to;
+
+ mutex_lock(&spi->lock);
+
+ ret = spi_write(spi, region, to, len, buf);
+ if (ret < 0) {
+ dev_dbg(&mtd->dev, "write failed with %zd\n", ret);
+ mutex_unlock(&spi->lock);
+ return ret;
+ }
+
+ *retlen = ret;
+
+ mutex_unlock(&spi->lock);
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/13] spi: intel-dg: align 64bit read and write
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
GSC SPI HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 9e8be7713f1a..d626e9526631 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -231,6 +231,24 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
len_s -= to_shift;
}
+ if (!IS_ALIGNED(to, sizeof(u64)) &&
+ ((to ^ (to + len_s)) & GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data;
+
+ memcpy(&data, &buf[0], sizeof(u32));
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+ buf += sizeof(u32);
+ to += sizeof(u32);
+ len_s -= sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data;
@@ -289,6 +307,23 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
from += from_shift;
}
+ if (!IS_ALIGNED(from, sizeof(u64)) &&
+ ((from ^ (from + len_s)) & GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data = spi_read32(spi, from);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], &data, sizeof(data));
+ len_s -= sizeof(u32);
+ buf += sizeof(u32);
+ from += sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data = spi_read64(spi, from + i);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 10/13] spi: intel-dg: align 64bit read and write
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
GSC SPI HW errors on quad access overlapping 1K border.
Align 64bit read and write to avoid readq/writeq over 1K border.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index 9e8be7713f1a..d626e9526631 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -231,6 +231,24 @@ static ssize_t spi_write(struct intel_dg_spi *spi, u8 region,
len_s -= to_shift;
}
+ if (!IS_ALIGNED(to, sizeof(u64)) &&
+ ((to ^ (to + len_s)) & GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data;
+
+ memcpy(&data, &buf[0], sizeof(u32));
+ spi_write32(spi, to, data);
+ if (spi_error(spi))
+ return -EIO;
+ buf += sizeof(u32);
+ to += sizeof(u32);
+ len_s -= sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data;
@@ -289,6 +307,23 @@ static ssize_t spi_read(struct intel_dg_spi *spi, u8 region,
from += from_shift;
}
+ if (!IS_ALIGNED(from, sizeof(u64)) &&
+ ((from ^ (from + len_s)) & GENMASK(31, 10))) {
+ /*
+ * Workaround reads/writes across 1k-aligned addresses
+ * (start u32 before 1k, end u32 after)
+ * as this fails on hardware.
+ */
+ u32 data = spi_read32(spi, from);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[0], &data, sizeof(data));
+ len_s -= sizeof(u32);
+ buf += sizeof(u32);
+ from += sizeof(u32);
+ }
+
len8 = ALIGN_DOWN(len_s, sizeof(u64));
for (i = 0; i < len8; i += sizeof(u64)) {
u64 data = spi_read64(spi, from + i);
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/13] spi: intel-dg: wake card on operations
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx, Lucas De Marchi
Enable runtime PM in spi driver to notify graphics driver that
whole card should be kept awake while spi operations are
performed through this driver.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 44 ++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index d626e9526631..24be2f7e14d7 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -12,11 +12,14 @@
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/pm_runtime.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/sizes.h>
#include <linux/types.h>
+#define INTEL_DG_SPI_RPM_TIMEOUT 500
+
struct intel_dg_spi {
struct kref refcnt;
struct mtd_info mtd;
@@ -471,6 +474,12 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
total_len = info->len;
addr = info->addr;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %d\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
while (total_len > 0) {
@@ -512,6 +521,8 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
out:
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return ret;
}
@@ -545,6 +556,12 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
if (len > spi->regions[idx].size - from)
len = spi->regions[idx].size - from;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_read(spi, region, from, len, buf);
@@ -557,6 +574,8 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -590,6 +609,12 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
if (len > spi->regions[idx].size - to)
len = spi->regions[idx].size - to;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_write(spi, region, to, len, buf);
@@ -602,6 +627,8 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -747,6 +774,17 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
}
}
+ pm_runtime_enable(device);
+
+ pm_runtime_set_autosuspend_delay(device, INTEL_DG_SPI_RPM_TIMEOUT);
+ pm_runtime_use_autosuspend(device);
+
+ ret = pm_runtime_resume_and_get(device);
+ if (ret < 0) {
+ dev_err(device, "rpm: get failed %d\n", ret);
+ goto err_norpm;
+ }
+
spi->base = devm_ioremap_resource(device, &ispi->bar);
if (IS_ERR(spi->base)) {
dev_err(device, "mmio not mapped\n");
@@ -771,9 +809,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
dev_dbg(device, "bound\n");
+ pm_runtime_put(device);
return 0;
err:
+ pm_runtime_put(device);
+err_norpm:
+ pm_runtime_disable(device);
kref_put(&spi->refcnt, intel_dg_spi_release);
return ret;
}
@@ -785,6 +827,8 @@ static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ pm_runtime_disable(&aux_dev->dev);
+
mtd_device_unregister(&spi->mtd);
dev_set_drvdata(&aux_dev->dev, NULL);
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 11/13] spi: intel-dg: wake card on operations
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx, Lucas De Marchi
Enable runtime PM in spi driver to notify graphics driver that
whole card should be kept awake while spi operations are
performed through this driver.
CC: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/spi/spi-intel-dg.c | 44 ++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/spi/spi-intel-dg.c b/drivers/spi/spi-intel-dg.c
index d626e9526631..24be2f7e14d7 100644
--- a/drivers/spi/spi-intel-dg.c
+++ b/drivers/spi/spi-intel-dg.c
@@ -12,11 +12,14 @@
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/pm_runtime.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/sizes.h>
#include <linux/types.h>
+#define INTEL_DG_SPI_RPM_TIMEOUT 500
+
struct intel_dg_spi {
struct kref refcnt;
struct mtd_info mtd;
@@ -471,6 +474,12 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
total_len = info->len;
addr = info->addr;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %d\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
while (total_len > 0) {
@@ -512,6 +521,8 @@ static int intel_dg_spi_erase(struct mtd_info *mtd, struct erase_info *info)
out:
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return ret;
}
@@ -545,6 +556,12 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
if (len > spi->regions[idx].size - from)
len = spi->regions[idx].size - from;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_read(spi, region, from, len, buf);
@@ -557,6 +574,8 @@ static int intel_dg_spi_read(struct mtd_info *mtd, loff_t from, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -590,6 +609,12 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
if (len > spi->regions[idx].size - to)
len = spi->regions[idx].size - to;
+ ret = pm_runtime_resume_and_get(mtd->dev.parent);
+ if (ret < 0) {
+ dev_err(&mtd->dev, "rpm: get failed %zd\n", ret);
+ return ret;
+ }
+
mutex_lock(&spi->lock);
ret = spi_write(spi, region, to, len, buf);
@@ -602,6 +627,8 @@ static int intel_dg_spi_write(struct mtd_info *mtd, loff_t to, size_t len,
*retlen = ret;
mutex_unlock(&spi->lock);
+ pm_runtime_mark_last_busy(mtd->dev.parent);
+ pm_runtime_put_autosuspend(mtd->dev.parent);
return 0;
}
@@ -747,6 +774,17 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
}
}
+ pm_runtime_enable(device);
+
+ pm_runtime_set_autosuspend_delay(device, INTEL_DG_SPI_RPM_TIMEOUT);
+ pm_runtime_use_autosuspend(device);
+
+ ret = pm_runtime_resume_and_get(device);
+ if (ret < 0) {
+ dev_err(device, "rpm: get failed %d\n", ret);
+ goto err_norpm;
+ }
+
spi->base = devm_ioremap_resource(device, &ispi->bar);
if (IS_ERR(spi->base)) {
dev_err(device, "mmio not mapped\n");
@@ -771,9 +809,13 @@ static int intel_dg_spi_probe(struct auxiliary_device *aux_dev,
dev_dbg(device, "bound\n");
+ pm_runtime_put(device);
return 0;
err:
+ pm_runtime_put(device);
+err_norpm:
+ pm_runtime_disable(device);
kref_put(&spi->refcnt, intel_dg_spi_release);
return ret;
}
@@ -785,6 +827,8 @@ static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
if (!spi)
return;
+ pm_runtime_disable(&aux_dev->dev);
+
mtd_device_unregister(&spi->mtd);
dev_set_drvdata(&aux_dev->dev, NULL);
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/13] drm/xe/spi: add on-die spi device
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 3 ++
drivers/gpu/drm/xe/xe_device_types.h | 5 ++
drivers/gpu/drm/xe/xe_spi.c | 78 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_spi.h | 15 ++++++
5 files changed, 102 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_spi.c
create mode 100644 drivers/gpu/drm/xe/xe_spi.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index efcf0ab7a1a6..3ea829591b8e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -124,6 +124,7 @@ xe-y += xe_bb.o \
xe_ring_ops.o \
xe_sa.o \
xe_sched_job.o \
+ xe_spi.o \
xe_step.o \
xe_sync.o \
xe_tile.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index b8d8da546670..5c9351f2c35f 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -35,6 +35,7 @@
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
+#include "xe_spi.h"
#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
@@ -515,6 +516,7 @@ int xe_device_probe(struct xe_device *xe)
goto err_irq_shutdown;
}
+ xe_spi_init(xe);
xe_heci_gsc_init(xe);
err = xe_display_init(xe);
@@ -562,6 +564,7 @@ void xe_device_remove(struct xe_device *xe)
xe_display_fini(xe);
xe_heci_gsc_fini(xe);
+ xe_spi_fini(xe);
xe_irq_shutdown(xe);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5dc9127a2029..dbb686a2ae53 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -12,6 +12,8 @@
#include <drm/drm_file.h>
#include <drm/ttm/ttm_device.h>
+#include <linux/intel_dg_spi_aux.h>
+
#include "xe_devcoredump_types.h"
#include "xe_heci_gsc.h"
#include "xe_gt_types.h"
@@ -432,6 +434,9 @@ struct xe_device {
/** @heci_gsc: graphics security controller */
struct xe_heci_gsc heci_gsc;
+ /** @spi: discrete graphics spi */
+ struct intel_dg_spi_dev spi;
+
/** @needs_flr_on_fini: requests function-reset on fini */
bool needs_flr_on_fini;
diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c
new file mode 100644
index 000000000000..3dde2ec9c389
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_spi.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/pci.h>
+#include "xe_device_types.h"
+#include "xe_spi.h"
+
+#define GEN12_GUNIT_SPI_BASE 0x00102040
+#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
+
+static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
+static void xe_spi_release_dev(struct device *dev)
+{
+}
+
+void xe_spi_init(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ spi->writeable_override = false;
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = xe_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+}
+
+void xe_spi_fini(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ dev_dbg(&pdev->dev, "removing xe-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
diff --git a/drivers/gpu/drm/xe/xe_spi.h b/drivers/gpu/drm/xe/xe_spi.h
new file mode 100644
index 000000000000..aef79893a864
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_spi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __XE_SPI_H__
+#define __XE_SPI_H__
+
+struct xe_device;
+
+void xe_spi_init(struct xe_device *xe);
+
+void xe_spi_fini(struct xe_device *xe);
+
+#endif /* __XE_SPI_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 12/13] drm/xe/spi: add on-die spi device
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 3 ++
drivers/gpu/drm/xe/xe_device_types.h | 5 ++
drivers/gpu/drm/xe/xe_spi.c | 78 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_spi.h | 15 ++++++
5 files changed, 102 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_spi.c
create mode 100644 drivers/gpu/drm/xe/xe_spi.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index efcf0ab7a1a6..3ea829591b8e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -124,6 +124,7 @@ xe-y += xe_bb.o \
xe_ring_ops.o \
xe_sa.o \
xe_sched_job.o \
+ xe_spi.o \
xe_step.o \
xe_sync.o \
xe_tile.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index b8d8da546670..5c9351f2c35f 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -35,6 +35,7 @@
#include "xe_pcode.h"
#include "xe_pm.h"
#include "xe_query.h"
+#include "xe_spi.h"
#include "xe_tile.h"
#include "xe_ttm_stolen_mgr.h"
#include "xe_ttm_sys_mgr.h"
@@ -515,6 +516,7 @@ int xe_device_probe(struct xe_device *xe)
goto err_irq_shutdown;
}
+ xe_spi_init(xe);
xe_heci_gsc_init(xe);
err = xe_display_init(xe);
@@ -562,6 +564,7 @@ void xe_device_remove(struct xe_device *xe)
xe_display_fini(xe);
xe_heci_gsc_fini(xe);
+ xe_spi_fini(xe);
xe_irq_shutdown(xe);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5dc9127a2029..dbb686a2ae53 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -12,6 +12,8 @@
#include <drm/drm_file.h>
#include <drm/ttm/ttm_device.h>
+#include <linux/intel_dg_spi_aux.h>
+
#include "xe_devcoredump_types.h"
#include "xe_heci_gsc.h"
#include "xe_gt_types.h"
@@ -432,6 +434,9 @@ struct xe_device {
/** @heci_gsc: graphics security controller */
struct xe_heci_gsc heci_gsc;
+ /** @spi: discrete graphics spi */
+ struct intel_dg_spi_dev spi;
+
/** @needs_flr_on_fini: requests function-reset on fini */
bool needs_flr_on_fini;
diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c
new file mode 100644
index 000000000000..3dde2ec9c389
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_spi.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/intel_dg_spi_aux.h>
+#include <linux/pci.h>
+#include "xe_device_types.h"
+#include "xe_spi.h"
+
+#define GEN12_GUNIT_SPI_BASE 0x00102040
+#define GEN12_GUNIT_SPI_SIZE 0x80
+#define HECI_FW_STATUS_2_SPI_ACCESS_MODE BIT(3)
+
+static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = {
+ [0] = { .name = "DESCRIPTOR", },
+ [2] = { .name = "GSC", },
+ [11] = { .name = "OptionROM", },
+ [12] = { .name = "DAM", },
+};
+
+static void xe_spi_release_dev(struct device *dev)
+{
+}
+
+void xe_spi_init(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ struct auxiliary_device *aux_dev = &spi->aux_dev;
+ int ret;
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ spi->writeable_override = false;
+ spi->bar.parent = &pdev->resource[0];
+ spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
+ spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
+ spi->bar.flags = IORESOURCE_MEM;
+ spi->bar.desc = IORES_DESC_NONE;
+ spi->regions = regions;
+
+ aux_dev->name = "spi";
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = xe_spi_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux init failed %d\n", ret);
+ return;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "xe-spi aux add failed %d\n", ret);
+ auxiliary_device_uninit(aux_dev);
+ return;
+ }
+}
+
+void xe_spi_fini(struct xe_device *xe)
+{
+ struct intel_dg_spi_dev *spi = &xe->spi;
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ /* Only the DGFX devices have internal SPI */
+ if (!IS_DGFX(xe))
+ return;
+
+ dev_dbg(&pdev->dev, "removing xe-spi cell\n");
+
+ auxiliary_device_delete(&spi->aux_dev);
+ auxiliary_device_uninit(&spi->aux_dev);
+}
diff --git a/drivers/gpu/drm/xe/xe_spi.h b/drivers/gpu/drm/xe/xe_spi.h
new file mode 100644
index 000000000000..aef79893a864
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_spi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2024 Intel Corporation. All rights reserved.
+ */
+
+#ifndef __XE_SPI_H__
+#define __XE_SPI_H__
+
+struct xe_device;
+
+void xe_spi_init(struct xe_device *xe);
+
+void xe_spi_fini(struct xe_device *xe);
+
+#endif /* __XE_SPI_H__ */
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 13/13] drm/xe/spi: add support for access mode
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-28 12:22 ` Alexander Usyskin
-1 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5 +++++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +----
drivers/gpu/drm/xe/xe_spi.c | 31 ++++++++++++++++++++++++++-
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
index 9886ec9cb08e..ef04fab3a4b0 100644
--- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
@@ -16,6 +16,11 @@
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
+#define DG1_GSC_HECI2_BASE 0x00259000
+#define PVC_GSC_HECI2_BASE 0x00285000
+#define DG2_GSC_HECI2_BASE 0x00374000
+
+
#define HECI_H_CSR(base) XE_REG((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
#define HECI_H_CSR_IS REG_BIT(1)
diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
index bfdd33b9b23b..f240a3fbb507 100644
--- a/drivers/gpu/drm/xe/xe_heci_gsc.c
+++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
@@ -11,14 +11,11 @@
#include "xe_device_types.h"
#include "xe_drv.h"
#include "xe_heci_gsc.h"
+#include "regs/xe_gsc_regs.h"
#include "xe_platform_types.h"
#define GSC_BAR_LENGTH 0x00000FFC
-#define DG1_GSC_HECI2_BASE 0x259000
-#define PVC_GSC_HECI2_BASE 0x285000
-#define DG2_GSC_HECI2_BASE 0x374000
-
static void heci_gsc_irq_mask(struct irq_data *d)
{
/* generic irq handling */
diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c
index 3dde2ec9c389..91632d68db8a 100644
--- a/drivers/gpu/drm/xe/xe_spi.c
+++ b/drivers/gpu/drm/xe/xe_spi.c
@@ -5,7 +5,10 @@
#include <linux/intel_dg_spi_aux.h>
#include <linux/pci.h>
+#include "xe_device.h"
#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "regs/xe_gsc_regs.h"
#include "xe_spi.h"
#define GEN12_GUNIT_SPI_BASE 0x00102040
@@ -23,6 +26,32 @@ static void xe_spi_release_dev(struct device *dev)
{
}
+static bool xe_spi_writeable_override(struct xe_device *xe)
+{
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ resource_size_t base;
+ bool writeable_override;
+
+ if (xe->info.platform == XE_PVC) {
+ base = PVC_GSC_HECI2_BASE;
+ } else if (xe->info.platform == XE_DG2) {
+ base = DG2_GSC_HECI2_BASE;
+ } else if (xe->info.platform == XE_DG1) {
+ base = DG1_GSC_HECI2_BASE;
+ } else {
+ dev_err(&pdev->dev, "Unknown platform\n");
+ return true;
+ }
+
+ writeable_override =
+ !(xe_mmio_read32(gt, HECI_H_GS1(base)) &
+ HECI_FW_STATUS_2_SPI_ACCESS_MODE);
+ if (writeable_override)
+ dev_info(&pdev->dev, "SPI access overridden by jumper\n");
+ return writeable_override;
+}
+
void xe_spi_init(struct xe_device *xe)
{
struct intel_dg_spi_dev *spi = &xe->spi;
@@ -34,7 +63,7 @@ void xe_spi_init(struct xe_device *xe)
if (!IS_DGFX(xe))
return;
- spi->writeable_override = false;
+ spi->writeable_override = xe_spi_writeable_override(xe);
spi->bar.parent = &pdev->resource[0];
spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
--
2.34.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 13/13] drm/xe/spi: add support for access mode
@ 2024-03-28 12:22 ` Alexander Usyskin
0 siblings, 0 replies; 39+ messages in thread
From: Alexander Usyskin @ 2024-03-28 12:22 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Alexander Usyskin, Vitaly Lubart, linux-mtd, intel-gfx
Check SPI access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 5 +++++
drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +----
drivers/gpu/drm/xe/xe_spi.c | 31 ++++++++++++++++++++++++++-
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
index 9886ec9cb08e..ef04fab3a4b0 100644
--- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
@@ -16,6 +16,11 @@
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
+#define DG1_GSC_HECI2_BASE 0x00259000
+#define PVC_GSC_HECI2_BASE 0x00285000
+#define DG2_GSC_HECI2_BASE 0x00374000
+
+
#define HECI_H_CSR(base) XE_REG((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
#define HECI_H_CSR_IS REG_BIT(1)
diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_gsc.c
index bfdd33b9b23b..f240a3fbb507 100644
--- a/drivers/gpu/drm/xe/xe_heci_gsc.c
+++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
@@ -11,14 +11,11 @@
#include "xe_device_types.h"
#include "xe_drv.h"
#include "xe_heci_gsc.h"
+#include "regs/xe_gsc_regs.h"
#include "xe_platform_types.h"
#define GSC_BAR_LENGTH 0x00000FFC
-#define DG1_GSC_HECI2_BASE 0x259000
-#define PVC_GSC_HECI2_BASE 0x285000
-#define DG2_GSC_HECI2_BASE 0x374000
-
static void heci_gsc_irq_mask(struct irq_data *d)
{
/* generic irq handling */
diff --git a/drivers/gpu/drm/xe/xe_spi.c b/drivers/gpu/drm/xe/xe_spi.c
index 3dde2ec9c389..91632d68db8a 100644
--- a/drivers/gpu/drm/xe/xe_spi.c
+++ b/drivers/gpu/drm/xe/xe_spi.c
@@ -5,7 +5,10 @@
#include <linux/intel_dg_spi_aux.h>
#include <linux/pci.h>
+#include "xe_device.h"
#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "regs/xe_gsc_regs.h"
#include "xe_spi.h"
#define GEN12_GUNIT_SPI_BASE 0x00102040
@@ -23,6 +26,32 @@ static void xe_spi_release_dev(struct device *dev)
{
}
+static bool xe_spi_writeable_override(struct xe_device *xe)
+{
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+ resource_size_t base;
+ bool writeable_override;
+
+ if (xe->info.platform == XE_PVC) {
+ base = PVC_GSC_HECI2_BASE;
+ } else if (xe->info.platform == XE_DG2) {
+ base = DG2_GSC_HECI2_BASE;
+ } else if (xe->info.platform == XE_DG1) {
+ base = DG1_GSC_HECI2_BASE;
+ } else {
+ dev_err(&pdev->dev, "Unknown platform\n");
+ return true;
+ }
+
+ writeable_override =
+ !(xe_mmio_read32(gt, HECI_H_GS1(base)) &
+ HECI_FW_STATUS_2_SPI_ACCESS_MODE);
+ if (writeable_override)
+ dev_info(&pdev->dev, "SPI access overridden by jumper\n");
+ return writeable_override;
+}
+
void xe_spi_init(struct xe_device *xe)
{
struct intel_dg_spi_dev *spi = &xe->spi;
@@ -34,7 +63,7 @@ void xe_spi_init(struct xe_device *xe)
if (!IS_DGFX(xe))
return;
- spi->writeable_override = false;
+ spi->writeable_override = xe_spi_writeable_override(xe);
spi->bar.parent = &pdev->resource[0];
spi->bar.start = GEN12_GUNIT_SPI_BASE + pdev->resource[0].start;
spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1;
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 39+ messages in thread
* ✗ Fi.CI.BUILD: failure for spi: add driver for Intel discrete graphics
2024-03-28 12:22 ` Alexander Usyskin
` (13 preceding siblings ...)
(?)
@ 2024-03-29 1:15 ` Patchwork
-1 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2024-03-29 1:15 UTC (permalink / raw)
To: Alexander Usyskin; +Cc: intel-gfx
== Series Details ==
Series: spi: add driver for Intel discrete graphics
URL : https://patchwork.freedesktop.org/series/131763/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/131763/revisions/1/mbox/ not applied
Applying: spi: add auxiliary device for intel dg spi
Applying: drm/i915/spi: add spi device for discrete graphics
Applying: drm/i915/spi: add intel_spi_region map
Applying: drm/i915/spi: add support for access mode
Applying: spi: add driver for intel graphics on-die spi device
Applying: spi: intel-dg: implement region enumeration
Applying: spi: intel-dg: implement spi access functions
Applying: spi: intel-dg: spi register with mtd
Applying: spi: intel-dg: implement mtd access handlers
Applying: spi: intel-dg: align 64bit read and write
Applying: spi: intel-dg: wake card on operations
Applying: drm/xe/spi: add on-die spi device
Using index info to reconstruct a base tree...
M drivers/gpu/drm/xe/Makefile
M drivers/gpu/drm/xe/xe_device.c
M drivers/gpu/drm/xe/xe_device_types.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/xe/xe_device_types.h
Auto-merging drivers/gpu/drm/xe/xe_device.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/xe/xe_device.c
Auto-merging drivers/gpu/drm/xe/Makefile
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0012 drm/xe/spi: add on-die spi device
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
2024-03-28 12:22 ` Alexander Usyskin
(?)
@ 2024-03-29 12:43 ` Krzysztof Kozlowski
2024-04-25 11:58 ` Usyskin, Alexander
-1 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-03-29 12:43 UTC (permalink / raw)
To: Alexander Usyskin, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Vitaly Lubart, linux-mtd, intel-gfx, Tomas Winkler, Lucas De Marchi
On 28/03/2024 13:22, Alexander Usyskin wrote:
> Add auxiliary driver for intel discrete graphics
> on-die spi device.
>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/spi/Kconfig | 11 +++
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-intel-dg.c | 146 +++++++++++++++++++++++++++++++++++++
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.
Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline), work on fork of kernel
(don't, instead use mainline) or you ignore some maintainers (really
don't). Just use b4 and everything should be fine, although remember
about `b4 prep --auto-to-cc` if you added new patches to the patchset.
...
> +
> + spi->base = devm_ioremap_resource(device, &ispi->bar);
> + if (IS_ERR(spi->base)) {
> + dev_err(device, "mmio not mapped\n");
> + ret = PTR_ERR(spi->base);
> + goto err;
> + }
> +
> + dev_set_drvdata(&aux_dev->dev, spi);
> +
> + dev_dbg(device, "bound\n");
Sorry, no. No silly function success messages. There is existing
infrastructure for this. Drop.
> +
> + return 0;
> +
> +err:
> + kref_put(&spi->refcnt, intel_dg_spi_release);
> + return ret;
> +}
> +
> +static void intel_dg_spi_remove(struct auxiliary_device *aux_dev)
> +{
> + struct intel_dg_spi *spi = dev_get_drvdata(&aux_dev->dev);
> +
> + if (!spi)
> + return;
> +
> + dev_set_drvdata(&aux_dev->dev, NULL);
> +
> + kref_put(&spi->refcnt, intel_dg_spi_release);
> +}
> +
> +static const struct auxiliary_device_id intel_dg_spi_id_table[] = {
> + {
> + .name = "i915.spi",
> + },
> + {
> + .name = "xe.spi",
> + },
> + {
> + /* sentinel */
> + }
> +};
> +MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table);
> +
> +static struct auxiliary_driver intel_dg_spi_driver = {
> + .probe = intel_dg_spi_probe,
> + .remove = intel_dg_spi_remove,
> + .driver = {
> + /* auxiliary_driver_register() sets .name to be the modname */
> + },
> + .id_table = intel_dg_spi_id_table
> +};
> +
> +module_auxiliary_driver(intel_dg_spi_driver);
> +
> +MODULE_ALIAS("auxiliary:i915.spi");
> +MODULE_ALIAS("auxiliary:xe.spi");
You should not need MODULE_ALIAS() in normal cases. If you need it,
usually it means your device ID table is wrong (e.g. misses either
entries or MODULE_DEVICE_TABLE()). MODULE_ALIAS() is not a substitute
for incomplete ID table.
Best regards,
Krzysztof
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 12/13] drm/xe/spi: add on-die spi device
2024-03-28 12:22 ` Alexander Usyskin
(?)
@ 2024-03-29 12:46 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-03-29 12:46 UTC (permalink / raw)
To: Alexander Usyskin, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Vitaly Lubart, linux-mtd, intel-gfx
On 28/03/2024 13:22, Alexander Usyskin wrote:
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_device.c | 3 ++
> drivers/gpu/drm/xe/xe_device_types.h | 5 ++
> drivers/gpu/drm/xe/xe_spi.c | 78 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_spi.h | 15 ++++++
> 5 files changed, 102 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_spi.c
> create mode 100644 drivers/gpu/drm/xe/xe_spi.h
...
> +
> +void xe_spi_fini(struct xe_device *xe)
> +{
> + struct intel_dg_spi_dev *spi = &xe->spi;
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> + /* Only the DGFX devices have internal SPI */
> + if (!IS_DGFX(xe))
> + return;
> +
> + dev_dbg(&pdev->dev, "removing xe-spi cell\n");
No need for simple functions entry/exit messages. There is already
infrastructure for this. Drop.
Best regards,
Krzysztof
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/13] spi: add auxiliary device for intel dg spi
2024-03-28 12:22 ` Alexander Usyskin
(?)
@ 2024-03-29 12:46 ` Krzysztof Kozlowski
2024-04-11 13:43 ` Usyskin, Alexander
-1 siblings, 1 reply; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-03-29 12:46 UTC (permalink / raw)
To: Alexander Usyskin, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi
Cc: Vitaly Lubart, linux-mtd, intel-gfx
On 28/03/2024 13:22, Alexander Usyskin wrote:
> Add auxilary bus device structure for
> Intel Discrete Graphics SPI device.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
There is no user of this header. Please add it in the patch which uses it.
It will also justify why you use this or other subject prefix. Now, it
looks just wrong: it's not a patch for spi.
If it was a patch for spi, then:
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.
Best regards,
Krzysztof
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
2024-03-28 12:22 ` Alexander Usyskin
@ 2024-03-29 14:11 ` Lucas De Marchi
-1 siblings, 0 replies; 39+ messages in thread
From: Lucas De Marchi @ 2024-03-29 14:11 UTC (permalink / raw)
To: Alexander Usyskin
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Vitaly Lubart,
linux-mtd, intel-gfx, Tomas Winkler
On Thu, Mar 28, 2024 at 02:22:28PM +0200, Alexander Usyskin wrote:
>Add auxiliary driver for intel discrete graphics
>on-die spi device.
>
>CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
did you mean to Cc me? I never gave my s-o-b afair.
The order of the s-o-b in these patches also seem to be messed up. Who
is the author of this patch (and others)? Is it you or Tomas? If it's
Tomas, then the commit in your tree is wrong and you have to fix it up
so when you send the patch git adds a "From:" to the body. Otherwise,
please fix the order.
Lucas De Marchi
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
@ 2024-03-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 39+ messages in thread
From: Lucas De Marchi @ 2024-03-29 14:11 UTC (permalink / raw)
To: Alexander Usyskin
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Vitaly Lubart,
linux-mtd, intel-gfx, Tomas Winkler
On Thu, Mar 28, 2024 at 02:22:28PM +0200, Alexander Usyskin wrote:
>Add auxiliary driver for intel discrete graphics
>on-die spi device.
>
>CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
did you mean to Cc me? I never gave my s-o-b afair.
The order of the s-o-b in these patches also seem to be messed up. Who
is the author of this patch (and others)? Is it you or Tomas? If it's
Tomas, then the commit in your tree is wrong and you have to fix it up
so when you send the patch git adds a "From:" to the body. Otherwise,
please fix the order.
Lucas De Marchi
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH 01/13] spi: add auxiliary device for intel dg spi
2024-03-29 12:46 ` Krzysztof Kozlowski
@ 2024-04-11 13:43 ` Usyskin, Alexander
0 siblings, 0 replies; 39+ messages in thread
From: Usyskin, Alexander @ 2024-04-11 13:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo
Cc: Lubart, Vitaly, linux-mtd, intel-gfx
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Friday, March 29, 2024 15:47
> To: Usyskin, Alexander <alexander.usyskin@intel.com>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Cc: Lubart, Vitaly <vitaly.lubart@intel.com>; linux-mtd@lists.infradead.org; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [PATCH 01/13] spi: add auxiliary device for intel dg spi
>
> On 28/03/2024 13:22, Alexander Usyskin wrote:
> > Add auxilary bus device structure for
> > Intel Discrete Graphics SPI device.
> >
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
>
> There is no user of this header. Please add it in the patch which uses it.
>
This header describes auxiliary device that bridges between
i915 or Xe driver with spi-intel-dg driver.
This header included in both drivers; this is the reason this header
has its own patch.
> It will also justify why you use this or other subject prefix. Now, it
> looks just wrong: it's not a patch for spi.
>
Can you suggest what subject prefix to use?
Like: "auxiliary:"? Something else?
> If it was a patch for spi, then:
>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
>
Sorry for that, will run this script to pick the fresh maintainers list and
push v2 with a new list.
> Best regards,
> Krzysztof
--
Thanks,
Sasha
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH 01/13] spi: add auxiliary device for intel dg spi
@ 2024-04-11 13:43 ` Usyskin, Alexander
0 siblings, 0 replies; 39+ messages in thread
From: Usyskin, Alexander @ 2024-04-11 13:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo
Cc: Lubart, Vitaly, linux-mtd, intel-gfx
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Friday, March 29, 2024 15:47
> To: Usyskin, Alexander <alexander.usyskin@intel.com>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Cc: Lubart, Vitaly <vitaly.lubart@intel.com>; linux-mtd@lists.infradead.org; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [PATCH 01/13] spi: add auxiliary device for intel dg spi
>
> On 28/03/2024 13:22, Alexander Usyskin wrote:
> > Add auxilary bus device structure for
> > Intel Discrete Graphics SPI device.
> >
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
>
> There is no user of this header. Please add it in the patch which uses it.
>
This header describes auxiliary device that bridges between
i915 or Xe driver with spi-intel-dg driver.
This header included in both drivers; this is the reason this header
has its own patch.
> It will also justify why you use this or other subject prefix. Now, it
> looks just wrong: it's not a patch for spi.
>
Can you suggest what subject prefix to use?
Like: "auxiliary:"? Something else?
> If it was a patch for spi, then:
>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.
>
Sorry for that, will run this script to pick the fresh maintainers list and
push v2 with a new list.
> Best regards,
> Krzysztof
--
Thanks,
Sasha
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/13] spi: add auxiliary device for intel dg spi
2024-04-11 13:43 ` Usyskin, Alexander
(?)
@ 2024-04-11 13:51 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 39+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-11 13:51 UTC (permalink / raw)
To: Usyskin, Alexander, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo
Cc: Lubart, Vitaly, linux-mtd, intel-gfx
On 11/04/2024 15:43, Usyskin, Alexander wrote:
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Friday, March 29, 2024 15:47
>> To: Usyskin, Alexander <alexander.usyskin@intel.com>; Miquel Raynal
>> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
>> Raghavendra <vigneshr@ti.com>; Jani Nikula <jani.nikula@linux.intel.com>;
>> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
>> <rodrigo.vivi@intel.com>
>> Cc: Lubart, Vitaly <vitaly.lubart@intel.com>; linux-mtd@lists.infradead.org; intel-
>> gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 01/13] spi: add auxiliary device for intel dg spi
>>
>> On 28/03/2024 13:22, Alexander Usyskin wrote:
>>> Add auxilary bus device structure for
>>> Intel Discrete Graphics SPI device.
>>>
>>> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
>>> ---
>>> include/linux/intel_dg_spi_aux.h | 27 +++++++++++++++++++++++++++
>>
>> There is no user of this header. Please add it in the patch which uses it.
>>
> This header describes auxiliary device that bridges between
> i915 or Xe driver with spi-intel-dg driver.
There is no driver here, just simple header.
> This header included in both drivers; this is the reason this header
> has its own patch.
Does it mean your patchset is going through different trees?
>
>> It will also justify why you use this or other subject prefix. Now, it
>> looks just wrong: it's not a patch for spi.
>>
> Can you suggest what subject prefix to use?
> Like: "auxiliary:"? Something else?
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
>
Best regards,
Krzysztof
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
2024-03-29 12:43 ` Krzysztof Kozlowski
@ 2024-04-25 11:58 ` Usyskin, Alexander
0 siblings, 0 replies; 39+ messages in thread
From: Usyskin, Alexander @ 2024-04-25 11:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo
Cc: Lubart, Vitaly, linux-mtd, intel-gfx, Winkler, Tomas, De Marchi, Lucas
> > +static const struct auxiliary_device_id intel_dg_spi_id_table[] = {
> > + {
> > + .name = "i915.spi",
> > + },
> > + {
> > + .name = "xe.spi",
> > + },
> > + {
> > + /* sentinel */
> > + }
> > +};
> > +MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table);
> > +
> > +static struct auxiliary_driver intel_dg_spi_driver = {
> > + .probe = intel_dg_spi_probe,
> > + .remove = intel_dg_spi_remove,
> > + .driver = {
> > + /* auxiliary_driver_register() sets .name to be the modname */
> > + },
> > + .id_table = intel_dg_spi_id_table
> > +};
> > +
> > +module_auxiliary_driver(intel_dg_spi_driver);
> > +
> > +MODULE_ALIAS("auxiliary:i915.spi");
> > +MODULE_ALIAS("auxiliary:xe.spi");
>
> You should not need MODULE_ALIAS() in normal cases. If you need it,
> usually it means your device ID table is wrong (e.g. misses either
> entries or MODULE_DEVICE_TABLE()). MODULE_ALIAS() is not a substitute
> for incomplete ID table.
>
>
> Best regards,
> Krzysztof
You are right, the auxiliary bus process aliases in the right way,
this is remnants from the platform device usage, will drop.
--
Thanks,
Sasha
^ permalink raw reply [flat|nested] 39+ messages in thread
* RE: [PATCH 05/13] spi: add driver for intel graphics on-die spi device
@ 2024-04-25 11:58 ` Usyskin, Alexander
0 siblings, 0 replies; 39+ messages in thread
From: Usyskin, Alexander @ 2024-04-25 11:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo
Cc: Lubart, Vitaly, linux-mtd, intel-gfx, Winkler, Tomas, De Marchi, Lucas
> > +static const struct auxiliary_device_id intel_dg_spi_id_table[] = {
> > + {
> > + .name = "i915.spi",
> > + },
> > + {
> > + .name = "xe.spi",
> > + },
> > + {
> > + /* sentinel */
> > + }
> > +};
> > +MODULE_DEVICE_TABLE(auxiliary, intel_dg_spi_id_table);
> > +
> > +static struct auxiliary_driver intel_dg_spi_driver = {
> > + .probe = intel_dg_spi_probe,
> > + .remove = intel_dg_spi_remove,
> > + .driver = {
> > + /* auxiliary_driver_register() sets .name to be the modname */
> > + },
> > + .id_table = intel_dg_spi_id_table
> > +};
> > +
> > +module_auxiliary_driver(intel_dg_spi_driver);
> > +
> > +MODULE_ALIAS("auxiliary:i915.spi");
> > +MODULE_ALIAS("auxiliary:xe.spi");
>
> You should not need MODULE_ALIAS() in normal cases. If you need it,
> usually it means your device ID table is wrong (e.g. misses either
> entries or MODULE_DEVICE_TABLE()). MODULE_ALIAS() is not a substitute
> for incomplete ID table.
>
>
> Best regards,
> Krzysztof
You are right, the auxiliary bus process aliases in the right way,
this is remnants from the platform device usage, will drop.
--
Thanks,
Sasha
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2024-04-25 11:58 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-28 12:22 [PATCH 00/13] spi: add driver for Intel discrete graphics Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 01/13] spi: add auxiliary device for intel dg spi Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-29 12:46 ` Krzysztof Kozlowski
2024-04-11 13:43 ` Usyskin, Alexander
2024-04-11 13:43 ` Usyskin, Alexander
2024-04-11 13:51 ` Krzysztof Kozlowski
2024-03-28 12:22 ` [PATCH 02/13] drm/i915/spi: add spi device for discrete graphics Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 03/13] drm/i915/spi: add intel_spi_region map Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 04/13] drm/i915/spi: add support for access mode Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 05/13] spi: add driver for intel graphics on-die spi device Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-29 12:43 ` Krzysztof Kozlowski
2024-04-25 11:58 ` Usyskin, Alexander
2024-04-25 11:58 ` Usyskin, Alexander
2024-03-29 14:11 ` Lucas De Marchi
2024-03-29 14:11 ` Lucas De Marchi
2024-03-28 12:22 ` [PATCH 06/13] spi: intel-dg: implement region enumeration Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 07/13] spi: intel-dg: implement spi access functions Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 08/13] spi: intel-dg: spi register with mtd Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 09/13] spi: intel-dg: implement mtd access handlers Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 10/13] spi: intel-dg: align 64bit read and write Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 11/13] spi: intel-dg: wake card on operations Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-28 12:22 ` [PATCH 12/13] drm/xe/spi: add on-die spi device Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-29 12:46 ` Krzysztof Kozlowski
2024-03-28 12:22 ` [PATCH 13/13] drm/xe/spi: add support for access mode Alexander Usyskin
2024-03-28 12:22 ` Alexander Usyskin
2024-03-29 1:15 ` ✗ Fi.CI.BUILD: failure for spi: add driver for Intel discrete graphics Patchwork
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