From: Jason Gunthorpe <jgg@nvidia.com> To: Will Deacon <will@kernel.org> Cc: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>, linux-arm-kernel@lists.infradead.org, Robin Murphy <robin.murphy@arm.com>, Lu Baolu <baolu.lu@linux.intel.com>, Eric Auger <eric.auger@redhat.com>, Jean-Philippe Brucker <jean-philippe@linaro.org>, Joerg Roedel <jroedel@suse.de>, Kevin Tian <kevin.tian@intel.com>, kernel test robot <lkp@intel.com>, Moritz Fischer <mdf@kernel.org>, Moritz Fischer <moritzf@google.com>, Michael Shavit <mshavit@google.com>, Nicolin Chen <nicolinc@nvidia.com>, patches@lists.linux.dev, Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>, Mostafa Saleh <smostafa@google.com>, Tony Zhu <tony.zhu@intel.com>, Yi Liu <yi.l.liu@intel.com>, Zhangfei Gao <zhangfei.gao@linaro.org> Subject: Re: [PATCH v6 06/29] iommu/arm-smmu-v3: Add an ops indirection to the STE code Date: Tue, 9 Apr 2024 20:55:12 -0300 [thread overview] Message-ID: <20240409235512.GK5383@nvidia.com> (raw) In-Reply-To: <20240409124007.GA23088@willie-the-truck> On Tue, Apr 09, 2024 at 01:40:08PM +0100, Will Deacon wrote: > On Wed, Mar 27, 2024 at 03:07:52PM -0300, Jason Gunthorpe wrote: > > Prepare to put the CD code into the same mechanism. Add an ops indirection > > around all the STE specific code and make the worker functions independent > > of the entry content being processed. > > > > get_used and sync ops are provided to hook the correct code. > > > > Signed-off-by: Michael Shavit <mshavit@google.com> > > Reviewed-by: Michael Shavit <mshavit@google.com> > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > > Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 170 ++++++++++++-------- > > 1 file changed, 102 insertions(+), 68 deletions(-) > > Any chance we can pull the STE testing stuff forward from Michael once > we have the entry writing ops indirection, please? It would be nice to > land that before adding the CD support, I think. Yes, I can. There is a bit more work because the CD testing is still not finished, but I can probably do that. How about this, I split part 2 into half and the first half ends at "iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd()" (it finishes changing the CD programming to look like the STE). I'll pull forward the selftest patch into that series. That is another 9 patches from what you have taken so far. The second half is all about "building a generic pasid layer". Those 8 patches have all been looked at now, so if we pick them up soonish we can more easially focus on the latter patches. Agree? > > used_qword_diff = > > - arm_smmu_entry_qword_diff(entry, target, &unused_update); > > + arm_smmu_entry_qword_diff(writer, entry, target, unused_update); > > if (hweight8(used_qword_diff) == 1) { > > /* > > * Only one qword needs its used bits to be changed. This is a > > nit: This comment (lost in the diff context) refers to STEs a couple of > times. Please update to e.g. "STE/CD". Ok, I'll check them Thanks, Jason
WARNING: multiple messages have this Message-ID (diff)
From: Jason Gunthorpe <jgg@nvidia.com> To: Will Deacon <will@kernel.org> Cc: iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>, linux-arm-kernel@lists.infradead.org, Robin Murphy <robin.murphy@arm.com>, Lu Baolu <baolu.lu@linux.intel.com>, Eric Auger <eric.auger@redhat.com>, Jean-Philippe Brucker <jean-philippe@linaro.org>, Joerg Roedel <jroedel@suse.de>, Kevin Tian <kevin.tian@intel.com>, kernel test robot <lkp@intel.com>, Moritz Fischer <mdf@kernel.org>, Moritz Fischer <moritzf@google.com>, Michael Shavit <mshavit@google.com>, Nicolin Chen <nicolinc@nvidia.com>, patches@lists.linux.dev, Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>, Mostafa Saleh <smostafa@google.com>, Tony Zhu <tony.zhu@intel.com>, Yi Liu <yi.l.liu@intel.com>, Zhangfei Gao <zhangfei.gao@linaro.org> Subject: Re: [PATCH v6 06/29] iommu/arm-smmu-v3: Add an ops indirection to the STE code Date: Tue, 9 Apr 2024 20:55:12 -0300 [thread overview] Message-ID: <20240409235512.GK5383@nvidia.com> (raw) In-Reply-To: <20240409124007.GA23088@willie-the-truck> On Tue, Apr 09, 2024 at 01:40:08PM +0100, Will Deacon wrote: > On Wed, Mar 27, 2024 at 03:07:52PM -0300, Jason Gunthorpe wrote: > > Prepare to put the CD code into the same mechanism. Add an ops indirection > > around all the STE specific code and make the worker functions independent > > of the entry content being processed. > > > > get_used and sync ops are provided to hook the correct code. > > > > Signed-off-by: Michael Shavit <mshavit@google.com> > > Reviewed-by: Michael Shavit <mshavit@google.com> > > Tested-by: Nicolin Chen <nicolinc@nvidia.com> > > Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> > > Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 170 ++++++++++++-------- > > 1 file changed, 102 insertions(+), 68 deletions(-) > > Any chance we can pull the STE testing stuff forward from Michael once > we have the entry writing ops indirection, please? It would be nice to > land that before adding the CD support, I think. Yes, I can. There is a bit more work because the CD testing is still not finished, but I can probably do that. How about this, I split part 2 into half and the first half ends at "iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd()" (it finishes changing the CD programming to look like the STE). I'll pull forward the selftest patch into that series. That is another 9 patches from what you have taken so far. The second half is all about "building a generic pasid layer". Those 8 patches have all been looked at now, so if we pick them up soonish we can more easially focus on the latter patches. Agree? > > used_qword_diff = > > - arm_smmu_entry_qword_diff(entry, target, &unused_update); > > + arm_smmu_entry_qword_diff(writer, entry, target, unused_update); > > if (hweight8(used_qword_diff) == 1) { > > /* > > * Only one qword needs its used bits to be changed. This is a > > nit: This comment (lost in the diff context) refers to STEs a couple of > times. Please update to e.g. "STE/CD". Ok, I'll check them Thanks, Jason _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-04-09 23:55 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-27 18:07 [PATCH v6 00/29] Update SMMUv3 to the modern iommu API (part 2/3) Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 01/29] iommu: Validate the PASID in iommu_attach_device_pasid() Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 02/29] iommu/arm-smmu-v3: Add cpu_to_le64() around STRTAB_STE_0_V Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 03/29] iommu/arm-smmu-v3: Do not allow a SVA domain to be set on the wrong PASID Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-28 13:18 ` Mostafa Saleh 2024-03-28 13:18 ` Mostafa Saleh 2024-04-04 14:04 ` Jason Gunthorpe 2024-04-04 14:04 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 04/29] iommu/arm-smmu-v3: Do not ATC invalidate the entire domain Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 05/29] iommu/arm-smmu-v3: Add a type for the CD entry Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 06/29] iommu/arm-smmu-v3: Add an ops indirection to the STE code Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-04-09 12:40 ` Will Deacon 2024-04-09 12:40 ` Will Deacon 2024-04-09 23:55 ` Jason Gunthorpe [this message] 2024-04-09 23:55 ` Jason Gunthorpe 2024-04-10 14:44 ` Will Deacon 2024-04-10 14:44 ` Will Deacon 2024-03-27 18:07 ` [PATCH v6 07/29] iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry() Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 08/29] iommu/arm-smmu-v3: Move the CD generation for S1 domains into a function Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 09/29] iommu/arm-smmu-v3: Consolidate clearing a CD table entry Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 10/29] iommu/arm-smmu-v3: Make arm_smmu_alloc_cd_ptr() Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 11/29] iommu/arm-smmu-v3: Allocate the CD table entry in advance Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 12/29] iommu/arm-smmu-v3: Move the CD generation for SVA into a function Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:07 ` [PATCH v6 13/29] iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd() Jason Gunthorpe 2024-03-27 18:07 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 14/29] iommu/arm-smmu-v3: Start building a generic PASID layer Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 15/29] iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 16/29] iommu/arm-smmu-v3: Make changing domains be hitless for ATS Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 17/29] iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 18/29] iommu/arm-smmu-v3: Do not use master->sva_enable to restrict attaches Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 19/29] iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 20/29] iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 21/29] iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 22/29] iommu: Add ops->domain_alloc_sva() Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 23/29] iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 24/29] iommu/arm-smmu-v3: Consolidate freeing the ASID/VMID Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 25/29] iommu/arm-smmu-v3: Move the arm_smmu_asid_xa to per-smmu like vmid Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 26/29] iommu/arm-smmu-v3: Bring back SVA BTM support Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 27/29] iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 28/29] iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-03-27 18:08 ` [PATCH v6 29/29] iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID Jason Gunthorpe 2024-03-27 18:08 ` Jason Gunthorpe 2024-04-09 12:54 ` [PATCH v6 00/29] Update SMMUv3 to the modern iommu API (part 2/3) Will Deacon 2024-04-09 12:54 ` Will Deacon 2024-04-09 23:55 ` Jason Gunthorpe 2024-04-09 23:55 ` Jason Gunthorpe
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