[PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Zayd Qumsieh]

x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
selectively use a TSO memory model. This can be done by setting the
ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
removes the need for emulators to insert memory barriers in order to abide
by the TSO memory model. This patch series will add ACTLR.TSOEN support to
virtualized linux on Apple Silicon machines. Userspace will be able to use
a prctl to change the memory model of the CPU from the default ARM64 memory
model to a TSO memory model.

A simple test can be used to determine if the TSO memory model is in use.
This must be done on Apple Silicon MacOS Sonoma version 14.4 or later,
since earlier versions do not support modification of the TSOEN bit.
https://github.com/saagarjha/TSOEnabler/blob/master/testtso/main.c

This program will hang indefinitely if TSO is in use, and will crash almost
immediately if it is not in use.

Zayd Qumsieh (3):
  tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN
  tso: aarch64: context-switch tso bit on thread switch
  tso: aarch64: allow userspace to set tso bit using prctl

 arch/arm64/Kconfig                 | 19 +++++++++
 arch/arm64/include/asm/processor.h |  4 ++
 arch/arm64/include/asm/sysreg.h    |  7 ++++
 arch/arm64/include/asm/tso.h       | 19 +++++++++
 arch/arm64/kernel/Makefile         |  2 +-
 arch/arm64/kernel/process.c        | 61 +++++++++++++++++++++++++++++
 arch/arm64/kernel/tso.c            | 62 ++++++++++++++++++++++++++++++
 include/uapi/linux/prctl.h         |  9 +++++
 kernel/sys.c                       | 11 ++++++
 9 files changed, 193 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/tso.h
 create mode 100644 arch/arm64/kernel/tso.c

-- 
2.39.3 (Apple Git-146)


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Zayd Qumsieh]

x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
selectively use a TSO memory model. This can be done by setting the
ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
removes the need for emulators to insert memory barriers in order to abide
by the TSO memory model. This patch series will add ACTLR.TSOEN support to
virtualized linux on Apple Silicon machines. Userspace will be able to use
a prctl to change the memory model of the CPU from the default ARM64 memory
model to a TSO memory model.

A simple test can be used to determine if the TSO memory model is in use.
This must be done on Apple Silicon MacOS Sonoma version 14.4 or later,
since earlier versions do not support modification of the TSOEN bit.
https://github.com/saagarjha/TSOEnabler/blob/master/testtso/main.c

This program will hang indefinitely if TSO is in use, and will crash almost
immediately if it is not in use.

Zayd Qumsieh (3):
  tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN
  tso: aarch64: context-switch tso bit on thread switch
  tso: aarch64: allow userspace to set tso bit using prctl

 arch/arm64/Kconfig                 | 19 +++++++++
 arch/arm64/include/asm/processor.h |  4 ++
 arch/arm64/include/asm/sysreg.h    |  7 ++++
 arch/arm64/include/asm/tso.h       | 19 +++++++++
 arch/arm64/kernel/Makefile         |  2 +-
 arch/arm64/kernel/process.c        | 61 +++++++++++++++++++++++++++++
 arch/arm64/kernel/tso.c            | 62 ++++++++++++++++++++++++++++++
 include/uapi/linux/prctl.h         |  9 +++++
 kernel/sys.c                       | 11 ++++++
 9 files changed, 193 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/tso.h
 create mode 100644 arch/arm64/kernel/tso.c

-- 
2.39.3 (Apple Git-146)

[PATCH 1/3] tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN

[Zayd Qumsieh]

Create a couple simplistic functions that can read / modify the
ACTLR.TSOEN bit on Apple Silicon. Setting this bit to 1 will change
the CPU's memory model to x86-64's TSO memory model. Clearing it will
set the CPU's memory model to the standard ARM64 memory model.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/Kconfig              | 13 +++++++++
 arch/arm64/include/asm/sysreg.h |  7 +++++
 arch/arm64/include/asm/tso.h    | 17 +++++++++++
 arch/arm64/kernel/Makefile      |  2 +-
 arch/arm64/kernel/tso.c         | 52 +++++++++++++++++++++++++++++++++
 5 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/tso.h
 create mode 100644 arch/arm64/kernel/tso.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..35162e5a0705 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
+# Copyright © 2024 Apple Inc. All rights reserved.
 config ARM64
 	def_bool y
 	select ACPI_APMT if ACPI
@@ -2079,6 +2080,18 @@ config ARM64_MTE
 
 	  Documentation/arch/arm64/memory-tagging-extension.rst.
 
+config ARM64_TSO
+	bool "ARM64 Apple Silicon TSO support"
+	default y
+	help
+	  Apple Silicon TSO mode allows the CPU's memory model to be
+	  dynamically switched between the default ARM64 memory model
+	  and x86_64's memory model (TSO).
+
+	  Selecting this option allows the feature to be detected at
+	  runtime. If the CPU doesn't implement TSO mode, then this
+	  feature will be disabled.
+
 endmenu # "ARMv8.5 architectural features"
 
 menu "ARMv8.7 architectural features"
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e8999592f3a..5464217c6bfd 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -4,6 +4,8 @@
  *
  * Copyright (C) 2014 ARM Ltd.
  * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 
 #ifndef __ASM_SYSREG_H
@@ -277,6 +279,9 @@
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
 
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
+#define SYS_ACTLR_EL1_TSOEN_SHIFT       1
+#define SYS_ACTLR_EL1_TSOEN_MASK        (1 << SYS_ACTLR_EL1_TSOEN_SHIFT)
+
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 
@@ -394,6 +399,8 @@
 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
 
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
+#define SYS_AIDR_EL1_TSO_SHIFT          9
+#define SYS_AIDR_EL1_TSO_MASK           (1 << SYS_AIDR_EL1_TSO_SHIFT)
 
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
new file mode 100644
index 000000000000..d9e1a7602c44
--- /dev/null
+++ b/arch/arm64/include/asm/tso.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
+#ifndef __ASM_TSO_H
+#define __ASM_TSO_H
+
+#ifdef CONFIG_ARM64_TSO
+
+#include <linux/sched.h>
+#include <linux/types.h>
+
+int modify_tso_enable(bool tso_enable);
+
+#endif /* CONFIG_ARM64_TSO */
+#endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 763824963ed1..a2a7c74fb00d 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -33,7 +33,7 @@ obj-y			:= debug-monitors.o entry.o irq.o fpsimd.o		\
 			   return_address.o cpuinfo.o cpu_errata.o		\
 			   cpufeature.o alternative.o cacheinfo.o		\
 			   smp.o smp_spin_table.o topology.o smccc-call.o	\
-			   syscall.o proton-pack.o idle.o patching.o pi/
+			   syscall.o proton-pack.o idle.o patching.o tso.o pi/ \
 
 obj-$(CONFIG_COMPAT)			+= sys32.o signal32.o			\
 					   sys_compat.o
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
new file mode 100644
index 000000000000..b3964db7aa66
--- /dev/null
+++ b/arch/arm64/kernel/tso.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+
+#include <asm/cputype.h>
+#include <asm/processor.h>
+#include <asm/sysreg.h>
+#include <asm/tso.h>
+
+#ifdef CONFIG_ARM64_TSO
+
+static bool tso_supported(void)
+{
+	unsigned int cpuid_implementor = read_cpuid_implementor();
+	u64 aidr = read_sysreg(aidr_el1);
+
+	return (cpuid_implementor == ARM_CPU_IMP_APPLE) &&
+		(aidr & SYS_AIDR_EL1_TSO_MASK);
+}
+
+static int tso_enabled(void)
+{
+	if (!tso_supported())
+		return -EOPNOTSUPP;
+
+	u64 actlr_el1 = read_sysreg(actlr_el1);
+
+	return !!(actlr_el1 & SYS_ACTLR_EL1_TSOEN_MASK);
+}
+
+int modify_tso_enable(bool tso_enable)
+{
+	if (!tso_supported())
+		return -EOPNOTSUPP;
+
+	u64 actlr_el1_old = read_sysreg(actlr_el1);
+	u64 actlr_el1_new =
+		(actlr_el1_old & ~SYS_ACTLR_EL1_TSOEN_MASK) |
+		(tso_enable << SYS_ACTLR_EL1_TSOEN_SHIFT);
+
+	write_sysreg(actlr_el1_new, actlr_el1);
+
+	if (tso_enabled() != tso_enable)
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
+#endif /* CONFIG_ARM64_TSO */
-- 
2.39.3 (Apple Git-146)

[PATCH 1/3] tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN

[Zayd Qumsieh]

Create a couple simplistic functions that can read / modify the
ACTLR.TSOEN bit on Apple Silicon. Setting this bit to 1 will change
the CPU's memory model to x86-64's TSO memory model. Clearing it will
set the CPU's memory model to the standard ARM64 memory model.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/Kconfig              | 13 +++++++++
 arch/arm64/include/asm/sysreg.h |  7 +++++
 arch/arm64/include/asm/tso.h    | 17 +++++++++++
 arch/arm64/kernel/Makefile      |  2 +-
 arch/arm64/kernel/tso.c         | 52 +++++++++++++++++++++++++++++++++
 5 files changed, 90 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/tso.h
 create mode 100644 arch/arm64/kernel/tso.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7b11c98b3e84..35162e5a0705 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
+# Copyright © 2024 Apple Inc. All rights reserved.
 config ARM64
 	def_bool y
 	select ACPI_APMT if ACPI
@@ -2079,6 +2080,18 @@ config ARM64_MTE
 
 	  Documentation/arch/arm64/memory-tagging-extension.rst.
 
+config ARM64_TSO
+	bool "ARM64 Apple Silicon TSO support"
+	default y
+	help
+	  Apple Silicon TSO mode allows the CPU's memory model to be
+	  dynamically switched between the default ARM64 memory model
+	  and x86_64's memory model (TSO).
+
+	  Selecting this option allows the feature to be detected at
+	  runtime. If the CPU doesn't implement TSO mode, then this
+	  feature will be disabled.
+
 endmenu # "ARMv8.5 architectural features"
 
 menu "ARMv8.7 architectural features"
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e8999592f3a..5464217c6bfd 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -4,6 +4,8 @@
  *
  * Copyright (C) 2014 ARM Ltd.
  * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 
 #ifndef __ASM_SYSREG_H
@@ -277,6 +279,9 @@
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
 
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
+#define SYS_ACTLR_EL1_TSOEN_SHIFT       1
+#define SYS_ACTLR_EL1_TSOEN_MASK        (1 << SYS_ACTLR_EL1_TSOEN_SHIFT)
+
 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
 
@@ -394,6 +399,8 @@
 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
 
 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
+#define SYS_AIDR_EL1_TSO_SHIFT          9
+#define SYS_AIDR_EL1_TSO_MASK           (1 << SYS_AIDR_EL1_TSO_SHIFT)
 
 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
new file mode 100644
index 000000000000..d9e1a7602c44
--- /dev/null
+++ b/arch/arm64/include/asm/tso.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
+#ifndef __ASM_TSO_H
+#define __ASM_TSO_H
+
+#ifdef CONFIG_ARM64_TSO
+
+#include <linux/sched.h>
+#include <linux/types.h>
+
+int modify_tso_enable(bool tso_enable);
+
+#endif /* CONFIG_ARM64_TSO */
+#endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 763824963ed1..a2a7c74fb00d 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -33,7 +33,7 @@ obj-y			:= debug-monitors.o entry.o irq.o fpsimd.o		\
 			   return_address.o cpuinfo.o cpu_errata.o		\
 			   cpufeature.o alternative.o cacheinfo.o		\
 			   smp.o smp_spin_table.o topology.o smccc-call.o	\
-			   syscall.o proton-pack.o idle.o patching.o pi/
+			   syscall.o proton-pack.o idle.o patching.o tso.o pi/ \
 
 obj-$(CONFIG_COMPAT)			+= sys32.o signal32.o			\
 					   sys_compat.o
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
new file mode 100644
index 000000000000..b3964db7aa66
--- /dev/null
+++ b/arch/arm64/kernel/tso.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+
+#include <asm/cputype.h>
+#include <asm/processor.h>
+#include <asm/sysreg.h>
+#include <asm/tso.h>
+
+#ifdef CONFIG_ARM64_TSO
+
+static bool tso_supported(void)
+{
+	unsigned int cpuid_implementor = read_cpuid_implementor();
+	u64 aidr = read_sysreg(aidr_el1);
+
+	return (cpuid_implementor == ARM_CPU_IMP_APPLE) &&
+		(aidr & SYS_AIDR_EL1_TSO_MASK);
+}
+
+static int tso_enabled(void)
+{
+	if (!tso_supported())
+		return -EOPNOTSUPP;
+
+	u64 actlr_el1 = read_sysreg(actlr_el1);
+
+	return !!(actlr_el1 & SYS_ACTLR_EL1_TSOEN_MASK);
+}
+
+int modify_tso_enable(bool tso_enable)
+{
+	if (!tso_supported())
+		return -EOPNOTSUPP;
+
+	u64 actlr_el1_old = read_sysreg(actlr_el1);
+	u64 actlr_el1_new =
+		(actlr_el1_old & ~SYS_ACTLR_EL1_TSOEN_MASK) |
+		(tso_enable << SYS_ACTLR_EL1_TSOEN_SHIFT);
+
+	write_sysreg(actlr_el1_new, actlr_el1);
+
+	if (tso_enabled() != tso_enable)
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
+#endif /* CONFIG_ARM64_TSO */
-- 
2.39.3 (Apple Git-146)


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/3] tso: aarch64: context-switch tso bit on thread switch

[Zayd Qumsieh]

Add support for context-switching the tso bit when the thread
switches. This allows per-thread setting of the tso bit, and prepares
future work to allow userspace to set the tso bit of their thread
at will.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/include/asm/processor.h | 4 ++++
 arch/arm64/include/asm/tso.h       | 1 +
 arch/arm64/kernel/process.c        | 9 +++++++++
 arch/arm64/kernel/tso.c            | 9 +++++++++
 4 files changed, 23 insertions(+)

diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f77371232d8c..a247bee24c73 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -4,6 +4,7 @@
  *
  * Copyright (C) 1995-1999 Russell King
  * Copyright (C) 2012 ARM Ltd.
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 #ifndef __ASM_PROCESSOR_H
 #define __ASM_PROCESSOR_H
@@ -184,6 +185,9 @@ struct thread_struct {
 	u64			sctlr_user;
 	u64			svcr;
 	u64			tpidr2_el0;
+#ifdef CONFIG_ARM64_TSO
+	bool        tso;
+#endif
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
index d9e1a7602c44..405e9a5efdf5 100644
--- a/arch/arm64/include/asm/tso.h
+++ b/arch/arm64/include/asm/tso.h
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 
 int modify_tso_enable(bool tso_enable);
+void tso_thread_switch(struct task_struct *next);
 
 #endif /* CONFIG_ARM64_TSO */
 #endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 4ae31b7af6c3..3831c1a97f79 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -5,6 +5,7 @@
  * Original Copyright (C) 1995  Linus Torvalds
  * Copyright (C) 1996-2000 Russell King - Converted to ARM.
  * Copyright (C) 2012 ARM Ltd.
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 #include <linux/compat.h>
 #include <linux/efi.h>
@@ -55,6 +56,7 @@
 #include <asm/stacktrace.h>
 #include <asm/switch_to.h>
 #include <asm/system_misc.h>
+#include <asm/tso.h>
 
 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
 #include <linux/stackprotector.h>
@@ -530,6 +532,9 @@ struct task_struct *__switch_to(struct task_struct *prev,
 	ssbs_thread_switch(next);
 	erratum_1418040_thread_switch(next);
 	ptrauth_thread_switch_user(next);
+#ifdef CONFIG_ARM64_TSO
+	tso_thread_switch(next);
+#endif
 
 	/*
 	 * Complete any pending TLB or cache maintenance on this CPU in case
@@ -651,6 +656,10 @@ void arch_setup_new_exec(void)
 		arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
 					 PR_SPEC_ENABLE);
 	}
+
+#ifdef CONFIG_ARM64_TSO
+	modify_tso_enable(false);
+#endif
 }
 
 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
index b3964db7aa66..9a15d825943f 100644
--- a/arch/arm64/kernel/tso.c
+++ b/arch/arm64/kernel/tso.c
@@ -3,6 +3,7 @@
  * Copyright © 2024 Apple Inc. All rights reserved.
  */
 
+#include <linux/sched.h>
 #include <linux/types.h>
 
 #include <asm/cputype.h>
@@ -49,4 +50,12 @@ int modify_tso_enable(bool tso_enable)
 	return 0;
 }
 
+void tso_thread_switch(struct task_struct *next)
+{
+	if (tso_supported()) {
+		current->thread.tso = tso_enabled();
+		modify_tso_enable(next->thread.tso);
+	}
+}
+
 #endif /* CONFIG_ARM64_TSO */
-- 
2.39.3 (Apple Git-146)


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 2/3] tso: aarch64: context-switch tso bit on thread switch

[Zayd Qumsieh]

Add support for context-switching the tso bit when the thread
switches. This allows per-thread setting of the tso bit, and prepares
future work to allow userspace to set the tso bit of their thread
at will.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/include/asm/processor.h | 4 ++++
 arch/arm64/include/asm/tso.h       | 1 +
 arch/arm64/kernel/process.c        | 9 +++++++++
 arch/arm64/kernel/tso.c            | 9 +++++++++
 4 files changed, 23 insertions(+)

diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f77371232d8c..a247bee24c73 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -4,6 +4,7 @@
  *
  * Copyright (C) 1995-1999 Russell King
  * Copyright (C) 2012 ARM Ltd.
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 #ifndef __ASM_PROCESSOR_H
 #define __ASM_PROCESSOR_H
@@ -184,6 +185,9 @@ struct thread_struct {
 	u64			sctlr_user;
 	u64			svcr;
 	u64			tpidr2_el0;
+#ifdef CONFIG_ARM64_TSO
+	bool        tso;
+#endif
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
index d9e1a7602c44..405e9a5efdf5 100644
--- a/arch/arm64/include/asm/tso.h
+++ b/arch/arm64/include/asm/tso.h
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 
 int modify_tso_enable(bool tso_enable);
+void tso_thread_switch(struct task_struct *next);
 
 #endif /* CONFIG_ARM64_TSO */
 #endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 4ae31b7af6c3..3831c1a97f79 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -5,6 +5,7 @@
  * Original Copyright (C) 1995  Linus Torvalds
  * Copyright (C) 1996-2000 Russell King - Converted to ARM.
  * Copyright (C) 2012 ARM Ltd.
+ * Copyright © 2024 Apple Inc. All rights reserved.
  */
 #include <linux/compat.h>
 #include <linux/efi.h>
@@ -55,6 +56,7 @@
 #include <asm/stacktrace.h>
 #include <asm/switch_to.h>
 #include <asm/system_misc.h>
+#include <asm/tso.h>
 
 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
 #include <linux/stackprotector.h>
@@ -530,6 +532,9 @@ struct task_struct *__switch_to(struct task_struct *prev,
 	ssbs_thread_switch(next);
 	erratum_1418040_thread_switch(next);
 	ptrauth_thread_switch_user(next);
+#ifdef CONFIG_ARM64_TSO
+	tso_thread_switch(next);
+#endif
 
 	/*
 	 * Complete any pending TLB or cache maintenance on this CPU in case
@@ -651,6 +656,10 @@ void arch_setup_new_exec(void)
 		arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
 					 PR_SPEC_ENABLE);
 	}
+
+#ifdef CONFIG_ARM64_TSO
+	modify_tso_enable(false);
+#endif
 }
 
 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
index b3964db7aa66..9a15d825943f 100644
--- a/arch/arm64/kernel/tso.c
+++ b/arch/arm64/kernel/tso.c
@@ -3,6 +3,7 @@
  * Copyright © 2024 Apple Inc. All rights reserved.
  */
 
+#include <linux/sched.h>
 #include <linux/types.h>
 
 #include <asm/cputype.h>
@@ -49,4 +50,12 @@ int modify_tso_enable(bool tso_enable)
 	return 0;
 }
 
+void tso_thread_switch(struct task_struct *next)
+{
+	if (tso_supported()) {
+		current->thread.tso = tso_enabled();
+		modify_tso_enable(next->thread.tso);
+	}
+}
+
 #endif /* CONFIG_ARM64_TSO */
-- 
2.39.3 (Apple Git-146)

[PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl

[Zayd Qumsieh]

Add a new prctl to allow userspace to change the TSO bit. This is
useful for emulators that recompile x86_64 to ARM64. Such programs used
to need to emulate TSO by hand, which has massive performance
ramifications. With this change, emulators can now use prctl to set the
TSO bit at will, and avoid emulating TSO.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/Kconfig           |  6 +++++
 arch/arm64/include/asm/tso.h |  1 +
 arch/arm64/kernel/process.c  | 52 ++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/tso.c      |  1 +
 include/uapi/linux/prctl.h   |  9 +++++++
 kernel/sys.c                 | 11 ++++++++
 6 files changed, 80 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 35162e5a0705..ecb7e1f080af 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2088,10 +2088,16 @@ config ARM64_TSO
 	  dynamically switched between the default ARM64 memory model
 	  and x86_64's memory model (TSO).
 
+	  This option enables the support for toggling TSO mode for
+	  userspace threads.
+
 	  Selecting this option allows the feature to be detected at
 	  runtime. If the CPU doesn't implement TSO mode, then this
 	  feature will be disabled.
 
+	  Userspace threads that want to use this feature must
+	  explicitly opt in via a prctl().
+
 endmenu # "ARMv8.5 architectural features"
 
 menu "ARMv8.7 architectural features"
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
index 405e9a5efdf5..cf31c685b1dd 100644
--- a/arch/arm64/include/asm/tso.h
+++ b/arch/arm64/include/asm/tso.h
@@ -13,6 +13,7 @@
 
 int modify_tso_enable(bool tso_enable);
 void tso_thread_switch(struct task_struct *next);
+int arch_set_mem_model(struct task_struct *task, int memory_model);
 
 #endif /* CONFIG_ARM64_TSO */
 #endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 3831c1a97f79..2b0e9a5331e0 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -763,3 +763,55 @@ int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
 	return prot;
 }
 #endif
+
+static int arch_set_mem_model_default(struct task_struct *task)
+{
+	int return_error = 0;
+
+#ifdef CONFIG_ARM64_TSO
+	int modify_tso_enable_error = modify_tso_enable(false);
+
+	if (modify_tso_enable_error == -EOPNOTSUPP)
+		// TSO is the only other memory model on arm64.
+		// If TSO is not supported, then the default memory
+		// model must already be set.
+		return_error = 0;
+	else
+		return_error = modify_tso_enable_error;
+
+	if (!return_error)
+		task->thread.tso = false;
+
+	return return_error;
+#endif
+
+	return return_error;
+}
+
+#ifdef CONFIG_ARM64_TSO
+
+static int arch_set_mem_model_tso(struct task_struct *task)
+{
+	int error = modify_tso_enable(true);
+
+	if (!error)
+		task->thread.tso = true;
+
+	return error;
+}
+
+#endif /* CONFIG_ARM64_TSO */
+
+int arch_set_mem_model(struct task_struct *task, int memory_model)
+{
+	switch (memory_model) {
+	case PR_SET_MEM_MODEL_DEFAULT:
+		return arch_set_mem_model_default(task);
+#ifdef CONFIG_ARM64_TSO
+	case PR_SET_MEM_MODEL_TSO:
+		return arch_set_mem_model_tso(task);
+#endif /* CONFIG_ARM64_TSO */
+	default:
+		return -EINVAL;
+	}
+}
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
index 9a15d825943f..44749f1f5e10 100644
--- a/arch/arm64/kernel/tso.c
+++ b/arch/arm64/kernel/tso.c
@@ -58,4 +58,5 @@ void tso_thread_switch(struct task_struct *next)
 	}
 }
 
+
 #endif /* CONFIG_ARM64_TSO */
diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h
index 370ed14b1ae0..62b767e6efcf 100644
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@ -1,4 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
 #ifndef _LINUX_PRCTL_H
 #define _LINUX_PRCTL_H
 
@@ -306,4 +310,9 @@ struct prctl_mm_map {
 # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK	0xc
 # define PR_RISCV_V_VSTATE_CTRL_MASK		0x1f
 
+/* Set the CPU memory model */
+#define PR_SET_MEM_MODEL		71
+# define PR_SET_MEM_MODEL_DEFAULT	0
+# define PR_SET_MEM_MODEL_TSO		1
+
 #endif /* _LINUX_PRCTL_H */
diff --git a/kernel/sys.c b/kernel/sys.c
index 8bb106a56b3a..94c18700b849 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -3,6 +3,7 @@
  *  linux/kernel/sys.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
+ *  Copyright © 2024 Apple Inc. All rights reserved.
  */
 
 #include <linux/export.h>
@@ -2315,6 +2316,11 @@ int __weak arch_prctl_spec_ctrl_set(struct task_struct *t, unsigned long which,
 	return -EINVAL;
 }
 
+int __weak arch_set_mem_model(struct task_struct *task, int memory_model)
+{
+	return -EINVAL;
+}
+
 #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE)
 
 #ifdef CONFIG_ANON_VMA_NAME
@@ -2760,6 +2766,11 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,
 	case PR_RISCV_V_GET_CONTROL:
 		error = RISCV_V_GET_CONTROL();
 		break;
+	case PR_SET_MEM_MODEL:
+		if (arg3 || arg4 || arg5)
+			return -EINVAL;
+		error = arch_set_mem_model(current, arg2);
+		break;
 	default:
 		error = -EINVAL;
 		break;
-- 
2.39.3 (Apple Git-146)


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl

[Zayd Qumsieh]

Add a new prctl to allow userspace to change the TSO bit. This is
useful for emulators that recompile x86_64 to ARM64. Such programs used
to need to emulate TSO by hand, which has massive performance
ramifications. With this change, emulators can now use prctl to set the
TSO bit at will, and avoid emulating TSO.

Signed-off-by: Zayd Qumsieh <zayd_qumsieh@apple.com>
---
 arch/arm64/Kconfig           |  6 +++++
 arch/arm64/include/asm/tso.h |  1 +
 arch/arm64/kernel/process.c  | 52 ++++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/tso.c      |  1 +
 include/uapi/linux/prctl.h   |  9 +++++++
 kernel/sys.c                 | 11 ++++++++
 6 files changed, 80 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 35162e5a0705..ecb7e1f080af 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -2088,10 +2088,16 @@ config ARM64_TSO
 	  dynamically switched between the default ARM64 memory model
 	  and x86_64's memory model (TSO).
 
+	  This option enables the support for toggling TSO mode for
+	  userspace threads.
+
 	  Selecting this option allows the feature to be detected at
 	  runtime. If the CPU doesn't implement TSO mode, then this
 	  feature will be disabled.
 
+	  Userspace threads that want to use this feature must
+	  explicitly opt in via a prctl().
+
 endmenu # "ARMv8.5 architectural features"
 
 menu "ARMv8.7 architectural features"
diff --git a/arch/arm64/include/asm/tso.h b/arch/arm64/include/asm/tso.h
index 405e9a5efdf5..cf31c685b1dd 100644
--- a/arch/arm64/include/asm/tso.h
+++ b/arch/arm64/include/asm/tso.h
@@ -13,6 +13,7 @@
 
 int modify_tso_enable(bool tso_enable);
 void tso_thread_switch(struct task_struct *next);
+int arch_set_mem_model(struct task_struct *task, int memory_model);
 
 #endif /* CONFIG_ARM64_TSO */
 #endif /* __ASM_TSO_H */
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 3831c1a97f79..2b0e9a5331e0 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -763,3 +763,55 @@ int arch_elf_adjust_prot(int prot, const struct arch_elf_state *state,
 	return prot;
 }
 #endif
+
+static int arch_set_mem_model_default(struct task_struct *task)
+{
+	int return_error = 0;
+
+#ifdef CONFIG_ARM64_TSO
+	int modify_tso_enable_error = modify_tso_enable(false);
+
+	if (modify_tso_enable_error == -EOPNOTSUPP)
+		// TSO is the only other memory model on arm64.
+		// If TSO is not supported, then the default memory
+		// model must already be set.
+		return_error = 0;
+	else
+		return_error = modify_tso_enable_error;
+
+	if (!return_error)
+		task->thread.tso = false;
+
+	return return_error;
+#endif
+
+	return return_error;
+}
+
+#ifdef CONFIG_ARM64_TSO
+
+static int arch_set_mem_model_tso(struct task_struct *task)
+{
+	int error = modify_tso_enable(true);
+
+	if (!error)
+		task->thread.tso = true;
+
+	return error;
+}
+
+#endif /* CONFIG_ARM64_TSO */
+
+int arch_set_mem_model(struct task_struct *task, int memory_model)
+{
+	switch (memory_model) {
+	case PR_SET_MEM_MODEL_DEFAULT:
+		return arch_set_mem_model_default(task);
+#ifdef CONFIG_ARM64_TSO
+	case PR_SET_MEM_MODEL_TSO:
+		return arch_set_mem_model_tso(task);
+#endif /* CONFIG_ARM64_TSO */
+	default:
+		return -EINVAL;
+	}
+}
diff --git a/arch/arm64/kernel/tso.c b/arch/arm64/kernel/tso.c
index 9a15d825943f..44749f1f5e10 100644
--- a/arch/arm64/kernel/tso.c
+++ b/arch/arm64/kernel/tso.c
@@ -58,4 +58,5 @@ void tso_thread_switch(struct task_struct *next)
 	}
 }
 
+
 #endif /* CONFIG_ARM64_TSO */
diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h
index 370ed14b1ae0..62b767e6efcf 100644
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@ -1,4 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright © 2024 Apple Inc. All rights reserved.
+ */
+
 #ifndef _LINUX_PRCTL_H
 #define _LINUX_PRCTL_H
 
@@ -306,4 +310,9 @@ struct prctl_mm_map {
 # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK	0xc
 # define PR_RISCV_V_VSTATE_CTRL_MASK		0x1f
 
+/* Set the CPU memory model */
+#define PR_SET_MEM_MODEL		71
+# define PR_SET_MEM_MODEL_DEFAULT	0
+# define PR_SET_MEM_MODEL_TSO		1
+
 #endif /* _LINUX_PRCTL_H */
diff --git a/kernel/sys.c b/kernel/sys.c
index 8bb106a56b3a..94c18700b849 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -3,6 +3,7 @@
  *  linux/kernel/sys.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
+ *  Copyright © 2024 Apple Inc. All rights reserved.
  */
 
 #include <linux/export.h>
@@ -2315,6 +2316,11 @@ int __weak arch_prctl_spec_ctrl_set(struct task_struct *t, unsigned long which,
 	return -EINVAL;
 }
 
+int __weak arch_set_mem_model(struct task_struct *task, int memory_model)
+{
+	return -EINVAL;
+}
+
 #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE)
 
 #ifdef CONFIG_ANON_VMA_NAME
@@ -2760,6 +2766,11 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,
 	case PR_RISCV_V_GET_CONTROL:
 		error = RISCV_V_GET_CONTROL();
 		break;
+	case PR_SET_MEM_MODEL:
+		if (arg3 || arg4 || arg5)
+			return -EINVAL;
+		error = arch_set_mem_model(current, arg2);
+		break;
 	default:
 		error = -EINVAL;
 		break;
-- 
2.39.3 (Apple Git-146)

Re: [PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Hector Martin]

On 2024/04/11 6:16, Zayd Qumsieh wrote:
> x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
> selectively use a TSO memory model. This can be done by setting the
> ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
> removes the need for emulators to insert memory barriers in order to abide
> by the TSO memory model. This patch series will add ACTLR.TSOEN support to
> virtualized linux on Apple Silicon machines. Userspace will be able to use
> a prctl to change the memory model of the CPU from the default ARM64 memory
> model to a TSO memory model.
> 
> A simple test can be used to determine if the TSO memory model is in use.
> This must be done on Apple Silicon MacOS Sonoma version 14.4 or later,
> since earlier versions do not support modification of the TSOEN bit.
> https://github.com/saagarjha/TSOEnabler/blob/master/testtso/main.c
> 
> This program will hang indefinitely if TSO is in use, and will crash almost
> immediately if it is not in use.

Well this is unexpected, given I talked to Justin Lu at Apple back in
December and I thought our plan was to work together on the series I've
had cooking in the Asahi tree [1] for a while now, which is actually
shipping in thousands of Asahi Linux systems in production and actually
already supported by the FEX-Emu project with our ABI. You CCed 30+
people, but not me nor the asahi@lists.linux.dev mailing list...

[1] https://github.com/AsahiLinux/linux/tree/bits/220-tso

Given that we're here now, I'll send out my series for review and see
what people think about that one.

> 
> Zayd Qumsieh (3):
>   tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN
>   tso: aarch64: context-switch tso bit on thread switch
>   tso: aarch64: allow userspace to set tso bit using prctl
> 
>  arch/arm64/Kconfig                 | 19 +++++++++
>  arch/arm64/include/asm/processor.h |  4 ++
>  arch/arm64/include/asm/sysreg.h    |  7 ++++
>  arch/arm64/include/asm/tso.h       | 19 +++++++++
>  arch/arm64/kernel/Makefile         |  2 +-
>  arch/arm64/kernel/process.c        | 61 +++++++++++++++++++++++++++++
>  arch/arm64/kernel/tso.c            | 62 ++++++++++++++++++++++++++++++
>  include/uapi/linux/prctl.h         |  9 +++++
>  kernel/sys.c                       | 11 ++++++
>  9 files changed, 193 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm64/include/asm/tso.h
>  create mode 100644 arch/arm64/kernel/tso.c
> 

- Hector

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Hector Martin]

On 2024/04/11 6:16, Zayd Qumsieh wrote:
> x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
> selectively use a TSO memory model. This can be done by setting the
> ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
> removes the need for emulators to insert memory barriers in order to abide
> by the TSO memory model. This patch series will add ACTLR.TSOEN support to
> virtualized linux on Apple Silicon machines. Userspace will be able to use
> a prctl to change the memory model of the CPU from the default ARM64 memory
> model to a TSO memory model.
> 
> A simple test can be used to determine if the TSO memory model is in use.
> This must be done on Apple Silicon MacOS Sonoma version 14.4 or later,
> since earlier versions do not support modification of the TSOEN bit.
> https://github.com/saagarjha/TSOEnabler/blob/master/testtso/main.c
> 
> This program will hang indefinitely if TSO is in use, and will crash almost
> immediately if it is not in use.

Well this is unexpected, given I talked to Justin Lu at Apple back in
December and I thought our plan was to work together on the series I've
had cooking in the Asahi tree [1] for a while now, which is actually
shipping in thousands of Asahi Linux systems in production and actually
already supported by the FEX-Emu project with our ABI. You CCed 30+
people, but not me nor the asahi@lists.linux.dev mailing list...

[1] https://github.com/AsahiLinux/linux/tree/bits/220-tso

Given that we're here now, I'll send out my series for review and see
what people think about that one.

> 
> Zayd Qumsieh (3):
>   tso: aarch64: allow linux kernel to read/write ACTLR.TSOEN
>   tso: aarch64: context-switch tso bit on thread switch
>   tso: aarch64: allow userspace to set tso bit using prctl
> 
>  arch/arm64/Kconfig                 | 19 +++++++++
>  arch/arm64/include/asm/processor.h |  4 ++
>  arch/arm64/include/asm/sysreg.h    |  7 ++++
>  arch/arm64/include/asm/tso.h       | 19 +++++++++
>  arch/arm64/kernel/Makefile         |  2 +-
>  arch/arm64/kernel/process.c        | 61 +++++++++++++++++++++++++++++
>  arch/arm64/kernel/tso.c            | 62 ++++++++++++++++++++++++++++++
>  include/uapi/linux/prctl.h         |  9 +++++
>  kernel/sys.c                       | 11 ++++++
>  9 files changed, 193 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm64/include/asm/tso.h
>  create mode 100644 arch/arm64/kernel/tso.c
> 

- Hector

Re: [PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl

[kernel test robot]

Hi Zayd,

kernel test robot noticed the following build warnings:

[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on linus/master v6.9-rc3 next-20240411]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Zayd-Qumsieh/tso-aarch64-allow-linux-kernel-to-read-write-ACTLR-TSOEN/20240411-061830
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link:    https://lore.kernel.org/r/20240410211652.16640-4-zayd_qumsieh%40apple.com
patch subject: [PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl
config: alpha-allnoconfig (https://download.01.org/0day-ci/archive/20240411/202404112024.tvGveZOX-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240411/202404112024.tvGveZOX-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404112024.tvGveZOX-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> kernel/sys.c:2319:12: warning: no previous prototype for 'arch_set_mem_model' [-Wmissing-prototypes]
    2319 | int __weak arch_set_mem_model(struct task_struct *task, int memory_model)
         |            ^~~~~~~~~~~~~~~~~~


vim +/arch_set_mem_model +2319 kernel/sys.c

  2318	
> 2319	int __weak arch_set_mem_model(struct task_struct *task, int memory_model)
  2320	{
  2321		return -EINVAL;
  2322	}
  2323	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl

[kernel test robot]

Hi Zayd,

kernel test robot noticed the following build warnings:

[auto build test WARNING on arm64/for-next/core]
[also build test WARNING on linus/master v6.9-rc3 next-20240411]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Zayd-Qumsieh/tso-aarch64-allow-linux-kernel-to-read-write-ACTLR-TSOEN/20240411-061830
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link:    https://lore.kernel.org/r/20240410211652.16640-4-zayd_qumsieh%40apple.com
patch subject: [PATCH 3/3] tso: aarch64: allow userspace to set tso bit using prctl
config: arm64-allnoconfig (https://download.01.org/0day-ci/archive/20240411/202404112107.DRkoPR2Y-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240411/202404112107.DRkoPR2Y-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404112107.DRkoPR2Y-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> arch/arm64/kernel/process.c:805:5: warning: no previous prototype for 'arch_set_mem_model' [-Wmissing-prototypes]
     805 | int arch_set_mem_model(struct task_struct *task, int memory_model)
         |     ^~~~~~~~~~~~~~~~~~


vim +/arch_set_mem_model +805 arch/arm64/kernel/process.c

   804	
 > 805	int arch_set_mem_model(struct task_struct *task, int memory_model)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Will Deacon]

Hi Zayd,

It makes a nice change to see an apple.com address on the mailing list!

On Wed, Apr 10, 2024 at 02:16:38PM -0700, Zayd Qumsieh wrote:
> x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
> selectively use a TSO memory model. This can be done by setting the
> ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
> removes the need for emulators to insert memory barriers in order to abide
> by the TSO memory model. This patch series will add ACTLR.TSOEN support to
> virtualized linux on Apple Silicon machines. Userspace will be able to use
> a prctl to change the memory model of the CPU from the default ARM64 memory
> model to a TSO memory model.

FWIW: I've replied on the other series from Hector:

https://lore.kernel.org/lkml/20240411132853.GA26481@willie-the-truck/T/#t

Will

Re: [PATCH 0/3] tso: aarch64: Expose TSO for virtualized linux on Apple Silicon

[Will Deacon]

Hi Zayd,

It makes a nice change to see an apple.com address on the mailing list!

On Wed, Apr 10, 2024 at 02:16:38PM -0700, Zayd Qumsieh wrote:
> x86 CPUs use a TSO memory model. Apple Silicon CPUs have the ability to
> selectively use a TSO memory model. This can be done by setting the
> ACTLR.TSOEN bit to 1. This feature is useful for x86 emulators, since it
> removes the need for emulators to insert memory barriers in order to abide
> by the TSO memory model. This patch series will add ACTLR.TSOEN support to
> virtualized linux on Apple Silicon machines. Userspace will be able to use
> a prctl to change the memory model of the CPU from the default ARM64 memory
> model to a TSO memory model.

FWIW: I've replied on the other series from Hector:

https://lore.kernel.org/lkml/20240411132853.GA26481@willie-the-truck/T/#t

Will

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