* [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump
@ 2024-04-17 9:38 Sunil Khatri
2024-04-17 9:38 ` [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump Sunil Khatri
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/si.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 1 +
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 +
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 +
64 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 6d72355ac492..34a62033a388 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.soft_reset = acp_soft_reset,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 95f80b9131a8..5bb9e0dacbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.hw_fini = umsch_mm_hw_fini,
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index 8baa2e0935cc..d1dc91009c0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -658,6 +658,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
.soft_reset = amdgpu_vkms_soft_reset,
.set_clockgating_state = amdgpu_vkms_set_clockgating_state,
.set_powergating_state = amdgpu_vkms_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index fdbc26346b54..884de42553a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2210,6 +2210,7 @@ static const struct amd_ip_funcs cik_common_ip_funcs = {
.soft_reset = cik_common_soft_reset,
.set_clockgating_state = cik_common_set_clockgating_state,
.set_powergating_state = cik_common_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ip_block_version cik_common_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index f24e34dc33d1..676f3f612fde 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -435,6 +435,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
.soft_reset = cik_ih_soft_reset,
.set_clockgating_state = cik_ih_set_clockgating_state,
.set_powergating_state = cik_ih_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs cik_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index a3fccc4c1f43..d797b1fbbffc 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1228,6 +1228,7 @@ static const struct amd_ip_funcs cik_sdma_ip_funcs = {
.soft_reset = cik_sdma_soft_reset,
.set_clockgating_state = cik_sdma_set_clockgating_state,
.set_powergating_state = cik_sdma_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index c19681492efa..958c84a6af7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -433,6 +433,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
.soft_reset = cz_ih_soft_reset,
.set_clockgating_state = cz_ih_set_clockgating_state,
.set_powergating_state = cz_ih_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs cz_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 221af054d874..7a32ca7d6fc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3333,6 +3333,7 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
.soft_reset = dce_v10_0_soft_reset,
.set_clockgating_state = dce_v10_0_set_clockgating_state,
.set_powergating_state = dce_v10_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 69e8b0db6cf7..67c01e137fac 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3464,6 +3464,7 @@ static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
.soft_reset = dce_v11_0_soft_reset,
.set_clockgating_state = dce_v11_0_set_clockgating_state,
.set_powergating_state = dce_v11_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 60d40201fdd1..209cd44bbcec 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3154,6 +3154,7 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
.soft_reset = dce_v6_0_soft_reset,
.set_clockgating_state = dce_v6_0_set_clockgating_state,
.set_powergating_state = dce_v6_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 5a5fcc45e452..fff7f4f766b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3242,6 +3242,7 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
.soft_reset = dce_v8_0_soft_reset,
.set_clockgating_state = dce_v8_0_set_clockgating_state,
.set_powergating_state = dce_v8_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d5b924222903..a0bc4196ff8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9170,6 +9170,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_clockgating_state = gfx_v10_0_set_clockgating_state,
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5dbfef49dd5d..fec076c90fd2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6169,6 +6169,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
.set_clockgating_state = gfx_v11_0_set_clockgating_state,
.set_powergating_state = gfx_v11_0_set_powergating_state,
.get_clockgating_state = gfx_v11_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 34f9211b2679..559250c8a147 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3457,6 +3457,7 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
.soft_reset = gfx_v6_0_soft_reset,
.set_clockgating_state = gfx_v6_0_set_clockgating_state,
.set_powergating_state = gfx_v6_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 86a4865b1ae5..81f7ab0dc135 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4977,6 +4977,7 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.soft_reset = gfx_v7_0_soft_reset,
.set_clockgating_state = gfx_v7_0_set_clockgating_state,
.set_powergating_state = gfx_v7_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 202ddda57f98..522cbd45dd46 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6878,6 +6878,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.set_clockgating_state = gfx_v8_0_set_clockgating_state,
.set_powergating_state = gfx_v8_0_set_powergating_state,
.get_clockgating_state = gfx_v8_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 71b555993b7a..ff4229b005dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6856,6 +6856,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.set_clockgating_state = gfx_v9_0_set_clockgating_state,
.set_powergating_state = gfx_v9_0_set_powergating_state,
.get_clockgating_state = gfx_v9_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index fc33354f1d3d..16881e9345c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4016,6 +4016,7 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
.set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
.set_powergating_state = gfx_v9_4_3_set_powergating_state,
.get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 23b478639921..060e54b8ffff 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1115,6 +1115,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
.soft_reset = gmc_v6_0_soft_reset,
.set_clockgating_state = gmc_v6_0_set_clockgating_state,
.set_powergating_state = gmc_v6_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 3da7b6a2b00d..534825022ddd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1354,6 +1354,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
.soft_reset = gmc_v7_0_soft_reset,
.set_clockgating_state = gmc_v7_0_set_clockgating_state,
.set_powergating_state = gmc_v7_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d20e5f20ee31..aba787e1386a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1717,6 +1717,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
.set_clockgating_state = gmc_v8_0_set_clockgating_state,
.set_powergating_state = gmc_v8_0_set_powergating_state,
.get_clockgating_state = gmc_v8_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 2c02ae69883d..2d6f969266b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -425,6 +425,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
.soft_reset = iceland_ih_soft_reset,
.set_clockgating_state = iceland_ih_set_clockgating_state,
.set_powergating_state = iceland_ih_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs iceland_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index c757ef99e3c5..77b5068b7be5 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -770,6 +770,7 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
.set_clockgating_state = ih_v6_0_set_clockgating_state,
.set_powergating_state = ih_v6_0_set_powergating_state,
.get_clockgating_state = ih_v6_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 29ed78798070..fc2c27a199c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -775,6 +775,7 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
.set_clockgating_state = ih_v6_1_set_clockgating_state,
.set_powergating_state = ih_v6_1_set_powergating_state,
.get_clockgating_state = ih_v6_1_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 7aed96fa10a9..31ed5030169b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -749,6 +749,7 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
.set_clockgating_state = ih_v7_0_set_clockgating_state,
.set_powergating_state = ih_v7_0_set_powergating_state,
.get_clockgating_state = ih_v7_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 1c8116d75f63..698c5d4b7484 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -759,6 +759,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v2_0_set_clockgating_state,
.set_powergating_state = jpeg_v2_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 99cd49ee8ef6..0a9a2d58e3ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -632,6 +632,7 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
.set_powergating_state = jpeg_v2_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
@@ -652,6 +653,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
.set_powergating_state = jpeg_v2_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index a92481da60cd..e03d46151ae3 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -557,6 +557,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
.set_powergating_state = jpeg_v3_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 88ea58d5c4ab..f142cb200552 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -719,6 +719,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v4_0_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 32caeb37cef9..bc3a6f16f4bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -1053,6 +1053,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_3_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index edf5bcdd2bc9..ee29c97721ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -762,6 +762,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index e70200f97555..f5664c92d10d 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -513,6 +513,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
.set_powergating_state = jpeg_v5_0_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 1e5ad1e08d2a..4ed0429cf4f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -1176,6 +1176,7 @@ static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
.hw_fini = mes_v10_1_hw_fini,
.suspend = mes_v10_1_suspend,
.resume = mes_v10_1_resume,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 81833395324a..57f17c699d80 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1334,6 +1334,7 @@ static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
.hw_fini = mes_v11_0_hw_fini,
.suspend = mes_v11_0_suspend,
.resume = mes_v11_0_resume,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 4178f4e5dad7..550c5ca4ea03 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -713,6 +713,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
.set_clockgating_state = navi10_ih_set_clockgating_state,
.set_powergating_state = navi10_ih_set_powergating_state,
.get_clockgating_state = navi10_ih_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs navi10_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4d7976b77767..d7d3b972392b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1131,4 +1131,5 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {
.set_clockgating_state = nv_common_set_clockgating_state,
.set_powergating_state = nv_common_set_powergating_state,
.get_clockgating_state = nv_common_get_clockgating_state,
+ .dump_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 07e19caf2bc1..5c67c8a5c35f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1113,6 +1113,7 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
.soft_reset = sdma_v2_4_soft_reset,
.set_clockgating_state = sdma_v2_4_set_clockgating_state,
.set_powergating_state = sdma_v2_4_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2ad615be4bb3..4fad06daa9c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1553,6 +1553,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.set_clockgating_state = sdma_v3_0_set_clockgating_state,
.set_powergating_state = sdma_v3_0_set_powergating_state,
.get_clockgating_state = sdma_v3_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 67e179c7e347..b5b15dba9a76 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2706,6 +2706,7 @@ static const struct amd_ip_funcs si_common_ip_funcs = {
.soft_reset = si_common_soft_reset,
.set_clockgating_state = si_common_set_clockgating_state,
.set_powergating_state = si_common_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ip_block_version si_common_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9aa0e11ee673..f969e5cc2a5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -708,6 +708,7 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
.soft_reset = si_dma_soft_reset,
.set_clockgating_state = si_dma_set_clockgating_state,
.set_powergating_state = si_dma_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index cada9f300a7f..3b7427f5a6c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -296,6 +296,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
.soft_reset = si_ih_soft_reset,
.set_clockgating_state = si_ih_set_clockgating_state,
.set_powergating_state = si_ih_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs si_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c8abbf5da736..6ba6c96c91c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1501,4 +1501,5 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {
.set_clockgating_state = soc15_common_set_clockgating_state,
.set_powergating_state = soc15_common_set_powergating_state,
.get_clockgating_state= soc15_common_get_clockgating_state,
+ .dump_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 43ca63fe85ac..40e7ab0716cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -985,4 +985,5 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {
.set_clockgating_state = soc21_common_set_clockgating_state,
.set_powergating_state = soc21_common_set_powergating_state,
.get_clockgating_state = soc21_common_get_clockgating_state,
+ .dump_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 450b6e831509..794a1f7bc2ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -486,6 +486,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
.post_soft_reset = tonga_ih_post_soft_reset,
.set_clockgating_state = tonga_ih_set_clockgating_state,
.set_powergating_state = tonga_ih_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ih_funcs tonga_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index a6006f231c65..1e232ed23102 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -819,6 +819,7 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
.soft_reset = uvd_v3_1_soft_reset,
.set_clockgating_state = uvd_v3_1_set_clockgating_state,
.set_powergating_state = uvd_v3_1_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 1aa09ad7bbe3..48bcf41e5558 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -769,6 +769,7 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
.soft_reset = uvd_v4_2_soft_reset,
.set_clockgating_state = uvd_v4_2_set_clockgating_state,
.set_powergating_state = uvd_v4_2_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index f8b229b75435..838b7d720c52 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -877,6 +877,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.set_clockgating_state = uvd_v5_0_set_clockgating_state,
.set_powergating_state = uvd_v5_0_set_powergating_state,
.get_clockgating_state = uvd_v5_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a9a6880f44e3..036378f5f53f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1545,6 +1545,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.set_clockgating_state = uvd_v6_0_set_clockgating_state,
.set_powergating_state = uvd_v6_0_set_powergating_state,
.get_clockgating_state = uvd_v6_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index a08e7abca423..2178cf5a27b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -626,6 +626,7 @@ static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
.soft_reset = vce_v2_0_soft_reset,
.set_clockgating_state = vce_v2_0_set_clockgating_state,
.set_powergating_state = vce_v2_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index f4760748d349..0f0d4b0d50cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -913,6 +913,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
.set_clockgating_state = vce_v3_0_set_clockgating_state,
.set_powergating_state = vce_v3_0_set_powergating_state,
.get_clockgating_state = vce_v3_0_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index aaceecd558cf..7ff5d0574454 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1902,6 +1902,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
.set_clockgating_state = vcn_v1_0_set_clockgating_state,
.set_powergating_state = vcn_v1_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index e357d8cf0c01..4df1b75f971a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2008,6 +2008,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v2_0_set_clockgating_state,
.set_powergating_state = vcn_v2_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 1cd8a94b0fbc..d91c3154641b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1901,6 +1901,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v2_5_set_clockgating_state,
.set_powergating_state = vcn_v2_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
@@ -1921,6 +1922,7 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v2_5_set_clockgating_state,
.set_powergating_state = vcn_v2_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 8f82fb887e9c..e64af339e924 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2230,6 +2230,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v3_0_set_clockgating_state,
.set_powergating_state = vcn_v3_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 832d15f7b5f6..efaad53e2ffe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2130,6 +2130,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v4_0_set_clockgating_state,
.set_powergating_state = vcn_v4_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 203fa988322b..599b6466183e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1660,6 +1660,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
.set_powergating_state = vcn_v4_0_3_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 501e53e69f2a..c649fa2c19e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1752,6 +1752,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
.set_powergating_state = vcn_v4_0_5_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index bc60c554eb32..9d0d1efd1acc 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1328,6 +1328,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
.post_soft_reset = NULL,
.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
.set_powergating_state = vcn_v5_0_0_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2415355b037c..a04aa6833fc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -2058,6 +2058,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
.set_clockgating_state = vi_common_set_clockgating_state,
.set_powergating_state = vi_common_set_powergating_state,
.get_clockgating_state = vi_common_get_clockgating_state,
+ .dump_ip_state = NULL,
};
static const struct amdgpu_ip_block_version vi_common_ip_block =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2c06f2bee4a5..8bd8bd77b9be 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3120,6 +3120,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
.soft_reset = dm_soft_reset,
.set_clockgating_state = dm_set_clockgating_state,
.set_powergating_state = dm_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version dm_ip_block = {
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index b0a6256e89f4..9884f6c48a7d 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -321,6 +321,7 @@ struct amd_ip_funcs {
int (*set_powergating_state)(void *handle,
enum amd_powergating_state state);
void (*get_clockgating_state)(void *handle, u64 *flags);
+ void (*dump_ip_state)(void *handle);
};
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 5cb4725c773f..8c07f8c7f3ab 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3316,6 +3316,7 @@ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
.soft_reset = kv_dpm_soft_reset,
.set_clockgating_state = kv_dpm_set_clockgating_state,
.set_powergating_state = kv_dpm_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version kv_smu_ip_block = {
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index eb4da3666e05..c312b9332326 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -8060,6 +8060,7 @@ static const struct amd_ip_funcs si_dpm_ip_funcs = {
.soft_reset = si_dpm_soft_reset,
.set_clockgating_state = si_dpm_set_clockgating_state,
.set_powergating_state = si_dpm_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version si_smu_ip_block =
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 133d1ee6e67c..c63474ee17a7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -302,6 +302,7 @@ static const struct amd_ip_funcs pp_ip_funcs = {
.soft_reset = pp_sw_reset,
.set_clockgating_state = pp_set_clockgating_state,
.set_powergating_state = pp_set_powergating_state,
+ .dump_ip_state = NULL,
};
const struct amdgpu_ip_block_version pp_smu_ip_block =
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
@ 2024-04-17 9:38 ` Sunil Khatri
2024-04-17 15:51 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 3/6] drm/amdgpu: add protype for print ip state Sunil Khatri
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
.../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
5 files changed, 155 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e0d7f4ee7e16..cac0ca64367b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -139,6 +139,14 @@ enum amdgpu_ss {
AMDGPU_SS_DRV_UNLOAD
};
+struct amdgpu_hwip_reg_entry {
+ u32 hwip;
+ u32 inst;
+ u32 seg;
+ u32 reg_offset;
+ const char *reg_name;
+};
+
struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 04a86dff71e6..64f197bbc866 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
uint32_t num_xcc_per_xcp;
struct mutex partition_mutex;
bool mcbp; /* mid command buffer preemption */
+
+ /* IP reg dump */
+ uint32_t *ip_dump;
+ uint32_t reg_count;
};
struct amdgpu_gfx_ras_reg_entry {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index a0bc4196ff8b..4a54161f4837 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
+static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
+ SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
+ SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
+ SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
+ SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
+};
+
static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
@@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
hw_prio, NULL);
}
+static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
+{
+ uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+ uint32_t *ptr;
+
+ ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
+ if (ptr == NULL) {
+ DRM_ERROR("Failed to allocate memory for IP Dump\n");
+ adev->gfx.ip_dump = NULL;
+ adev->gfx.reg_count = 0;
+ } else {
+ adev->gfx.ip_dump = ptr;
+ adev->gfx.reg_count = reg_count;
+ }
+}
+
static int gfx_v10_0_sw_init(void *handle)
{
int i, j, k, r, ring_id = 0;
@@ -4642,6 +4751,8 @@ static int gfx_v10_0_sw_init(void *handle)
gfx_v10_0_gpu_early_init(adev);
+ gfx_v10_0_alloc_dump_mem(adev);
+
return 0;
}
@@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
gfx_v10_0_free_microcode(adev);
+ kfree(adev->gfx.ip_dump);
+
return 0;
}
@@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
}
+static void gfx_v10_ip_dump(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ uint32_t i;
+ uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+ if (!adev->gfx.ip_dump)
+ return;
+
+ amdgpu_gfx_off_ctrl(adev, false);
+ for (i = 0; i < reg_count; i++)
+ adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
+ amdgpu_gfx_off_ctrl(adev, true);
+}
+
static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.name = "gfx_v10_0",
.early_init = gfx_v10_0_early_init,
@@ -9170,7 +9298,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_clockgating_state = gfx_v10_0_set_clockgating_state,
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
- .dump_ip_state = NULL,
+ .dump_ip_state = gfx_v10_ip_dump,
};
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 1444b7765e4b..282584a48be0 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
};
#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
+#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
+ { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 4908044f7409..4c8e7fdb6976 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -4830,6 +4830,8 @@
#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
#define mmGB_EDC_MODE 0x1e1e
#define mmGB_EDC_MODE_BASE_IDX 0
+#define mmCP_DEBUG 0x1e1f
+#define mmCP_DEBUG_BASE_IDX 0
#define mmCP_FETCHER_SOURCE 0x1e22
#define mmCP_FETCHER_SOURCE_BASE_IDX 0
#define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
@@ -7778,6 +7780,8 @@
#define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
#define mmCP_MES_DOORBELL_CONTROL6 0x2841
#define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
+#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
+#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
#define mmCP_MES_GP0_LO 0x2843
#define mmCP_MES_GP0_LO_BASE_IDX 1
#define mmCP_MES_GP0_HI 0x2844
@@ -9332,10 +9336,16 @@
#define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
#define mmRLC_LB_CNTR_1 0x4c1c
#define mmRLC_LB_CNTR_1_BASE_IDX 1
+#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
+#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
#define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
#define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
#define mmRLC_PG_DELAY_2 0x4c1f
#define mmRLC_PG_DELAY_2_BASE_IDX 1
+#define mmRLC_GPM_DEBUG_INST_A 0x4c22
+#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
+#define mmRLC_GPM_DEBUG_INST_B 0x4c23
+#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
#define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
#define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
#define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
@@ -9720,6 +9730,8 @@
#define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
#define mmRLC_LB_CNTR_2 0x4de7
#define mmRLC_LB_CNTR_2_BASE_IDX 1
+#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
+#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
#define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
#define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
#define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 3/6] drm/amdgpu: add protype for print ip state
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
2024-04-17 9:38 ` [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump Sunil Khatri
@ 2024-04-17 9:38 ` Sunil Khatri
2024-04-17 15:48 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print Sunil Khatri
` (3 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/si.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 1 +
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 +
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 +
64 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 34a62033a388..bf6c4a0d0525 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version acp_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5bb9e0dacbf3..06ad68714172 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
.suspend = umsch_mm_suspend,
.resume = umsch_mm_resume,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index d1dc91009c0e..e30eecd02ae1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -659,6 +659,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
.set_clockgating_state = amdgpu_vkms_set_clockgating_state,
.set_powergating_state = amdgpu_vkms_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 884de42553a6..cf1d5d462b67 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2211,6 +2211,7 @@ static const struct amd_ip_funcs cik_common_ip_funcs = {
.set_clockgating_state = cik_common_set_clockgating_state,
.set_powergating_state = cik_common_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ip_block_version cik_common_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 676f3f612fde..576baa9dbb0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -436,6 +436,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
.set_clockgating_state = cik_ih_set_clockgating_state,
.set_powergating_state = cik_ih_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs cik_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index d797b1fbbffc..555f763077cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1229,6 +1229,7 @@ static const struct amd_ip_funcs cik_sdma_ip_funcs = {
.set_clockgating_state = cik_sdma_set_clockgating_state,
.set_powergating_state = cik_sdma_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 958c84a6af7e..072643787384 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -434,6 +434,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
.set_clockgating_state = cz_ih_set_clockgating_state,
.set_powergating_state = cz_ih_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs cz_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 7a32ca7d6fc4..b44fce44c066 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3334,6 +3334,7 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
.set_clockgating_state = dce_v10_0_set_clockgating_state,
.set_powergating_state = dce_v10_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 67c01e137fac..80b2e7f79acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3465,6 +3465,7 @@ static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
.set_clockgating_state = dce_v11_0_set_clockgating_state,
.set_powergating_state = dce_v11_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 209cd44bbcec..db20012600f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3155,6 +3155,7 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
.set_clockgating_state = dce_v6_0_set_clockgating_state,
.set_powergating_state = dce_v6_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index fff7f4f766b2..5b56100ec902 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3243,6 +3243,7 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
.set_clockgating_state = dce_v8_0_set_clockgating_state,
.set_powergating_state = dce_v8_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static void
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4a54161f4837..ceeeafef668c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9299,6 +9299,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index fec076c90fd2..45f655c2b03d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6170,6 +6170,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
.set_powergating_state = gfx_v11_0_set_powergating_state,
.get_clockgating_state = gfx_v11_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 559250c8a147..d0992ce9fb47 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3458,6 +3458,7 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
.set_clockgating_state = gfx_v6_0_set_clockgating_state,
.set_powergating_state = gfx_v6_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 81f7ab0dc135..541dbd70d8c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4978,6 +4978,7 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.set_clockgating_state = gfx_v7_0_set_clockgating_state,
.set_powergating_state = gfx_v7_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 522cbd45dd46..2f0e72caee1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6879,6 +6879,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.set_powergating_state = gfx_v8_0_set_powergating_state,
.get_clockgating_state = gfx_v8_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ff4229b005dc..75ea7c9e9c4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6857,6 +6857,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.set_powergating_state = gfx_v9_0_set_powergating_state,
.get_clockgating_state = gfx_v9_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 16881e9345c8..835004187a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4017,6 +4017,7 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
.set_powergating_state = gfx_v9_4_3_set_powergating_state,
.get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 060e54b8ffff..3e38d8bfcb69 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1116,6 +1116,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
.set_clockgating_state = gmc_v6_0_set_clockgating_state,
.set_powergating_state = gmc_v6_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 534825022ddd..85df8fc81065 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1355,6 +1355,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
.set_clockgating_state = gmc_v7_0_set_clockgating_state,
.set_powergating_state = gmc_v7_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index aba787e1386a..fc97757e33d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1718,6 +1718,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
.set_powergating_state = gmc_v8_0_set_powergating_state,
.get_clockgating_state = gmc_v8_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 2d6f969266b8..07984f7c3ae7 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -426,6 +426,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
.set_clockgating_state = iceland_ih_set_clockgating_state,
.set_powergating_state = iceland_ih_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs iceland_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 77b5068b7be5..3cb64c8f7175 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -771,6 +771,7 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
.set_powergating_state = ih_v6_0_set_powergating_state,
.get_clockgating_state = ih_v6_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index fc2c27a199c6..0fbf5fa7b0f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -776,6 +776,7 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
.set_powergating_state = ih_v6_1_set_powergating_state,
.get_clockgating_state = ih_v6_1_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 31ed5030169b..aa6235dd4f2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -750,6 +750,7 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
.set_powergating_state = ih_v7_0_set_powergating_state,
.get_clockgating_state = ih_v7_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 698c5d4b7484..ef3e42f6b841 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -760,6 +760,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
.set_clockgating_state = jpeg_v2_0_set_clockgating_state,
.set_powergating_state = jpeg_v2_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 0a9a2d58e3ee..afeaf3c64e27 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -633,6 +633,7 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
.set_powergating_state = jpeg_v2_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
@@ -654,6 +655,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
.set_clockgating_state = jpeg_v2_5_set_clockgating_state,
.set_powergating_state = jpeg_v2_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index e03d46151ae3..1c7cf4800bf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -558,6 +558,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
.set_powergating_state = jpeg_v3_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index f142cb200552..237fe5df5a8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -720,6 +720,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
.set_clockgating_state = jpeg_v4_0_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index bc3a6f16f4bf..d66af11aa66c 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -1054,6 +1054,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
.set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_3_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index ee29c97721ec..da6bb9022b80 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -763,6 +763,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
.set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
.set_powergating_state = jpeg_v4_0_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index f5664c92d10d..64c856bfe0cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -514,6 +514,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
.set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
.set_powergating_state = jpeg_v5_0_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 4ed0429cf4f7..a626bf904926 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -1177,6 +1177,7 @@ static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
.suspend = mes_v10_1_suspend,
.resume = mes_v10_1_resume,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 57f17c699d80..515938961629 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1335,6 +1335,7 @@ static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
.suspend = mes_v11_0_suspend,
.resume = mes_v11_0_resume,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 550c5ca4ea03..b281462093f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -714,6 +714,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
.set_powergating_state = navi10_ih_set_powergating_state,
.get_clockgating_state = navi10_ih_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs navi10_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index d7d3b972392b..b5303cd3cb53 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1132,4 +1132,5 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {
.set_powergating_state = nv_common_set_powergating_state,
.get_clockgating_state = nv_common_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 5c67c8a5c35f..3c67bd35302d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1114,6 +1114,7 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
.set_clockgating_state = sdma_v2_4_set_clockgating_state,
.set_powergating_state = sdma_v2_4_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 4fad06daa9c9..060798bf04db 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1554,6 +1554,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.set_powergating_state = sdma_v3_0_set_powergating_state,
.get_clockgating_state = sdma_v3_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index b5b15dba9a76..85235470e872 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2707,6 +2707,7 @@ static const struct amd_ip_funcs si_common_ip_funcs = {
.set_clockgating_state = si_common_set_clockgating_state,
.set_powergating_state = si_common_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ip_block_version si_common_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index f969e5cc2a5e..c23d85542cfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -709,6 +709,7 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
.set_clockgating_state = si_dma_set_clockgating_state,
.set_powergating_state = si_dma_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 3b7427f5a6c9..5237395e4fab 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -297,6 +297,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
.set_clockgating_state = si_ih_set_clockgating_state,
.set_powergating_state = si_ih_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs si_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6ba6c96c91c8..a5d3c66b5868 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1502,4 +1502,5 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {
.set_powergating_state = soc15_common_set_powergating_state,
.get_clockgating_state= soc15_common_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 40e7ab0716cd..27c26e42120e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -986,4 +986,5 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {
.set_powergating_state = soc21_common_set_powergating_state,
.get_clockgating_state = soc21_common_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 794a1f7bc2ca..24d49d813607 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -487,6 +487,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
.set_clockgating_state = tonga_ih_set_clockgating_state,
.set_powergating_state = tonga_ih_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ih_funcs tonga_ih_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 1e232ed23102..805d6662c88b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -820,6 +820,7 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
.set_clockgating_state = uvd_v3_1_set_clockgating_state,
.set_powergating_state = uvd_v3_1_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 48bcf41e5558..3f19c606f4de 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -770,6 +770,7 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
.set_clockgating_state = uvd_v4_2_set_clockgating_state,
.set_powergating_state = uvd_v4_2_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 838b7d720c52..efd903c21d48 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -878,6 +878,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.set_powergating_state = uvd_v5_0_set_powergating_state,
.get_clockgating_state = uvd_v5_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 036378f5f53f..495de5068455 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1546,6 +1546,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.set_powergating_state = uvd_v6_0_set_powergating_state,
.get_clockgating_state = uvd_v6_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 2178cf5a27b7..66fada199bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -627,6 +627,7 @@ static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
.set_clockgating_state = vce_v2_0_set_clockgating_state,
.set_powergating_state = vce_v2_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 0f0d4b0d50cb..32517c364cf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -914,6 +914,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
.set_powergating_state = vce_v3_0_set_powergating_state,
.get_clockgating_state = vce_v3_0_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 7ff5d0574454..cb253bd3a2a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1903,6 +1903,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.set_clockgating_state = vcn_v1_0_set_clockgating_state,
.set_powergating_state = vcn_v1_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 4df1b75f971a..f18fd61c435e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2009,6 +2009,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
.set_clockgating_state = vcn_v2_0_set_clockgating_state,
.set_powergating_state = vcn_v2_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index d91c3154641b..baec14bde2a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1902,6 +1902,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
.set_clockgating_state = vcn_v2_5_set_clockgating_state,
.set_powergating_state = vcn_v2_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
@@ -1923,6 +1924,7 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
.set_clockgating_state = vcn_v2_5_set_clockgating_state,
.set_powergating_state = vcn_v2_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e64af339e924..91bfad1ef1a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2231,6 +2231,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
.set_clockgating_state = vcn_v3_0_set_clockgating_state,
.set_powergating_state = vcn_v3_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index efaad53e2ffe..92478b1c0dc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2131,6 +2131,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
.set_clockgating_state = vcn_v4_0_set_clockgating_state,
.set_powergating_state = vcn_v4_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 599b6466183e..2279d8fce03d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1661,6 +1661,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
.set_powergating_state = vcn_v4_0_3_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index c649fa2c19e8..874b780ee09c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1753,6 +1753,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
.set_powergating_state = vcn_v4_0_5_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 9d0d1efd1acc..cfd351e22c14 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1329,6 +1329,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
.set_powergating_state = vcn_v5_0_0_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a04aa6833fc5..d39c670f6220 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -2059,6 +2059,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
.set_powergating_state = vi_common_set_powergating_state,
.get_clockgating_state = vi_common_get_clockgating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
static const struct amdgpu_ip_block_version vi_common_ip_block =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8bd8bd77b9be..af1685090246 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3121,6 +3121,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
.set_clockgating_state = dm_set_clockgating_state,
.set_powergating_state = dm_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version dm_ip_block = {
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 9884f6c48a7d..7536c173a546 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -24,6 +24,7 @@
#define __AMD_SHARED_H__
#include <drm/amd_asic_type.h>
+#include <drm/drm_print.h>
#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
@@ -322,6 +323,7 @@ struct amd_ip_funcs {
enum amd_powergating_state state);
void (*get_clockgating_state)(void *handle, u64 *flags);
void (*dump_ip_state)(void *handle);
+ void (*print_ip_state)(void *handle, struct drm_printer *p);
};
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 8c07f8c7f3ab..6bb42d04b247 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3317,6 +3317,7 @@ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
.set_clockgating_state = kv_dpm_set_clockgating_state,
.set_powergating_state = kv_dpm_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version kv_smu_ip_block = {
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index c312b9332326..f245fc0bc6d3 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -8061,6 +8061,7 @@ static const struct amd_ip_funcs si_dpm_ip_funcs = {
.set_clockgating_state = si_dpm_set_clockgating_state,
.set_powergating_state = si_dpm_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version si_smu_ip_block =
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index c63474ee17a7..5fb21a0508cd 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -303,6 +303,7 @@ static const struct amd_ip_funcs pp_ip_funcs = {
.set_clockgating_state = pp_set_clockgating_state,
.set_powergating_state = pp_set_powergating_state,
.dump_ip_state = NULL,
+ .print_ip_state = NULL,
};
const struct amdgpu_ip_block_version pp_smu_ip_block =
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
2024-04-17 9:38 ` [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump Sunil Khatri
2024-04-17 9:38 ` [PATCH v5 3/6] drm/amdgpu: add protype for print ip state Sunil Khatri
@ 2024-04-17 9:38 ` Sunil Khatri
2024-04-17 15:52 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip Sunil Khatri
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Add support to print ip information to be
used to print registers in devcoredump
buffer.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ceeeafef668c..9b0b8ce5f5e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
}
+static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ uint32_t i;
+ uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
+
+ if (!adev->gfx.ip_dump)
+ return;
+
+ for (i = 0; i < reg_count; i++)
+ drm_printf(p, "%-50s \t 0x%08x\n",
+ gc_reg_list_10_1[i].reg_name,
+ adev->gfx.ip_dump[i]);
+}
+
static void gfx_v10_ip_dump(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.set_powergating_state = gfx_v10_0_set_powergating_state,
.get_clockgating_state = gfx_v10_0_get_clockgating_state,
.dump_ip_state = gfx_v10_ip_dump,
- .print_ip_state = NULL,
+ .print_ip_state = gfx_v10_ip_print,
};
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
` (2 preceding siblings ...)
2024-04-17 9:38 ` [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print Sunil Khatri
@ 2024-04-17 9:38 ` Sunil Khatri
2024-04-17 15:52 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump Sunil Khatri
2024-04-17 15:45 ` [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Alex Deucher
5 siblings, 1 reply; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Invoke the dump_ip_state function for each ip before
the asic resets and save the register values for
debugging via devcoredump.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f3b7cb18fd46..f8a34db5d9e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5353,6 +5353,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
struct amdgpu_device *tmp_adev = NULL;
bool need_full_reset, skip_hw_reset, vram_lost = false;
int r = 0;
+ uint32_t i;
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
@@ -5361,6 +5362,12 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags))
amdgpu_reset_reg_dumps(tmp_adev);
+ /* Trigger ip dump before we reset the asic */
+ for (i = 0; i < tmp_adev->num_ip_blocks; i++)
+ if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
+ tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
+ (void *)tmp_adev);
+
reset_context->reset_device_list = device_list_handle;
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
` (3 preceding siblings ...)
2024-04-17 9:38 ` [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip Sunil Khatri
@ 2024-04-17 9:38 ` Sunil Khatri
2024-04-17 15:53 ` Alex Deucher
2024-04-17 15:45 ` [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Alex Deucher
5 siblings, 1 reply; 20+ messages in thread
From: Sunil Khatri @ 2024-04-17 9:38 UTC (permalink / raw)
To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri
Add ip dump for each ip of the asic in the
devcoredump for all the ips where a callback
is registered for register dump.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
index 64fe564b8036..c1cb62683695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
@@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
+ /* dump the ip state for each ip */
+ drm_printf(&p, "IP Dump\n");
+ for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
+ if (coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
+ drm_printf(&p, "IP: %s\n",
+ coredump->adev->ip_blocks[i]
+ .version->funcs->name);
+ coredump->adev->ip_blocks[i]
+ .version->funcs->print_ip_state(
+ (void *)coredump->adev, &p);
+ drm_printf(&p, "\n");
+ }
+ }
+
/* Add ring buffer information */
drm_printf(&p, "Ring buffer information\n");
for (int i = 0; i < coredump->adev->num_rings; i++) {
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
` (4 preceding siblings ...)
2024-04-17 9:38 ` [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump Sunil Khatri
@ 2024-04-17 15:45 ` Alex Deucher
2024-04-18 8:45 ` Christian König
5 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:45 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add the prototype to dump ip registers
> for all ips of different asics and set
> them to NULL for now. Based on the
> requirement add a function pointer for
> each of them.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> drivers/gpu/drm/amd/include/amd_shared.h | 1 +
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 1 +
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 +
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 +
> 64 files changed, 66 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 6d72355ac492..34a62033a388 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
> .soft_reset = acp_soft_reset,
> .set_clockgating_state = acp_set_clockgating_state,
> .set_powergating_state = acp_set_powergating_state,
> + .dump_ip_state = NULL,
You can skip all of the NULL assignments. Static global structures
will be 0 initialized. Either way:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Alex
> };
>
> const struct amdgpu_ip_block_version acp_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> index 95f80b9131a8..5bb9e0dacbf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> @@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
> .hw_fini = umsch_mm_hw_fini,
> .suspend = umsch_mm_suspend,
> .resume = umsch_mm_resume,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index 8baa2e0935cc..d1dc91009c0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -658,6 +658,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
> .soft_reset = amdgpu_vkms_soft_reset,
> .set_clockgating_state = amdgpu_vkms_set_clockgating_state,
> .set_powergating_state = amdgpu_vkms_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index fdbc26346b54..884de42553a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2210,6 +2210,7 @@ static const struct amd_ip_funcs cik_common_ip_funcs = {
> .soft_reset = cik_common_soft_reset,
> .set_clockgating_state = cik_common_set_clockgating_state,
> .set_powergating_state = cik_common_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version cik_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index f24e34dc33d1..676f3f612fde 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -435,6 +435,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
> .soft_reset = cik_ih_soft_reset,
> .set_clockgating_state = cik_ih_set_clockgating_state,
> .set_powergating_state = cik_ih_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs cik_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index a3fccc4c1f43..d797b1fbbffc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1228,6 +1228,7 @@ static const struct amd_ip_funcs cik_sdma_ip_funcs = {
> .soft_reset = cik_sdma_soft_reset,
> .set_clockgating_state = cik_sdma_set_clockgating_state,
> .set_powergating_state = cik_sdma_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index c19681492efa..958c84a6af7e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -433,6 +433,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
> .soft_reset = cz_ih_soft_reset,
> .set_clockgating_state = cz_ih_set_clockgating_state,
> .set_powergating_state = cz_ih_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs cz_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 221af054d874..7a32ca7d6fc4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3333,6 +3333,7 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
> .soft_reset = dce_v10_0_soft_reset,
> .set_clockgating_state = dce_v10_0_set_clockgating_state,
> .set_powergating_state = dce_v10_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 69e8b0db6cf7..67c01e137fac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3464,6 +3464,7 @@ static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
> .soft_reset = dce_v11_0_soft_reset,
> .set_clockgating_state = dce_v11_0_set_clockgating_state,
> .set_powergating_state = dce_v11_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 60d40201fdd1..209cd44bbcec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3154,6 +3154,7 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
> .soft_reset = dce_v6_0_soft_reset,
> .set_clockgating_state = dce_v6_0_set_clockgating_state,
> .set_powergating_state = dce_v6_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 5a5fcc45e452..fff7f4f766b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3242,6 +3242,7 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
> .soft_reset = dce_v8_0_soft_reset,
> .set_clockgating_state = dce_v8_0_set_clockgating_state,
> .set_powergating_state = dce_v8_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index d5b924222903..a0bc4196ff8b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9170,6 +9170,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
> .set_powergating_state = gfx_v10_0_set_powergating_state,
> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 5dbfef49dd5d..fec076c90fd2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -6169,6 +6169,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
> .set_clockgating_state = gfx_v11_0_set_clockgating_state,
> .set_powergating_state = gfx_v11_0_set_powergating_state,
> .get_clockgating_state = gfx_v11_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 34f9211b2679..559250c8a147 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3457,6 +3457,7 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
> .soft_reset = gfx_v6_0_soft_reset,
> .set_clockgating_state = gfx_v6_0_set_clockgating_state,
> .set_powergating_state = gfx_v6_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 86a4865b1ae5..81f7ab0dc135 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4977,6 +4977,7 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
> .soft_reset = gfx_v7_0_soft_reset,
> .set_clockgating_state = gfx_v7_0_set_clockgating_state,
> .set_powergating_state = gfx_v7_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 202ddda57f98..522cbd45dd46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6878,6 +6878,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
> .set_clockgating_state = gfx_v8_0_set_clockgating_state,
> .set_powergating_state = gfx_v8_0_set_powergating_state,
> .get_clockgating_state = gfx_v8_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 71b555993b7a..ff4229b005dc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6856,6 +6856,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
> .set_clockgating_state = gfx_v9_0_set_clockgating_state,
> .set_powergating_state = gfx_v9_0_set_powergating_state,
> .get_clockgating_state = gfx_v9_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index fc33354f1d3d..16881e9345c8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -4016,6 +4016,7 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
> .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
> .set_powergating_state = gfx_v9_4_3_set_powergating_state,
> .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 23b478639921..060e54b8ffff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1115,6 +1115,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
> .soft_reset = gmc_v6_0_soft_reset,
> .set_clockgating_state = gmc_v6_0_set_clockgating_state,
> .set_powergating_state = gmc_v6_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 3da7b6a2b00d..534825022ddd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1354,6 +1354,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
> .soft_reset = gmc_v7_0_soft_reset,
> .set_clockgating_state = gmc_v7_0_set_clockgating_state,
> .set_powergating_state = gmc_v7_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index d20e5f20ee31..aba787e1386a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1717,6 +1717,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
> .set_clockgating_state = gmc_v8_0_set_clockgating_state,
> .set_powergating_state = gmc_v8_0_set_powergating_state,
> .get_clockgating_state = gmc_v8_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 2c02ae69883d..2d6f969266b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -425,6 +425,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
> .soft_reset = iceland_ih_soft_reset,
> .set_clockgating_state = iceland_ih_set_clockgating_state,
> .set_powergating_state = iceland_ih_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index c757ef99e3c5..77b5068b7be5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -770,6 +770,7 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
> .set_clockgating_state = ih_v6_0_set_clockgating_state,
> .set_powergating_state = ih_v6_0_set_powergating_state,
> .get_clockgating_state = ih_v6_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index 29ed78798070..fc2c27a199c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -775,6 +775,7 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
> .set_clockgating_state = ih_v6_1_set_clockgating_state,
> .set_powergating_state = ih_v6_1_set_powergating_state,
> .get_clockgating_state = ih_v6_1_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index 7aed96fa10a9..31ed5030169b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -749,6 +749,7 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
> .set_clockgating_state = ih_v7_0_set_clockgating_state,
> .set_powergating_state = ih_v7_0_set_powergating_state,
> .get_clockgating_state = ih_v7_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 1c8116d75f63..698c5d4b7484 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -759,6 +759,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
> .set_powergating_state = jpeg_v2_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index 99cd49ee8ef6..0a9a2d58e3ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -632,6 +632,7 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
> .set_powergating_state = jpeg_v2_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
> @@ -652,6 +653,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
> .set_powergating_state = jpeg_v2_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index a92481da60cd..e03d46151ae3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -557,6 +557,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
> .set_powergating_state = jpeg_v3_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index 88ea58d5c4ab..f142cb200552 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -719,6 +719,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v4_0_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index 32caeb37cef9..bc3a6f16f4bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -1053,6 +1053,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_3_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> index edf5bcdd2bc9..ee29c97721ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> @@ -762,6 +762,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index e70200f97555..f5664c92d10d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -513,6 +513,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
> .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 1e5ad1e08d2a..4ed0429cf4f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -1176,6 +1176,7 @@ static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
> .hw_fini = mes_v10_1_hw_fini,
> .suspend = mes_v10_1_suspend,
> .resume = mes_v10_1_resume,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 81833395324a..57f17c699d80 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1334,6 +1334,7 @@ static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
> .hw_fini = mes_v11_0_hw_fini,
> .suspend = mes_v11_0_suspend,
> .resume = mes_v11_0_resume,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 4178f4e5dad7..550c5ca4ea03 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -713,6 +713,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
> .set_clockgating_state = navi10_ih_set_clockgating_state,
> .set_powergating_state = navi10_ih_set_powergating_state,
> .get_clockgating_state = navi10_ih_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs navi10_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 4d7976b77767..d7d3b972392b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1131,4 +1131,5 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {
> .set_clockgating_state = nv_common_set_clockgating_state,
> .set_powergating_state = nv_common_set_powergating_state,
> .get_clockgating_state = nv_common_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 07e19caf2bc1..5c67c8a5c35f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1113,6 +1113,7 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
> .soft_reset = sdma_v2_4_soft_reset,
> .set_clockgating_state = sdma_v2_4_set_clockgating_state,
> .set_powergating_state = sdma_v2_4_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 2ad615be4bb3..4fad06daa9c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1553,6 +1553,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
> .set_clockgating_state = sdma_v3_0_set_clockgating_state,
> .set_powergating_state = sdma_v3_0_set_powergating_state,
> .get_clockgating_state = sdma_v3_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 67e179c7e347..b5b15dba9a76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -2706,6 +2706,7 @@ static const struct amd_ip_funcs si_common_ip_funcs = {
> .soft_reset = si_common_soft_reset,
> .set_clockgating_state = si_common_set_clockgating_state,
> .set_powergating_state = si_common_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version si_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 9aa0e11ee673..f969e5cc2a5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -708,6 +708,7 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
> .soft_reset = si_dma_soft_reset,
> .set_clockgating_state = si_dma_set_clockgating_state,
> .set_powergating_state = si_dma_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index cada9f300a7f..3b7427f5a6c9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -296,6 +296,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
> .soft_reset = si_ih_soft_reset,
> .set_clockgating_state = si_ih_set_clockgating_state,
> .set_powergating_state = si_ih_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs si_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index c8abbf5da736..6ba6c96c91c8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1501,4 +1501,5 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {
> .set_clockgating_state = soc15_common_set_clockgating_state,
> .set_powergating_state = soc15_common_set_powergating_state,
> .get_clockgating_state= soc15_common_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 43ca63fe85ac..40e7ab0716cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -985,4 +985,5 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {
> .set_clockgating_state = soc21_common_set_clockgating_state,
> .set_powergating_state = soc21_common_set_powergating_state,
> .get_clockgating_state = soc21_common_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 450b6e831509..794a1f7bc2ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -486,6 +486,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
> .post_soft_reset = tonga_ih_post_soft_reset,
> .set_clockgating_state = tonga_ih_set_clockgating_state,
> .set_powergating_state = tonga_ih_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index a6006f231c65..1e232ed23102 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -819,6 +819,7 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
> .soft_reset = uvd_v3_1_soft_reset,
> .set_clockgating_state = uvd_v3_1_set_clockgating_state,
> .set_powergating_state = uvd_v3_1_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 1aa09ad7bbe3..48bcf41e5558 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -769,6 +769,7 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
> .soft_reset = uvd_v4_2_soft_reset,
> .set_clockgating_state = uvd_v4_2_set_clockgating_state,
> .set_powergating_state = uvd_v4_2_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index f8b229b75435..838b7d720c52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -877,6 +877,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> .set_clockgating_state = uvd_v5_0_set_clockgating_state,
> .set_powergating_state = uvd_v5_0_set_powergating_state,
> .get_clockgating_state = uvd_v5_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index a9a6880f44e3..036378f5f53f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1545,6 +1545,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> .set_clockgating_state = uvd_v6_0_set_clockgating_state,
> .set_powergating_state = uvd_v6_0_set_powergating_state,
> .get_clockgating_state = uvd_v6_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index a08e7abca423..2178cf5a27b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -626,6 +626,7 @@ static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
> .soft_reset = vce_v2_0_soft_reset,
> .set_clockgating_state = vce_v2_0_set_clockgating_state,
> .set_powergating_state = vce_v2_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index f4760748d349..0f0d4b0d50cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -913,6 +913,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
> .set_clockgating_state = vce_v3_0_set_clockgating_state,
> .set_powergating_state = vce_v3_0_set_powergating_state,
> .get_clockgating_state = vce_v3_0_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index aaceecd558cf..7ff5d0574454 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1902,6 +1902,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
> .set_clockgating_state = vcn_v1_0_set_clockgating_state,
> .set_powergating_state = vcn_v1_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index e357d8cf0c01..4df1b75f971a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -2008,6 +2008,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v2_0_set_clockgating_state,
> .set_powergating_state = vcn_v2_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 1cd8a94b0fbc..d91c3154641b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1901,6 +1901,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
> .set_powergating_state = vcn_v2_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
> @@ -1921,6 +1922,7 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
> .set_powergating_state = vcn_v2_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 8f82fb887e9c..e64af339e924 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2230,6 +2230,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v3_0_set_clockgating_state,
> .set_powergating_state = vcn_v3_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 832d15f7b5f6..efaad53e2ffe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -2130,6 +2130,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v4_0_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 203fa988322b..599b6466183e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1660,6 +1660,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_3_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 501e53e69f2a..c649fa2c19e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1752,6 +1752,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_5_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index bc60c554eb32..9d0d1efd1acc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1328,6 +1328,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
> .post_soft_reset = NULL,
> .set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
> .set_powergating_state = vcn_v5_0_0_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 2415355b037c..a04aa6833fc5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -2058,6 +2058,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
> .set_clockgating_state = vi_common_set_clockgating_state,
> .set_powergating_state = vi_common_set_powergating_state,
> .get_clockgating_state = vi_common_get_clockgating_state,
> + .dump_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version vi_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 2c06f2bee4a5..8bd8bd77b9be 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3120,6 +3120,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
> .soft_reset = dm_soft_reset,
> .set_clockgating_state = dm_set_clockgating_state,
> .set_powergating_state = dm_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version dm_ip_block = {
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index b0a6256e89f4..9884f6c48a7d 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -321,6 +321,7 @@ struct amd_ip_funcs {
> int (*set_powergating_state)(void *handle,
> enum amd_powergating_state state);
> void (*get_clockgating_state)(void *handle, u64 *flags);
> + void (*dump_ip_state)(void *handle);
> };
>
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index 5cb4725c773f..8c07f8c7f3ab 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -3316,6 +3316,7 @@ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
> .soft_reset = kv_dpm_soft_reset,
> .set_clockgating_state = kv_dpm_set_clockgating_state,
> .set_powergating_state = kv_dpm_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version kv_smu_ip_block = {
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index eb4da3666e05..c312b9332326 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -8060,6 +8060,7 @@ static const struct amd_ip_funcs si_dpm_ip_funcs = {
> .soft_reset = si_dpm_soft_reset,
> .set_clockgating_state = si_dpm_set_clockgating_state,
> .set_powergating_state = si_dpm_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version si_smu_ip_block =
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index 133d1ee6e67c..c63474ee17a7 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -302,6 +302,7 @@ static const struct amd_ip_funcs pp_ip_funcs = {
> .soft_reset = pp_sw_reset,
> .set_clockgating_state = pp_set_clockgating_state,
> .set_powergating_state = pp_set_powergating_state,
> + .dump_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version pp_smu_ip_block =
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 3/6] drm/amdgpu: add protype for print ip state
2024-04-17 9:38 ` [PATCH v5 3/6] drm/amdgpu: add protype for print ip state Sunil Khatri
@ 2024-04-17 15:48 ` Alex Deucher
0 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:48 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add the protoype for print ip state to be used
> to print the registers in devcoredump during
> a gpu reset.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 +
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 +
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 +
> drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
> drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 1 +
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 +
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 +
> 64 files changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 34a62033a388..bf6c4a0d0525 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -638,6 +638,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
> .set_clockgating_state = acp_set_clockgating_state,
> .set_powergating_state = acp_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
Same comment as patch 1. Either way,
Reviewed-by: Alex Duecher <alexander.deucher@amd.com>
> };
>
> const struct amdgpu_ip_block_version acp_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> index 5bb9e0dacbf3..06ad68714172 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
> @@ -876,6 +876,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
> .suspend = umsch_mm_suspend,
> .resume = umsch_mm_resume,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index d1dc91009c0e..e30eecd02ae1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -659,6 +659,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
> .set_clockgating_state = amdgpu_vkms_set_clockgating_state,
> .set_powergating_state = amdgpu_vkms_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 884de42553a6..cf1d5d462b67 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2211,6 +2211,7 @@ static const struct amd_ip_funcs cik_common_ip_funcs = {
> .set_clockgating_state = cik_common_set_clockgating_state,
> .set_powergating_state = cik_common_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version cik_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 676f3f612fde..576baa9dbb0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -436,6 +436,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
> .set_clockgating_state = cik_ih_set_clockgating_state,
> .set_powergating_state = cik_ih_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs cik_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index d797b1fbbffc..555f763077cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1229,6 +1229,7 @@ static const struct amd_ip_funcs cik_sdma_ip_funcs = {
> .set_clockgating_state = cik_sdma_set_clockgating_state,
> .set_powergating_state = cik_sdma_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 958c84a6af7e..072643787384 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -434,6 +434,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
> .set_clockgating_state = cz_ih_set_clockgating_state,
> .set_powergating_state = cz_ih_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs cz_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 7a32ca7d6fc4..b44fce44c066 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3334,6 +3334,7 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
> .set_clockgating_state = dce_v10_0_set_clockgating_state,
> .set_powergating_state = dce_v10_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 67c01e137fac..80b2e7f79acf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3465,6 +3465,7 @@ static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
> .set_clockgating_state = dce_v11_0_set_clockgating_state,
> .set_powergating_state = dce_v11_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 209cd44bbcec..db20012600f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3155,6 +3155,7 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
> .set_clockgating_state = dce_v6_0_set_clockgating_state,
> .set_powergating_state = dce_v6_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index fff7f4f766b2..5b56100ec902 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3243,6 +3243,7 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
> .set_clockgating_state = dce_v8_0_set_clockgating_state,
> .set_powergating_state = dce_v8_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static void
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 4a54161f4837..ceeeafef668c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9299,6 +9299,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> .set_powergating_state = gfx_v10_0_set_powergating_state,
> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> .dump_ip_state = gfx_v10_ip_dump,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index fec076c90fd2..45f655c2b03d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -6170,6 +6170,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
> .set_powergating_state = gfx_v11_0_set_powergating_state,
> .get_clockgating_state = gfx_v11_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 559250c8a147..d0992ce9fb47 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3458,6 +3458,7 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
> .set_clockgating_state = gfx_v6_0_set_clockgating_state,
> .set_powergating_state = gfx_v6_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 81f7ab0dc135..541dbd70d8c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4978,6 +4978,7 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
> .set_clockgating_state = gfx_v7_0_set_clockgating_state,
> .set_powergating_state = gfx_v7_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 522cbd45dd46..2f0e72caee1a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6879,6 +6879,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
> .set_powergating_state = gfx_v8_0_set_powergating_state,
> .get_clockgating_state = gfx_v8_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ff4229b005dc..75ea7c9e9c4d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6857,6 +6857,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
> .set_powergating_state = gfx_v9_0_set_powergating_state,
> .get_clockgating_state = gfx_v9_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 16881e9345c8..835004187a58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -4017,6 +4017,7 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
> .set_powergating_state = gfx_v9_4_3_set_powergating_state,
> .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 060e54b8ffff..3e38d8bfcb69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1116,6 +1116,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
> .set_clockgating_state = gmc_v6_0_set_clockgating_state,
> .set_powergating_state = gmc_v6_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 534825022ddd..85df8fc81065 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1355,6 +1355,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
> .set_clockgating_state = gmc_v7_0_set_clockgating_state,
> .set_powergating_state = gmc_v7_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index aba787e1386a..fc97757e33d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1718,6 +1718,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
> .set_powergating_state = gmc_v8_0_set_powergating_state,
> .get_clockgating_state = gmc_v8_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 2d6f969266b8..07984f7c3ae7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -426,6 +426,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
> .set_clockgating_state = iceland_ih_set_clockgating_state,
> .set_powergating_state = iceland_ih_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 77b5068b7be5..3cb64c8f7175 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -771,6 +771,7 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
> .set_powergating_state = ih_v6_0_set_powergating_state,
> .get_clockgating_state = ih_v6_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index fc2c27a199c6..0fbf5fa7b0f8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -776,6 +776,7 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
> .set_powergating_state = ih_v6_1_set_powergating_state,
> .get_clockgating_state = ih_v6_1_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index 31ed5030169b..aa6235dd4f2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -750,6 +750,7 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
> .set_powergating_state = ih_v7_0_set_powergating_state,
> .get_clockgating_state = ih_v7_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 698c5d4b7484..ef3e42f6b841 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -760,6 +760,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
> .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
> .set_powergating_state = jpeg_v2_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index 0a9a2d58e3ee..afeaf3c64e27 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -633,6 +633,7 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
> .set_powergating_state = jpeg_v2_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
> @@ -654,6 +655,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
> .set_powergating_state = jpeg_v2_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index e03d46151ae3..1c7cf4800bf7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -558,6 +558,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
> .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
> .set_powergating_state = jpeg_v3_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index f142cb200552..237fe5df5a8f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -720,6 +720,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
> .set_clockgating_state = jpeg_v4_0_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index bc3a6f16f4bf..d66af11aa66c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -1054,6 +1054,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
> .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_3_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> index ee29c97721ec..da6bb9022b80 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> @@ -763,6 +763,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
> .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
> .set_powergating_state = jpeg_v4_0_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index f5664c92d10d..64c856bfe0cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -514,6 +514,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
> .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
> .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> index 4ed0429cf4f7..a626bf904926 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
> @@ -1177,6 +1177,7 @@ static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
> .suspend = mes_v10_1_suspend,
> .resume = mes_v10_1_resume,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 57f17c699d80..515938961629 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1335,6 +1335,7 @@ static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
> .suspend = mes_v11_0_suspend,
> .resume = mes_v11_0_resume,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 550c5ca4ea03..b281462093f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -714,6 +714,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
> .set_powergating_state = navi10_ih_set_powergating_state,
> .get_clockgating_state = navi10_ih_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs navi10_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index d7d3b972392b..b5303cd3cb53 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1132,4 +1132,5 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {
> .set_powergating_state = nv_common_set_powergating_state,
> .get_clockgating_state = nv_common_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 5c67c8a5c35f..3c67bd35302d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1114,6 +1114,7 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
> .set_clockgating_state = sdma_v2_4_set_clockgating_state,
> .set_powergating_state = sdma_v2_4_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 4fad06daa9c9..060798bf04db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1554,6 +1554,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
> .set_powergating_state = sdma_v3_0_set_powergating_state,
> .get_clockgating_state = sdma_v3_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index b5b15dba9a76..85235470e872 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -2707,6 +2707,7 @@ static const struct amd_ip_funcs si_common_ip_funcs = {
> .set_clockgating_state = si_common_set_clockgating_state,
> .set_powergating_state = si_common_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version si_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index f969e5cc2a5e..c23d85542cfb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -709,6 +709,7 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
> .set_clockgating_state = si_dma_set_clockgating_state,
> .set_powergating_state = si_dma_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 3b7427f5a6c9..5237395e4fab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -297,6 +297,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
> .set_clockgating_state = si_ih_set_clockgating_state,
> .set_powergating_state = si_ih_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs si_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 6ba6c96c91c8..a5d3c66b5868 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1502,4 +1502,5 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {
> .set_powergating_state = soc15_common_set_powergating_state,
> .get_clockgating_state= soc15_common_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 40e7ab0716cd..27c26e42120e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -986,4 +986,5 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {
> .set_powergating_state = soc21_common_set_powergating_state,
> .get_clockgating_state = soc21_common_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 794a1f7bc2ca..24d49d813607 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -487,6 +487,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
> .set_clockgating_state = tonga_ih_set_clockgating_state,
> .set_powergating_state = tonga_ih_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index 1e232ed23102..805d6662c88b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -820,6 +820,7 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
> .set_clockgating_state = uvd_v3_1_set_clockgating_state,
> .set_powergating_state = uvd_v3_1_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 48bcf41e5558..3f19c606f4de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -770,6 +770,7 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
> .set_clockgating_state = uvd_v4_2_set_clockgating_state,
> .set_powergating_state = uvd_v4_2_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 838b7d720c52..efd903c21d48 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -878,6 +878,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
> .set_powergating_state = uvd_v5_0_set_powergating_state,
> .get_clockgating_state = uvd_v5_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 036378f5f53f..495de5068455 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1546,6 +1546,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
> .set_powergating_state = uvd_v6_0_set_powergating_state,
> .get_clockgating_state = uvd_v6_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 2178cf5a27b7..66fada199bda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -627,6 +627,7 @@ static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
> .set_clockgating_state = vce_v2_0_set_clockgating_state,
> .set_powergating_state = vce_v2_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 0f0d4b0d50cb..32517c364cf7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -914,6 +914,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
> .set_powergating_state = vce_v3_0_set_powergating_state,
> .get_clockgating_state = vce_v3_0_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 7ff5d0574454..cb253bd3a2a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1903,6 +1903,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> .set_clockgating_state = vcn_v1_0_set_clockgating_state,
> .set_powergating_state = vcn_v1_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 4df1b75f971a..f18fd61c435e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -2009,6 +2009,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> .set_clockgating_state = vcn_v2_0_set_clockgating_state,
> .set_powergating_state = vcn_v2_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index d91c3154641b..baec14bde2a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1902,6 +1902,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
> .set_powergating_state = vcn_v2_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
> @@ -1923,6 +1924,7 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
> .set_powergating_state = vcn_v2_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index e64af339e924..91bfad1ef1a9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2231,6 +2231,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
> .set_clockgating_state = vcn_v3_0_set_clockgating_state,
> .set_powergating_state = vcn_v3_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index efaad53e2ffe..92478b1c0dc8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -2131,6 +2131,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
> .set_clockgating_state = vcn_v4_0_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 599b6466183e..2279d8fce03d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1661,6 +1661,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
> .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_3_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index c649fa2c19e8..874b780ee09c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1753,6 +1753,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
> .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
> .set_powergating_state = vcn_v4_0_5_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 9d0d1efd1acc..cfd351e22c14 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1329,6 +1329,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
> .set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
> .set_powergating_state = vcn_v5_0_0_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index a04aa6833fc5..d39c670f6220 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -2059,6 +2059,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
> .set_powergating_state = vi_common_set_powergating_state,
> .get_clockgating_state = vi_common_get_clockgating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> static const struct amdgpu_ip_block_version vi_common_ip_block =
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 8bd8bd77b9be..af1685090246 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3121,6 +3121,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
> .set_clockgating_state = dm_set_clockgating_state,
> .set_powergating_state = dm_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version dm_ip_block = {
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 9884f6c48a7d..7536c173a546 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -24,6 +24,7 @@
> #define __AMD_SHARED_H__
>
> #include <drm/amd_asic_type.h>
> +#include <drm/drm_print.h>
>
>
> #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
> @@ -322,6 +323,7 @@ struct amd_ip_funcs {
> enum amd_powergating_state state);
> void (*get_clockgating_state)(void *handle, u64 *flags);
> void (*dump_ip_state)(void *handle);
> + void (*print_ip_state)(void *handle, struct drm_printer *p);
> };
>
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index 8c07f8c7f3ab..6bb42d04b247 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -3317,6 +3317,7 @@ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
> .set_clockgating_state = kv_dpm_set_clockgating_state,
> .set_powergating_state = kv_dpm_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version kv_smu_ip_block = {
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index c312b9332326..f245fc0bc6d3 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -8061,6 +8061,7 @@ static const struct amd_ip_funcs si_dpm_ip_funcs = {
> .set_clockgating_state = si_dpm_set_clockgating_state,
> .set_powergating_state = si_dpm_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version si_smu_ip_block =
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index c63474ee17a7..5fb21a0508cd 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -303,6 +303,7 @@ static const struct amd_ip_funcs pp_ip_funcs = {
> .set_clockgating_state = pp_set_clockgating_state,
> .set_powergating_state = pp_set_powergating_state,
> .dump_ip_state = NULL,
> + .print_ip_state = NULL,
> };
>
> const struct amdgpu_ip_block_version pp_smu_ip_block =
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 9:38 ` [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump Sunil Khatri
@ 2024-04-17 15:51 ` Alex Deucher
2024-04-17 16:01 ` Lazar, Lijo
0 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:51 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Adding gfx10 gc registers to be used for register
> dump via devcoredump during a gpu reset.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
> 5 files changed, 155 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index e0d7f4ee7e16..cac0ca64367b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -139,6 +139,14 @@ enum amdgpu_ss {
> AMDGPU_SS_DRV_UNLOAD
> };
>
> +struct amdgpu_hwip_reg_entry {
> + u32 hwip;
> + u32 inst;
> + u32 seg;
> + u32 reg_offset;
> + const char *reg_name;
> +};
> +
> struct amdgpu_watchdog_timer {
> bool timeout_fatal_disable;
> uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 04a86dff71e6..64f197bbc866 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
> uint32_t num_xcc_per_xcp;
> struct mutex partition_mutex;
> bool mcbp; /* mid command buffer preemption */
> +
> + /* IP reg dump */
> + uint32_t *ip_dump;
> + uint32_t reg_count;
> };
>
> struct amdgpu_gfx_ras_reg_entry {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index a0bc4196ff8b..4a54161f4837 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>
> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
> +};
> +
> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
> @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> hw_prio, NULL);
> }
>
> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
> +{
> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> + uint32_t *ptr;
> +
> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
> + if (ptr == NULL) {
> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
> + adev->gfx.ip_dump = NULL;
> + adev->gfx.reg_count = 0;
> + } else {
> + adev->gfx.ip_dump = ptr;
> + adev->gfx.reg_count = reg_count;
> + }
> +}
> +
> static int gfx_v10_0_sw_init(void *handle)
> {
> int i, j, k, r, ring_id = 0;
> @@ -4642,6 +4751,8 @@ static int gfx_v10_0_sw_init(void *handle)
>
> gfx_v10_0_gpu_early_init(adev);
>
> + gfx_v10_0_alloc_dump_mem(adev);
> +
> return 0;
> }
>
> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>
> gfx_v10_0_free_microcode(adev);
>
> + kfree(adev->gfx.ip_dump);
> +
> return 0;
> }
>
> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
> }
>
> +static void gfx_v10_ip_dump(void *handle)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + uint32_t i;
> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> +
> + if (!adev->gfx.ip_dump)
> + return;
> +
> + amdgpu_gfx_off_ctrl(adev, false);
> + for (i = 0; i < reg_count; i++)
> + adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> + amdgpu_gfx_off_ctrl(adev, true);
> +}
> +
> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> .name = "gfx_v10_0",
> .early_init = gfx_v10_0_early_init,
> @@ -9170,7 +9298,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
> .set_powergating_state = gfx_v10_0_set_powergating_state,
> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> - .dump_ip_state = NULL,
> + .dump_ip_state = gfx_v10_ip_dump,
> };
>
> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
> index 1444b7765e4b..282584a48be0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
> };
>
> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>
> #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> index 4908044f7409..4c8e7fdb6976 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> @@ -4830,6 +4830,8 @@
> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
> #define mmGB_EDC_MODE 0x1e1e
> #define mmGB_EDC_MODE_BASE_IDX 0
> +#define mmCP_DEBUG 0x1e1f
> +#define mmCP_DEBUG_BASE_IDX 0
> #define mmCP_FETCHER_SOURCE 0x1e22
> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
> @@ -7778,6 +7780,8 @@
> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
> #define mmCP_MES_GP0_LO 0x2843
> #define mmCP_MES_GP0_LO_BASE_IDX 1
> #define mmCP_MES_GP0_HI 0x2844
> @@ -9332,10 +9336,16 @@
> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
> #define mmRLC_LB_CNTR_1 0x4c1c
> #define mmRLC_LB_CNTR_1_BASE_IDX 1
> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
> #define mmRLC_PG_DELAY_2 0x4c1f
> #define mmRLC_PG_DELAY_2_BASE_IDX 1
> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
> @@ -9720,6 +9730,8 @@
> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
> #define mmRLC_LB_CNTR_2 0x4de7
> #define mmRLC_LB_CNTR_2_BASE_IDX 1
> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print
2024-04-17 9:38 ` [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print Sunil Khatri
@ 2024-04-17 15:52 ` Alex Deucher
0 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:52 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add support to print ip information to be
> used to print registers in devcoredump
> buffer.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index ceeeafef668c..9b0b8ce5f5e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -9267,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
> }
>
> +static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
> +{
> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + uint32_t i;
> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> +
> + if (!adev->gfx.ip_dump)
> + return;
> +
> + for (i = 0; i < reg_count; i++)
> + drm_printf(p, "%-50s \t 0x%08x\n",
> + gc_reg_list_10_1[i].reg_name,
> + adev->gfx.ip_dump[i]);
> +}
> +
> static void gfx_v10_ip_dump(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -9299,7 +9314,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> .set_powergating_state = gfx_v10_0_set_powergating_state,
> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> .dump_ip_state = gfx_v10_ip_dump,
> - .print_ip_state = NULL,
> + .print_ip_state = gfx_v10_ip_print,
> };
>
> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip
2024-04-17 9:38 ` [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip Sunil Khatri
@ 2024-04-17 15:52 ` Alex Deucher
0 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:52 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Invoke the dump_ip_state function for each ip before
> the asic resets and save the register values for
> debugging via devcoredump.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f3b7cb18fd46..f8a34db5d9e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -5353,6 +5353,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
> struct amdgpu_device *tmp_adev = NULL;
> bool need_full_reset, skip_hw_reset, vram_lost = false;
> int r = 0;
> + uint32_t i;
>
> /* Try reset handler method first */
> tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
> @@ -5361,6 +5362,12 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
> if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags))
> amdgpu_reset_reg_dumps(tmp_adev);
>
> + /* Trigger ip dump before we reset the asic */
> + for (i = 0; i < tmp_adev->num_ip_blocks; i++)
> + if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state)
> + tmp_adev->ip_blocks[i].version->funcs->dump_ip_state(
> + (void *)tmp_adev);
> +
> reset_context->reset_device_list = device_list_handle;
> r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
> /* If reset handler not implemented, continue; otherwise return */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump
2024-04-17 9:38 ` [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump Sunil Khatri
@ 2024-04-17 15:53 ` Alex Deucher
0 siblings, 0 replies; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 15:53 UTC (permalink / raw)
To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add ip dump for each ip of the asic in the
> devcoredump for all the ips where a callback
> is registered for register dump.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> index 64fe564b8036..c1cb62683695 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
> @@ -262,6 +262,20 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
> drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
> drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
>
> + /* dump the ip state for each ip */
> + drm_printf(&p, "IP Dump\n");
> + for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
> + if (coredump->adev->ip_blocks[i].version->funcs->print_ip_state) {
> + drm_printf(&p, "IP: %s\n",
> + coredump->adev->ip_blocks[i]
> + .version->funcs->name);
> + coredump->adev->ip_blocks[i]
> + .version->funcs->print_ip_state(
> + (void *)coredump->adev, &p);
> + drm_printf(&p, "\n");
> + }
> + }
> +
> /* Add ring buffer information */
> drm_printf(&p, "Ring buffer information\n");
> for (int i = 0; i < coredump->adev->num_rings; i++) {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 15:51 ` Alex Deucher
@ 2024-04-17 16:01 ` Lazar, Lijo
2024-04-17 16:11 ` Khatri, Sunil
0 siblings, 1 reply; 20+ messages in thread
From: Lazar, Lijo @ 2024-04-17 16:01 UTC (permalink / raw)
To: Alex Deucher, Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
On 4/17/2024 9:21 PM, Alex Deucher wrote:
> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>
>> Adding gfx10 gc registers to be used for register
>> dump via devcoredump during a gpu reset.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
>> 5 files changed, 155 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index e0d7f4ee7e16..cac0ca64367b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
>> AMDGPU_SS_DRV_UNLOAD
>> };
>>
>> +struct amdgpu_hwip_reg_entry {
>> + u32 hwip;
>> + u32 inst;
>> + u32 seg;
>> + u32 reg_offset;
>> + const char *reg_name;
>> +};
>> +
>> struct amdgpu_watchdog_timer {
>> bool timeout_fatal_disable;
>> uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> index 04a86dff71e6..64f197bbc866 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
>> uint32_t num_xcc_per_xcp;
>> struct mutex partition_mutex;
>> bool mcbp; /* mid command buffer preemption */
>> +
>> + /* IP reg dump */
>> + uint32_t *ip_dump;
>> + uint32_t reg_count;
>> };
>>
>> struct amdgpu_gfx_ras_reg_entry {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index a0bc4196ff8b..4a54161f4837 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>>
>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
>> +};
>> +
>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
>> @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>> hw_prio, NULL);
>> }
>>
>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
>> +{
>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>> + uint32_t *ptr;
>> +
>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
>> + if (ptr == NULL) {
>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
>> + adev->gfx.ip_dump = NULL;
>> + adev->gfx.reg_count = 0;
>> + } else {
>> + adev->gfx.ip_dump = ptr;
>> + adev->gfx.reg_count = reg_count;
>> + }
>> +}
>> +
>> static int gfx_v10_0_sw_init(void *handle)
>> {
>> int i, j, k, r, ring_id = 0;
>> @@ -4642,6 +4751,8 @@ static int gfx_v10_0_sw_init(void *handle)
>>
>> gfx_v10_0_gpu_early_init(adev);
>>
>> + gfx_v10_0_alloc_dump_mem(adev);
>> +
>> return 0;
>> }
>>
>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>>
>> gfx_v10_0_free_microcode(adev);
>>
>> + kfree(adev->gfx.ip_dump);
>> +
>> return 0;
>> }
>>
>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
>> }
>>
>> +static void gfx_v10_ip_dump(void *handle)
>> +{
>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + uint32_t i;
>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>> +
>> + if (!adev->gfx.ip_dump)
>> + return;
>> +
>> + amdgpu_gfx_off_ctrl(adev, false);
>> + for (i = 0; i < reg_count; i++)
>> + adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
This may cause a bigger hang, if PMFW is already hung (in that case
reset also won't work, but a dump is still useful). To be on the safer
side, there should be some sort of return value for gfx_off which should
be checked.
Thanks,
Lijo
>> + amdgpu_gfx_off_ctrl(adev, true);
>> +}
>> +
>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>> .name = "gfx_v10_0",
>> .early_init = gfx_v10_0_early_init,
>> @@ -9170,7 +9298,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>> - .dump_ip_state = NULL,
>> + .dump_ip_state = gfx_v10_ip_dump,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
>> index 1444b7765e4b..282584a48be0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
>> };
>>
>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>>
>> #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
>>
>> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>> index 4908044f7409..4c8e7fdb6976 100644
>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>> @@ -4830,6 +4830,8 @@
>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
>> #define mmGB_EDC_MODE 0x1e1e
>> #define mmGB_EDC_MODE_BASE_IDX 0
>> +#define mmCP_DEBUG 0x1e1f
>> +#define mmCP_DEBUG_BASE_IDX 0
>> #define mmCP_FETCHER_SOURCE 0x1e22
>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
>> @@ -7778,6 +7780,8 @@
>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
>> #define mmCP_MES_GP0_LO 0x2843
>> #define mmCP_MES_GP0_LO_BASE_IDX 1
>> #define mmCP_MES_GP0_HI 0x2844
>> @@ -9332,10 +9336,16 @@
>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
>> #define mmRLC_LB_CNTR_1 0x4c1c
>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
>> #define mmRLC_PG_DELAY_2 0x4c1f
>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
>> @@ -9720,6 +9730,8 @@
>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
>> #define mmRLC_LB_CNTR_2 0x4de7
>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 16:01 ` Lazar, Lijo
@ 2024-04-17 16:11 ` Khatri, Sunil
2024-04-17 16:23 ` Lazar, Lijo
0 siblings, 1 reply; 20+ messages in thread
From: Khatri, Sunil @ 2024-04-17 16:11 UTC (permalink / raw)
To: Lazar, Lijo, Alex Deucher, Sunil Khatri
Cc: Alex Deucher, Christian König, amd-gfx
On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
>
> On 4/17/2024 9:21 PM, Alex Deucher wrote:
>> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>> Adding gfx10 gc registers to be used for register
>>> dump via devcoredump during a gpu reset.
>>>
>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
>>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
>>> 5 files changed, 155 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index e0d7f4ee7e16..cac0ca64367b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
>>> AMDGPU_SS_DRV_UNLOAD
>>> };
>>>
>>> +struct amdgpu_hwip_reg_entry {
>>> + u32 hwip;
>>> + u32 inst;
>>> + u32 seg;
>>> + u32 reg_offset;
>>> + const char *reg_name;
>>> +};
>>> +
>>> struct amdgpu_watchdog_timer {
>>> bool timeout_fatal_disable;
>>> uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> index 04a86dff71e6..64f197bbc866 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
>>> uint32_t num_xcc_per_xcp;
>>> struct mutex partition_mutex;
>>> bool mcbp; /* mid command buffer preemption */
>>> +
>>> + /* IP reg dump */
>>> + uint32_t *ip_dump;
>>> + uint32_t reg_count;
>>> };
>>>
>>> struct amdgpu_gfx_ras_reg_entry {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> index a0bc4196ff8b..4a54161f4837 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>>>
>>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST)
>>> +};
>>> +
>>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
>>> @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>>> hw_prio, NULL);
>>> }
>>>
>>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev)
>>> +{
>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>> + uint32_t *ptr;
>>> +
>>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
>>> + if (ptr == NULL) {
>>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
>>> + adev->gfx.ip_dump = NULL;
>>> + adev->gfx.reg_count = 0;
>>> + } else {
>>> + adev->gfx.ip_dump = ptr;
>>> + adev->gfx.reg_count = reg_count;
>>> + }
>>> +}
>>> +
>>> static int gfx_v10_0_sw_init(void *handle)
>>> {
>>> int i, j, k, r, ring_id = 0;
>>> @@ -4642,6 +4751,8 @@ static int gfx_v10_0_sw_init(void *handle)
>>>
>>> gfx_v10_0_gpu_early_init(adev);
>>>
>>> + gfx_v10_0_alloc_dump_mem(adev);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>>>
>>> gfx_v10_0_free_microcode(adev);
>>>
>>> + kfree(adev->gfx.ip_dump);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
>>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
>>> }
>>>
>>> +static void gfx_v10_ip_dump(void *handle)
>>> +{
>>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>> + uint32_t i;
>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>> +
>>> + if (!adev->gfx.ip_dump)
>>> + return;
>>> +
>>> + amdgpu_gfx_off_ctrl(adev, false);
>>> + for (i = 0; i < reg_count; i++)
>>> + adev->gfx.ip_dump[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> This may cause a bigger hang, if PMFW is already hung (in that case
> reset also won't work, but a dump is still useful). To be on the safer
> side, there should be some sort of return value for gfx_off which should
> be checked.
amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
Regards
Sunil Khatri
>
> Thanks,
> Lijo
>
>>> + amdgpu_gfx_off_ctrl(adev, true);
>>> +}
>>> +
>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>> .name = "gfx_v10_0",
>>> .early_init = gfx_v10_0_early_init,
>>> @@ -9170,7 +9298,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>>> - .dump_ip_state = NULL,
>>> + .dump_ip_state = gfx_v10_ip_dump,
>>> };
>>>
>>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> index 1444b7765e4b..282584a48be0 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
>>> };
>>>
>>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
>>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
>>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>>>
>>> #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
>>>
>>> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> index 4908044f7409..4c8e7fdb6976 100644
>>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> @@ -4830,6 +4830,8 @@
>>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
>>> #define mmGB_EDC_MODE 0x1e1e
>>> #define mmGB_EDC_MODE_BASE_IDX 0
>>> +#define mmCP_DEBUG 0x1e1f
>>> +#define mmCP_DEBUG_BASE_IDX 0
>>> #define mmCP_FETCHER_SOURCE 0x1e22
>>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
>>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
>>> @@ -7778,6 +7780,8 @@
>>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
>>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
>>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
>>> #define mmCP_MES_GP0_LO 0x2843
>>> #define mmCP_MES_GP0_LO_BASE_IDX 1
>>> #define mmCP_MES_GP0_HI 0x2844
>>> @@ -9332,10 +9336,16 @@
>>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
>>> #define mmRLC_LB_CNTR_1 0x4c1c
>>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
>>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
>>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
>>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
>>> #define mmRLC_PG_DELAY_2 0x4c1f
>>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
>>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
>>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
>>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
>>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
>>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
>>> @@ -9720,6 +9730,8 @@
>>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
>>> #define mmRLC_LB_CNTR_2 0x4de7
>>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
>>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
>>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
>>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
>>> --
>>> 2.34.1
>>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 16:11 ` Khatri, Sunil
@ 2024-04-17 16:23 ` Lazar, Lijo
2024-04-17 16:51 ` Alex Deucher
0 siblings, 1 reply; 20+ messages in thread
From: Lazar, Lijo @ 2024-04-17 16:23 UTC (permalink / raw)
To: Khatri, Sunil, Alex Deucher
Cc: Deucher, Alexander, Koenig, Christian, amd-gfx
[AMD Official Use Only - General]
Yes, right now that API doesn't return anything. What I meant is to add that check as well as coredump API is essentially used in hang situations.
Old times, access to registers while in GFXOFF resulted in system hang (basically it won't go beyond this point). If that happens, then the purpose of the patch - to get the context of a device hang - is lost. We may not even get a proper dmesg log.
Thanks,
Lijo
-----Original Message-----
From: Khatri, Sunil <Sunil.Khatri@amd.com>
Sent: Wednesday, April 17, 2024 9:42 PM
To: Lazar, Lijo <Lijo.Lazar@amd.com>; Alex Deucher <alexdeucher@gmail.com>; Khatri, Sunil <Sunil.Khatri@amd.com>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
>
> On 4/17/2024 9:21 PM, Alex Deucher wrote:
>> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>> Adding gfx10 gc registers to be used for register dump via
>>> devcoredump during a gpu reset.
>>>
>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
>>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
>>> 5 files changed, 155 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index e0d7f4ee7e16..cac0ca64367b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
>>> AMDGPU_SS_DRV_UNLOAD
>>> };
>>>
>>> +struct amdgpu_hwip_reg_entry {
>>> + u32 hwip;
>>> + u32 inst;
>>> + u32 seg;
>>> + u32 reg_offset;
>>> + const char *reg_name;
>>> +};
>>> +
>>> struct amdgpu_watchdog_timer {
>>> bool timeout_fatal_disable;
>>> uint32_t period; /* maxCycles = (1 << period), the number
>>> of cycles before a timeout */ diff --git
>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> index 04a86dff71e6..64f197bbc866 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
>>> uint32_t num_xcc_per_xcp;
>>> struct mutex partition_mutex;
>>> bool mcbp; /* mid command buffer preemption */
>>> +
>>> + /* IP reg dump */
>>> + uint32_t *ip_dump;
>>> + uint32_t reg_count;
>>> };
>>>
>>> struct amdgpu_gfx_ras_reg_entry {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> index a0bc4196ff8b..4a54161f4837 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>>>
>>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) };
>>> +
>>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
>>> 0xfcff8fff, 0xf8000100), @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>>> hw_prio, NULL);
>>> }
>>>
>>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) {
>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>> + uint32_t *ptr;
>>> +
>>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
>>> + if (ptr == NULL) {
>>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
>>> + adev->gfx.ip_dump = NULL;
>>> + adev->gfx.reg_count = 0;
>>> + } else {
>>> + adev->gfx.ip_dump = ptr;
>>> + adev->gfx.reg_count = reg_count;
>>> + }
>>> +}
>>> +
>>> static int gfx_v10_0_sw_init(void *handle)
>>> {
>>> int i, j, k, r, ring_id = 0; @@ -4642,6 +4751,8 @@ static
>>> int gfx_v10_0_sw_init(void *handle)
>>>
>>> gfx_v10_0_gpu_early_init(adev);
>>>
>>> + gfx_v10_0_alloc_dump_mem(adev);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>>>
>>> gfx_v10_0_free_microcode(adev);
>>>
>>> + kfree(adev->gfx.ip_dump);
>>> +
>>> return 0;
>>> }
>>>
>>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
>>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
>>> }
>>>
>>> +static void gfx_v10_ip_dump(void *handle) {
>>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>> + uint32_t i;
>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>> +
>>> + if (!adev->gfx.ip_dump)
>>> + return;
>>> +
>>> + amdgpu_gfx_off_ctrl(adev, false);
>>> + for (i = 0; i < reg_count; i++)
>>> + adev->gfx.ip_dump[i] =
>>> + RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> This may cause a bigger hang, if PMFW is already hung (in that case
> reset also won't work, but a dump is still useful). To be on the safer
> side, there should be some sort of return value for gfx_off which
> should be checked.
amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
Regards
Sunil Khatri
>
> Thanks,
> Lijo
>
>>> + amdgpu_gfx_off_ctrl(adev, true); }
>>> +
>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>> .name = "gfx_v10_0",
>>> .early_init = gfx_v10_0_early_init, @@ -9170,7 +9298,7 @@
>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>>> - .dump_ip_state = NULL,
>>> + .dump_ip_state = gfx_v10_ip_dump,
>>> };
>>>
>>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> index 1444b7765e4b..282584a48be0 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
>>> };
>>>
>>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst,
>>> reg##_BASE_IDX, reg
>>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
>>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>>>
>>> #define SOC15_REG_ENTRY_OFFSET(entry)
>>> (adev->reg_offset[entry.hwip][entry.inst][entry.seg] +
>>> entry.reg_offset)
>>>
>>> diff --git
>>> a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> index 4908044f7409..4c8e7fdb6976 100644
>>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>> @@ -4830,6 +4830,8 @@
>>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
>>> #define mmGB_EDC_MODE 0x1e1e
>>> #define mmGB_EDC_MODE_BASE_IDX 0
>>> +#define mmCP_DEBUG 0x1e1f
>>> +#define mmCP_DEBUG_BASE_IDX 0
>>> #define mmCP_FETCHER_SOURCE 0x1e22
>>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
>>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
>>> @@ -7778,6 +7780,8 @@
>>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
>>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
>>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
>>> #define mmCP_MES_GP0_LO 0x2843
>>> #define mmCP_MES_GP0_LO_BASE_IDX 1
>>> #define mmCP_MES_GP0_HI 0x2844
>>> @@ -9332,10 +9336,16 @@
>>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
>>> #define mmRLC_LB_CNTR_1 0x4c1c
>>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
>>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
>>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
>>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
>>> #define mmRLC_PG_DELAY_2 0x4c1f
>>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
>>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
>>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
>>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
>>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
>>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
>>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
>>> @@ -9720,6 +9730,8 @@
>>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
>>> #define mmRLC_LB_CNTR_2 0x4de7
>>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
>>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
>>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
>>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
>>> --
>>> 2.34.1
>>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 16:23 ` Lazar, Lijo
@ 2024-04-17 16:51 ` Alex Deucher
2024-04-17 17:01 ` Khatri, Sunil
0 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 16:51 UTC (permalink / raw)
To: Lazar, Lijo; +Cc: Khatri, Sunil, Deucher, Alexander, Koenig, Christian, amd-gfx
On Wed, Apr 17, 2024 at 12:24 PM Lazar, Lijo <Lijo.Lazar@amd.com> wrote:
>
> [AMD Official Use Only - General]
>
> Yes, right now that API doesn't return anything. What I meant is to add that check as well as coredump API is essentially used in hang situations.
>
> Old times, access to registers while in GFXOFF resulted in system hang (basically it won't go beyond this point). If that happens, then the purpose of the patch - to get the context of a device hang - is lost. We may not even get a proper dmesg log.
Maybe add a call to amdgpu_get_gfx_off_status(), but unfortunately,
it's not implemented on every chip yet.
Alex
>
> Thanks,
> Lijo
> -----Original Message-----
> From: Khatri, Sunil <Sunil.Khatri@amd.com>
> Sent: Wednesday, April 17, 2024 9:42 PM
> To: Lazar, Lijo <Lijo.Lazar@amd.com>; Alex Deucher <alexdeucher@gmail.com>; Khatri, Sunil <Sunil.Khatri@amd.com>
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
>
>
> On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
> >
> > On 4/17/2024 9:21 PM, Alex Deucher wrote:
> >> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
> >>> Adding gfx10 gc registers to be used for register dump via
> >>> devcoredump during a gpu reset.
> >>>
> >>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> >> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> >>
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
> >>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
> >>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
> >>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
> >>> 5 files changed, 155 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index e0d7f4ee7e16..cac0ca64367b 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
> >>> AMDGPU_SS_DRV_UNLOAD
> >>> };
> >>>
> >>> +struct amdgpu_hwip_reg_entry {
> >>> + u32 hwip;
> >>> + u32 inst;
> >>> + u32 seg;
> >>> + u32 reg_offset;
> >>> + const char *reg_name;
> >>> +};
> >>> +
> >>> struct amdgpu_watchdog_timer {
> >>> bool timeout_fatal_disable;
> >>> uint32_t period; /* maxCycles = (1 << period), the number
> >>> of cycles before a timeout */ diff --git
> >>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>> index 04a86dff71e6..64f197bbc866 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
> >>> uint32_t num_xcc_per_xcp;
> >>> struct mutex partition_mutex;
> >>> bool mcbp; /* mid command buffer preemption */
> >>> +
> >>> + /* IP reg dump */
> >>> + uint32_t *ip_dump;
> >>> + uint32_t reg_count;
> >>> };
> >>>
> >>> struct amdgpu_gfx_ras_reg_entry {
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> index a0bc4196ff8b..4a54161f4837 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
> >>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
> >>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
> >>>
> >>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
> >>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) };
> >>> +
> >>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> >>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
> >>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
> >>> 0xfcff8fff, 0xf8000100), @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> >>> hw_prio, NULL);
> >>> }
> >>>
> >>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) {
> >>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> >>> + uint32_t *ptr;
> >>> +
> >>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
> >>> + if (ptr == NULL) {
> >>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
> >>> + adev->gfx.ip_dump = NULL;
> >>> + adev->gfx.reg_count = 0;
> >>> + } else {
> >>> + adev->gfx.ip_dump = ptr;
> >>> + adev->gfx.reg_count = reg_count;
> >>> + }
> >>> +}
> >>> +
> >>> static int gfx_v10_0_sw_init(void *handle)
> >>> {
> >>> int i, j, k, r, ring_id = 0; @@ -4642,6 +4751,8 @@ static
> >>> int gfx_v10_0_sw_init(void *handle)
> >>>
> >>> gfx_v10_0_gpu_early_init(adev);
> >>>
> >>> + gfx_v10_0_alloc_dump_mem(adev);
> >>> +
> >>> return 0;
> >>> }
> >>>
> >>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
> >>>
> >>> gfx_v10_0_free_microcode(adev);
> >>>
> >>> + kfree(adev->gfx.ip_dump);
> >>> +
> >>> return 0;
> >>> }
> >>>
> >>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
> >>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
> >>> }
> >>>
> >>> +static void gfx_v10_ip_dump(void *handle) {
> >>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>> + uint32_t i;
> >>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> >>> +
> >>> + if (!adev->gfx.ip_dump)
> >>> + return;
> >>> +
> >>> + amdgpu_gfx_off_ctrl(adev, false);
> >>> + for (i = 0; i < reg_count; i++)
> >>> + adev->gfx.ip_dump[i] =
> >>> + RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> > This may cause a bigger hang, if PMFW is already hung (in that case
> > reset also won't work, but a dump is still useful). To be on the safer
> > side, there should be some sort of return value for gfx_off which
> > should be checked.
>
> amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
> I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
>
> Regards
> Sunil Khatri
>
> >
> > Thanks,
> > Lijo
> >
> >>> + amdgpu_gfx_off_ctrl(adev, true); }
> >>> +
> >>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> >>> .name = "gfx_v10_0",
> >>> .early_init = gfx_v10_0_early_init, @@ -9170,7 +9298,7 @@
> >>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> >>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
> >>> .set_powergating_state = gfx_v10_0_set_powergating_state,
> >>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> >>> - .dump_ip_state = NULL,
> >>> + .dump_ip_state = gfx_v10_ip_dump,
> >>> };
> >>>
> >>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>> index 1444b7765e4b..282584a48be0 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
> >>> };
> >>>
> >>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst,
> >>> reg##_BASE_IDX, reg
> >>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
> >>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
> >>>
> >>> #define SOC15_REG_ENTRY_OFFSET(entry)
> >>> (adev->reg_offset[entry.hwip][entry.inst][entry.seg] +
> >>> entry.reg_offset)
> >>>
> >>> diff --git
> >>> a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>> index 4908044f7409..4c8e7fdb6976 100644
> >>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>> @@ -4830,6 +4830,8 @@
> >>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
> >>> #define mmGB_EDC_MODE 0x1e1e
> >>> #define mmGB_EDC_MODE_BASE_IDX 0
> >>> +#define mmCP_DEBUG 0x1e1f
> >>> +#define mmCP_DEBUG_BASE_IDX 0
> >>> #define mmCP_FETCHER_SOURCE 0x1e22
> >>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
> >>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
> >>> @@ -7778,6 +7780,8 @@
> >>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
> >>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
> >>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
> >>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
> >>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
> >>> #define mmCP_MES_GP0_LO 0x2843
> >>> #define mmCP_MES_GP0_LO_BASE_IDX 1
> >>> #define mmCP_MES_GP0_HI 0x2844
> >>> @@ -9332,10 +9336,16 @@
> >>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
> >>> #define mmRLC_LB_CNTR_1 0x4c1c
> >>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
> >>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
> >>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
> >>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
> >>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
> >>> #define mmRLC_PG_DELAY_2 0x4c1f
> >>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
> >>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
> >>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
> >>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
> >>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
> >>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
> >>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
> >>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
> >>> @@ -9720,6 +9730,8 @@
> >>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
> >>> #define mmRLC_LB_CNTR_2 0x4de7
> >>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
> >>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
> >>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
> >>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
> >>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
> >>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
> >>> --
> >>> 2.34.1
> >>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 16:51 ` Alex Deucher
@ 2024-04-17 17:01 ` Khatri, Sunil
2024-04-17 17:30 ` Alex Deucher
0 siblings, 1 reply; 20+ messages in thread
From: Khatri, Sunil @ 2024-04-17 17:01 UTC (permalink / raw)
To: Alex Deucher, Lazar, Lijo
Cc: Khatri, Sunil, Deucher, Alexander, Koenig, Christian, amd-gfx
On 4/17/2024 10:21 PM, Alex Deucher wrote:
> On Wed, Apr 17, 2024 at 12:24 PM Lazar, Lijo <Lijo.Lazar@amd.com> wrote:
>> [AMD Official Use Only - General]
>>
>> Yes, right now that API doesn't return anything. What I meant is to add that check as well as coredump API is essentially used in hang situations.
>>
>> Old times, access to registers while in GFXOFF resulted in system hang (basically it won't go beyond this point). If that happens, then the purpose of the patch - to get the context of a device hang - is lost. We may not even get a proper dmesg log.
> Maybe add a call to amdgpu_get_gfx_off_status(), but unfortunately,
> it's not implemented on every chip yet.
So we need both the things do gfx_off and then try status and then read
reg and enable gfx_off again.
amdgpu_gfx_off_ctrl(adev, false);
r= amdgpu_get_gfx_off_status
if (!r) {
for (i = 0; i < reg_count; i++)
adev->gfx.ip_dump[i] =
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
}
amdgpu_gfx_off_ctrl(adev, true);
Sunil
>
> Alex
>
>> Thanks,
>> Lijo
>> -----Original Message-----
>> From: Khatri, Sunil <Sunil.Khatri@amd.com>
>> Sent: Wednesday, April 17, 2024 9:42 PM
>> To: Lazar, Lijo <Lijo.Lazar@amd.com>; Alex Deucher <alexdeucher@gmail.com>; Khatri, Sunil <Sunil.Khatri@amd.com>
>> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
>>
>>
>> On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
>>> On 4/17/2024 9:21 PM, Alex Deucher wrote:
>>>> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>>>> Adding gfx10 gc registers to be used for register dump via
>>>>> devcoredump during a gpu reset.
>>>>>
>>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>>>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
>>>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
>>>>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
>>>>> 5 files changed, 155 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>> index e0d7f4ee7e16..cac0ca64367b 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
>>>>> AMDGPU_SS_DRV_UNLOAD
>>>>> };
>>>>>
>>>>> +struct amdgpu_hwip_reg_entry {
>>>>> + u32 hwip;
>>>>> + u32 inst;
>>>>> + u32 seg;
>>>>> + u32 reg_offset;
>>>>> + const char *reg_name;
>>>>> +};
>>>>> +
>>>>> struct amdgpu_watchdog_timer {
>>>>> bool timeout_fatal_disable;
>>>>> uint32_t period; /* maxCycles = (1 << period), the number
>>>>> of cycles before a timeout */ diff --git
>>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>> index 04a86dff71e6..64f197bbc866 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
>>>>> uint32_t num_xcc_per_xcp;
>>>>> struct mutex partition_mutex;
>>>>> bool mcbp; /* mid command buffer preemption */
>>>>> +
>>>>> + /* IP reg dump */
>>>>> + uint32_t *ip_dump;
>>>>> + uint32_t reg_count;
>>>>> };
>>>>>
>>>>> struct amdgpu_gfx_ras_reg_entry {
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>> index a0bc4196ff8b..4a54161f4837 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
>>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
>>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>>>>>
>>>>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) };
>>>>> +
>>>>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
>>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
>>>>> 0xfcff8fff, 0xf8000100), @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>>>>> hw_prio, NULL);
>>>>> }
>>>>>
>>>>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) {
>>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>>>> + uint32_t *ptr;
>>>>> +
>>>>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
>>>>> + if (ptr == NULL) {
>>>>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
>>>>> + adev->gfx.ip_dump = NULL;
>>>>> + adev->gfx.reg_count = 0;
>>>>> + } else {
>>>>> + adev->gfx.ip_dump = ptr;
>>>>> + adev->gfx.reg_count = reg_count;
>>>>> + }
>>>>> +}
>>>>> +
>>>>> static int gfx_v10_0_sw_init(void *handle)
>>>>> {
>>>>> int i, j, k, r, ring_id = 0; @@ -4642,6 +4751,8 @@ static
>>>>> int gfx_v10_0_sw_init(void *handle)
>>>>>
>>>>> gfx_v10_0_gpu_early_init(adev);
>>>>>
>>>>> + gfx_v10_0_alloc_dump_mem(adev);
>>>>> +
>>>>> return 0;
>>>>> }
>>>>>
>>>>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>>>>>
>>>>> gfx_v10_0_free_microcode(adev);
>>>>>
>>>>> + kfree(adev->gfx.ip_dump);
>>>>> +
>>>>> return 0;
>>>>> }
>>>>>
>>>>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
>>>>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
>>>>> }
>>>>>
>>>>> +static void gfx_v10_ip_dump(void *handle) {
>>>>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>> + uint32_t i;
>>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>>>> +
>>>>> + if (!adev->gfx.ip_dump)
>>>>> + return;
>>>>> +
>>>>> + amdgpu_gfx_off_ctrl(adev, false);
>>>>> + for (i = 0; i < reg_count; i++)
>>>>> + adev->gfx.ip_dump[i] =
>>>>> + RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
>>> This may cause a bigger hang, if PMFW is already hung (in that case
>>> reset also won't work, but a dump is still useful). To be on the safer
>>> side, there should be some sort of return value for gfx_off which
>>> should be checked.
>> amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
>> I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
>>
>> Regards
>> Sunil Khatri
>>
>>> Thanks,
>>> Lijo
>>>
>>>>> + amdgpu_gfx_off_ctrl(adev, true); }
>>>>> +
>>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>>>> .name = "gfx_v10_0",
>>>>> .early_init = gfx_v10_0_early_init, @@ -9170,7 +9298,7 @@
>>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>>>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>>>>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>>>>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>>>>> - .dump_ip_state = NULL,
>>>>> + .dump_ip_state = gfx_v10_ip_dump,
>>>>> };
>>>>>
>>>>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>> index 1444b7765e4b..282584a48be0 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
>>>>> };
>>>>>
>>>>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst,
>>>>> reg##_BASE_IDX, reg
>>>>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
>>>>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>>>>>
>>>>> #define SOC15_REG_ENTRY_OFFSET(entry)
>>>>> (adev->reg_offset[entry.hwip][entry.inst][entry.seg] +
>>>>> entry.reg_offset)
>>>>>
>>>>> diff --git
>>>>> a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>> index 4908044f7409..4c8e7fdb6976 100644
>>>>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>> @@ -4830,6 +4830,8 @@
>>>>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
>>>>> #define mmGB_EDC_MODE 0x1e1e
>>>>> #define mmGB_EDC_MODE_BASE_IDX 0
>>>>> +#define mmCP_DEBUG 0x1e1f
>>>>> +#define mmCP_DEBUG_BASE_IDX 0
>>>>> #define mmCP_FETCHER_SOURCE 0x1e22
>>>>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
>>>>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
>>>>> @@ -7778,6 +7780,8 @@
>>>>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
>>>>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
>>>>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
>>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
>>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
>>>>> #define mmCP_MES_GP0_LO 0x2843
>>>>> #define mmCP_MES_GP0_LO_BASE_IDX 1
>>>>> #define mmCP_MES_GP0_HI 0x2844
>>>>> @@ -9332,10 +9336,16 @@
>>>>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
>>>>> #define mmRLC_LB_CNTR_1 0x4c1c
>>>>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
>>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
>>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
>>>>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
>>>>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
>>>>> #define mmRLC_PG_DELAY_2 0x4c1f
>>>>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
>>>>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
>>>>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
>>>>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
>>>>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
>>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
>>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
>>>>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
>>>>> @@ -9720,6 +9730,8 @@
>>>>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
>>>>> #define mmRLC_LB_CNTR_2 0x4de7
>>>>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
>>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
>>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
>>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
>>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
>>>>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
>>>>> --
>>>>> 2.34.1
>>>>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 17:01 ` Khatri, Sunil
@ 2024-04-17 17:30 ` Alex Deucher
2024-04-18 6:12 ` Christian König
0 siblings, 1 reply; 20+ messages in thread
From: Alex Deucher @ 2024-04-17 17:30 UTC (permalink / raw)
To: Khatri, Sunil
Cc: Lazar, Lijo, Khatri, Sunil, Deucher, Alexander, Koenig,
Christian, amd-gfx
On Wed, Apr 17, 2024 at 1:01 PM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 4/17/2024 10:21 PM, Alex Deucher wrote:
> > On Wed, Apr 17, 2024 at 12:24 PM Lazar, Lijo <Lijo.Lazar@amd.com> wrote:
> >> [AMD Official Use Only - General]
> >>
> >> Yes, right now that API doesn't return anything. What I meant is to add that check as well as coredump API is essentially used in hang situations.
> >>
> >> Old times, access to registers while in GFXOFF resulted in system hang (basically it won't go beyond this point). If that happens, then the purpose of the patch - to get the context of a device hang - is lost. We may not even get a proper dmesg log.
> > Maybe add a call to amdgpu_get_gfx_off_status(), but unfortunately,
> > it's not implemented on every chip yet.
> So we need both the things do gfx_off and then try status and then read
> reg and enable gfx_off again.
RIght, but first we need to implement the get_gfxoff_status smu
callback for all of the chips that are missing it.
Alex
>
> amdgpu_gfx_off_ctrl(adev, false);
> r= amdgpu_get_gfx_off_status
> if (!r) {
>
> for (i = 0; i < reg_count; i++)
> adev->gfx.ip_dump[i] =
> RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> }
> amdgpu_gfx_off_ctrl(adev, true);
>
> Sunil
>
> >
> > Alex
> >
> >> Thanks,
> >> Lijo
> >> -----Original Message-----
> >> From: Khatri, Sunil <Sunil.Khatri@amd.com>
> >> Sent: Wednesday, April 17, 2024 9:42 PM
> >> To: Lazar, Lijo <Lijo.Lazar@amd.com>; Alex Deucher <alexdeucher@gmail.com>; Khatri, Sunil <Sunil.Khatri@amd.com>
> >> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org
> >> Subject: Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
> >>
> >>
> >> On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
> >>> On 4/17/2024 9:21 PM, Alex Deucher wrote:
> >>>> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
> >>>>> Adding gfx10 gc registers to be used for register dump via
> >>>>> devcoredump during a gpu reset.
> >>>>>
> >>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> >>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> >>>>
> >>>>> ---
> >>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
> >>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
> >>>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
> >>>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
> >>>>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
> >>>>> 5 files changed, 155 insertions(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>>>> index e0d7f4ee7e16..cac0ca64367b 100644
> >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>>>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
> >>>>> AMDGPU_SS_DRV_UNLOAD
> >>>>> };
> >>>>>
> >>>>> +struct amdgpu_hwip_reg_entry {
> >>>>> + u32 hwip;
> >>>>> + u32 inst;
> >>>>> + u32 seg;
> >>>>> + u32 reg_offset;
> >>>>> + const char *reg_name;
> >>>>> +};
> >>>>> +
> >>>>> struct amdgpu_watchdog_timer {
> >>>>> bool timeout_fatal_disable;
> >>>>> uint32_t period; /* maxCycles = (1 << period), the number
> >>>>> of cycles before a timeout */ diff --git
> >>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>>>> index 04a86dff71e6..64f197bbc866 100644
> >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> >>>>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
> >>>>> uint32_t num_xcc_per_xcp;
> >>>>> struct mutex partition_mutex;
> >>>>> bool mcbp; /* mid command buffer preemption */
> >>>>> +
> >>>>> + /* IP reg dump */
> >>>>> + uint32_t *ip_dump;
> >>>>> + uint32_t reg_count;
> >>>>> };
> >>>>>
> >>>>> struct amdgpu_gfx_ras_reg_entry {
> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>>>> index a0bc4196ff8b..4a54161f4837 100644
> >>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> >>>>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
> >>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
> >>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
> >>>>>
> >>>>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
> >>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) };
> >>>>> +
> >>>>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
> >>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
> >>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
> >>>>> 0xfcff8fff, 0xf8000100), @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
> >>>>> hw_prio, NULL);
> >>>>> }
> >>>>>
> >>>>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) {
> >>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> >>>>> + uint32_t *ptr;
> >>>>> +
> >>>>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
> >>>>> + if (ptr == NULL) {
> >>>>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
> >>>>> + adev->gfx.ip_dump = NULL;
> >>>>> + adev->gfx.reg_count = 0;
> >>>>> + } else {
> >>>>> + adev->gfx.ip_dump = ptr;
> >>>>> + adev->gfx.reg_count = reg_count;
> >>>>> + }
> >>>>> +}
> >>>>> +
> >>>>> static int gfx_v10_0_sw_init(void *handle)
> >>>>> {
> >>>>> int i, j, k, r, ring_id = 0; @@ -4642,6 +4751,8 @@ static
> >>>>> int gfx_v10_0_sw_init(void *handle)
> >>>>>
> >>>>> gfx_v10_0_gpu_early_init(adev);
> >>>>>
> >>>>> + gfx_v10_0_alloc_dump_mem(adev);
> >>>>> +
> >>>>> return 0;
> >>>>> }
> >>>>>
> >>>>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
> >>>>>
> >>>>> gfx_v10_0_free_microcode(adev);
> >>>>>
> >>>>> + kfree(adev->gfx.ip_dump);
> >>>>> +
> >>>>> return 0;
> >>>>> }
> >>>>>
> >>>>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
> >>>>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
> >>>>> }
> >>>>>
> >>>>> +static void gfx_v10_ip_dump(void *handle) {
> >>>>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>> + uint32_t i;
> >>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
> >>>>> +
> >>>>> + if (!adev->gfx.ip_dump)
> >>>>> + return;
> >>>>> +
> >>>>> + amdgpu_gfx_off_ctrl(adev, false);
> >>>>> + for (i = 0; i < reg_count; i++)
> >>>>> + adev->gfx.ip_dump[i] =
> >>>>> + RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
> >>> This may cause a bigger hang, if PMFW is already hung (in that case
> >>> reset also won't work, but a dump is still useful). To be on the safer
> >>> side, there should be some sort of return value for gfx_off which
> >>> should be checked.
> >> amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
> >> I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
> >>
> >> Regards
> >> Sunil Khatri
> >>
> >>> Thanks,
> >>> Lijo
> >>>
> >>>>> + amdgpu_gfx_off_ctrl(adev, true); }
> >>>>> +
> >>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> >>>>> .name = "gfx_v10_0",
> >>>>> .early_init = gfx_v10_0_early_init, @@ -9170,7 +9298,7 @@
> >>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
> >>>>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
> >>>>> .set_powergating_state = gfx_v10_0_set_powergating_state,
> >>>>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
> >>>>> - .dump_ip_state = NULL,
> >>>>> + .dump_ip_state = gfx_v10_ip_dump,
> >>>>> };
> >>>>>
> >>>>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>>>> b/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>>>> index 1444b7765e4b..282584a48be0 100644
> >>>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
> >>>>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
> >>>>> };
> >>>>>
> >>>>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst,
> >>>>> reg##_BASE_IDX, reg
> >>>>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
> >>>>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
> >>>>>
> >>>>> #define SOC15_REG_ENTRY_OFFSET(entry)
> >>>>> (adev->reg_offset[entry.hwip][entry.inst][entry.seg] +
> >>>>> entry.reg_offset)
> >>>>>
> >>>>> diff --git
> >>>>> a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>>>> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>>>> index 4908044f7409..4c8e7fdb6976 100644
> >>>>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>>>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> >>>>> @@ -4830,6 +4830,8 @@
> >>>>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
> >>>>> #define mmGB_EDC_MODE 0x1e1e
> >>>>> #define mmGB_EDC_MODE_BASE_IDX 0
> >>>>> +#define mmCP_DEBUG 0x1e1f
> >>>>> +#define mmCP_DEBUG_BASE_IDX 0
> >>>>> #define mmCP_FETCHER_SOURCE 0x1e22
> >>>>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
> >>>>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
> >>>>> @@ -7778,6 +7780,8 @@
> >>>>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
> >>>>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
> >>>>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
> >>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
> >>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
> >>>>> #define mmCP_MES_GP0_LO 0x2843
> >>>>> #define mmCP_MES_GP0_LO_BASE_IDX 1
> >>>>> #define mmCP_MES_GP0_HI 0x2844
> >>>>> @@ -9332,10 +9336,16 @@
> >>>>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
> >>>>> #define mmRLC_LB_CNTR_1 0x4c1c
> >>>>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
> >>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
> >>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
> >>>>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
> >>>>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
> >>>>> #define mmRLC_PG_DELAY_2 0x4c1f
> >>>>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
> >>>>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
> >>>>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
> >>>>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
> >>>>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
> >>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
> >>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
> >>>>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
> >>>>> @@ -9720,6 +9730,8 @@
> >>>>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
> >>>>> #define mmRLC_LB_CNTR_2 0x4de7
> >>>>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
> >>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
> >>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
> >>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
> >>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
> >>>>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
> >>>>> --
> >>>>> 2.34.1
> >>>>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
2024-04-17 17:30 ` Alex Deucher
@ 2024-04-18 6:12 ` Christian König
0 siblings, 0 replies; 20+ messages in thread
From: Christian König @ 2024-04-18 6:12 UTC (permalink / raw)
To: Alex Deucher, Khatri, Sunil
Cc: Lazar, Lijo, Khatri, Sunil, Deucher, Alexander, Koenig,
Christian, amd-gfx
Am 17.04.24 um 19:30 schrieb Alex Deucher:
> On Wed, Apr 17, 2024 at 1:01 PM Khatri, Sunil <sukhatri@amd.com> wrote:
>>
>> On 4/17/2024 10:21 PM, Alex Deucher wrote:
>>> On Wed, Apr 17, 2024 at 12:24 PM Lazar, Lijo <Lijo.Lazar@amd.com> wrote:
>>>> [AMD Official Use Only - General]
>>>>
>>>> Yes, right now that API doesn't return anything. What I meant is to add that check as well as coredump API is essentially used in hang situations.
>>>>
>>>> Old times, access to registers while in GFXOFF resulted in system hang (basically it won't go beyond this point). If that happens, then the purpose of the patch - to get the context of a device hang - is lost. We may not even get a proper dmesg log.
>>> Maybe add a call to amdgpu_get_gfx_off_status(), but unfortunately,
>>> it's not implemented on every chip yet.
>> So we need both the things do gfx_off and then try status and then read
>> reg and enable gfx_off again.
> RIght, but first we need to implement the get_gfxoff_status smu
> callback for all of the chips that are missing it.
The question is if it's save to query the status and disable it while
the GPU is in a hung state?
I mean most of unrecoverable hungs are caused by the GFX block or the
memory interface getting into a state where it can't get out again.
Regards,
Christian.
>
> Alex
>
>> amdgpu_gfx_off_ctrl(adev, false);
>> r= amdgpu_get_gfx_off_status
>> if (!r) {
>>
>> for (i = 0; i < reg_count; i++)
>> adev->gfx.ip_dump[i] =
>> RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
>> }
>> amdgpu_gfx_off_ctrl(adev, true);
>>
>> Sunil
>>
>>> Alex
>>>
>>>> Thanks,
>>>> Lijo
>>>> -----Original Message-----
>>>> From: Khatri, Sunil <Sunil.Khatri@amd.com>
>>>> Sent: Wednesday, April 17, 2024 9:42 PM
>>>> To: Lazar, Lijo <Lijo.Lazar@amd.com>; Alex Deucher <alexdeucher@gmail.com>; Khatri, Sunil <Sunil.Khatri@amd.com>
>>>> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org
>>>> Subject: Re: [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump
>>>>
>>>>
>>>> On 4/17/2024 9:31 PM, Lazar, Lijo wrote:
>>>>> On 4/17/2024 9:21 PM, Alex Deucher wrote:
>>>>>> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>>>>>> Adding gfx10 gc registers to be used for register dump via
>>>>>>> devcoredump during a gpu reset.
>>>>>>>
>>>>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>>>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>>>>>
>>>>>>> ---
>>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++
>>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
>>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 130 +++++++++++++++++-
>>>>>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 2 +
>>>>>>> .../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
>>>>>>> 5 files changed, 155 insertions(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>>>> index e0d7f4ee7e16..cac0ca64367b 100644
>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>>>>>> @@ -139,6 +139,14 @@ enum amdgpu_ss {
>>>>>>> AMDGPU_SS_DRV_UNLOAD
>>>>>>> };
>>>>>>>
>>>>>>> +struct amdgpu_hwip_reg_entry {
>>>>>>> + u32 hwip;
>>>>>>> + u32 inst;
>>>>>>> + u32 seg;
>>>>>>> + u32 reg_offset;
>>>>>>> + const char *reg_name;
>>>>>>> +};
>>>>>>> +
>>>>>>> struct amdgpu_watchdog_timer {
>>>>>>> bool timeout_fatal_disable;
>>>>>>> uint32_t period; /* maxCycles = (1 << period), the number
>>>>>>> of cycles before a timeout */ diff --git
>>>>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>>>> index 04a86dff71e6..64f197bbc866 100644
>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>>>>>> @@ -433,6 +433,10 @@ struct amdgpu_gfx {
>>>>>>> uint32_t num_xcc_per_xcp;
>>>>>>> struct mutex partition_mutex;
>>>>>>> bool mcbp; /* mid command buffer preemption */
>>>>>>> +
>>>>>>> + /* IP reg dump */
>>>>>>> + uint32_t *ip_dump;
>>>>>>> + uint32_t reg_count;
>>>>>>> };
>>>>>>>
>>>>>>> struct amdgpu_gfx_ras_reg_entry {
>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>>>> index a0bc4196ff8b..4a54161f4837 100644
>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>>>>>> @@ -276,6 +276,99 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
>>>>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
>>>>>>> MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
>>>>>>>
>>>>>>> +static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
>>>>>>> + SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) };
>>>>>>> +
>>>>>>> static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
>>>>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>>>>>>> SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
>>>>>>> 0xfcff8fff, 0xf8000100), @@ -4490,6 +4583,22 @@ static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
>>>>>>> hw_prio, NULL);
>>>>>>> }
>>>>>>>
>>>>>>> +static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device *adev) {
>>>>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>>>>>> + uint32_t *ptr;
>>>>>>> +
>>>>>>> + ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
>>>>>>> + if (ptr == NULL) {
>>>>>>> + DRM_ERROR("Failed to allocate memory for IP Dump\n");
>>>>>>> + adev->gfx.ip_dump = NULL;
>>>>>>> + adev->gfx.reg_count = 0;
>>>>>>> + } else {
>>>>>>> + adev->gfx.ip_dump = ptr;
>>>>>>> + adev->gfx.reg_count = reg_count;
>>>>>>> + }
>>>>>>> +}
>>>>>>> +
>>>>>>> static int gfx_v10_0_sw_init(void *handle)
>>>>>>> {
>>>>>>> int i, j, k, r, ring_id = 0; @@ -4642,6 +4751,8 @@ static
>>>>>>> int gfx_v10_0_sw_init(void *handle)
>>>>>>>
>>>>>>> gfx_v10_0_gpu_early_init(adev);
>>>>>>>
>>>>>>> + gfx_v10_0_alloc_dump_mem(adev);
>>>>>>> +
>>>>>>> return 0;
>>>>>>> }
>>>>>>>
>>>>>>> @@ -4694,6 +4805,8 @@ static int gfx_v10_0_sw_fini(void *handle)
>>>>>>>
>>>>>>> gfx_v10_0_free_microcode(adev);
>>>>>>>
>>>>>>> + kfree(adev->gfx.ip_dump);
>>>>>>> +
>>>>>>> return 0;
>>>>>>> }
>>>>>>>
>>>>>>> @@ -9154,6 +9267,21 @@ static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
>>>>>>> amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
>>>>>>> }
>>>>>>>
>>>>>>> +static void gfx_v10_ip_dump(void *handle) {
>>>>>>> + struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>>>> + uint32_t i;
>>>>>>> + uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
>>>>>>> +
>>>>>>> + if (!adev->gfx.ip_dump)
>>>>>>> + return;
>>>>>>> +
>>>>>>> + amdgpu_gfx_off_ctrl(adev, false);
>>>>>>> + for (i = 0; i < reg_count; i++)
>>>>>>> + adev->gfx.ip_dump[i] =
>>>>>>> + RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
>>>>> This may cause a bigger hang, if PMFW is already hung (in that case
>>>>> reset also won't work, but a dump is still useful). To be on the safer
>>>>> side, there should be some sort of return value for gfx_off which
>>>>> should be checked.
>>>> amdgpu_gfx_off_ctrl doesnt return any value to confirm if it worked or not else would have checked return value.
>>>> I guess assumption is that it will work until there is a bigger hang as you mentioned and i guess in that case nothing will work and needs a reset only.
>>>>
>>>> Regards
>>>> Sunil Khatri
>>>>
>>>>> Thanks,
>>>>> Lijo
>>>>>
>>>>>>> + amdgpu_gfx_off_ctrl(adev, true); }
>>>>>>> +
>>>>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>>>>>> .name = "gfx_v10_0",
>>>>>>> .early_init = gfx_v10_0_early_init, @@ -9170,7 +9298,7 @@
>>>>>>> static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>>>>>>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>>>>>>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>>>>>>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>>>>>>> - .dump_ip_state = NULL,
>>>>>>> + .dump_ip_state = gfx_v10_ip_dump,
>>>>>>> };
>>>>>>>
>>>>>>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>>>> b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>>>> index 1444b7765e4b..282584a48be0 100644
>>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
>>>>>>> @@ -88,6 +88,8 @@ struct soc15_ras_field_entry {
>>>>>>> };
>>>>>>>
>>>>>>> #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst,
>>>>>>> reg##_BASE_IDX, reg
>>>>>>> +#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
>>>>>>> + { ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
>>>>>>>
>>>>>>> #define SOC15_REG_ENTRY_OFFSET(entry)
>>>>>>> (adev->reg_offset[entry.hwip][entry.inst][entry.seg] +
>>>>>>> entry.reg_offset)
>>>>>>>
>>>>>>> diff --git
>>>>>>> a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>>>> b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>>>> index 4908044f7409..4c8e7fdb6976 100644
>>>>>>> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>>>> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>>>>>>> @@ -4830,6 +4830,8 @@
>>>>>>> #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
>>>>>>> #define mmGB_EDC_MODE 0x1e1e
>>>>>>> #define mmGB_EDC_MODE_BASE_IDX 0
>>>>>>> +#define mmCP_DEBUG 0x1e1f
>>>>>>> +#define mmCP_DEBUG_BASE_IDX 0
>>>>>>> #define mmCP_FETCHER_SOURCE 0x1e22
>>>>>>> #define mmCP_FETCHER_SOURCE_BASE_IDX 0
>>>>>>> #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23
>>>>>>> @@ -7778,6 +7780,8 @@
>>>>>>> #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1
>>>>>>> #define mmCP_MES_DOORBELL_CONTROL6 0x2841
>>>>>>> #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1
>>>>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842
>>>>>>> +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
>>>>>>> #define mmCP_MES_GP0_LO 0x2843
>>>>>>> #define mmCP_MES_GP0_LO_BASE_IDX 1
>>>>>>> #define mmCP_MES_GP0_HI 0x2844
>>>>>>> @@ -9332,10 +9336,16 @@
>>>>>>> #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1
>>>>>>> #define mmRLC_LB_CNTR_1 0x4c1c
>>>>>>> #define mmRLC_LB_CNTR_1_BASE_IDX 1
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1
>>>>>>> #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e
>>>>>>> #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1
>>>>>>> #define mmRLC_PG_DELAY_2 0x4c1f
>>>>>>> #define mmRLC_PG_DELAY_2_BASE_IDX 1
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_A 0x4c22
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_B 0x4c23
>>>>>>> +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1
>>>>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24
>>>>>>> #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1
>>>>>>> #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25
>>>>>>> @@ -9720,6 +9730,8 @@
>>>>>>> #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1
>>>>>>> #define mmRLC_LB_CNTR_2 0x4de7
>>>>>>> #define mmRLC_LB_CNTR_2_BASE_IDX 1
>>>>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb
>>>>>>> +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1
>>>>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1
>>>>>>> #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1
>>>>>>> #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2
>>>>>>> --
>>>>>>> 2.34.1
>>>>>>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump
2024-04-17 15:45 ` [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Alex Deucher
@ 2024-04-18 8:45 ` Christian König
0 siblings, 0 replies; 20+ messages in thread
From: Christian König @ 2024-04-18 8:45 UTC (permalink / raw)
To: Alex Deucher, Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx
Am 17.04.24 um 17:45 schrieb Alex Deucher:
> On Wed, Apr 17, 2024 at 5:38 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>> Add the prototype to dump ip registers
>> for all ips of different asics and set
>> them to NULL for now. Based on the
>> requirement add a function pointer for
>> each of them.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 ++
>> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/si.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 +
>> drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
>> drivers/gpu/drm/amd/include/amd_shared.h | 1 +
>> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 1 +
>> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 +
>> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 1 +
>> 64 files changed, 66 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> index 6d72355ac492..34a62033a388 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> @@ -637,6 +637,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
>> .soft_reset = acp_soft_reset,
>> .set_clockgating_state = acp_set_clockgating_state,
>> .set_powergating_state = acp_set_powergating_state,
>> + .dump_ip_state = NULL,
> You can skip all of the NULL assignments. Static global structures
> will be 0 initialized.
Oh, that's a really good point. We have automated checkers complaining
about NULL initialization in structures.
So that here would cause tons of automated complains.
Regards,
Christian.
> Either way:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Alex
>
>> };
>>
>> const struct amdgpu_ip_block_version acp_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
>> index 95f80b9131a8..5bb9e0dacbf3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
>> @@ -875,6 +875,7 @@ static const struct amd_ip_funcs umsch_mm_v4_0_ip_funcs = {
>> .hw_fini = umsch_mm_hw_fini,
>> .suspend = umsch_mm_suspend,
>> .resume = umsch_mm_resume,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> index 8baa2e0935cc..d1dc91009c0e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> @@ -658,6 +658,7 @@ static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
>> .soft_reset = amdgpu_vkms_soft_reset,
>> .set_clockgating_state = amdgpu_vkms_set_clockgating_state,
>> .set_powergating_state = amdgpu_vkms_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
>> index fdbc26346b54..884de42553a6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>> @@ -2210,6 +2210,7 @@ static const struct amd_ip_funcs cik_common_ip_funcs = {
>> .soft_reset = cik_common_soft_reset,
>> .set_clockgating_state = cik_common_set_clockgating_state,
>> .set_powergating_state = cik_common_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ip_block_version cik_common_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index f24e34dc33d1..676f3f612fde 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -435,6 +435,7 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
>> .soft_reset = cik_ih_soft_reset,
>> .set_clockgating_state = cik_ih_set_clockgating_state,
>> .set_powergating_state = cik_ih_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs cik_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index a3fccc4c1f43..d797b1fbbffc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -1228,6 +1228,7 @@ static const struct amd_ip_funcs cik_sdma_ip_funcs = {
>> .soft_reset = cik_sdma_soft_reset,
>> .set_clockgating_state = cik_sdma_set_clockgating_state,
>> .set_powergating_state = cik_sdma_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index c19681492efa..958c84a6af7e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -433,6 +433,7 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
>> .soft_reset = cz_ih_soft_reset,
>> .set_clockgating_state = cz_ih_set_clockgating_state,
>> .set_powergating_state = cz_ih_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs cz_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> index 221af054d874..7a32ca7d6fc4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> @@ -3333,6 +3333,7 @@ static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
>> .soft_reset = dce_v10_0_soft_reset,
>> .set_clockgating_state = dce_v10_0_set_clockgating_state,
>> .set_powergating_state = dce_v10_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static void
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> index 69e8b0db6cf7..67c01e137fac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> @@ -3464,6 +3464,7 @@ static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
>> .soft_reset = dce_v11_0_soft_reset,
>> .set_clockgating_state = dce_v11_0_set_clockgating_state,
>> .set_powergating_state = dce_v11_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static void
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> index 60d40201fdd1..209cd44bbcec 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> @@ -3154,6 +3154,7 @@ static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
>> .soft_reset = dce_v6_0_soft_reset,
>> .set_clockgating_state = dce_v6_0_set_clockgating_state,
>> .set_powergating_state = dce_v6_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static void
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> index 5a5fcc45e452..fff7f4f766b2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> @@ -3242,6 +3242,7 @@ static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
>> .soft_reset = dce_v8_0_soft_reset,
>> .set_clockgating_state = dce_v8_0_set_clockgating_state,
>> .set_powergating_state = dce_v8_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static void
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index d5b924222903..a0bc4196ff8b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -9170,6 +9170,7 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
>> .set_clockgating_state = gfx_v10_0_set_clockgating_state,
>> .set_powergating_state = gfx_v10_0_set_powergating_state,
>> .get_clockgating_state = gfx_v10_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index 5dbfef49dd5d..fec076c90fd2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -6169,6 +6169,7 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
>> .set_clockgating_state = gfx_v11_0_set_clockgating_state,
>> .set_powergating_state = gfx_v11_0_set_powergating_state,
>> .get_clockgating_state = gfx_v11_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 34f9211b2679..559250c8a147 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -3457,6 +3457,7 @@ static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
>> .soft_reset = gfx_v6_0_soft_reset,
>> .set_clockgating_state = gfx_v6_0_set_clockgating_state,
>> .set_powergating_state = gfx_v6_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index 86a4865b1ae5..81f7ab0dc135 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -4977,6 +4977,7 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
>> .soft_reset = gfx_v7_0_soft_reset,
>> .set_clockgating_state = gfx_v7_0_set_clockgating_state,
>> .set_powergating_state = gfx_v7_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 202ddda57f98..522cbd45dd46 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -6878,6 +6878,7 @@ static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
>> .set_clockgating_state = gfx_v8_0_set_clockgating_state,
>> .set_powergating_state = gfx_v8_0_set_powergating_state,
>> .get_clockgating_state = gfx_v8_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 71b555993b7a..ff4229b005dc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -6856,6 +6856,7 @@ static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
>> .set_clockgating_state = gfx_v9_0_set_clockgating_state,
>> .set_powergating_state = gfx_v9_0_set_powergating_state,
>> .get_clockgating_state = gfx_v9_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> index fc33354f1d3d..16881e9345c8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> @@ -4016,6 +4016,7 @@ static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
>> .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
>> .set_powergating_state = gfx_v9_4_3_set_powergating_state,
>> .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index 23b478639921..060e54b8ffff 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -1115,6 +1115,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
>> .soft_reset = gmc_v6_0_soft_reset,
>> .set_clockgating_state = gmc_v6_0_set_clockgating_state,
>> .set_powergating_state = gmc_v6_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index 3da7b6a2b00d..534825022ddd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -1354,6 +1354,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
>> .soft_reset = gmc_v7_0_soft_reset,
>> .set_clockgating_state = gmc_v7_0_set_clockgating_state,
>> .set_powergating_state = gmc_v7_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index d20e5f20ee31..aba787e1386a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -1717,6 +1717,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
>> .set_clockgating_state = gmc_v8_0_set_clockgating_state,
>> .set_powergating_state = gmc_v8_0_set_powergating_state,
>> .get_clockgating_state = gmc_v8_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index 2c02ae69883d..2d6f969266b8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -425,6 +425,7 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
>> .soft_reset = iceland_ih_soft_reset,
>> .set_clockgating_state = iceland_ih_set_clockgating_state,
>> .set_powergating_state = iceland_ih_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> index c757ef99e3c5..77b5068b7be5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> @@ -770,6 +770,7 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
>> .set_clockgating_state = ih_v6_0_set_clockgating_state,
>> .set_powergating_state = ih_v6_0_set_powergating_state,
>> .get_clockgating_state = ih_v6_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs ih_v6_0_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> index 29ed78798070..fc2c27a199c6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> @@ -775,6 +775,7 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
>> .set_clockgating_state = ih_v6_1_set_clockgating_state,
>> .set_powergating_state = ih_v6_1_set_powergating_state,
>> .get_clockgating_state = ih_v6_1_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> index 7aed96fa10a9..31ed5030169b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> @@ -749,6 +749,7 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
>> .set_clockgating_state = ih_v7_0_set_clockgating_state,
>> .set_powergating_state = ih_v7_0_set_powergating_state,
>> .get_clockgating_state = ih_v7_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> index 1c8116d75f63..698c5d4b7484 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> @@ -759,6 +759,7 @@ static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
>> .set_powergating_state = jpeg_v2_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> index 99cd49ee8ef6..0a9a2d58e3ee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> @@ -632,6 +632,7 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
>> .set_powergating_state = jpeg_v2_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
>> @@ -652,6 +653,7 @@ static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
>> .set_powergating_state = jpeg_v2_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> index a92481da60cd..e03d46151ae3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> @@ -557,6 +557,7 @@ static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
>> .set_powergating_state = jpeg_v3_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> index 88ea58d5c4ab..f142cb200552 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> @@ -719,6 +719,7 @@ static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v4_0_set_clockgating_state,
>> .set_powergating_state = jpeg_v4_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> index 32caeb37cef9..bc3a6f16f4bf 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> @@ -1053,6 +1053,7 @@ static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state,
>> .set_powergating_state = jpeg_v4_0_3_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> index edf5bcdd2bc9..ee29c97721ec 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> @@ -762,6 +762,7 @@ static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state,
>> .set_powergating_state = jpeg_v4_0_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> index e70200f97555..f5664c92d10d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> @@ -513,6 +513,7 @@ static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
>> .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
>> index 1e5ad1e08d2a..4ed0429cf4f7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
>> @@ -1176,6 +1176,7 @@ static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
>> .hw_fini = mes_v10_1_hw_fini,
>> .suspend = mes_v10_1_suspend,
>> .resume = mes_v10_1_resume,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> index 81833395324a..57f17c699d80 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
>> @@ -1334,6 +1334,7 @@ static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
>> .hw_fini = mes_v11_0_hw_fini,
>> .suspend = mes_v11_0_suspend,
>> .resume = mes_v11_0_resume,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index 4178f4e5dad7..550c5ca4ea03 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -713,6 +713,7 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
>> .set_clockgating_state = navi10_ih_set_clockgating_state,
>> .set_powergating_state = navi10_ih_set_powergating_state,
>> .get_clockgating_state = navi10_ih_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs navi10_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 4d7976b77767..d7d3b972392b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -1131,4 +1131,5 @@ static const struct amd_ip_funcs nv_common_ip_funcs = {
>> .set_clockgating_state = nv_common_set_clockgating_state,
>> .set_powergating_state = nv_common_set_powergating_state,
>> .get_clockgating_state = nv_common_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> index 07e19caf2bc1..5c67c8a5c35f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> @@ -1113,6 +1113,7 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
>> .soft_reset = sdma_v2_4_soft_reset,
>> .set_clockgating_state = sdma_v2_4_set_clockgating_state,
>> .set_powergating_state = sdma_v2_4_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index 2ad615be4bb3..4fad06daa9c9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -1553,6 +1553,7 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
>> .set_clockgating_state = sdma_v3_0_set_clockgating_state,
>> .set_powergating_state = sdma_v3_0_set_powergating_state,
>> .get_clockgating_state = sdma_v3_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
>> index 67e179c7e347..b5b15dba9a76 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
>> @@ -2706,6 +2706,7 @@ static const struct amd_ip_funcs si_common_ip_funcs = {
>> .soft_reset = si_common_soft_reset,
>> .set_clockgating_state = si_common_set_clockgating_state,
>> .set_powergating_state = si_common_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ip_block_version si_common_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> index 9aa0e11ee673..f969e5cc2a5e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> @@ -708,6 +708,7 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
>> .soft_reset = si_dma_soft_reset,
>> .set_clockgating_state = si_dma_set_clockgating_state,
>> .set_powergating_state = si_dma_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index cada9f300a7f..3b7427f5a6c9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -296,6 +296,7 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
>> .soft_reset = si_ih_soft_reset,
>> .set_clockgating_state = si_ih_set_clockgating_state,
>> .set_powergating_state = si_ih_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs si_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index c8abbf5da736..6ba6c96c91c8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -1501,4 +1501,5 @@ static const struct amd_ip_funcs soc15_common_ip_funcs = {
>> .set_clockgating_state = soc15_common_set_clockgating_state,
>> .set_powergating_state = soc15_common_set_powergating_state,
>> .get_clockgating_state= soc15_common_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> index 43ca63fe85ac..40e7ab0716cd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> @@ -985,4 +985,5 @@ static const struct amd_ip_funcs soc21_common_ip_funcs = {
>> .set_clockgating_state = soc21_common_set_clockgating_state,
>> .set_powergating_state = soc21_common_set_powergating_state,
>> .get_clockgating_state = soc21_common_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index 450b6e831509..794a1f7bc2ca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -486,6 +486,7 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
>> .post_soft_reset = tonga_ih_post_soft_reset,
>> .set_clockgating_state = tonga_ih_set_clockgating_state,
>> .set_powergating_state = tonga_ih_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> index a6006f231c65..1e232ed23102 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> @@ -819,6 +819,7 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
>> .soft_reset = uvd_v3_1_soft_reset,
>> .set_clockgating_state = uvd_v3_1_set_clockgating_state,
>> .set_powergating_state = uvd_v3_1_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> index 1aa09ad7bbe3..48bcf41e5558 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> @@ -769,6 +769,7 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
>> .soft_reset = uvd_v4_2_soft_reset,
>> .set_clockgating_state = uvd_v4_2_set_clockgating_state,
>> .set_powergating_state = uvd_v4_2_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> index f8b229b75435..838b7d720c52 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> @@ -877,6 +877,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
>> .set_clockgating_state = uvd_v5_0_set_clockgating_state,
>> .set_powergating_state = uvd_v5_0_set_powergating_state,
>> .get_clockgating_state = uvd_v5_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index a9a6880f44e3..036378f5f53f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1545,6 +1545,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
>> .set_clockgating_state = uvd_v6_0_set_clockgating_state,
>> .set_powergating_state = uvd_v6_0_set_powergating_state,
>> .get_clockgating_state = uvd_v6_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> index a08e7abca423..2178cf5a27b7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> @@ -626,6 +626,7 @@ static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
>> .soft_reset = vce_v2_0_soft_reset,
>> .set_clockgating_state = vce_v2_0_set_clockgating_state,
>> .set_powergating_state = vce_v2_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> index f4760748d349..0f0d4b0d50cb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> @@ -913,6 +913,7 @@ static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
>> .set_clockgating_state = vce_v3_0_set_clockgating_state,
>> .set_powergating_state = vce_v3_0_set_powergating_state,
>> .get_clockgating_state = vce_v3_0_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> index aaceecd558cf..7ff5d0574454 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> @@ -1902,6 +1902,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
>> .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
>> .set_clockgating_state = vcn_v1_0_set_clockgating_state,
>> .set_powergating_state = vcn_v1_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> /*
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index e357d8cf0c01..4df1b75f971a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -2008,6 +2008,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v2_0_set_clockgating_state,
>> .set_powergating_state = vcn_v2_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index 1cd8a94b0fbc..d91c3154641b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -1901,6 +1901,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
>> .set_powergating_state = vcn_v2_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
>> @@ -1921,6 +1922,7 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v2_5_set_clockgating_state,
>> .set_powergating_state = vcn_v2_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 8f82fb887e9c..e64af339e924 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -2230,6 +2230,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v3_0_set_clockgating_state,
>> .set_powergating_state = vcn_v3_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> index 832d15f7b5f6..efaad53e2ffe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> @@ -2130,6 +2130,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v4_0_set_clockgating_state,
>> .set_powergating_state = vcn_v4_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index 203fa988322b..599b6466183e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -1660,6 +1660,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>> .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> index 501e53e69f2a..c649fa2c19e8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> @@ -1752,6 +1752,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
>> .set_powergating_state = vcn_v4_0_5_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> index bc60c554eb32..9d0d1efd1acc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> @@ -1328,6 +1328,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
>> .post_soft_reset = NULL,
>> .set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
>> .set_powergating_state = vcn_v5_0_0_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
>> index 2415355b037c..a04aa6833fc5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -2058,6 +2058,7 @@ static const struct amd_ip_funcs vi_common_ip_funcs = {
>> .set_clockgating_state = vi_common_set_clockgating_state,
>> .set_powergating_state = vi_common_set_powergating_state,
>> .get_clockgating_state = vi_common_get_clockgating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> static const struct amdgpu_ip_block_version vi_common_ip_block =
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 2c06f2bee4a5..8bd8bd77b9be 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -3120,6 +3120,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
>> .soft_reset = dm_soft_reset,
>> .set_clockgating_state = dm_set_clockgating_state,
>> .set_powergating_state = dm_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version dm_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
>> index b0a6256e89f4..9884f6c48a7d 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -321,6 +321,7 @@ struct amd_ip_funcs {
>> int (*set_powergating_state)(void *handle,
>> enum amd_powergating_state state);
>> void (*get_clockgating_state)(void *handle, u64 *flags);
>> + void (*dump_ip_state)(void *handle);
>> };
>>
>>
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> index 5cb4725c773f..8c07f8c7f3ab 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> @@ -3316,6 +3316,7 @@ static const struct amd_ip_funcs kv_dpm_ip_funcs = {
>> .soft_reset = kv_dpm_soft_reset,
>> .set_clockgating_state = kv_dpm_set_clockgating_state,
>> .set_powergating_state = kv_dpm_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version kv_smu_ip_block = {
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> index eb4da3666e05..c312b9332326 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> @@ -8060,6 +8060,7 @@ static const struct amd_ip_funcs si_dpm_ip_funcs = {
>> .soft_reset = si_dpm_soft_reset,
>> .set_clockgating_state = si_dpm_set_clockgating_state,
>> .set_powergating_state = si_dpm_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version si_smu_ip_block =
>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> index 133d1ee6e67c..c63474ee17a7 100644
>> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> @@ -302,6 +302,7 @@ static const struct amd_ip_funcs pp_ip_funcs = {
>> .soft_reset = pp_sw_reset,
>> .set_clockgating_state = pp_set_clockgating_state,
>> .set_powergating_state = pp_set_powergating_state,
>> + .dump_ip_state = NULL,
>> };
>>
>> const struct amdgpu_ip_block_version pp_smu_ip_block =
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2024-04-18 8:45 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-17 9:38 [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Sunil Khatri
2024-04-17 9:38 ` [PATCH v5 2/6] drm/amdgpu: add support of gfx10 register dump Sunil Khatri
2024-04-17 15:51 ` Alex Deucher
2024-04-17 16:01 ` Lazar, Lijo
2024-04-17 16:11 ` Khatri, Sunil
2024-04-17 16:23 ` Lazar, Lijo
2024-04-17 16:51 ` Alex Deucher
2024-04-17 17:01 ` Khatri, Sunil
2024-04-17 17:30 ` Alex Deucher
2024-04-18 6:12 ` Christian König
2024-04-17 9:38 ` [PATCH v5 3/6] drm/amdgpu: add protype for print ip state Sunil Khatri
2024-04-17 15:48 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 4/6] drm/amdgpu: add support for gfx v10 print Sunil Khatri
2024-04-17 15:52 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 5/6] drm/amdgpu: dump ip state before reset for each ip Sunil Khatri
2024-04-17 15:52 ` Alex Deucher
2024-04-17 9:38 ` [PATCH v5 6/6] drm/amdgpu: add ip dump for each ip in devcoredump Sunil Khatri
2024-04-17 15:53 ` Alex Deucher
2024-04-17 15:45 ` [PATCH v5 1/6] drm/amdgpu: add prototype for ip dump Alex Deucher
2024-04-18 8:45 ` Christian König
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