* [PATCH 1/3] clk: imx8mm: Add support for PCIe clocks
@ 2024-04-17 20:09 Tim Harvey
2024-04-17 20:09 ` [PATCH 2/3] pci: dw_imx: add support for IMX8MM Tim Harvey
2024-04-17 20:09 ` [PATCH 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support Tim Harvey
0 siblings, 2 replies; 5+ messages in thread
From: Tim Harvey @ 2024-04-17 20:09 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Sumit Garg,
Fabio Estevam, Martyn Welch, Simon Glass, Marek Vasut, u-boot
Cc: Tim Harvey
Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b5c253e49663..c2f01b385201 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
+ "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
+
+static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4", "sys_pll1_400m", };
+
+static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
+ "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
+
#ifndef CONFIG_SPL_BUILD
static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
@@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
/* IP */
+ clk_dm(IMX8MM_CLK_PCIE1_CTRL,
+ imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ base + 0xa300));
+ clk_dm(IMX8MM_CLK_PCIE1_PHY,
+ imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ base + 0xa380));
+ clk_dm(IMX8MM_CLK_PCIE1_AUX,
+ imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ base + 0xa400));
clk_dm(IMX8MM_CLK_USDHC1,
imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
base + 0xac00));
@@ -339,6 +357,9 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
#endif
+ clk_dm(IMX8MM_CLK_PCIE1_ROOT,
+ imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+
#if CONFIG_IS_ENABLED(DM_SPI)
clk_dm(IMX8MM_CLK_ECSPI1,
imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] pci: dw_imx: add support for IMX8MM
2024-04-17 20:09 [PATCH 1/3] clk: imx8mm: Add support for PCIe clocks Tim Harvey
@ 2024-04-17 20:09 ` Tim Harvey
2024-04-18 1:17 ` Marek Vasut
2024-04-17 20:09 ` [PATCH 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support Tim Harvey
1 sibling, 1 reply; 5+ messages in thread
From: Tim Harvey @ 2024-04-17 20:09 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Sumit Garg,
Fabio Estevam, Martyn Welch, Simon Glass, Marek Vasut, u-boot
Cc: Tim Harvey
Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/pci/pcie_dw_imx.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index a2ee228224b5..10d926c30645 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -45,6 +45,10 @@
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+struct pcie_chip_info {
+ const char *gpr;
+};
+
struct pcie_dw_imx {
/* Must be first member of the struct */
struct pcie_dw dw;
@@ -54,6 +58,15 @@ struct pcie_dw_imx {
struct reset_ctl apps_reset;
struct phy phy;
struct udevice *vpcie;
+ struct pcie_chip_info *info;
+};
+
+static const struct pcie_chip_info imx8mm_chip_info = {
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct pcie_chip_info imx8mp_chip_info = {
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
};
static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
@@ -246,6 +259,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
ofnode gpr;
int ret;
+ priv->info = (void *)dev_get_driver_data(dev);
+
/* Get the controller base address */
priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
@@ -287,7 +302,7 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
goto err_phy;
}
- gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr");
+ gpr = ofnode_by_compatible(ofnode_null(), priv->info->gpr);
if (ofnode_equal(gpr, ofnode_null())) {
dev_err(dev, "unable to find GPR node\n");
ret = -ENODEV;
@@ -322,7 +337,8 @@ static const struct dm_pci_ops pcie_dw_imx_ops = {
};
static const struct udevice_id pcie_dw_imx_ids[] = {
- { .compatible = "fsl,imx8mp-pcie" },
+ { .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, },
+ { .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, },
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support
2024-04-17 20:09 [PATCH 1/3] clk: imx8mm: Add support for PCIe clocks Tim Harvey
2024-04-17 20:09 ` [PATCH 2/3] pci: dw_imx: add support for IMX8MM Tim Harvey
@ 2024-04-17 20:09 ` Tim Harvey
1 sibling, 0 replies; 5+ messages in thread
From: Tim Harvey @ 2024-04-17 20:09 UTC (permalink / raw)
To: Tom Rini, Lukasz Majewski, Sean Anderson, Sumit Garg,
Fabio Estevam, Martyn Welch, Simon Glass, Marek Vasut, u-boot
Cc: Tim Harvey
Enable PCIe/NVMe support. Also, enable the reset
driver which is a prerequisite for PCIe support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
configs/imx8mm_venice_defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index c3fd4c45ab3d..d34dd7cc2bac 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_VENICE=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -20,6 +21,7 @@ CONFIG_SPL_STACK=0x920000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f8000
CONFIG_SYS_LOAD_ADDR=0x48200000
+CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_FIT=y
@@ -60,6 +62,7 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP6=y
@@ -119,6 +122,9 @@ CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_KSZ9477=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/3] pci: dw_imx: add support for IMX8MM
2024-04-17 20:09 ` [PATCH 2/3] pci: dw_imx: add support for IMX8MM Tim Harvey
@ 2024-04-18 1:17 ` Marek Vasut
2024-04-18 15:31 ` Tim Harvey
0 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2024-04-18 1:17 UTC (permalink / raw)
To: Tim Harvey, Tom Rini, Lukasz Majewski, Sean Anderson, Sumit Garg,
Fabio Estevam, Martyn Welch, Simon Glass, u-boot
On 4/17/24 10:09 PM, Tim Harvey wrote:
> Add support for the IMX8MM SoC by adding driver data with the compatible
> string of the GPR controller.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
> drivers/pci/pcie_dw_imx.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
> index a2ee228224b5..10d926c30645 100644
> --- a/drivers/pci/pcie_dw_imx.c
> +++ b/drivers/pci/pcie_dw_imx.c
> @@ -45,6 +45,10 @@
> #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
> #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
>
> +struct pcie_chip_info {
> + const char *gpr;
> +};
> +
> struct pcie_dw_imx {
> /* Must be first member of the struct */
> struct pcie_dw dw;
> @@ -54,6 +58,15 @@ struct pcie_dw_imx {
> struct reset_ctl apps_reset;
> struct phy phy;
> struct udevice *vpcie;
> + struct pcie_chip_info *info;
> +};
> +
> +static const struct pcie_chip_info imx8mm_chip_info = {
> + .gpr = "fsl,imx8mm-iomuxc-gpr",
> +};
> +
> +static const struct pcie_chip_info imx8mp_chip_info = {
> + .gpr = "fsl,imx8mp-iomuxc-gpr",
> };
>
> static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
> @@ -246,6 +259,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
> ofnode gpr;
> int ret;
>
> + priv->info = (void *)dev_get_driver_data(dev);
> +
Does this really have to be cached in priv ?
The priv->info seems used only in this function.
[...]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/3] pci: dw_imx: add support for IMX8MM
2024-04-18 1:17 ` Marek Vasut
@ 2024-04-18 15:31 ` Tim Harvey
0 siblings, 0 replies; 5+ messages in thread
From: Tim Harvey @ 2024-04-18 15:31 UTC (permalink / raw)
To: Marek Vasut
Cc: Tom Rini, Lukasz Majewski, Sean Anderson, Sumit Garg,
Fabio Estevam, Martyn Welch, Simon Glass, u-boot
On Wed, Apr 17, 2024 at 8:04 PM Marek Vasut <marex@denx.de> wrote:
>
> On 4/17/24 10:09 PM, Tim Harvey wrote:
> > Add support for the IMX8MM SoC by adding driver data with the compatible
> > string of the GPR controller.
> >
> > Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> > ---
> > drivers/pci/pcie_dw_imx.c | 20 ++++++++++++++++++--
> > 1 file changed, 18 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
> > index a2ee228224b5..10d926c30645 100644
> > --- a/drivers/pci/pcie_dw_imx.c
> > +++ b/drivers/pci/pcie_dw_imx.c
> > @@ -45,6 +45,10 @@
> > #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
> > #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
> >
> > +struct pcie_chip_info {
> > + const char *gpr;
> > +};
> > +
> > struct pcie_dw_imx {
> > /* Must be first member of the struct */
> > struct pcie_dw dw;
> > @@ -54,6 +58,15 @@ struct pcie_dw_imx {
> > struct reset_ctl apps_reset;
> > struct phy phy;
> > struct udevice *vpcie;
> > + struct pcie_chip_info *info;
> > +};
> > +
> > +static const struct pcie_chip_info imx8mm_chip_info = {
> > + .gpr = "fsl,imx8mm-iomuxc-gpr",
> > +};
> > +
> > +static const struct pcie_chip_info imx8mp_chip_info = {
> > + .gpr = "fsl,imx8mp-iomuxc-gpr",
> > };
> >
> > static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
> > @@ -246,6 +259,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
> > ofnode gpr;
> > int ret;
> >
> > + priv->info = (void *)dev_get_driver_data(dev);
> > +
>
> Does this really have to be cached in priv ?
>
> The priv->info seems used only in this function.
>
Hi Marek,
Good point. I will remove that. Thanks for the review!
Best Regards,
Tim
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-04-18 15:31 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2024-04-17 20:09 [PATCH 1/3] clk: imx8mm: Add support for PCIe clocks Tim Harvey
2024-04-17 20:09 ` [PATCH 2/3] pci: dw_imx: add support for IMX8MM Tim Harvey
2024-04-18 1:17 ` Marek Vasut
2024-04-18 15:31 ` Tim Harvey
2024-04-17 20:09 ` [PATCH 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support Tim Harvey
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