[PATCH 1/3] pinctrl: qcom: allow selecting with ARCH_IPQ40XX

[PATCH 1/3] pinctrl: qcom: allow selecting with ARCH_IPQ40XX

[Robert Marko]

IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.

Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
 drivers/pinctrl/qcom/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe6398147..bd2019c866 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_SNAPDRAGON
+if ARCH_SNAPDRAGON || ARCH_IPQ40XX
 
 config PINCTRL_QCOM
 	depends on PINCTRL_GENERIC
-- 
2.44.0

[PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon

[Robert Marko]

Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.

Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
 arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++++++++++++++++++----
 1 file changed, 31 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h
index a45747c0fe..53c6ae0649 100644
--- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
+++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
@@ -1,10 +1,35 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Empty gpio.h
+ * Qualcomm common pin control data.
  *
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko <robert.marko@sartura.hr>
+ * Copyright (C) 2023 Linaro Ltd.
  */
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include <asm/types.h>
+#include <stdbool.h>
+
+struct msm_pin_data {
+	int pin_count;
+	const unsigned int *pin_offsets;
+	/* Index of first special pin, these are ignored for now */
+	unsigned int special_pins_start;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
+{
+	u32 out = (selector * 0x1000);
+
+	if (offs)
+		return out + offs[selector];
+
+	return out;
+}
+
+static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin)
+{
+	return pindata->special_pins_start && pin >= pindata->special_pins_start;
+}
+
+#endif /* _QCOM_GPIO_H_ */
-- 
2.44.0

[PATCH 3/3] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS

[Robert Marko]

We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4479230313..4fcc4b1810 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -36,7 +36,7 @@ static const char *ipq4019_get_function_name(struct udevice *dev,
 static const char *ipq4019_get_pin_name(struct udevice *dev,
 					unsigned int selector)
 {
-	snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
 	return pin_name;
 }
 
-- 
2.44.0

Re: [PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon

[Caleb Connolly]

Hi Robert,

On 18/04/2024 10:14, Robert Marko wrote:
> Pinctrl driver was refactored and moved, but the required header that
> it depends on was not included.

Thanks for these patches!

I'm a bit worried about duplicating this header file, we could probably
move it to the main include directory instead?

Alternatively, do you think it would be sensible to combine
mach-snapdragon with mach-ipq40xx ?

I received some patches a while ago from some Qualcomm engineers trying
to introduce support for newer IPQ SoCs, where they also seem to want to
build U-Boot as 32-bit (something I guess ipq40xx may also do?).

I'm easy either way, just want to get a better understanding of this.

Kind regards,
> 
> Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
>  arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++++++++++++++++++----
>  1 file changed, 31 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> index a45747c0fe..53c6ae0649 100644
> --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> @@ -1,10 +1,35 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
> - * Empty gpio.h
> + * Qualcomm common pin control data.
>   *
> - * This file must stay as arch/arm/include/asm/gpio.h requires it.
> - *
> - * Copyright (c) 2019 Sartura Ltd.
> - *
> - * Author: Robert Marko <robert.marko@sartura.hr>
> + * Copyright (C) 2023 Linaro Ltd.
>   */
> +#ifndef _QCOM_GPIO_H_
> +#define _QCOM_GPIO_H_
> +
> +#include <asm/types.h>
> +#include <stdbool.h>
> +
> +struct msm_pin_data {
> +	int pin_count;
> +	const unsigned int *pin_offsets;
> +	/* Index of first special pin, these are ignored for now */
> +	unsigned int special_pins_start;
> +};
> +
> +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
> +{
> +	u32 out = (selector * 0x1000);
> +
> +	if (offs)
> +		return out + offs[selector];
> +
> +	return out;
> +}
> +
> +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin)
> +{
> +	return pindata->special_pins_start && pin >= pindata->special_pins_start;
> +}
> +
> +#endif /* _QCOM_GPIO_H_ */

-- 
// Caleb (they/them)

Re: [PATCH 1/3] pinctrl: qcom: allow selecting with ARCH_IPQ40XX

[Caleb Connolly]

On 18/04/2024 10:14, Robert Marko wrote:
> IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
> directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
> PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
> 
> Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/pinctrl/qcom/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 2fe6398147..bd2019c866 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -1,4 +1,4 @@
> -if ARCH_SNAPDRAGON
> +if ARCH_SNAPDRAGON || ARCH_IPQ40XX
>  
>  config PINCTRL_QCOM
>  	depends on PINCTRL_GENERIC

-- 
// Caleb (they/them)

Re: [PATCH 3/3] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS

[Caleb Connolly]

On 18/04/2024 10:14, Robert Marko wrote:
> We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
> as a preparation update pinctrl driver to look for the upstream pin format.
> 
> Signed-off-by: Robert Marko <robert.marko@sartura.hr>

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index 4479230313..4fcc4b1810 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -36,7 +36,7 @@ static const char *ipq4019_get_function_name(struct udevice *dev,
>  static const char *ipq4019_get_pin_name(struct udevice *dev,
>  					unsigned int selector)
>  {
> -	snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
> +	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>  	return pin_name;
>  }
>  

-- 
// Caleb (they/them)

Re: [PATCH 2/3] mach-ipq40xx: import GPIO header from mach-snapgradon

[Robert Marko]

On Thu, Apr 18, 2024 at 1:02 PM Caleb Connolly
<caleb.connolly@linaro.org> wrote:
>
> Hi Robert,
>
> On 18/04/2024 10:14, Robert Marko wrote:
> > Pinctrl driver was refactored and moved, but the required header that
> > it depends on was not included.
>
> Thanks for these patches!
>
> I'm a bit worried about duplicating this header file, we could probably
> move it to the main include directory instead?

Hi Caleb,
That works for me as its a straight copy from mach-snapdragon.

>
> Alternatively, do you think it would be sensible to combine
> mach-snapdragon with mach-ipq40xx ?
>
> I received some patches a while ago from some Qualcomm engineers trying
> to introduce support for newer IPQ SoCs, where they also seem to want to
> build U-Boot as 32-bit (something I guess ipq40xx may also do?).

If it's possible, I would prefer to keep mach-ipq40xx separate and
probably convert it
to mach-ipq later since I would also love to see some newer SoC-s as well.
While Snapdragon and IPQ40xx are similar currently they will diverge for sure.

I dont understand why Qualcomm still insists on building the stock
U-Boot in ARMv7 32-bit
compatibility mode for all of the Cortex-A53 based IPQ807x/60xx/50xx and so on.

Regards,
Robert

>
> I'm easy either way, just want to get a better understanding of this.
>
> Kind regards,
> >
> > Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
> > Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> > ---
> >  arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++++++++++++++++++----
> >  1 file changed, 31 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > index a45747c0fe..53c6ae0649 100644
> > --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
> > @@ -1,10 +1,35 @@
> >  /* SPDX-License-Identifier: GPL-2.0+ */
> >  /*
> > - * Empty gpio.h
> > + * Qualcomm common pin control data.
> >   *
> > - * This file must stay as arch/arm/include/asm/gpio.h requires it.
> > - *
> > - * Copyright (c) 2019 Sartura Ltd.
> > - *
> > - * Author: Robert Marko <robert.marko@sartura.hr>
> > + * Copyright (C) 2023 Linaro Ltd.
> >   */
> > +#ifndef _QCOM_GPIO_H_
> > +#define _QCOM_GPIO_H_
> > +
> > +#include <asm/types.h>
> > +#include <stdbool.h>
> > +
> > +struct msm_pin_data {
> > +     int pin_count;
> > +     const unsigned int *pin_offsets;
> > +     /* Index of first special pin, these are ignored for now */
> > +     unsigned int special_pins_start;
> > +};
> > +
> > +static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
> > +{
> > +     u32 out = (selector * 0x1000);
> > +
> > +     if (offs)
> > +             return out + offs[selector];
> > +
> > +     return out;
> > +}
> > +
> > +static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata, unsigned int pin)
> > +{
> > +     return pindata->special_pins_start && pin >= pindata->special_pins_start;
> > +}
> > +
> > +#endif /* _QCOM_GPIO_H_ */
>
> --
> // Caleb (they/them)



-- 
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@sartura.hr
Web: www.sartura.hr