* [PATCH v2 00/10] Power11 support for QEMU
@ 2024-04-26 11:00 Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type Aditya Gupta
` (9 more replies)
0 siblings, 10 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc
Overview
============
Add support for Power11 pseries and powernv machine types, to emulate VMs
running on Power11.
As Power11 core is same as Power10, hence much of the code has been reused from
Power10.
Also make Power11 as default cpu type for 'pseries' and 'powernv'
machine types, with Power11 being the newest supported Power processor in QEMU.
Git Tree for Testing
====================
QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-v2
Has been tested with following cases:
* '-M pseries' / '-M pseries -cpu Power11'
* '-M powernv' / '-M powernv10' / '-M powernv11'
* '-smp' option tested
* with compat mode: 'max-cpu-compat=power10' and 'max-cpu-compat=power9'
* with/without device 'virtio-scsi-pci'
* with/without -kernel and -drive with qcow_file
skiboot with Power11 support: https://github.com/maheshsal/skiboot/tree/upstream_power11
Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1
Changelog
=========
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (10):
ppc/pseries: Add Power11 cpu type
ppc/pnv: Introduce 'PnvChipClass::chip_type'
ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
ppc/pnv: Add HOMER for POWER11
ppc/pnv: Add a LPC controller for POWER11
ppc/pnv: Add OCC for Power11
ppc/pnv: Add a PSI bridge model for Power11
ppc/pnv: Add SBE model for Power11
ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
ppc/pnv: Update skiboot.lid to support Power11
docs/system/ppc/powernv.rst | 9 +--
docs/system/ppc/pseries.rst | 6 +-
hw/ppc/pnv.c | 107 ++++++++++++++++++++++++++++++++++--
hw/ppc/pnv_core.c | 16 +++++-
hw/ppc/pnv_homer.c | 8 +++
hw/ppc/pnv_lpc.c | 14 +++++
hw/ppc/pnv_occ.c | 14 +++++
hw/ppc/pnv_psi.c | 24 ++++++++
hw/ppc/pnv_sbe.c | 15 +++++
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_cpu_core.c | 1 +
include/hw/ppc/pnv.h | 5 ++
include/hw/ppc/pnv_chip.h | 20 +++++++
include/hw/ppc/pnv_homer.h | 3 +
include/hw/ppc/pnv_lpc.h | 4 ++
include/hw/ppc/pnv_occ.h | 2 +
include/hw/ppc/pnv_psi.h | 2 +
include/hw/ppc/pnv_sbe.h | 2 +
pc-bios/skiboot.lid | Bin 2527328 -> 2527328 bytes
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 2 +
target/ppc/cpu-models.h | 2 +
target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++
23 files changed, 350 insertions(+), 14 deletions(-)
--
2.44.0
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:27 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type' Aditya Gupta
` (8 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
Add base support for "--cpu power11" in QEMU.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/pseries.rst | 6 +--
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 2 +
target/ppc/cpu-models.h | 2 +
target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++
6 files changed, 114 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -15,9 +15,9 @@ Supported devices
=================
* Multi processor support for many Power processors generations: POWER7,
- POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
- but its state is unknown.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
+ POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
+ exists, but its state is unknown.
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
* vPHB PCIe Host bridge.
* vscsi and vnet devices, compatible with the same devices available on a
PowerVM hypervisor with VIOS managing LPARs.
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index e7c9edd033c8..c6e85c031178 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
+ DEFINE_SPAPR_CPU_CORE_TYPE("power11"),
#ifdef CONFIG_KVM
DEFINE_SPAPR_CPU_CORE_TYPE("host"),
#endif
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index ebef2cccecf3..12dd8ae290ca 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
.pcr_level = PCR_COMPAT_3_10,
.max_vthreads = 8,
},
+ { /* POWER11, ISA3.10 */
+ .name = "power11",
+ .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS,
+ .pcr = PCR_COMPAT_3_10,
+ .pcr_level = PCR_COMPAT_3_10,
+ .max_vthreads = 8,
+ },
};
static const CompatInfo *compat_by_pvr(uint32_t pvr)
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index f2301b43f78b..1870e69b63df 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -734,6 +734,8 @@
"POWER9 v2.2")
POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
"POWER10 v2.0")
+ POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11,
+ "POWER11")
#endif /* defined (TARGET_PPC64) */
/***************************************************************************/
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 0229ef3a9a5c..a1b540c3aa9e 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -354,6 +354,7 @@ enum {
CPU_POWERPC_POWER10_BASE = 0x00800000,
CPU_POWERPC_POWER10_DD1 = 0x00801100,
CPU_POWERPC_POWER10_DD20 = 0x00801200,
+ CPU_POWERPC_POWER11 = 0x00821200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
@@ -391,6 +392,7 @@ enum {
CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
+ CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007,
};
/* System version register (used on MPC 8xxx) */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6d82f24c8756..17c159c8187b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
}
+static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
+{
+ uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
+ uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
+
+ if (!best && (base == CPU_POWERPC_POWER11))
+ return true;
+
+ if (base != pcc_base)
+ return false;
+
+ if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00))
+ return true;
+
+ return false;
+}
+
+POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->fw_name = "PowerPC,POWER11";
+ dc->desc = "POWER11";
+ pcc->pvr_match = ppc_pvr_match_power11;
+ pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_3_00 | PCR_COMPAT_3_10;
+ pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
+ PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
+ pcc->init_proc = init_proc_POWER10;
+ pcc->check_pow = check_pow_nocheck;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
+ PPC_FLOAT_FRSQRTES |
+ PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
+ PPC_SEGMENT_64B | PPC_SLBI |
+ PPC_POPCNTB | PPC_POPCNTWD |
+ PPC_CILDST;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
+ PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
+ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
+ pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_HV) |
+ (1ull << MSR_TM) |
+ (1ull << MSR_VR) |
+ (1ull << MSR_VSX) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_PMM) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ /* DD2 adds an extra HAIL bit */
+ pcc->lpcr_mask |= LPCR_HAIL;
+
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
+ pcc->mmu_model = POWERPC_MMU_3_00;
+#if !defined(CONFIG_USER_ONLY)
+ /* segment page size remain the same */
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
+ pcc->radix_page_info = &POWER10_radix_page_info;
+ pcc->lrg_decr_bits = 56;
+#endif
+ pcc->excp_model = POWERPC_EXCP_POWER10;
+ pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
+ pcc->bfd_mach = bfd_mach_ppc64;
+ pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
+ POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
+ pcc->l1_dcache_size = 0x8000;
+ pcc->l1_icache_size = 0x8000;
+}
+
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
{
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type'
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:16 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Aditya Gupta
` (7 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Introduce 'PnvChipClass::chip_type' to easily get which Power chip is
it.
This helps generalise similar codes such as *_dt_populate, and removes
duplication of code between Power11 and Power10 changes in following
patches.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 5 +++++
include/hw/ppc/pnv_chip.h | 10 ++++++++++
2 files changed, 15 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec76..74e7908e5ffb 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1457,6 +1457,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
+ k->chip_type = PNV_TYPE_POWER8E;
k->cores_mask = POWER8E_CORE_MASK;
k->num_phbs = 3;
k->chip_pir = pnv_chip_pir_p8;
@@ -1481,6 +1482,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
+ k->chip_type = PNV_TYPE_POWER8;
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 3;
k->chip_pir = pnv_chip_pir_p8;
@@ -1505,6 +1507,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
PnvChipClass *k = PNV_CHIP_CLASS(klass);
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
+ k->chip_type = PNV_TYPE_POWER8NVL;
k->cores_mask = POWER8_CORE_MASK;
k->num_phbs = 4;
k->chip_pir = pnv_chip_pir_p8;
@@ -1779,6 +1782,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
+ k->chip_type = PNV_TYPE_POWER9;
k->cores_mask = POWER9_CORE_MASK;
k->chip_pir = pnv_chip_pir_p9;
k->intc_create = pnv_chip_power9_intc_create;
@@ -2091,6 +2095,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
+ k->chip_type = PNV_TYPE_POWER10;
k->cores_mask = POWER10_CORE_MASK;
k->chip_pir = pnv_chip_pir_p10;
k->intc_create = pnv_chip_power10_intc_create;
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 8589f3291ed3..ebfe82b89537 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -17,12 +17,21 @@
OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
PNV_CHIP)
+typedef enum PnvChipType {
+ PNV_TYPE_POWER8E, /* AKA Murano (default) */
+ PNV_TYPE_POWER8, /* AKA Venice */
+ PNV_TYPE_POWER8NVL, /* AKA Naples */
+ PNV_TYPE_POWER9, /* AKA Nimbus */
+ PNV_TYPE_POWER10,
+} PnvChipType;
+
struct PnvChip {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
uint32_t chip_id;
+
uint64_t ram_start;
uint64_t ram_size;
@@ -137,6 +146,7 @@ struct PnvChipClass {
SysBusDeviceClass parent_class;
/*< public >*/
+ PnvChipType chip_type;
uint64_t chip_cfam_id;
uint64_t cores_mask;
uint32_t num_pecs;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type' Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:55 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11 Aditya Gupta
` (6 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
docs/system/ppc/powernv.rst | 9 ++--
hw/ppc/pnv.c | 98 +++++++++++++++++++++++++++++++++++--
hw/ppc/pnv_core.c | 16 +++++-
include/hw/ppc/pnv.h | 5 ++
include/hw/ppc/pnv_chip.h | 10 ++++
5 files changed, 130 insertions(+), 8 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index 09f39658587d..626f2a119521 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -1,5 +1,5 @@
-PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
-==================================================================
+PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
+================================================================================
PowerNV (as Non-Virtualized) is the "bare metal" platform using the
OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
@@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
Supported devices
-----------------
- * Multi processor support for POWER8, POWER8NVL and POWER9.
+ * Multi processor support for POWER8, POWER8NVL, POWER9, POWER10 and Power11.
* XSCOM, serial communication sideband bus to configure chiplets.
* Simple LPC Controller.
* Processor Service Interface (PSI) Controller.
- * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
+ Power11).
* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
* Simple OCC is an on-chip micro-controller used for power management tasks.
* iBT device to handle BMC communication, with the internal BMC simulator
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 74e7908e5ffb..06e272f3bdd3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -431,13 +431,27 @@ static const uint8_t pa_features_31[] = { 74, 0,
static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
{
- static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
+ static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
+ static const char compat_p11[] = "ibm,power11-xscom\0ibm,xscom";
+
+ PnvChipType chip_type = pcc->chip_type;
+ const char *compat;
+ int compat_len;
int i;
+ if (chip_type == PNV_TYPE_POWER11) {
+ compat = compat_p11;
+ compat_len = sizeof(compat_p11);
+ } else {
+ compat = compat_p10;
+ compat_len = sizeof(compat_p10);
+ }
+
pnv_dt_xscom(chip, fdt, 0,
cpu_to_be64(PNV10_XSCOM_BASE(chip)),
cpu_to_be64(PNV10_XSCOM_SIZE),
- compat, sizeof(compat));
+ compat, compat_len);
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
@@ -1288,6 +1302,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
#define POWER10_CORE_MASK (0xffffffffffffffull)
+#define POWER11_CORE_MASK (0xffffffffffffffull)
+
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -1838,6 +1854,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip10);
+ PnvChipClass *chip_class = PNV_CHIP_GET_CLASS(chip);
int i;
chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
@@ -1846,7 +1863,11 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
for (i = 0; i < chip10->nr_quads; i++) {
PnvQuad *eq = &chip10->quads[i];
- pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ if (chip_class->chip_type == PNV_TYPE_POWER11)
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
+ PNV_QUAD_TYPE_NAME("power11"));
+ else
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
PNV_QUAD_TYPE_NAME("power10"));
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
@@ -2116,6 +2137,35 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
&k->parent_realize);
}
+static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvChipClass *k = PNV_CHIP_CLASS(klass);
+
+ static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
+
+ k->chip_cfam_id = 0x120da04900008000ull; /* P11 (with NX) */
+ k->chip_type = PNV_TYPE_POWER11;
+ k->cores_mask = POWER11_CORE_MASK;
+ k->chip_pir = pnv_chip_pir_p10;
+ k->intc_create = pnv_chip_power10_intc_create;
+ k->intc_reset = pnv_chip_power10_intc_reset;
+ k->intc_destroy = pnv_chip_power10_intc_destroy;
+ k->intc_print_info = pnv_chip_power10_intc_print_info;
+ k->isa_create = pnv_chip_power10_isa_create;
+ k->dt_populate = pnv_chip_power10_dt_populate;
+ k->pic_print_info = pnv_chip_power10_pic_print_info;
+ k->xscom_core_base = pnv_chip_power10_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power10_xscom_pcba;
+ dc->desc = "PowerNV Chip POWER11";
+ k->num_pecs = PNV10_CHIP_MAX_PEC;
+ k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
+ k->i2c_ports_per_engine = i2c_ports_per_engine;
+
+ device_class_set_parent_realize(dc, pnv_chip_power10_realize,
+ &k->parent_realize);
+}
+
static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
@@ -2510,6 +2560,22 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
pmc->i2c_init = pnv_rainier_i2c_init;
}
+static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static const char compat[] = "qemu,powernv11\0ibm,powernv";
+
+ /* do power10_class_init as p11 core is same as p10 */
+ pnv_machine_p10_common_class_init(oc, data);
+
+ mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
+
+ pmc->compat = compat;
+ pmc->compat_size = sizeof(compat);
+}
+
static bool pnv_machine_get_hb(Object *obj, Error **errp)
{
PnvMachineState *pnv = PNV_MACHINE(obj);
@@ -2613,7 +2679,23 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
.parent = TYPE_PNV10_CHIP, \
}
+#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
+ { \
+ .name = type, \
+ .class_init = class_initfn, \
+ .parent = TYPE_PNV11_CHIP, \
+ }
+
static const TypeInfo types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("powernv11"),
+ .parent = TYPE_PNV_MACHINE,
+ .class_init = pnv_machine_power11_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
+ },
{
.name = MACHINE_TYPE_NAME("powernv10-rainier"),
.parent = MACHINE_TYPE_NAME("powernv10"),
@@ -2668,6 +2750,16 @@ static const TypeInfo types[] = {
.abstract = true,
},
+ /*
+ * P11 chip and variants
+ */
+ {
+ .name = TYPE_PNV11_CHIP,
+ .parent = TYPE_PNV10_CHIP,
+ .instance_size = sizeof(Pnv11Chip),
+ },
+ DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
+
/*
* P10 chip and variants
*/
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index f40ab721d6fc..4522655793da 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -402,7 +402,16 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
- DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
+ {
+ .parent = TYPE_PNV_CORE,
+ .name = PNV_CORE_TYPE_NAME("power10_v2.0"),
+ .class_init = pnv_core_power10_class_init,
+ .class_base_init = pnv_core_power10_class_init,
+ },
+ {
+ .parent = PNV_CORE_TYPE_NAME("power10_v2.0"),
+ .name = PNV_CORE_TYPE_NAME("power11"),
+ }
};
DEFINE_TYPES(pnv_core_infos)
@@ -633,6 +642,11 @@ static const TypeInfo pnv_quad_infos[] = {
.parent = TYPE_PNV_QUAD,
.name = PNV_QUAD_TYPE_NAME("power10"),
.class_init = pnv_quad_power10_class_init,
+ .class_base_init = pnv_quad_power10_class_init,
+ },
+ {
+ .parent = PNV_QUAD_TYPE_NAME("power10"),
+ .name = PNV_QUAD_TYPE_NAME("power11"),
},
};
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 476b13614640..7c5431500512 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip;
typedef struct Pnv8Chip Pnv8Chip;
typedef struct Pnv9Chip Pnv9Chip;
typedef struct Pnv10Chip Pnv10Chip;
+typedef struct Pnv11Chip Pnv11Chip;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
@@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
+#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11")
+DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11,
+ TYPE_PNV_CHIP_POWER11)
+
PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index ebfe82b89537..e56433676bca 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -23,6 +23,7 @@ typedef enum PnvChipType {
PNV_TYPE_POWER8NVL, /* AKA Naples */
PNV_TYPE_POWER9, /* AKA Nimbus */
PNV_TYPE_POWER10,
+ PNV_TYPE_POWER11,
} PnvChipType;
struct PnvChip {
@@ -141,6 +142,15 @@ struct Pnv10Chip {
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
+#define TYPE_PNV11_CHIP "pnv11-chip"
+DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP,
+ TYPE_PNV11_CHIP)
+
+struct Pnv11Chip {
+ /*< private >*/
+ Pnv10Chip parent_obj;
+};
+
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (2 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 05/10] ppc/pnv: Add a LPC controller " Aditya Gupta
` (5 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_homer.c | 8 ++++++++
include/hw/ppc/pnv_homer.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index f9a203d11d0d..1b0123a6f2ea 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -394,6 +394,13 @@ static const TypeInfo pnv_homer_power10_type_info = {
.parent = TYPE_PNV_HOMER,
.instance_size = sizeof(PnvHomer),
.class_init = pnv_homer_power10_class_init,
+ .class_base_init = pnv_homer_power10_class_init,
+};
+
+static const TypeInfo pnv_homer_power11_type_info = {
+ .name = TYPE_PNV11_HOMER,
+ .parent = TYPE_PNV10_HOMER,
+ .instance_size = sizeof(PnvHomer),
};
static void pnv_homer_realize(DeviceState *dev, Error **errp)
@@ -442,6 +449,7 @@ static void pnv_homer_register_types(void)
type_register_static(&pnv_homer_power8_type_info);
type_register_static(&pnv_homer_power9_type_info);
type_register_static(&pnv_homer_power10_type_info);
+ type_register_static(&pnv_homer_power11_type_info);
}
type_init(pnv_homer_register_types);
diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
index b1c5d498dc55..8f1cc8135937 100644
--- a/include/hw/ppc/pnv_homer.h
+++ b/include/hw/ppc/pnv_homer.h
@@ -35,6 +35,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
#define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
TYPE_PNV10_HOMER)
+#define TYPE_PNV11_HOMER TYPE_PNV_HOMER "-POWER11"
+DECLARE_INSTANCE_CHECKER(PnvHomer, PNV11_HOMER,
+ TYPE_PNV11_HOMER)
struct PnvHomer {
DeviceState parent;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 05/10] ppc/pnv: Add a LPC controller for POWER11
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (3 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11 Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 06/10] ppc/pnv: Add OCC for Power11 Aditya Gupta
` (4 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_lpc.c | 14 ++++++++++++++
include/hw/ppc/pnv_lpc.h | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index d692858bee78..54b366221bc7 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -698,6 +698,19 @@ static const TypeInfo pnv_lpc_power10_info = {
.class_init = pnv_lpc_power10_class_init,
};
+static void pnv_lpc_power11_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV LPC Controller POWER11";
+}
+
+static const TypeInfo pnv_lpc_power11_info = {
+ .name = TYPE_PNV11_LPC,
+ .parent = TYPE_PNV10_LPC,
+ .class_init = pnv_lpc_power11_class_init,
+};
+
static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
@@ -771,6 +784,7 @@ static void pnv_lpc_register_types(void)
type_register_static(&pnv_lpc_power8_info);
type_register_static(&pnv_lpc_power9_info);
type_register_static(&pnv_lpc_power10_info);
+ type_register_static(&pnv_lpc_power11_info);
}
type_init(pnv_lpc_register_types)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index 5d22c4557041..1069bca38dfd 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -41,6 +41,10 @@ DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC,
DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC,
TYPE_PNV10_LPC)
+#define TYPE_PNV11_LPC TYPE_PNV_LPC "-POWER11"
+DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV11_LPC,
+ TYPE_PNV11_LPC)
+
struct PnvLpcController {
DeviceState parent;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 06/10] ppc/pnv: Add OCC for Power11
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (4 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 05/10] ppc/pnv: Add a LPC controller " Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model " Aditya Gupta
` (3 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_occ.c | 14 ++++++++++++++
include/hw/ppc/pnv_occ.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 48123ceae176..4f510419045e 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -262,6 +262,19 @@ static const TypeInfo pnv_occ_power10_type_info = {
.class_init = pnv_occ_power10_class_init,
};
+static void pnv_occ_power11_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV OCC Controller (POWER11)";
+}
+
+static const TypeInfo pnv_occ_power11_type_info = {
+ .name = TYPE_PNV11_OCC,
+ .parent = TYPE_PNV10_OCC,
+ .class_init = pnv_occ_power11_class_init,
+};
+
static void pnv_occ_realize(DeviceState *dev, Error **errp)
{
PnvOCC *occ = PNV_OCC(dev);
@@ -305,6 +318,7 @@ static void pnv_occ_register_types(void)
type_register_static(&pnv_occ_power8_type_info);
type_register_static(&pnv_occ_power9_type_info);
type_register_static(&pnv_occ_power10_type_info);
+ type_register_static(&pnv_occ_power11_type_info);
}
type_init(pnv_occ_register_types);
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index df321244e3b1..7b5e28f13b4f 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -34,6 +34,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
TYPE_PNV9_OCC)
#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
+#define TYPE_PNV11_OCC TYPE_PNV_OCC "-POWER11"
+DECLARE_INSTANCE_CHECKER(PnvOCC, PNV11_OCC, TYPE_PNV11_OCC)
#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model for Power11
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (5 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 06/10] ppc/pnv: Add OCC for Power11 Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 08/10] ppc/pnv: Add SBE " Aditya Gupta
` (2 subsequent siblings)
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_psi.c | 24 ++++++++++++++++++++++++
include/hw/ppc/pnv_psi.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 26460d210deb..1f708b183a87 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -939,6 +939,29 @@ static const TypeInfo pnv_psi_power10_info = {
.name = TYPE_PNV10_PSI,
.parent = TYPE_PNV9_PSI,
.class_init = pnv_psi_power10_class_init,
+ .class_base_init = pnv_psi_power10_class_init,
+};
+
+static void pnv_psi_power11_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
+ static const char compat[] = "ibm,power11-psihb-x\0ibm,psihb-x";
+
+ dc->desc = "PowerNV PSI Controller POWER11";
+
+ /*
+ * ppc->xscom_pbca and ppc->xscom_size will be set up by
+ * pnv_psi_power10_class_init
+ */
+ ppc->compat = compat;
+ ppc->compat_size = sizeof(compat);
+}
+
+static const TypeInfo pnv_psi_power11_info = {
+ .name = TYPE_PNV11_PSI,
+ .parent = TYPE_PNV10_PSI,
+ .class_init = pnv_psi_power11_class_init,
};
static void pnv_psi_class_init(ObjectClass *klass, void *data)
@@ -973,6 +996,7 @@ static void pnv_psi_register_types(void)
type_register_static(&pnv_psi_power8_info);
type_register_static(&pnv_psi_power9_info);
type_register_static(&pnv_psi_power10_info);
+ type_register_static(&pnv_psi_power11_info);
}
type_init(pnv_psi_register_types);
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index 2a6f715350b6..9e1d31779204 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -70,6 +70,8 @@ struct Pnv9Psi {
#define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
+#define TYPE_PNV11_PSI TYPE_PNV_PSI "-POWER11"
+
struct PnvPsiClass {
SysBusDeviceClass parent_class;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 08/10] ppc/pnv: Add SBE model for Power11
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (6 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model " Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 11:00 ` [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv' Aditya Gupta
[not found] ` <20240426110023.733309-11-adityag@linux.ibm.com>
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_sbe.c | 15 +++++++++++++++
include/hw/ppc/pnv_sbe.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index 74cee4eea7ad..a655cc7f8c9e 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -366,6 +366,20 @@ static const TypeInfo pnv_sbe_power10_type_info = {
.name = TYPE_PNV10_SBE,
.parent = TYPE_PNV9_SBE,
.class_init = pnv_sbe_power10_class_init,
+ .class_base_init = pnv_sbe_power10_class_init,
+};
+
+static void pnv_sbe_power11_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV SBE Controller (POWER11)";
+}
+
+static const TypeInfo pnv_sbe_power11_type_info = {
+ .name = TYPE_PNV11_SBE,
+ .parent = TYPE_PNV10_SBE,
+ .class_init = pnv_sbe_power11_class_init,
};
static void pnv_sbe_realize(DeviceState *dev, Error **errp)
@@ -409,6 +423,7 @@ static void pnv_sbe_register_types(void)
type_register_static(&pnv_sbe_type_info);
type_register_static(&pnv_sbe_power9_type_info);
type_register_static(&pnv_sbe_power10_type_info);
+ type_register_static(&pnv_sbe_power11_type_info);
}
type_init(pnv_sbe_register_types);
diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
index b6b378ad14c7..09073a1256d6 100644
--- a/include/hw/ppc/pnv_sbe.h
+++ b/include/hw/ppc/pnv_sbe.h
@@ -29,6 +29,8 @@ OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
DECLARE_INSTANCE_CHECKER(PnvSBE, PNV9_SBE, TYPE_PNV9_SBE)
#define TYPE_PNV10_SBE TYPE_PNV_SBE "-POWER10"
DECLARE_INSTANCE_CHECKER(PnvSBE, PNV10_SBE, TYPE_PNV10_SBE)
+#define TYPE_PNV11_SBE TYPE_PNV_SBE "-POWER11"
+DECLARE_INSTANCE_CHECKER(PnvSBE, PNV11_SBE, TYPE_PNV11_SBE)
struct PnvSBE {
DeviceState xd;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
` (7 preceding siblings ...)
2024-04-26 11:00 ` [PATCH v2 08/10] ppc/pnv: Add SBE " Aditya Gupta
@ 2024-04-26 11:00 ` Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
[not found] ` <20240426110023.733309-11-adityag@linux.ibm.com>
9 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 11:00 UTC (permalink / raw)
To: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Frédéric Barrat, Harsh Prateek Bora
Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
with Power11 being the newest supported Power processor in QEMU.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 06e272f3bdd3..0c5a6bc424af 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2531,8 +2531,6 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
- mc->alias = "powernv";
-
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->dt_power_mgt = pnv_dt_power_mgt;
@@ -2569,6 +2567,8 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
/* do power10_class_init as p11 core is same as p10 */
pnv_machine_p10_common_class_init(oc, data);
+ mc->alias = "powernv";
+
mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d2d1e310a3be..1c3e2da8e9e4 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4698,7 +4698,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->dr_lmb_enabled = true;
smc->update_dt_enabled = true;
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
mc->has_hotpluggable_cpus = true;
mc->nvdimm_supported = true;
smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
--
2.44.0
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type'
2024-04-26 11:00 ` [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type' Aditya Gupta
@ 2024-04-26 14:16 ` Cédric Le Goater
2024-04-26 17:18 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:16 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Introduce 'PnvChipClass::chip_type' to easily get which Power chip is
> it.
> This helps generalise similar codes such as *_dt_populate, and removes
> duplication of code between Power11 and Power10 changes in following
> patches.
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> hw/ppc/pnv.c | 5 +++++
> include/hw/ppc/pnv_chip.h | 10 ++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 6e3a5ccdec76..74e7908e5ffb 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1457,6 +1457,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> PnvChipClass *k = PNV_CHIP_CLASS(klass);
>
> k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
> + k->chip_type = PNV_TYPE_POWER8E;
> k->cores_mask = POWER8E_CORE_MASK;
> k->num_phbs = 3;
> k->chip_pir = pnv_chip_pir_p8;
> @@ -1481,6 +1482,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
> PnvChipClass *k = PNV_CHIP_CLASS(klass);
>
> k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
> + k->chip_type = PNV_TYPE_POWER8;
> k->cores_mask = POWER8_CORE_MASK;
> k->num_phbs = 3;
> k->chip_pir = pnv_chip_pir_p8;
> @@ -1505,6 +1507,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
> PnvChipClass *k = PNV_CHIP_CLASS(klass);
>
> k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
> + k->chip_type = PNV_TYPE_POWER8NVL;
> k->cores_mask = POWER8_CORE_MASK;
> k->num_phbs = 4;
> k->chip_pir = pnv_chip_pir_p8;
> @@ -1779,6 +1782,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2};
>
> k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
> + k->chip_type = PNV_TYPE_POWER9;
> k->cores_mask = POWER9_CORE_MASK;
> k->chip_pir = pnv_chip_pir_p9;
> k->intc_create = pnv_chip_power9_intc_create;
> @@ -2091,6 +2095,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
> static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
>
> k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
> + k->chip_type = PNV_TYPE_POWER10;
> k->cores_mask = POWER10_CORE_MASK;
> k->chip_pir = pnv_chip_pir_p10;
> k->intc_create = pnv_chip_power10_intc_create;
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index 8589f3291ed3..ebfe82b89537 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -17,12 +17,21 @@
> OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
> PNV_CHIP)
>
> +typedef enum PnvChipType {
> + PNV_TYPE_POWER8E, /* AKA Murano (default) */
> + PNV_TYPE_POWER8, /* AKA Venice */
> + PNV_TYPE_POWER8NVL, /* AKA Naples */
> + PNV_TYPE_POWER9, /* AKA Nimbus */
> + PNV_TYPE_POWER10,
> +} PnvChipType;
Nope.
> +
> struct PnvChip {
> /*< private >*/
> SysBusDevice parent_obj;
>
> /*< public >*/
> uint32_t chip_id;
> +
> uint64_t ram_start;
> uint64_t ram_size;
>
> @@ -137,6 +146,7 @@ struct PnvChipClass {
> SysBusDeviceClass parent_class;
>
> /*< public >*/
> + PnvChipType chip_type;
> uint64_t chip_cfam_id;
> uint64_t cores_mask;
> uint32_t num_pecs;
Adding an enum type under PnvChipClass which is a type already
looks wrong. Please find another way. It is possible I am sure.
Thanks,
C.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 11:00 ` [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type Aditya Gupta
@ 2024-04-26 14:27 ` Cédric Le Goater
2024-04-26 17:05 ` Aditya Gupta
2024-04-26 17:12 ` Aditya Gupta
0 siblings, 2 replies; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:27 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
Hello Aditya
On 4/26/24 13:00, Aditya Gupta wrote:
> Add base support for "--cpu power11" in QEMU.
>
> Power11 core is same as Power10, hence reuse functions defined for
> Power10.
Power11 uses the same ISA it seems. What's the value then ?
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> docs/system/ppc/pseries.rst | 6 +--
> hw/ppc/spapr_cpu_core.c | 1 +
I would separate the CPU target code adding support for a new POWER
Processor from the machine code (pseries).
> target/ppc/compat.c | 7 +++
> target/ppc/cpu-models.c | 2 +
> target/ppc/cpu-models.h | 2 +
> target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++
> 6 files changed, 114 insertions(+), 3 deletions(-)
>
> diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
> index a876d897b6e4..3277564b34c2 100644
> --- a/docs/system/ppc/pseries.rst
> +++ b/docs/system/ppc/pseries.rst
> @@ -15,9 +15,9 @@ Supported devices
> =================
>
> * Multi processor support for many Power processors generations: POWER7,
> - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
> - but its state is unknown.
> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
> + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
> + exists, but its state is unknown.
The POWER5+ pseries machine seems functionnal with SLOF
(Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth
to mention (for AIX users) in another patch.
> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
> * vPHB PCIe Host bridge.
> * vscsi and vnet devices, compatible with the same devices available on a
> PowerVM hypervisor with VIOS managing LPARs.
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index e7c9edd033c8..c6e85c031178 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
> DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
> + DEFINE_SPAPR_CPU_CORE_TYPE("power11"),
> #ifdef CONFIG_KVM
> DEFINE_SPAPR_CPU_CORE_TYPE("host"),
> #endif
> diff --git a/target/ppc/compat.c b/target/ppc/compat.c
> index ebef2cccecf3..12dd8ae290ca 100644
> --- a/target/ppc/compat.c
> +++ b/target/ppc/compat.c
> @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
> .pcr_level = PCR_COMPAT_3_10,
> .max_vthreads = 8,
> },
> + { /* POWER11, ISA3.10 */
> + .name = "power11",
> + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS,
> + .pcr = PCR_COMPAT_3_10,
> + .pcr_level = PCR_COMPAT_3_10,
> + .max_vthreads = 8,
> + },
> };
>
> static const CompatInfo *compat_by_pvr(uint32_t pvr)
> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> index f2301b43f78b..1870e69b63df 100644
> --- a/target/ppc/cpu-models.c
> +++ b/target/ppc/cpu-models.c
> @@ -734,6 +734,8 @@
> "POWER9 v2.2")
> POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
> "POWER10 v2.0")
> + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11,
> + "POWER11")
> #endif /* defined (TARGET_PPC64) */
>
> /***************************************************************************/
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> index 0229ef3a9a5c..a1b540c3aa9e 100644
> --- a/target/ppc/cpu-models.h
> +++ b/target/ppc/cpu-models.h
> @@ -354,6 +354,7 @@ enum {
> CPU_POWERPC_POWER10_BASE = 0x00800000,
> CPU_POWERPC_POWER10_DD1 = 0x00801100,
> CPU_POWERPC_POWER10_DD20 = 0x00801200,
> + CPU_POWERPC_POWER11 = 0x00821200,
is that a DD2.2 PVR ? If so, It should be mentionned in the definition.
Thanks,
C.
> CPU_POWERPC_970_v22 = 0x00390202,
> CPU_POWERPC_970FX_v10 = 0x00391100,
> CPU_POWERPC_970FX_v20 = 0x003C0200,
> @@ -391,6 +392,7 @@ enum {
> CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
> CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
> CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
> + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007,
> };
>
> /* System version register (used on MPC 8xxx) */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 6d82f24c8756..17c159c8187b 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> pcc->l1_icache_size = 0x8000;
> }
>
> +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
> +{
> + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
> + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
> +
> + if (!best && (base == CPU_POWERPC_POWER11))
> + return true;
> +
> + if (base != pcc_base)
> + return false;
> +
> + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00))
> + return true;
> +
> + return false;
> +}
> +
> +POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +
> + dc->fw_name = "PowerPC,POWER11";
> + dc->desc = "POWER11";
> + pcc->pvr_match = ppc_pvr_match_power11;
> + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
> + PCR_COMPAT_3_00 | PCR_COMPAT_3_10;
> + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
> + PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> + pcc->init_proc = init_proc_POWER10;
> + pcc->check_pow = check_pow_nocheck;
> + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> + PPC_FLOAT_FRSQRTES |
> + PPC_FLOAT_STFIWX |
> + PPC_FLOAT_EXT |
> + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> + PPC_MEM_SYNC | PPC_MEM_EIEIO |
> + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
> + PPC_SEGMENT_64B | PPC_SLBI |
> + PPC_POPCNTB | PPC_POPCNTWD |
> + PPC_CILDST;
> + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
> + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
> + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
> + pcc->msr_mask = (1ull << MSR_SF) |
> + (1ull << MSR_HV) |
> + (1ull << MSR_TM) |
> + (1ull << MSR_VR) |
> + (1ull << MSR_VSX) |
> + (1ull << MSR_EE) |
> + (1ull << MSR_PR) |
> + (1ull << MSR_FP) |
> + (1ull << MSR_ME) |
> + (1ull << MSR_FE0) |
> + (1ull << MSR_SE) |
> + (1ull << MSR_DE) |
> + (1ull << MSR_FE1) |
> + (1ull << MSR_IR) |
> + (1ull << MSR_DR) |
> + (1ull << MSR_PMM) |
> + (1ull << MSR_RI) |
> + (1ull << MSR_LE);
> + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> + LPCR_DEE | LPCR_OEE))
> + | LPCR_MER | LPCR_GTSE | LPCR_TC |
> + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> + /* DD2 adds an extra HAIL bit */
> + pcc->lpcr_mask |= LPCR_HAIL;
> +
> + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> + pcc->mmu_model = POWERPC_MMU_3_00;
> +#if !defined(CONFIG_USER_ONLY)
> + /* segment page size remain the same */
> + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> + pcc->radix_page_info = &POWER10_radix_page_info;
> + pcc->lrg_decr_bits = 56;
> +#endif
> + pcc->excp_model = POWERPC_EXCP_POWER10;
> + pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
> + pcc->bfd_mach = bfd_mach_ppc64;
> + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> + POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
> + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
> + pcc->l1_dcache_size = 0x8000;
> + pcc->l1_icache_size = 0x8000;
> +}
> +
> #if !defined(CONFIG_USER_ONLY)
> void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
> {
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-26 11:00 ` [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv' Aditya Gupta
@ 2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:40 ` Aditya Gupta
` (2 more replies)
0 siblings, 3 replies; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:32 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Frédéric Barrat, Harsh Prateek Bora
On 4/26/24 13:00, Aditya Gupta wrote:
> Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> with Power11 being the newest supported Power processor in QEMU.
This is too early. We should merge Power11 support first, possibly in 9.1,
and then change default in a future release, 9.2, 10.0
Thanks,
C.
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> hw/ppc/pnv.c | 4 ++--
> hw/ppc/spapr.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 06e272f3bdd3..0c5a6bc424af 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -2531,8 +2531,6 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
>
> - mc->alias = "powernv";
> -
> pmc->compat = compat;
> pmc->compat_size = sizeof(compat);
> pmc->dt_power_mgt = pnv_dt_power_mgt;
> @@ -2569,6 +2567,8 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> /* do power10_class_init as p11 core is same as p10 */
> pnv_machine_p10_common_class_init(oc, data);
>
> + mc->alias = "powernv";
> +
> mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index d2d1e310a3be..1c3e2da8e9e4 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -4698,7 +4698,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
>
> smc->dr_lmb_enabled = true;
> smc->update_dt_enabled = true;
> - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
> mc->has_hotpluggable_cpus = true;
> mc->nvdimm_supported = true;
> smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11
2024-04-26 11:00 ` [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11 Aditya Gupta
@ 2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:32 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10, declare PNV11_HOMER as a child
> class of PNV10_HOMER, so it goes through same class init
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_homer.c | 8 ++++++++
> include/hw/ppc/pnv_homer.h | 3 +++
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
> index f9a203d11d0d..1b0123a6f2ea 100644
> --- a/hw/ppc/pnv_homer.c
> +++ b/hw/ppc/pnv_homer.c
> @@ -394,6 +394,13 @@ static const TypeInfo pnv_homer_power10_type_info = {
> .parent = TYPE_PNV_HOMER,
> .instance_size = sizeof(PnvHomer),
> .class_init = pnv_homer_power10_class_init,
> + .class_base_init = pnv_homer_power10_class_init,
> +};
> +
> +static const TypeInfo pnv_homer_power11_type_info = {
> + .name = TYPE_PNV11_HOMER,
> + .parent = TYPE_PNV10_HOMER,
> + .instance_size = sizeof(PnvHomer),
> };
>
> static void pnv_homer_realize(DeviceState *dev, Error **errp)
> @@ -442,6 +449,7 @@ static void pnv_homer_register_types(void)
> type_register_static(&pnv_homer_power8_type_info);
> type_register_static(&pnv_homer_power9_type_info);
> type_register_static(&pnv_homer_power10_type_info);
> + type_register_static(&pnv_homer_power11_type_info);
> }
>
> type_init(pnv_homer_register_types);
> diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
> index b1c5d498dc55..8f1cc8135937 100644
> --- a/include/hw/ppc/pnv_homer.h
> +++ b/include/hw/ppc/pnv_homer.h
> @@ -35,6 +35,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
> #define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
> DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
> TYPE_PNV10_HOMER)
> +#define TYPE_PNV11_HOMER TYPE_PNV_HOMER "-POWER11"
> +DECLARE_INSTANCE_CHECKER(PnvHomer, PNV11_HOMER,
> + TYPE_PNV11_HOMER)
>
> struct PnvHomer {
> DeviceState parent;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 05/10] ppc/pnv: Add a LPC controller for POWER11
2024-04-26 11:00 ` [PATCH v2 05/10] ppc/pnv: Add a LPC controller " Aditya Gupta
@ 2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:32 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10 core, declare PNV11_LPC as a child
> class of PNV10_LPC, so it goes through same class init
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_lpc.c | 14 ++++++++++++++
> include/hw/ppc/pnv_lpc.h | 4 ++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index d692858bee78..54b366221bc7 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -698,6 +698,19 @@ static const TypeInfo pnv_lpc_power10_info = {
> .class_init = pnv_lpc_power10_class_init,
> };
>
> +static void pnv_lpc_power11_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV LPC Controller POWER11";
> +}
> +
> +static const TypeInfo pnv_lpc_power11_info = {
> + .name = TYPE_PNV11_LPC,
> + .parent = TYPE_PNV10_LPC,
> + .class_init = pnv_lpc_power11_class_init,
> +};
> +
> static void pnv_lpc_realize(DeviceState *dev, Error **errp)
> {
> PnvLpcController *lpc = PNV_LPC(dev);
> @@ -771,6 +784,7 @@ static void pnv_lpc_register_types(void)
> type_register_static(&pnv_lpc_power8_info);
> type_register_static(&pnv_lpc_power9_info);
> type_register_static(&pnv_lpc_power10_info);
> + type_register_static(&pnv_lpc_power11_info);
> }
>
> type_init(pnv_lpc_register_types)
> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
> index 5d22c4557041..1069bca38dfd 100644
> --- a/include/hw/ppc/pnv_lpc.h
> +++ b/include/hw/ppc/pnv_lpc.h
> @@ -41,6 +41,10 @@ DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC,
> DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC,
> TYPE_PNV10_LPC)
>
> +#define TYPE_PNV11_LPC TYPE_PNV_LPC "-POWER11"
> +DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV11_LPC,
> + TYPE_PNV11_LPC)
> +
> struct PnvLpcController {
> DeviceState parent;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 06/10] ppc/pnv: Add OCC for Power11
2024-04-26 11:00 ` [PATCH v2 06/10] ppc/pnv: Add OCC for Power11 Aditya Gupta
@ 2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:33 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10, reuse PNV10_OCC initialisation,
> by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> hw/ppc/pnv_occ.c | 14 ++++++++++++++
> include/hw/ppc/pnv_occ.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 48123ceae176..4f510419045e 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -262,6 +262,19 @@ static const TypeInfo pnv_occ_power10_type_info = {
> .class_init = pnv_occ_power10_class_init,
> };
>
> +static void pnv_occ_power11_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV OCC Controller (POWER11)";
> +}
> +
> +static const TypeInfo pnv_occ_power11_type_info = {
> + .name = TYPE_PNV11_OCC,
> + .parent = TYPE_PNV10_OCC,
> + .class_init = pnv_occ_power11_class_init,
> +};
> +
> static void pnv_occ_realize(DeviceState *dev, Error **errp)
> {
> PnvOCC *occ = PNV_OCC(dev);
> @@ -305,6 +318,7 @@ static void pnv_occ_register_types(void)
> type_register_static(&pnv_occ_power8_type_info);
> type_register_static(&pnv_occ_power9_type_info);
> type_register_static(&pnv_occ_power10_type_info);
> + type_register_static(&pnv_occ_power11_type_info);
> }
>
> type_init(pnv_occ_register_types);
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index df321244e3b1..7b5e28f13b4f 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -34,6 +34,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
> TYPE_PNV9_OCC)
> #define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
> DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
> +#define TYPE_PNV11_OCC TYPE_PNV_OCC "-POWER11"
> +DECLARE_INSTANCE_CHECKER(PnvOCC, PNV11_OCC, TYPE_PNV11_OCC)
>
> #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
> #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model for Power11
2024-04-26 11:00 ` [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model " Aditya Gupta
@ 2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:39 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:33 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
> declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_psi.c | 24 ++++++++++++++++++++++++
> include/hw/ppc/pnv_psi.h | 2 ++
> 2 files changed, 26 insertions(+)
>
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 26460d210deb..1f708b183a87 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -939,6 +939,29 @@ static const TypeInfo pnv_psi_power10_info = {
> .name = TYPE_PNV10_PSI,
> .parent = TYPE_PNV9_PSI,
> .class_init = pnv_psi_power10_class_init,
> + .class_base_init = pnv_psi_power10_class_init,
> +};
> +
> +static void pnv_psi_power11_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
> + static const char compat[] = "ibm,power11-psihb-x\0ibm,psihb-x";
> +
> + dc->desc = "PowerNV PSI Controller POWER11";
> +
> + /*
> + * ppc->xscom_pbca and ppc->xscom_size will be set up by
> + * pnv_psi_power10_class_init
> + */
> + ppc->compat = compat;
> + ppc->compat_size = sizeof(compat);
> +}
> +
> +static const TypeInfo pnv_psi_power11_info = {
> + .name = TYPE_PNV11_PSI,
> + .parent = TYPE_PNV10_PSI,
> + .class_init = pnv_psi_power11_class_init,
> };
>
> static void pnv_psi_class_init(ObjectClass *klass, void *data)
> @@ -973,6 +996,7 @@ static void pnv_psi_register_types(void)
> type_register_static(&pnv_psi_power8_info);
> type_register_static(&pnv_psi_power9_info);
> type_register_static(&pnv_psi_power10_info);
> + type_register_static(&pnv_psi_power11_info);
> }
>
> type_init(pnv_psi_register_types);
> diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
> index 2a6f715350b6..9e1d31779204 100644
> --- a/include/hw/ppc/pnv_psi.h
> +++ b/include/hw/ppc/pnv_psi.h
> @@ -70,6 +70,8 @@ struct Pnv9Psi {
>
> #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
>
> +#define TYPE_PNV11_PSI TYPE_PNV_PSI "-POWER11"
> +
>
> struct PnvPsiClass {
> SysBusDeviceClass parent_class;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 08/10] ppc/pnv: Add SBE model for Power11
2024-04-26 11:00 ` [PATCH v2 08/10] ppc/pnv: Add SBE " Aditya Gupta
@ 2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:39 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:33 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
> declaring PNV11_PSI as child class of PNV10_PSI
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/pnv_sbe.c | 15 +++++++++++++++
> include/hw/ppc/pnv_sbe.h | 2 ++
> 2 files changed, 17 insertions(+)
>
> diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
> index 74cee4eea7ad..a655cc7f8c9e 100644
> --- a/hw/ppc/pnv_sbe.c
> +++ b/hw/ppc/pnv_sbe.c
> @@ -366,6 +366,20 @@ static const TypeInfo pnv_sbe_power10_type_info = {
> .name = TYPE_PNV10_SBE,
> .parent = TYPE_PNV9_SBE,
> .class_init = pnv_sbe_power10_class_init,
> + .class_base_init = pnv_sbe_power10_class_init,
> +};
> +
> +static void pnv_sbe_power11_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV SBE Controller (POWER11)";
> +}
> +
> +static const TypeInfo pnv_sbe_power11_type_info = {
> + .name = TYPE_PNV11_SBE,
> + .parent = TYPE_PNV10_SBE,
> + .class_init = pnv_sbe_power11_class_init,
> };
>
> static void pnv_sbe_realize(DeviceState *dev, Error **errp)
> @@ -409,6 +423,7 @@ static void pnv_sbe_register_types(void)
> type_register_static(&pnv_sbe_type_info);
> type_register_static(&pnv_sbe_power9_type_info);
> type_register_static(&pnv_sbe_power10_type_info);
> + type_register_static(&pnv_sbe_power11_type_info);
> }
>
> type_init(pnv_sbe_register_types);
> diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
> index b6b378ad14c7..09073a1256d6 100644
> --- a/include/hw/ppc/pnv_sbe.h
> +++ b/include/hw/ppc/pnv_sbe.h
> @@ -29,6 +29,8 @@ OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
> DECLARE_INSTANCE_CHECKER(PnvSBE, PNV9_SBE, TYPE_PNV9_SBE)
> #define TYPE_PNV10_SBE TYPE_PNV_SBE "-POWER10"
> DECLARE_INSTANCE_CHECKER(PnvSBE, PNV10_SBE, TYPE_PNV10_SBE)
> +#define TYPE_PNV11_SBE TYPE_PNV_SBE "-POWER11"
> +DECLARE_INSTANCE_CHECKER(PnvSBE, PNV11_SBE, TYPE_PNV11_SBE)
>
> struct PnvSBE {
> DeviceState xd;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 10/10] ppc/pnv: Update skiboot.lid to support Power11
[not found] ` <20240426110023.733309-11-adityag@linux.ibm.com>
@ 2024-04-26 14:38 ` Cédric Le Goater
2024-04-26 17:42 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:38 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Joel Stanley
On 4/26/24 13:00, Aditya Gupta wrote:
> Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> commits in github repository [2].
>
> Update skiboot.lid, with binary built from 'upstream_power11' branch
> of skiboot repository with Power11 enablement patches [2].
>
> ---
> This patch can be skipped for now, if need to wait for patches to be
> merged in open-power/skiboot.
yes.
> Have updated the skiboot.lid to aid in testing this patch series.
Thanks for doing so.
> ---
>
> [1]:https://lists.ozlabs.org/pipermail/skiboot/2024-April/018963.html
> [2]:https://github.com/maheshsal/skiboot.
>
> Cc: Cédric Le Goater<clg@kaod.org>
> Cc: Joel Stanley<joel@jms.id.au>
> Cc: Mahesh J Salgaonkar<mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan<maddy@linux.ibm.com>
> Cc: Nicholas Piggin<npiggin@gmail.com>
> Signed-off-by: Aditya Gupta<adityag@linux.ibm.com>
> ---
> pc-bios/skiboot.lid | Bin 2527328 -> 2527328 bytes
> 1 file changed, 0 insertions(+), 0 deletions(-)
We avoid sending such big blobs on the mailing list. We usually send a
PR to the sub-system maintainer (Nick). When time comes (support is
merged is skiboot), we will address the skiboot image update in QEMU.
C.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
2024-04-26 11:00 ` [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Aditya Gupta
@ 2024-04-26 14:55 ` Cédric Le Goater
2024-04-26 17:34 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 14:55 UTC (permalink / raw)
To: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin
Cc: qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 13:00, Aditya Gupta wrote:
> Power11 core is same as Power10, use the existing functionalities to
> introduce a Power11 chip and machine, with Power10 chip as parent of
> Power11 chip, thus going through similar class_init paths
>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> docs/system/ppc/powernv.rst | 9 ++--
> hw/ppc/pnv.c | 98 +++++++++++++++++++++++++++++++++++--
> hw/ppc/pnv_core.c | 16 +++++-
> include/hw/ppc/pnv.h | 5 ++
> include/hw/ppc/pnv_chip.h | 10 ++++
> 5 files changed, 130 insertions(+), 8 deletions(-)
>
> diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
> index 09f39658587d..626f2a119521 100644
> --- a/docs/system/ppc/powernv.rst
> +++ b/docs/system/ppc/powernv.rst
> @@ -1,5 +1,5 @@
> -PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
> -==================================================================
> +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
> +================================================================================
>
> PowerNV (as Non-Virtualized) is the "bare metal" platform using the
> OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
> @@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
> Supported devices
> -----------------
>
> - * Multi processor support for POWER8, POWER8NVL and POWER9.
> + * Multi processor support for POWER8, POWER8NVL, POWER9, POWER10 and Power11.
POWER10 -> Power10. Don't ask me why.
> * XSCOM, serial communication sideband bus to configure chiplets.
> * Simple LPC Controller.
> * Processor Service Interface (PSI) Controller.
> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
> + Power11).
> * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
> * Simple OCC is an on-chip micro-controller used for power management tasks.
> * iBT device to handle BMC communication, with the internal BMC simulator
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 74e7908e5ffb..06e272f3bdd3 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -431,13 +431,27 @@ static const uint8_t pa_features_31[] = { 74, 0,
>
> static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> {
> - static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> + static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
> + static const char compat_p11[] = "ibm,power11-xscom\0ibm,xscom";
> +
> + PnvChipType chip_type = pcc->chip_type;
> + const char *compat;
> + int compat_len;
> int i;
>
> + if (chip_type == PNV_TYPE_POWER11) {
> + compat = compat_p11;
> + compat_len = sizeof(compat_p11);
> + } else {
> + compat = compat_p10;
> + compat_len = sizeof(compat_p10);
> + }
please introduce a pnv_chip_power11_dt_populate() routine instead.
> pnv_dt_xscom(chip, fdt, 0,
> cpu_to_be64(PNV10_XSCOM_BASE(chip)),
> cpu_to_be64(PNV10_XSCOM_SIZE),
> - compat, sizeof(compat));
> + compat, compat_len);
>
> for (i = 0; i < chip->nr_cores; i++) {
> PnvCore *pnv_core = chip->cores[i];
> @@ -1288,6 +1302,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
>
> #define POWER10_CORE_MASK (0xffffffffffffffull)
>
> +#define POWER11_CORE_MASK (0xffffffffffffffull)
> +
> static void pnv_chip_power8_instance_init(Object *obj)
> {
> Pnv8Chip *chip8 = PNV8_CHIP(obj);
> @@ -1838,6 +1854,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
> static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> {
> PnvChip *chip = PNV_CHIP(chip10);
> + PnvChipClass *chip_class = PNV_CHIP_GET_CLASS(chip);
> int i;
>
> chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
> @@ -1846,7 +1863,11 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> for (i = 0; i < chip10->nr_quads; i++) {
> PnvQuad *eq = &chip10->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + if (chip_class->chip_type == PNV_TYPE_POWER11)
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power11"));
> + else
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> PNV_QUAD_TYPE_NAME("power10"));
Please change introduce a new pnv_chip_quad_realize() routine taking an
extra type_name argument.
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> @@ -2116,6 +2137,35 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
> &k->parent_realize);
> }
>
> +static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PnvChipClass *k = PNV_CHIP_CLASS(klass);
> +
> + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
> +
> + k->chip_cfam_id = 0x120da04900008000ull; /* P11 (with NX) */
> + k->chip_type = PNV_TYPE_POWER11;
> + k->cores_mask = POWER11_CORE_MASK;
> + k->chip_pir = pnv_chip_pir_p10;
> + k->intc_create = pnv_chip_power10_intc_create;
> + k->intc_reset = pnv_chip_power10_intc_reset;
> + k->intc_destroy = pnv_chip_power10_intc_destroy;
> + k->intc_print_info = pnv_chip_power10_intc_print_info;
> + k->isa_create = pnv_chip_power10_isa_create;
> + k->dt_populate = pnv_chip_power10_dt_populate;
> + k->pic_print_info = pnv_chip_power10_pic_print_info;
> + k->xscom_core_base = pnv_chip_power10_xscom_core_base;
> + k->xscom_pcba = pnv_chip_power10_xscom_pcba;
> + dc->desc = "PowerNV Chip POWER11";
> + k->num_pecs = PNV10_CHIP_MAX_PEC;
> + k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
> + k->i2c_ports_per_engine = i2c_ports_per_engine;
> +
> + device_class_set_parent_realize(dc, pnv_chip_power10_realize,
> + &k->parent_realize);
> +}
> +
> static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
> {
> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> @@ -2510,6 +2560,22 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
> pmc->i2c_init = pnv_rainier_i2c_init;
> }
>
> +static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> + static const char compat[] = "qemu,powernv11\0ibm,powernv";
> +
> + /* do power10_class_init as p11 core is same as p10 */
> + pnv_machine_p10_common_class_init(oc, data);
> +
> + mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
This should be using a versionned CPU "power11_vx.y".
> +
> + pmc->compat = compat;
> + pmc->compat_size = sizeof(compat);
> +}
> +
> static bool pnv_machine_get_hb(Object *obj, Error **errp)
> {
> PnvMachineState *pnv = PNV_MACHINE(obj);
> @@ -2613,7 +2679,23 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
> .parent = TYPE_PNV10_CHIP, \
> }
>
> +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
> + { \
> + .name = type, \
> + .class_init = class_initfn, \
> + .parent = TYPE_PNV11_CHIP, \
> + }
> +
> static const TypeInfo types[] = {
> + {
> + .name = MACHINE_TYPE_NAME("powernv11"),
> + .parent = TYPE_PNV_MACHINE,
> + .class_init = pnv_machine_power11_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_XIVE_FABRIC },
> + { },
> + },
> + },
> {
> .name = MACHINE_TYPE_NAME("powernv10-rainier"),
> .parent = MACHINE_TYPE_NAME("powernv10"),
> @@ -2668,6 +2750,16 @@ static const TypeInfo types[] = {
> .abstract = true,
> },
>
> + /*
> + * P11 chip and variants
> + */
> + {
> + .name = TYPE_PNV11_CHIP,
> + .parent = TYPE_PNV10_CHIP,
> + .instance_size = sizeof(Pnv11Chip),
> + },
> + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
> +
> /*
> * P10 chip and variants
> */
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index f40ab721d6fc..4522655793da 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -402,7 +402,16 @@ static const TypeInfo pnv_core_infos[] = {
> DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
> DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
> DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
> - DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
> + {
> + .parent = TYPE_PNV_CORE,
> + .name = PNV_CORE_TYPE_NAME("power10_v2.0"),
> + .class_init = pnv_core_power10_class_init,
> + .class_base_init = pnv_core_power10_class_init,
> + },
hmm, what is this change ?
> + {
> + .parent = PNV_CORE_TYPE_NAME("power10_v2.0"),
> + .name = PNV_CORE_TYPE_NAME("power11"),
> + }
nope. please use DEFINE_PNV_CORE_TYPE()
> };
>
> DEFINE_TYPES(pnv_core_infos)
> @@ -633,6 +642,11 @@ static const TypeInfo pnv_quad_infos[] = {
> .parent = TYPE_PNV_QUAD,
> .name = PNV_QUAD_TYPE_NAME("power10"),
> .class_init = pnv_quad_power10_class_init,
> + .class_base_init = pnv_quad_power10_class_init,
> + },
> + {
> + .parent = PNV_QUAD_TYPE_NAME("power10"),
> + .name = PNV_QUAD_TYPE_NAME("power11"),
hmm, I'd rather introduce pnv_quad_power11_class_init.
> },
> };
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 476b13614640..7c5431500512 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -33,6 +33,7 @@ typedef struct PnvChip PnvChip;
> typedef struct Pnv8Chip Pnv8Chip;
> typedef struct Pnv9Chip Pnv9Chip;
> typedef struct Pnv10Chip Pnv10Chip;
> +typedef struct Pnv11Chip Pnv11Chip;
>
> #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
> #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
> @@ -57,6 +58,10 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
> DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
> TYPE_PNV_CHIP_POWER10)
>
> +#define TYPE_PNV_CHIP_POWER11 PNV_CHIP_TYPE_NAME("power11")
> +DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER11,
> + TYPE_PNV_CHIP_POWER11)
> +
> PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
>
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index ebfe82b89537..e56433676bca 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -23,6 +23,7 @@ typedef enum PnvChipType {
> PNV_TYPE_POWER8NVL, /* AKA Naples */
> PNV_TYPE_POWER9, /* AKA Nimbus */
> PNV_TYPE_POWER10,
> + PNV_TYPE_POWER11,
> } PnvChipType;
>
> struct PnvChip {
> @@ -141,6 +142,15 @@ struct Pnv10Chip {
> #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
>
> +#define TYPE_PNV11_CHIP "pnv11-chip"
> +DECLARE_INSTANCE_CHECKER(Pnv11Chip, PNV11_CHIP,
> + TYPE_PNV11_CHIP)
> +
> +struct Pnv11Chip {
> + /*< private >*/
> + Pnv10Chip parent_obj;
Can't you use a typedef instead ?
Thanks,
C.
> +};
> +
> struct PnvChipClass {
> /*< private >*/
> SysBusDeviceClass parent_class;
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 14:27 ` Cédric Le Goater
@ 2024-04-26 17:05 ` Aditya Gupta
2024-04-26 17:41 ` Cédric Le Goater
2024-04-26 17:12 ` Aditya Gupta
1 sibling, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:05 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
Hello Cédric,
Thanks for your reviews.
On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote:
> Hello Aditya
>
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Add base support for "--cpu power11" in QEMU.
> >
> > Power11 core is same as Power10, hence reuse functions defined for
> > Power10.
>
> Power11 uses the same ISA it seems. What's the value then ?
Yes, it uses the same ISA. But I added this option so we can have a
Power11 PVR in QEMU, which should be identified as Power11 in skiboot
and linux, hence defined Power11 cpu type, even though code here is
almost same as Power10.
>
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> > Cc: David Gibson <david@gibson.dropbear.id.au>
> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> > ---
> > docs/system/ppc/pseries.rst | 6 +--
> > hw/ppc/spapr_cpu_core.c | 1 +
>
>
> I would separate the CPU target code adding support for a new POWER
> Processor from the machine code (pseries).
Sure, I will split it in v3.
>
>
> > target/ppc/compat.c | 7 +++
> > target/ppc/cpu-models.c | 2 +
> > target/ppc/cpu-models.h | 2 +
> > target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++
> > 6 files changed, 114 insertions(+), 3 deletions(-)
> >
> > diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
> > index a876d897b6e4..3277564b34c2 100644
> > --- a/docs/system/ppc/pseries.rst
> > +++ b/docs/system/ppc/pseries.rst
> > @@ -15,9 +15,9 @@ Supported devices
> > =================
> > * Multi processor support for many Power processors generations: POWER7,
> > - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
> > - but its state is unknown.
> > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
> > + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
> > + exists, but its state is unknown.
>
> The POWER5+ pseries machine seems functionnal with SLOF
> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth
> to mention (for AIX users) in another patch.
>
> > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
> > * vPHB PCIe Host bridge.
> > * vscsi and vnet devices, compatible with the same devices available on a
> > PowerVM hypervisor with VIOS managing LPARs.
> > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> > index e7c9edd033c8..c6e85c031178 100644
> > --- a/hw/ppc/spapr_cpu_core.c
> > +++ b/hw/ppc/spapr_cpu_core.c
> > @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
> > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
> > DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
> > DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
> > + DEFINE_SPAPR_CPU_CORE_TYPE("power11"),
> > #ifdef CONFIG_KVM
> > DEFINE_SPAPR_CPU_CORE_TYPE("host"),
> > #endif
> > diff --git a/target/ppc/compat.c b/target/ppc/compat.c
> > index ebef2cccecf3..12dd8ae290ca 100644
> > --- a/target/ppc/compat.c
> > +++ b/target/ppc/compat.c
> > @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
> > .pcr_level = PCR_COMPAT_3_10,
> > .max_vthreads = 8,
> > },
> > + { /* POWER11, ISA3.10 */
> > + .name = "power11",
> > + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS,
> > + .pcr = PCR_COMPAT_3_10,
> > + .pcr_level = PCR_COMPAT_3_10,
> > + .max_vthreads = 8,
> > + },
> > };
> > static const CompatInfo *compat_by_pvr(uint32_t pvr)
> > diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
> > index f2301b43f78b..1870e69b63df 100644
> > --- a/target/ppc/cpu-models.c
> > +++ b/target/ppc/cpu-models.c
> > @@ -734,6 +734,8 @@
> > "POWER9 v2.2")
> > POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
> > "POWER10 v2.0")
> > + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11,
> > + "POWER11")
> > #endif /* defined (TARGET_PPC64) */
> > /***************************************************************************/
> > diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
> > index 0229ef3a9a5c..a1b540c3aa9e 100644
> > --- a/target/ppc/cpu-models.h
> > +++ b/target/ppc/cpu-models.h
> > @@ -354,6 +354,7 @@ enum {
> > CPU_POWERPC_POWER10_BASE = 0x00800000,
> > CPU_POWERPC_POWER10_DD1 = 0x00801100,
> > CPU_POWERPC_POWER10_DD20 = 0x00801200,
> > + CPU_POWERPC_POWER11 = 0x00821200,
>
> is that a DD2.2 PVR ? If so, It should be mentionned in the definition.
>
Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it
above the line I have added it, in v3.
Thanks,
Aditya Gupta
>
>
> Thanks,
>
> C.
>
>
>
> > CPU_POWERPC_970_v22 = 0x00390202,
> > CPU_POWERPC_970FX_v10 = 0x00391100,
> > CPU_POWERPC_970FX_v20 = 0x003C0200,
> > @@ -391,6 +392,7 @@ enum {
> > CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
> > CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
> > CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
> > + CPU_POWERPC_LOGICAL_3_10_PLUS = 0x0F000007,
> > };
> > /* System version register (used on MPC 8xxx) */
> > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> > index 6d82f24c8756..17c159c8187b 100644
> > --- a/target/ppc/cpu_init.c
> > +++ b/target/ppc/cpu_init.c
> > @@ -6655,6 +6655,105 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> > pcc->l1_icache_size = 0x8000;
> > }
> > +static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
> > +{
> > + uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
> > + uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
> > +
> > + if (!best && (base == CPU_POWERPC_POWER11))
> > + return true;
> > +
> > + if (base != pcc_base)
> > + return false;
> > +
> > + if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00))
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > +POWERPC_FAMILY(POWER11)(ObjectClass * oc, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(oc);
> > + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> > +
> > + dc->fw_name = "PowerPC,POWER11";
> > + dc->desc = "POWER11";
> > + pcc->pvr_match = ppc_pvr_match_power11;
> > + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
> > + PCR_COMPAT_3_00 | PCR_COMPAT_3_10;
> > + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
> > + PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
> > + pcc->init_proc = init_proc_POWER10;
> > + pcc->check_pow = check_pow_nocheck;
> > + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> > + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> > + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> > + PPC_FLOAT_FRSQRTES |
> > + PPC_FLOAT_STFIWX |
> > + PPC_FLOAT_EXT |
> > + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> > + PPC_MEM_SYNC | PPC_MEM_EIEIO |
> > + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> > + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
> > + PPC_SEGMENT_64B | PPC_SLBI |
> > + PPC_POPCNTB | PPC_POPCNTWD |
> > + PPC_CILDST;
> > + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
> > + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
> > + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
> > + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> > + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> > + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> > + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
> > + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
> > + pcc->msr_mask = (1ull << MSR_SF) |
> > + (1ull << MSR_HV) |
> > + (1ull << MSR_TM) |
> > + (1ull << MSR_VR) |
> > + (1ull << MSR_VSX) |
> > + (1ull << MSR_EE) |
> > + (1ull << MSR_PR) |
> > + (1ull << MSR_FP) |
> > + (1ull << MSR_ME) |
> > + (1ull << MSR_FE0) |
> > + (1ull << MSR_SE) |
> > + (1ull << MSR_DE) |
> > + (1ull << MSR_FE1) |
> > + (1ull << MSR_IR) |
> > + (1ull << MSR_DR) |
> > + (1ull << MSR_PMM) |
> > + (1ull << MSR_RI) |
> > + (1ull << MSR_LE);
> > + pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> > + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> > + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
> > + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> > + LPCR_DEE | LPCR_OEE))
> > + | LPCR_MER | LPCR_GTSE | LPCR_TC |
> > + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
> > + /* DD2 adds an extra HAIL bit */
> > + pcc->lpcr_mask |= LPCR_HAIL;
> > +
> > + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
> > + pcc->mmu_model = POWERPC_MMU_3_00;
> > +#if !defined(CONFIG_USER_ONLY)
> > + /* segment page size remain the same */
> > + pcc->hash64_opts = &ppc_hash64_opts_POWER7;
> > + pcc->radix_page_info = &POWER10_radix_page_info;
> > + pcc->lrg_decr_bits = 56;
> > +#endif
> > + pcc->excp_model = POWERPC_EXCP_POWER10;
> > + pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
> > + pcc->bfd_mach = bfd_mach_ppc64;
> > + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> > + POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> > + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
> > + POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
> > + pcc->l1_dcache_size = 0x8000;
> > + pcc->l1_icache_size = 0x8000;
> > +}
> > +
> > #if !defined(CONFIG_USER_ONLY)
> > void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
> > {
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 14:27 ` Cédric Le Goater
2024-04-26 17:05 ` Aditya Gupta
@ 2024-04-26 17:12 ` Aditya Gupta
2024-04-26 17:28 ` Cédric Le Goater
1 sibling, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:12 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
Hello Cédric,
> > diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
> > index a876d897b6e4..3277564b34c2 100644
> > --- a/docs/system/ppc/pseries.rst
> > +++ b/docs/system/ppc/pseries.rst
> > @@ -15,9 +15,9 @@ Supported devices
> > =================
> > * Multi processor support for many Power processors generations: POWER7,
> > - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
> > - but its state is unknown.
> > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
> > + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
> > + exists, but its state is unknown.
>
> The POWER5+ pseries machine seems functionnal with SLOF
> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth
> to mention (for AIX users) in another patch.
Sure, thanks for pointing this, will add these changes in a separate
patch.
There were some points in 'powernv' docs, that might need updating:
Quoting lines from docs/system/ppc/powernv.rst:
> Missing devices
> ---------------
>
> A lot is missing, among which :
>
> * I2C controllers (yet to be merged).
> * NPU/NPU2/NPU3 controllers.
> * EEH support for PCIe Host bridge controllers.
> * NX controller.
> * VAS controller.
> * chipTOD (Time Of Day).
> * Self Boot Engine (SBE).
> * FSI bus.
I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
yet to merge, is it merged yet ?
I will check whether this needs updating, but might do it in a separate
patch than this series.
Thanks,
- Aditya Gupta
>
> > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
> > * vPHB PCIe Host bridge.
> > * vscsi and vnet devices, compatible with the same devices available on a
> > PowerVM hypervisor with VIOS managing LPARs.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type'
2024-04-26 14:16 ` Cédric Le Goater
@ 2024-04-26 17:18 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:18 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
Hello Cédric,
> >
> > <...snip...>
> >
> > diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> > index 8589f3291ed3..ebfe82b89537 100644
> > --- a/include/hw/ppc/pnv_chip.h
> > +++ b/include/hw/ppc/pnv_chip.h
> > @@ -17,12 +17,21 @@
> > OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
> > PNV_CHIP)
> > +typedef enum PnvChipType {
> > + PNV_TYPE_POWER8E, /* AKA Murano (default) */
> > + PNV_TYPE_POWER8, /* AKA Venice */
> > + PNV_TYPE_POWER8NVL, /* AKA Naples */
> > + PNV_TYPE_POWER9, /* AKA Nimbus */
> > + PNV_TYPE_POWER10,
> > +} PnvChipType;
>
> Nope.
>
> > +
> > struct PnvChip {
> > /*< private >*/
> > SysBusDevice parent_obj;
> > /*< public >*/
> > uint32_t chip_id;
> > +
> > uint64_t ram_start;
> > uint64_t ram_size;
> > @@ -137,6 +146,7 @@ struct PnvChipClass {
> > SysBusDeviceClass parent_class;
> > /*< public >*/
> > + PnvChipType chip_type;
> > uint64_t chip_cfam_id;
> > uint64_t cores_mask;
> > uint32_t num_pecs;
>
> Adding an enum type under PnvChipClass which is a type already
> looks wrong. Please find another way. It is possible I am sure.
True. You suggested one possible way in patch #3, to replicate the
*_dt_populate and quad_realize functions for Power11 also.
Another way to do this was depending on the type string in qemu
object's class type name, or object_cast_cache, but I decided not to go
with string comparison or depending on internal strings.
Will use your suggestion in patch #3.
Thanks,
Aditya Gupta
>
> Thanks,
>
> C.
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 17:12 ` Aditya Gupta
@ 2024-04-26 17:28 ` Cédric Le Goater
2024-04-26 17:44 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 17:28 UTC (permalink / raw)
To: Aditya Gupta
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
On 4/26/24 19:12, Aditya Gupta wrote:
> Hello Cédric,
>
>>> diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
>>> index a876d897b6e4..3277564b34c2 100644
>>> --- a/docs/system/ppc/pseries.rst
>>> +++ b/docs/system/ppc/pseries.rst
>>> @@ -15,9 +15,9 @@ Supported devices
>>> =================
>>> * Multi processor support for many Power processors generations: POWER7,
>>> - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
>>> - but its state is unknown.
>>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
>>> + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
>>> + exists, but its state is unknown.
>>
>> The POWER5+ pseries machine seems functionnal with SLOF
>> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth
>> to mention (for AIX users) in another patch.
>
> Sure, thanks for pointing this, will add these changes in a separate
> patch.
>
> There were some points in 'powernv' docs, that might need updating:
>
> Quoting lines from docs/system/ppc/powernv.rst:
>
>> Missing devices
>> ---------------
>>
>> A lot is missing, among which :
>>
>> * I2C controllers (yet to be merged).
>> * NPU/NPU2/NPU3 controllers.
>> * EEH support for PCIe Host bridge controllers.
>> * NX controller.
>> * VAS controller.
>> * chipTOD (Time Of Day).
>> * Self Boot Engine (SBE).
>> * FSI bus.
>
> I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
> yet to merge, is it merged yet ?
yes.
>
> I will check whether this needs updating, but might do it in a separate
> patch than this series.
Thanks,
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
2024-04-26 14:55 ` Cédric Le Goater
@ 2024-04-26 17:34 ` Aditya Gupta
2024-04-26 17:53 ` Cédric Le Goater
0 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:34 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
Hello Cédric,
> >
> > <...snip...>
> >
> > - * Multi processor support for POWER8, POWER8NVL and POWER9.
> > + * Multi processor support for POWER8, POWER8NVL, POWER9, POWER10 and Power11.
>
> POWER10 -> Power10. Don't ask me why.
Sure, got it !
>
> > * XSCOM, serial communication sideband bus to configure chiplets.
> > * Simple LPC Controller.
> > * Processor Service Interface (PSI) Controller.
> > - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
> > + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
> > + Power11).
> > * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
> > * Simple OCC is an on-chip micro-controller used for power management tasks.
> > * iBT device to handle BMC communication, with the internal BMC simulator
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 74e7908e5ffb..06e272f3bdd3 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -431,13 +431,27 @@ static const uint8_t pa_features_31[] = { 74, 0,
> > static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> > {
> > - static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
> > + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> > + static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
> > + static const char compat_p11[] = "ibm,power11-xscom\0ibm,xscom";
> > +
> > + PnvChipType chip_type = pcc->chip_type;
> > + const char *compat;
> > + int compat_len;
> > int i;
> > + if (chip_type == PNV_TYPE_POWER11) {
> > + compat = compat_p11;
> > + compat_len = sizeof(compat_p11);
> > + } else {
> > + compat = compat_p10;
> > + compat_len = sizeof(compat_p10);
> > + }
>
> please introduce a pnv_chip_power11_dt_populate() routine instead.
Okay.
>
> > pnv_dt_xscom(chip, fdt, 0,
> > cpu_to_be64(PNV10_XSCOM_BASE(chip)),
> > cpu_to_be64(PNV10_XSCOM_SIZE),
> > - compat, sizeof(compat));
> > + compat, compat_len);
> > for (i = 0; i < chip->nr_cores; i++) {
> > PnvCore *pnv_core = chip->cores[i];
> > @@ -1288,6 +1302,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
> > #define POWER10_CORE_MASK (0xffffffffffffffull)
> > +#define POWER11_CORE_MASK (0xffffffffffffffull)
> > +
> > static void pnv_chip_power8_instance_init(Object *obj)
> > {
> > Pnv8Chip *chip8 = PNV8_CHIP(obj);
> > @@ -1838,6 +1854,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
> > static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> > {
> > PnvChip *chip = PNV_CHIP(chip10);
> > + PnvChipClass *chip_class = PNV_CHIP_GET_CLASS(chip);
> > int i;
> > chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
> > @@ -1846,7 +1863,11 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> > for (i = 0; i < chip10->nr_quads; i++) {
> > PnvQuad *eq = &chip10->quads[i];
> > - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> > + if (chip_class->chip_type == PNV_TYPE_POWER11)
> > + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> > + PNV_QUAD_TYPE_NAME("power11"));
> > + else
> > + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> > PNV_QUAD_TYPE_NAME("power10"));
>
>
> Please change introduce a new pnv_chip_quad_realize() routine taking an
> extra type_name argument.
Sure, can do it. But as it's called from 'pnv_chip_power10_realize',
might require a 'pnv_chip_power11_realize' function also, so it can pass
type_name as "power11" vs "power10".
Will do it.
>
>
> > pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> > @@ -2116,6 +2137,35 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
> > &k->parent_realize);
> > }
> > +static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + PnvChipClass *k = PNV_CHIP_CLASS(klass);
> > +
> > + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
> > +
> > + k->chip_cfam_id = 0x120da04900008000ull; /* P11 (with NX) */
> > + k->chip_type = PNV_TYPE_POWER11;
> > + k->cores_mask = POWER11_CORE_MASK;
> > + k->chip_pir = pnv_chip_pir_p10;
> > + k->intc_create = pnv_chip_power10_intc_create;
> > + k->intc_reset = pnv_chip_power10_intc_reset;
> > + k->intc_destroy = pnv_chip_power10_intc_destroy;
> > + k->intc_print_info = pnv_chip_power10_intc_print_info;
> > + k->isa_create = pnv_chip_power10_isa_create;
> > + k->dt_populate = pnv_chip_power10_dt_populate;
> > + k->pic_print_info = pnv_chip_power10_pic_print_info;
> > + k->xscom_core_base = pnv_chip_power10_xscom_core_base;
> > + k->xscom_pcba = pnv_chip_power10_xscom_pcba;
> > + dc->desc = "PowerNV Chip POWER11";
> > + k->num_pecs = PNV10_CHIP_MAX_PEC;
> > + k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
> > + k->i2c_ports_per_engine = i2c_ports_per_engine;
> > +
> > + device_class_set_parent_realize(dc, pnv_chip_power10_realize,
> > + &k->parent_realize);
> > +}
> > +
> > static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
> > {
> > PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> > @@ -2510,6 +2560,22 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
> > pmc->i2c_init = pnv_rainier_i2c_init;
> > }
> > +static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> > +{
> > + MachineClass *mc = MACHINE_CLASS(oc);
> > + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> > + static const char compat[] = "qemu,powernv11\0ibm,powernv";
> > +
> > + /* do power10_class_init as p11 core is same as p10 */
> > + pnv_machine_p10_common_class_init(oc, data);
> > +
> > + mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
> > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
>
> This should be using a versionned CPU "power11_vx.y".
Okay.
>
> > +
> > + pmc->compat = compat;
> > + pmc->compat_size = sizeof(compat);
> > +}
> > +
> > static bool pnv_machine_get_hb(Object *obj, Error **errp)
> > {
> > PnvMachineState *pnv = PNV_MACHINE(obj);
> > @@ -2613,7 +2679,23 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
> > .parent = TYPE_PNV10_CHIP, \
> > }
> > +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
> > + { \
> > + .name = type, \
> > + .class_init = class_initfn, \
> > + .parent = TYPE_PNV11_CHIP, \
> > + }
> > +
> > static const TypeInfo types[] = {
> > + {
> > + .name = MACHINE_TYPE_NAME("powernv11"),
> > + .parent = TYPE_PNV_MACHINE,
> > + .class_init = pnv_machine_power11_class_init,
> > + .interfaces = (InterfaceInfo[]) {
> > + { TYPE_XIVE_FABRIC },
> > + { },
> > + },
> > + },
> > {
> > .name = MACHINE_TYPE_NAME("powernv10-rainier"),
> > .parent = MACHINE_TYPE_NAME("powernv10"),
> > @@ -2668,6 +2750,16 @@ static const TypeInfo types[] = {
> > .abstract = true,
> > },
> > + /*
> > + * P11 chip and variants
> > + */
> > + {
> > + .name = TYPE_PNV11_CHIP,
> > + .parent = TYPE_PNV10_CHIP,
> > + .instance_size = sizeof(Pnv11Chip),
> > + },
> > + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
> > +
> > /*
> > * P10 chip and variants
> > */
> > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> > index f40ab721d6fc..4522655793da 100644
> > --- a/hw/ppc/pnv_core.c
> > +++ b/hw/ppc/pnv_core.c
> > @@ -402,7 +402,16 @@ static const TypeInfo pnv_core_infos[] = {
> > DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
> > DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
> > DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
> > - DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
> > + {
> > + .parent = TYPE_PNV_CORE,
> > + .name = PNV_CORE_TYPE_NAME("power10_v2.0"),
> > + .class_init = pnv_core_power10_class_init,
> > + .class_base_init = pnv_core_power10_class_init,
> > + },
>
> hmm, what is this change ?
I expanded the macro, to add '.class_base_init', as .class_base_init
will be run by QEMU during initialisation of any child classes also. And
I wanted to let QEMU call 'pnv_core_power10_class_init' when it
initialises 'power11' type.
>
>
> > + {
> > + .parent = PNV_CORE_TYPE_NAME("power10_v2.0"),
> > + .name = PNV_CORE_TYPE_NAME("power11"),
> > + }
>
> nope. please use DEFINE_PNV_CORE_TYPE()
Okay, then, should I have a 'pnv_core_power11_class_init' call
'pnv_core_power10_class_init' ?
>
> > };
> > DEFINE_TYPES(pnv_core_infos)
> > @@ -633,6 +642,11 @@ static const TypeInfo pnv_quad_infos[] = {
> > .parent = TYPE_PNV_QUAD,
> > .name = PNV_QUAD_TYPE_NAME("power10"),
> > .class_init = pnv_quad_power10_class_init,
> > + .class_base_init = pnv_quad_power10_class_init,
> > + },
> > + {
> > + .parent = PNV_QUAD_TYPE_NAME("power10"),
> > + .name = PNV_QUAD_TYPE_NAME("power11"),
>
> hmm, I'd rather introduce pnv_quad_power11_class_init.
Same, in that case, I can have a 'pnv_quad_power11_class_init' which
just calls 'pnv_quad_power10_class_init'.
Any comments ?
> > <...snip...>
> >
> > +struct Pnv11Chip {
> > + /*< private >*/
> > + Pnv10Chip parent_obj;
>
> Can't you use a typedef instead ?
Yes, makes sense. Thanks Cédric.
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
> > +};
> > +
> > struct PnvChipClass {
> > /*< private >*/
> > SysBusDeviceClass parent_class;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11
2024-04-26 14:32 ` Cédric Le Goater
@ 2024-04-26 17:38 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On Fri, Apr 26, 2024 at 04:32:37PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, declare PNV11_HOMER as a child
> > class of PNV10_HOMER, so it goes through same class init
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thank you Cédric.
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/ppc/pnv_homer.c | 8 ++++++++
> > include/hw/ppc/pnv_homer.h | 3 +++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
> > index f9a203d11d0d..1b0123a6f2ea 100644
> > --- a/hw/ppc/pnv_homer.c
> > +++ b/hw/ppc/pnv_homer.c
> > @@ -394,6 +394,13 @@ static const TypeInfo pnv_homer_power10_type_info = {
> > .parent = TYPE_PNV_HOMER,
> > .instance_size = sizeof(PnvHomer),
> > .class_init = pnv_homer_power10_class_init,
> > + .class_base_init = pnv_homer_power10_class_init,
> > +};
> > +
> > +static const TypeInfo pnv_homer_power11_type_info = {
> > + .name = TYPE_PNV11_HOMER,
> > + .parent = TYPE_PNV10_HOMER,
> > + .instance_size = sizeof(PnvHomer),
> > };
> > static void pnv_homer_realize(DeviceState *dev, Error **errp)
> > @@ -442,6 +449,7 @@ static void pnv_homer_register_types(void)
> > type_register_static(&pnv_homer_power8_type_info);
> > type_register_static(&pnv_homer_power9_type_info);
> > type_register_static(&pnv_homer_power10_type_info);
> > + type_register_static(&pnv_homer_power11_type_info);
> > }
> > type_init(pnv_homer_register_types);
> > diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
> > index b1c5d498dc55..8f1cc8135937 100644
> > --- a/include/hw/ppc/pnv_homer.h
> > +++ b/include/hw/ppc/pnv_homer.h
> > @@ -35,6 +35,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
> > #define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
> > DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
> > TYPE_PNV10_HOMER)
> > +#define TYPE_PNV11_HOMER TYPE_PNV_HOMER "-POWER11"
> > +DECLARE_INSTANCE_CHECKER(PnvHomer, PNV11_HOMER,
> > + TYPE_PNV11_HOMER)
> > struct PnvHomer {
> > DeviceState parent;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 05/10] ppc/pnv: Add a LPC controller for POWER11
2024-04-26 14:32 ` Cédric Le Goater
@ 2024-04-26 17:38 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On Fri, Apr 26, 2024 at 04:32:52PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10 core, declare PNV11_LPC as a child
> > class of PNV10_LPC, so it goes through same class init
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thank you Cédric.
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/ppc/pnv_lpc.c | 14 ++++++++++++++
> > include/hw/ppc/pnv_lpc.h | 4 ++++
> > 2 files changed, 18 insertions(+)
> >
> > diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> > index d692858bee78..54b366221bc7 100644
> > --- a/hw/ppc/pnv_lpc.c
> > +++ b/hw/ppc/pnv_lpc.c
> > @@ -698,6 +698,19 @@ static const TypeInfo pnv_lpc_power10_info = {
> > .class_init = pnv_lpc_power10_class_init,
> > };
> > +static void pnv_lpc_power11_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->desc = "PowerNV LPC Controller POWER11";
> > +}
> > +
> > +static const TypeInfo pnv_lpc_power11_info = {
> > + .name = TYPE_PNV11_LPC,
> > + .parent = TYPE_PNV10_LPC,
> > + .class_init = pnv_lpc_power11_class_init,
> > +};
> > +
> > static void pnv_lpc_realize(DeviceState *dev, Error **errp)
> > {
> > PnvLpcController *lpc = PNV_LPC(dev);
> > @@ -771,6 +784,7 @@ static void pnv_lpc_register_types(void)
> > type_register_static(&pnv_lpc_power8_info);
> > type_register_static(&pnv_lpc_power9_info);
> > type_register_static(&pnv_lpc_power10_info);
> > + type_register_static(&pnv_lpc_power11_info);
> > }
> > type_init(pnv_lpc_register_types)
> > diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
> > index 5d22c4557041..1069bca38dfd 100644
> > --- a/include/hw/ppc/pnv_lpc.h
> > +++ b/include/hw/ppc/pnv_lpc.h
> > @@ -41,6 +41,10 @@ DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC,
> > DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC,
> > TYPE_PNV10_LPC)
> > +#define TYPE_PNV11_LPC TYPE_PNV_LPC "-POWER11"
> > +DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV11_LPC,
> > + TYPE_PNV11_LPC)
> > +
> > struct PnvLpcController {
> > DeviceState parent;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 06/10] ppc/pnv: Add OCC for Power11
2024-04-26 14:33 ` Cédric Le Goater
@ 2024-04-26 17:38 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:38 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On Fri, Apr 26, 2024 at 04:33:13PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_OCC initialisation,
> > by declaring `PNV11_OCC` as child class of `PNV10_OCC`
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks Cédric !
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
>
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> > ---
> > hw/ppc/pnv_occ.c | 14 ++++++++++++++
> > include/hw/ppc/pnv_occ.h | 2 ++
> > 2 files changed, 16 insertions(+)
> >
> > diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> > index 48123ceae176..4f510419045e 100644
> > --- a/hw/ppc/pnv_occ.c
> > +++ b/hw/ppc/pnv_occ.c
> > @@ -262,6 +262,19 @@ static const TypeInfo pnv_occ_power10_type_info = {
> > .class_init = pnv_occ_power10_class_init,
> > };
> > +static void pnv_occ_power11_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->desc = "PowerNV OCC Controller (POWER11)";
> > +}
> > +
> > +static const TypeInfo pnv_occ_power11_type_info = {
> > + .name = TYPE_PNV11_OCC,
> > + .parent = TYPE_PNV10_OCC,
> > + .class_init = pnv_occ_power11_class_init,
> > +};
> > +
> > static void pnv_occ_realize(DeviceState *dev, Error **errp)
> > {
> > PnvOCC *occ = PNV_OCC(dev);
> > @@ -305,6 +318,7 @@ static void pnv_occ_register_types(void)
> > type_register_static(&pnv_occ_power8_type_info);
> > type_register_static(&pnv_occ_power9_type_info);
> > type_register_static(&pnv_occ_power10_type_info);
> > + type_register_static(&pnv_occ_power11_type_info);
> > }
> > type_init(pnv_occ_register_types);
> > diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> > index df321244e3b1..7b5e28f13b4f 100644
> > --- a/include/hw/ppc/pnv_occ.h
> > +++ b/include/hw/ppc/pnv_occ.h
> > @@ -34,6 +34,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
> > TYPE_PNV9_OCC)
> > #define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
> > DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
> > +#define TYPE_PNV11_OCC TYPE_PNV_OCC "-POWER11"
> > +DECLARE_INSTANCE_CHECKER(PnvOCC, PNV11_OCC, TYPE_PNV11_OCC)
> > #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
> > #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model for Power11
2024-04-26 14:33 ` Cédric Le Goater
@ 2024-04-26 17:39 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:39 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On Fri, Apr 26, 2024 at 04:33:23PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
> > declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks Cédric !
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/ppc/pnv_psi.c | 24 ++++++++++++++++++++++++
> > include/hw/ppc/pnv_psi.h | 2 ++
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> > index 26460d210deb..1f708b183a87 100644
> > --- a/hw/ppc/pnv_psi.c
> > +++ b/hw/ppc/pnv_psi.c
> > @@ -939,6 +939,29 @@ static const TypeInfo pnv_psi_power10_info = {
> > .name = TYPE_PNV10_PSI,
> > .parent = TYPE_PNV9_PSI,
> > .class_init = pnv_psi_power10_class_init,
> > + .class_base_init = pnv_psi_power10_class_init,
> > +};
> > +
> > +static void pnv_psi_power11_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
> > + static const char compat[] = "ibm,power11-psihb-x\0ibm,psihb-x";
> > +
> > + dc->desc = "PowerNV PSI Controller POWER11";
> > +
> > + /*
> > + * ppc->xscom_pbca and ppc->xscom_size will be set up by
> > + * pnv_psi_power10_class_init
> > + */
> > + ppc->compat = compat;
> > + ppc->compat_size = sizeof(compat);
> > +}
> > +
> > +static const TypeInfo pnv_psi_power11_info = {
> > + .name = TYPE_PNV11_PSI,
> > + .parent = TYPE_PNV10_PSI,
> > + .class_init = pnv_psi_power11_class_init,
> > };
> > static void pnv_psi_class_init(ObjectClass *klass, void *data)
> > @@ -973,6 +996,7 @@ static void pnv_psi_register_types(void)
> > type_register_static(&pnv_psi_power8_info);
> > type_register_static(&pnv_psi_power9_info);
> > type_register_static(&pnv_psi_power10_info);
> > + type_register_static(&pnv_psi_power11_info);
> > }
> > type_init(pnv_psi_register_types);
> > diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
> > index 2a6f715350b6..9e1d31779204 100644
> > --- a/include/hw/ppc/pnv_psi.h
> > +++ b/include/hw/ppc/pnv_psi.h
> > @@ -70,6 +70,8 @@ struct Pnv9Psi {
> > #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
> > +#define TYPE_PNV11_PSI TYPE_PNV_PSI "-POWER11"
> > +
> > struct PnvPsiClass {
> > SysBusDeviceClass parent_class;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 08/10] ppc/pnv: Add SBE model for Power11
2024-04-26 14:33 ` Cédric Le Goater
@ 2024-04-26 17:39 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:39 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On Fri, Apr 26, 2024 at 04:33:33PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
> > declaring PNV11_PSI as child class of PNV10_PSI
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thank you Cédric !
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/ppc/pnv_sbe.c | 15 +++++++++++++++
> > include/hw/ppc/pnv_sbe.h | 2 ++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
> > index 74cee4eea7ad..a655cc7f8c9e 100644
> > --- a/hw/ppc/pnv_sbe.c
> > +++ b/hw/ppc/pnv_sbe.c
> > @@ -366,6 +366,20 @@ static const TypeInfo pnv_sbe_power10_type_info = {
> > .name = TYPE_PNV10_SBE,
> > .parent = TYPE_PNV9_SBE,
> > .class_init = pnv_sbe_power10_class_init,
> > + .class_base_init = pnv_sbe_power10_class_init,
> > +};
> > +
> > +static void pnv_sbe_power11_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->desc = "PowerNV SBE Controller (POWER11)";
> > +}
> > +
> > +static const TypeInfo pnv_sbe_power11_type_info = {
> > + .name = TYPE_PNV11_SBE,
> > + .parent = TYPE_PNV10_SBE,
> > + .class_init = pnv_sbe_power11_class_init,
> > };
> > static void pnv_sbe_realize(DeviceState *dev, Error **errp)
> > @@ -409,6 +423,7 @@ static void pnv_sbe_register_types(void)
> > type_register_static(&pnv_sbe_type_info);
> > type_register_static(&pnv_sbe_power9_type_info);
> > type_register_static(&pnv_sbe_power10_type_info);
> > + type_register_static(&pnv_sbe_power11_type_info);
> > }
> > type_init(pnv_sbe_register_types);
> > diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
> > index b6b378ad14c7..09073a1256d6 100644
> > --- a/include/hw/ppc/pnv_sbe.h
> > +++ b/include/hw/ppc/pnv_sbe.h
> > @@ -29,6 +29,8 @@ OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
> > DECLARE_INSTANCE_CHECKER(PnvSBE, PNV9_SBE, TYPE_PNV9_SBE)
> > #define TYPE_PNV10_SBE TYPE_PNV_SBE "-POWER10"
> > DECLARE_INSTANCE_CHECKER(PnvSBE, PNV10_SBE, TYPE_PNV10_SBE)
> > +#define TYPE_PNV11_SBE TYPE_PNV_SBE "-POWER11"
> > +DECLARE_INSTANCE_CHECKER(PnvSBE, PNV11_SBE, TYPE_PNV11_SBE)
> > struct PnvSBE {
> > DeviceState xd;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-26 14:32 ` Cédric Le Goater
@ 2024-04-26 17:40 ` Aditya Gupta
2024-04-29 1:44 ` David Gibson
2024-05-03 4:52 ` Nicholas Piggin
2 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:40 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Frédéric Barrat, Harsh Prateek Bora
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power11 support first, possibly in 9.1,
> and then change default in a future release, 9.2, 10.0
Okay, makes sense.
I will drop this change from v3.
Thanks,
- Aditya Gupta
>
> Thanks,
>
> C.
>
>
>
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> > Cc: David Gibson <david@gibson.dropbear.id.au>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> > ---
> > hw/ppc/pnv.c | 4 ++--
> > hw/ppc/spapr.c | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 06e272f3bdd3..0c5a6bc424af 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -2531,8 +2531,6 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
> > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
> > - mc->alias = "powernv";
> > -
> > pmc->compat = compat;
> > pmc->compat_size = sizeof(compat);
> > pmc->dt_power_mgt = pnv_dt_power_mgt;
> > @@ -2569,6 +2567,8 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> > /* do power10_class_init as p11 core is same as p10 */
> > pnv_machine_p10_common_class_init(oc, data);
> > + mc->alias = "powernv";
> > +
> > mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
> > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index d2d1e310a3be..1c3e2da8e9e4 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -4698,7 +4698,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
> > smc->dr_lmb_enabled = true;
> > smc->update_dt_enabled = true;
> > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
> > mc->has_hotpluggable_cpus = true;
> > mc->nvdimm_supported = true;
> > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 17:05 ` Aditya Gupta
@ 2024-04-26 17:41 ` Cédric Le Goater
2024-05-01 13:22 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 17:41 UTC (permalink / raw)
To: Aditya Gupta
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
On 4/26/24 19:05, Aditya Gupta wrote:
> Hello Cédric,
>
> Thanks for your reviews.
>
> On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote:
>> Hello Aditya
>>
>> On 4/26/24 13:00, Aditya Gupta wrote:
>>> Add base support for "--cpu power11" in QEMU.
>>>
>>> Power11 core is same as Power10, hence reuse functions defined for
>>> Power10.
>>
>> Power11 uses the same ISA it seems. What's the value then ?
>
> Yes, it uses the same ISA. But I added this option so we can have a
> Power11 PVR in QEMU, which should be identified as Power11 in skiboot
> and linux, hence defined Power11 cpu type, even though code here is
> almost same as Power10.
>
>>
>>>
>>> Cc: Cédric Le Goater <clg@kaod.org>
>>> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
>>> Cc: David Gibson <david@gibson.dropbear.id.au>
>>> Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
>>> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
>>> Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
>>> Cc: Nicholas Piggin <npiggin@gmail.com>
>>> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
>>> ---
>>> docs/system/ppc/pseries.rst | 6 +--
>>> hw/ppc/spapr_cpu_core.c | 1 +
>>
>>
>> I would separate the CPU target code adding support for a new POWER
>> Processor from the machine code (pseries).
>
> Sure, I will split it in v3.
>
>>
>>
>>> target/ppc/compat.c | 7 +++
>>> target/ppc/cpu-models.c | 2 +
>>> target/ppc/cpu-models.h | 2 +
>>> target/ppc/cpu_init.c | 99 +++++++++++++++++++++++++++++++++++++
>>> 6 files changed, 114 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
>>> index a876d897b6e4..3277564b34c2 100644
>>> --- a/docs/system/ppc/pseries.rst
>>> +++ b/docs/system/ppc/pseries.rst
>>> @@ -15,9 +15,9 @@ Supported devices
>>> =================
>>> * Multi processor support for many Power processors generations: POWER7,
>>> - POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists,
>>> - but its state is unknown.
>>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10)
>>> + POWER7+, POWER8, POWER8NVL, POWER9, Power10 and Power11. Support for POWER5+
>>> + exists, but its state is unknown.
>>
>> The POWER5+ pseries machine seems functionnal with SLOF
>> (Sep 18 2023 18:57:48) and Linux 6.6.3 under TCG. May be worth
>> to mention (for AIX users) in another patch.
>>
>>> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9, Power10, Power11)
>>> * vPHB PCIe Host bridge.
>>> * vscsi and vnet devices, compatible with the same devices available on a
>>> PowerVM hypervisor with VIOS managing LPARs.
>>> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
>>> index e7c9edd033c8..c6e85c031178 100644
>>> --- a/hw/ppc/spapr_cpu_core.c
>>> +++ b/hw/ppc/spapr_cpu_core.c
>>> @@ -401,6 +401,7 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
>>> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
>>> DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
>>> DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
>>> + DEFINE_SPAPR_CPU_CORE_TYPE("power11"),
>>> #ifdef CONFIG_KVM
>>> DEFINE_SPAPR_CPU_CORE_TYPE("host"),
>>> #endif
>>> diff --git a/target/ppc/compat.c b/target/ppc/compat.c
>>> index ebef2cccecf3..12dd8ae290ca 100644
>>> --- a/target/ppc/compat.c
>>> +++ b/target/ppc/compat.c
>>> @@ -100,6 +100,13 @@ static const CompatInfo compat_table[] = {
>>> .pcr_level = PCR_COMPAT_3_10,
>>> .max_vthreads = 8,
>>> },
>>> + { /* POWER11, ISA3.10 */
>>> + .name = "power11",
>>> + .pvr = CPU_POWERPC_LOGICAL_3_10_PLUS,
>>> + .pcr = PCR_COMPAT_3_10,
>>> + .pcr_level = PCR_COMPAT_3_10,
>>> + .max_vthreads = 8,
>>> + },
>>> };
>>> static const CompatInfo *compat_by_pvr(uint32_t pvr)
>>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>>> index f2301b43f78b..1870e69b63df 100644
>>> --- a/target/ppc/cpu-models.c
>>> +++ b/target/ppc/cpu-models.c
>>> @@ -734,6 +734,8 @@
>>> "POWER9 v2.2")
>>> POWERPC_DEF("power10_v2.0", CPU_POWERPC_POWER10_DD20, POWER10,
>>> "POWER10 v2.0")
>>> + POWERPC_DEF("power11", CPU_POWERPC_POWER11, POWER11,
>>> + "POWER11")
>>> #endif /* defined (TARGET_PPC64) */
>>> /***************************************************************************/
>>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>>> index 0229ef3a9a5c..a1b540c3aa9e 100644
>>> --- a/target/ppc/cpu-models.h
>>> +++ b/target/ppc/cpu-models.h
>>> @@ -354,6 +354,7 @@ enum {
>>> CPU_POWERPC_POWER10_BASE = 0x00800000,
>>> CPU_POWERPC_POWER10_DD1 = 0x00801100,
>>> CPU_POWERPC_POWER10_DD20 = 0x00801200,
>>> + CPU_POWERPC_POWER11 = 0x00821200,
>>
>> is that a DD2.2 PVR ? If so, It should be mentionned in the definition.
>>
>
> Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it
> above the line I have added it, in v3.
Skiboot reports :
[ 0.121234172,6] P11 DD1.00 detected
C.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 10/10] ppc/pnv: Update skiboot.lid to support Power11
2024-04-26 14:38 ` [PATCH v2 10/10] ppc/pnv: Update skiboot.lid to support Power11 Cédric Le Goater
@ 2024-04-26 17:42 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:42 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Joel Stanley
On Fri, Apr 26, 2024 at 04:38:13PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> > commits in github repository [2].
> >
> > Update skiboot.lid, with binary built from 'upstream_power11' branch
> > of skiboot repository with Power11 enablement patches [2].
> >
> > ---
> > This patch can be skipped for now, if need to wait for patches to be
> > merged in open-power/skiboot.
>
> yes.
>
> > Have updated the skiboot.lid to aid in testing this patch series.
>
> Thanks for doing so.
Good it helped !
Thanks,
- Aditya Gupta
>
> > ---
> >
> > [1]:https://lists.ozlabs.org/pipermail/skiboot/2024-April/018963.html
> > [2]:https://github.com/maheshsal/skiboot.
> >
> > Cc: Cédric Le Goater<clg@kaod.org>
> > Cc: Joel Stanley<joel@jms.id.au>
> > Cc: Mahesh J Salgaonkar<mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan<maddy@linux.ibm.com>
> > Cc: Nicholas Piggin<npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta<adityag@linux.ibm.com>
> > ---
> > pc-bios/skiboot.lid | Bin 2527328 -> 2527328 bytes
> > 1 file changed, 0 insertions(+), 0 deletions(-)
>
> We avoid sending such big blobs on the mailing list. We usually send a
> PR to the sub-system maintainer (Nick). When time comes (support is
> merged is skiboot), we will address the skiboot image update in QEMU.
>
> C.
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 17:28 ` Cédric Le Goater
@ 2024-04-26 17:44 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-04-26 17:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
> > Quoting lines from docs/system/ppc/powernv.rst:
> >
> > > Missing devices
> > > ---------------
> > >
> > > A lot is missing, among which :
> > >
> > > * I2C controllers (yet to be merged).
> > > * NPU/NPU2/NPU3 controllers.
> > > * EEH support for PCIe Host bridge controllers.
> > > * NX controller.
> > > * VAS controller.
> > > * chipTOD (Time Of Day).
> > > * Self Boot Engine (SBE).
> > > * FSI bus.
> >
> > I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
> > yet to merge, is it merged yet ?
>
> yes.
Thanks for confirming Cédric !
- Aditya Gupta
>
> >
> > I will check whether this needs updating, but might do it in a separate
> > patch than this series.
>
> Thanks,
>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
2024-04-26 17:34 ` Aditya Gupta
@ 2024-04-26 17:53 ` Cédric Le Goater
2024-05-01 13:28 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Cédric Le Goater @ 2024-04-26 17:53 UTC (permalink / raw)
To: Aditya Gupta
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
On 4/26/24 19:34, Aditya Gupta wrote:
> Hello Cédric,
>
>>>
>>> <...snip...>
>>>
>>> - * Multi processor support for POWER8, POWER8NVL and POWER9.
>>> + * Multi processor support for POWER8, POWER8NVL, POWER9, POWER10 and Power11.
>>
>> POWER10 -> Power10. Don't ask me why.
>
> Sure, got it !
>
>>
>>> * XSCOM, serial communication sideband bus to configure chiplets.
>>> * Simple LPC Controller.
>>> * Processor Service Interface (PSI) Controller.
>>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
>>> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
>>> + Power11).
>>> * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
>>> * Simple OCC is an on-chip micro-controller used for power management tasks.
>>> * iBT device to handle BMC communication, with the internal BMC simulator
>>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>>> index 74e7908e5ffb..06e272f3bdd3 100644
>>> --- a/hw/ppc/pnv.c
>>> +++ b/hw/ppc/pnv.c
>>> @@ -431,13 +431,27 @@ static const uint8_t pa_features_31[] = { 74, 0,
>>> static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
>>> {
>>> - static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
>>> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>>> + static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom";
>>> + static const char compat_p11[] = "ibm,power11-xscom\0ibm,xscom";
>>> +
>>> + PnvChipType chip_type = pcc->chip_type;
>>> + const char *compat;
>>> + int compat_len;
>>> int i;
>>> + if (chip_type == PNV_TYPE_POWER11) {
>>> + compat = compat_p11;
>>> + compat_len = sizeof(compat_p11);
>>> + } else {
>>> + compat = compat_p10;
>>> + compat_len = sizeof(compat_p10);
>>> + }
>>
>> please introduce a pnv_chip_power11_dt_populate() routine instead.
>
> Okay.
>
>>
>>> pnv_dt_xscom(chip, fdt, 0,
>>> cpu_to_be64(PNV10_XSCOM_BASE(chip)),
>>> cpu_to_be64(PNV10_XSCOM_SIZE),
>>> - compat, sizeof(compat));
>>> + compat, compat_len);
>>> for (i = 0; i < chip->nr_cores; i++) {
>>> PnvCore *pnv_core = chip->cores[i];
>>> @@ -1288,6 +1302,8 @@ static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
>>> #define POWER10_CORE_MASK (0xffffffffffffffull)
>>> +#define POWER11_CORE_MASK (0xffffffffffffffull)
>>> +
>>> static void pnv_chip_power8_instance_init(Object *obj)
>>> {
>>> Pnv8Chip *chip8 = PNV8_CHIP(obj);
>>> @@ -1838,6 +1854,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
>>> static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
>>> {
>>> PnvChip *chip = PNV_CHIP(chip10);
>>> + PnvChipClass *chip_class = PNV_CHIP_GET_CLASS(chip);
>>> int i;
>>> chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
>>> @@ -1846,7 +1863,11 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
>>> for (i = 0; i < chip10->nr_quads; i++) {
>>> PnvQuad *eq = &chip10->quads[i];
>>> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>> + if (chip_class->chip_type == PNV_TYPE_POWER11)
>>> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>> + PNV_QUAD_TYPE_NAME("power11"));
>>> + else
>>> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>> PNV_QUAD_TYPE_NAME("power10"));
>>
>>
>> Please change introduce a new pnv_chip_quad_realize() routine taking an
>> extra type_name argument.
>
> Sure, can do it. But as it's called from 'pnv_chip_power10_realize',
> might require a 'pnv_chip_power11_realize' function also, so it can pass
> type_name as "power11" vs "power10".
Do the Power11 and Power10 processors have the same XSCOM and MMIO
address spaces ?
> Will do it.
>
>>
>>
>>> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
>>> @@ -2116,6 +2137,35 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
>>> &k->parent_realize);
>>> }
>>> +static void pnv_chip_power11_class_init(ObjectClass *klass, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> + PnvChipClass *k = PNV_CHIP_CLASS(klass);
>>> +
>>> + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16};
>>> +
>>> + k->chip_cfam_id = 0x120da04900008000ull; /* P11 (with NX) */
>>> + k->chip_type = PNV_TYPE_POWER11;
>>> + k->cores_mask = POWER11_CORE_MASK;
>>> + k->chip_pir = pnv_chip_pir_p10;
>>> + k->intc_create = pnv_chip_power10_intc_create;
>>> + k->intc_reset = pnv_chip_power10_intc_reset;
>>> + k->intc_destroy = pnv_chip_power10_intc_destroy;
>>> + k->intc_print_info = pnv_chip_power10_intc_print_info;
>>> + k->isa_create = pnv_chip_power10_isa_create;
>>> + k->dt_populate = pnv_chip_power10_dt_populate;
>>> + k->pic_print_info = pnv_chip_power10_pic_print_info;
>>> + k->xscom_core_base = pnv_chip_power10_xscom_core_base;
>>> + k->xscom_pcba = pnv_chip_power10_xscom_pcba;
>>> + dc->desc = "PowerNV Chip POWER11";
>>> + k->num_pecs = PNV10_CHIP_MAX_PEC;
>>> + k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
>>> + k->i2c_ports_per_engine = i2c_ports_per_engine;
>>> +
>>> + device_class_set_parent_realize(dc, pnv_chip_power10_realize,
>>> + &k->parent_realize);
>>> +}
>>> +
>>> static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
>>> {
>>> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>>> @@ -2510,6 +2560,22 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
>>> pmc->i2c_init = pnv_rainier_i2c_init;
>>> }
>>> +static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
>>> +{
>>> + MachineClass *mc = MACHINE_CLASS(oc);
>>> + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
>>> + static const char compat[] = "qemu,powernv11\0ibm,powernv";
>>> +
>>> + /* do power10_class_init as p11 core is same as p10 */
>>> + pnv_machine_p10_common_class_init(oc, data);
>>> +
>>> + mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
>>> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
>>
>> This should be using a versionned CPU "power11_vx.y".
>
> Okay.
>
>>
>>> +
>>> + pmc->compat = compat;
>>> + pmc->compat_size = sizeof(compat);
>>> +}
>>> +
>>> static bool pnv_machine_get_hb(Object *obj, Error **errp)
>>> {
>>> PnvMachineState *pnv = PNV_MACHINE(obj);
>>> @@ -2613,7 +2679,23 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
>>> .parent = TYPE_PNV10_CHIP, \
>>> }
>>> +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
>>> + { \
>>> + .name = type, \
>>> + .class_init = class_initfn, \
>>> + .parent = TYPE_PNV11_CHIP, \
>>> + }
>>> +
>>> static const TypeInfo types[] = {
>>> + {
>>> + .name = MACHINE_TYPE_NAME("powernv11"),
>>> + .parent = TYPE_PNV_MACHINE,
>>> + .class_init = pnv_machine_power11_class_init,
>>> + .interfaces = (InterfaceInfo[]) {
>>> + { TYPE_XIVE_FABRIC },
>>> + { },
>>> + },
>>> + },
>>> {
>>> .name = MACHINE_TYPE_NAME("powernv10-rainier"),
>>> .parent = MACHINE_TYPE_NAME("powernv10"),
>>> @@ -2668,6 +2750,16 @@ static const TypeInfo types[] = {
>>> .abstract = true,
>>> },
>>> + /*
>>> + * P11 chip and variants
>>> + */
>>> + {
>>> + .name = TYPE_PNV11_CHIP,
>>> + .parent = TYPE_PNV10_CHIP,
>>> + .instance_size = sizeof(Pnv11Chip),
>>> + },
>>> + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11, pnv_chip_power11_class_init),
>>> +
>>> /*
>>> * P10 chip and variants
>>> */
>>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>>> index f40ab721d6fc..4522655793da 100644
>>> --- a/hw/ppc/pnv_core.c
>>> +++ b/hw/ppc/pnv_core.c
>>> @@ -402,7 +402,16 @@ static const TypeInfo pnv_core_infos[] = {
>>> DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
>>> DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
>>> DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
>>> - DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
>>> + {
>>> + .parent = TYPE_PNV_CORE,
>>> + .name = PNV_CORE_TYPE_NAME("power10_v2.0"),
>>> + .class_init = pnv_core_power10_class_init,
>>> + .class_base_init = pnv_core_power10_class_init,
>>> + },
>>
>> hmm, what is this change ?
>
> I expanded the macro, to add '.class_base_init', as .class_base_init
> will be run by QEMU during initialisation of any child classes also. And
> I wanted to let QEMU call 'pnv_core_power10_class_init' when it
> initialises 'power11' type.
>
>>
>>
>>> + {
>>> + .parent = PNV_CORE_TYPE_NAME("power10_v2.0"),
>>> + .name = PNV_CORE_TYPE_NAME("power11"),
>>> + }
>>
>> nope. please use DEFINE_PNV_CORE_TYPE()
>
> Okay, then, should I have a 'pnv_core_power11_class_init' call
> 'pnv_core_power10_class_init' ?
yes.
>
>>
>>> };
>>> DEFINE_TYPES(pnv_core_infos)
>>> @@ -633,6 +642,11 @@ static const TypeInfo pnv_quad_infos[] = {
>>> .parent = TYPE_PNV_QUAD,
>>> .name = PNV_QUAD_TYPE_NAME("power10"),
>>> .class_init = pnv_quad_power10_class_init,
>>> + .class_base_init = pnv_quad_power10_class_init,
>>> + },
>>> + {
>>> + .parent = PNV_QUAD_TYPE_NAME("power10"),
>>> + .name = PNV_QUAD_TYPE_NAME("power11"),
>>
>> hmm, I'd rather introduce pnv_quad_power11_class_init.
>
> Same, in that case, I can have a 'pnv_quad_power11_class_init' which
> just calls 'pnv_quad_power10_class_init'.
yes.
Thanks,
C.
>
> Any comments ?
>
>>> <...snip...>
>>>
>>> +struct Pnv11Chip {
>>> + /*< private >*/
>>> + Pnv10Chip parent_obj;
>>
>> Can't you use a typedef instead ?
>
> Yes, makes sense. Thanks Cédric.
>
> - Aditya Gupta
>
>>
>> Thanks,
>>
>> C.
>>
>>
>>> +};
>>> +
>>> struct PnvChipClass {
>>> /*< private >*/
>>> SysBusDeviceClass parent_class;
>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:40 ` Aditya Gupta
@ 2024-04-29 1:44 ` David Gibson
2024-05-01 13:29 ` Aditya Gupta
2024-05-03 4:52 ` Nicholas Piggin
2 siblings, 1 reply; 42+ messages in thread
From: David Gibson @ 2024-04-29 1:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Aditya Gupta, Mahesh J Salgaonkar, Madhavan Srinivasan,
Nicholas Piggin, qemu-devel, qemu-ppc, Daniel Henrique Barboza,
Frédéric Barrat, Harsh Prateek Bora
[-- Attachment #1: Type: text/plain, Size: 2927 bytes --]
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power11 support first, possibly in 9.1,
> and then change default in a future release, 9.2, 10.0
Additionally, changes to defaults in pseries must be versioned, so
that the behaviour of existing machine types won't change.
>
> Thanks,
>
> C.
>
>
>
> >
> > Cc: Cédric Le Goater <clg@kaod.org>
> > Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> > Cc: David Gibson <david@gibson.dropbear.id.au>
> > Cc: Frédéric Barrat <fbarrat@linux.ibm.com>
> > Cc: Harsh Prateek Bora <harshpb@linux.ibm.com>
> > Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
> > Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Cc: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> > ---
> > hw/ppc/pnv.c | 4 ++--
> > hw/ppc/spapr.c | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 06e272f3bdd3..0c5a6bc424af 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -2531,8 +2531,6 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)
> > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> > compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
> > - mc->alias = "powernv";
> > -
> > pmc->compat = compat;
> > pmc->compat_size = sizeof(compat);
> > pmc->dt_power_mgt = pnv_dt_power_mgt;
> > @@ -2569,6 +2567,8 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)
> > /* do power10_class_init as p11 core is same as p10 */
> > pnv_machine_p10_common_class_init(oc, data);
> > + mc->alias = "powernv";
> > +
> > mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
> > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index d2d1e310a3be..1c3e2da8e9e4 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -4698,7 +4698,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
> > smc->dr_lmb_enabled = true;
> > smc->update_dt_enabled = true;
> > - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
> > + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
> > mc->has_hotpluggable_cpus = true;
> > mc->nvdimm_supported = true;
> > smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-04-26 17:41 ` Cédric Le Goater
@ 2024-05-01 13:22 ` Aditya Gupta
2024-05-01 14:39 ` Aditya Gupta
0 siblings, 1 reply; 42+ messages in thread
From: Aditya Gupta @ 2024-05-01 13:22 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Harsh Prateek Bora
Hi Cédric,
> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>>>> index 0229ef3a9a5c..a1b540c3aa9e 100644
>>>> --- a/target/ppc/cpu-models.h
>>>> +++ b/target/ppc/cpu-models.h
>>>> @@ -354,6 +354,7 @@ enum {
>>>> CPU_POWERPC_POWER10_BASE = 0x00800000,
>>>> CPU_POWERPC_POWER10_DD1 = 0x00801100,
>>>> CPU_POWERPC_POWER10_DD20 = 0x00801200,
>>>> + CPU_POWERPC_POWER11 = 0x00821200,
>>>
>>> is that a DD2.2 PVR ? If so, It should be mentionned in the definition.
>>>
>>
>> Yes, I have kept the last 2 bytes same as P10 DD2. I will mention it
>> above the line I have added it, in v3.
>
> Skiboot reports :
>
> [ 0.121234172,6] P11 DD1.00 detected
>
It is a DD2.0, with major revision = 0x2, and minor revision = 0. Might
need some change in skiboot. Will post a v3 series with changes.
Thanks,
- Aditya Gupta
>
> C.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
2024-04-26 17:53 ` Cédric Le Goater
@ 2024-05-01 13:28 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-05-01 13:28 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Frédéric Barrat
Hello Cédric,
Sorry I missed this mail earlier.
>>>> @@ -1846,7 +1863,11 @@ static void
>>>> pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
>>>> for (i = 0; i < chip10->nr_quads; i++) {
>>>> PnvQuad *eq = &chip10->quads[i];
>>>> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>>> + if (chip_class->chip_type == PNV_TYPE_POWER11)
>>>> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>>> + PNV_QUAD_TYPE_NAME("power11"));
>>>> + else
>>>> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
>>>> PNV_QUAD_TYPE_NAME("power10"));
>>>
>>>
>>> Please change introduce a new pnv_chip_quad_realize() routine taking an
>>> extra type_name argument.
>>
>> Sure, can do it. But as it's called from 'pnv_chip_power10_realize',
>> might require a 'pnv_chip_power11_realize' function also, so it can pass
>> type_name as "power11" vs "power10".
>
> Do the Power11 and Power10 processors have the same XSCOM and MMIO
> address spaces ?
Yes. Hence using the same base and sizes.
Thanks,
Aditya Gupta
>
>> Will do it.
>>
>>>
>>>
>>>> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
>>>> @@ -2116,6 +2137,35 @@ static void
>>>> pnv_chip_power10_class_init(ObjectClass *klass, void *data)
>>>> &k->parent_realize);
>>>> }
>>>> +static void pnv_chip_power11_class_init(ObjectClass *klass, void
>>>> *data)
>>>> +{
>>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>>> + PnvChipClass *k = PNV_CHIP_CLASS(klass);
>>>> +
>>>> + static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] =
>>>> {14, 14, 2, 16};
>>>> +
>>>> + k->chip_cfam_id = 0x120da04900008000ull; /* P11 (with NX) */
>>>> + k->chip_type = PNV_TYPE_POWER11;
>>>> + k->cores_mask = POWER11_CORE_MASK;
>>>> + k->chip_pir = pnv_chip_pir_p10;
>>>> + k->intc_create = pnv_chip_power10_intc_create;
>>>> + k->intc_reset = pnv_chip_power10_intc_reset;
>>>> + k->intc_destroy = pnv_chip_power10_intc_destroy;
>>>> + k->intc_print_info = pnv_chip_power10_intc_print_info;
>>>> + k->isa_create = pnv_chip_power10_isa_create;
>>>> + k->dt_populate = pnv_chip_power10_dt_populate;
>>>> + k->pic_print_info = pnv_chip_power10_pic_print_info;
>>>> + k->xscom_core_base = pnv_chip_power10_xscom_core_base;
>>>> + k->xscom_pcba = pnv_chip_power10_xscom_pcba;
>>>> + dc->desc = "PowerNV Chip POWER11";
>>>> + k->num_pecs = PNV10_CHIP_MAX_PEC;
>>>> + k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
>>>> + k->i2c_ports_per_engine = i2c_ports_per_engine;
>>>> +
>>>> + device_class_set_parent_realize(dc, pnv_chip_power10_realize,
>>>> + &k->parent_realize);
>>>> +}
>>>> +
>>>> static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
>>>> {
>>>> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>>>> @@ -2510,6 +2560,22 @@ static void
>>>> pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)
>>>> pmc->i2c_init = pnv_rainier_i2c_init;
>>>> }
>>>> +static void pnv_machine_power11_class_init(ObjectClass *oc, void
>>>> *data)
>>>> +{
>>>> + MachineClass *mc = MACHINE_CLASS(oc);
>>>> + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
>>>> + static const char compat[] = "qemu,powernv11\0ibm,powernv";
>>>> +
>>>> + /* do power10_class_init as p11 core is same as p10 */
>>>> + pnv_machine_p10_common_class_init(oc, data);
>>>> +
>>>> + mc->desc = "IBM PowerNV (Non-Virtualized) POWER11";
>>>> + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11");
>>>
>>> This should be using a versionned CPU "power11_vx.y".
>>
>> Okay.
>>
>>>
>>>> +
>>>> + pmc->compat = compat;
>>>> + pmc->compat_size = sizeof(compat);
>>>> +}
>>>> +
>>>> static bool pnv_machine_get_hb(Object *obj, Error **errp)
>>>> {
>>>> PnvMachineState *pnv = PNV_MACHINE(obj);
>>>> @@ -2613,7 +2679,23 @@ static void
>>>> pnv_machine_class_init(ObjectClass *oc, void *data)
>>>> .parent = TYPE_PNV10_CHIP, \
>>>> }
>>>> +#define DEFINE_PNV11_CHIP_TYPE(type, class_initfn) \
>>>> + { \
>>>> + .name = type, \
>>>> + .class_init = class_initfn, \
>>>> + .parent = TYPE_PNV11_CHIP, \
>>>> + }
>>>> +
>>>> static const TypeInfo types[] = {
>>>> + {
>>>> + .name = MACHINE_TYPE_NAME("powernv11"),
>>>> + .parent = TYPE_PNV_MACHINE,
>>>> + .class_init = pnv_machine_power11_class_init,
>>>> + .interfaces = (InterfaceInfo[]) {
>>>> + { TYPE_XIVE_FABRIC },
>>>> + { },
>>>> + },
>>>> + },
>>>> {
>>>> .name = MACHINE_TYPE_NAME("powernv10-rainier"),
>>>> .parent = MACHINE_TYPE_NAME("powernv10"),
>>>> @@ -2668,6 +2750,16 @@ static const TypeInfo types[] = {
>>>> .abstract = true,
>>>> },
>>>> + /*
>>>> + * P11 chip and variants
>>>> + */
>>>> + {
>>>> + .name = TYPE_PNV11_CHIP,
>>>> + .parent = TYPE_PNV10_CHIP,
>>>> + .instance_size = sizeof(Pnv11Chip),
>>>> + },
>>>> + DEFINE_PNV11_CHIP_TYPE(TYPE_PNV_CHIP_POWER11,
>>>> pnv_chip_power11_class_init),
>>>> +
>>>> /*
>>>> * P10 chip and variants
>>>> */
>>>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>>>> index f40ab721d6fc..4522655793da 100644
>>>> --- a/hw/ppc/pnv_core.c
>>>> +++ b/hw/ppc/pnv_core.c
>>>> @@ -402,7 +402,16 @@ static const TypeInfo pnv_core_infos[] = {
>>>> DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
>>>> DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
>>>> DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"),
>>>> - DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
>>>> + {
>>>> + .parent = TYPE_PNV_CORE,
>>>> + .name = PNV_CORE_TYPE_NAME("power10_v2.0"),
>>>> + .class_init = pnv_core_power10_class_init,
>>>> + .class_base_init = pnv_core_power10_class_init,
>>>> + },
>>>
>>> hmm, what is this change ?
>>
>> I expanded the macro, to add '.class_base_init', as .class_base_init
>> will be run by QEMU during initialisation of any child classes also. And
>> I wanted to let QEMU call 'pnv_core_power10_class_init' when it
>> initialises 'power11' type.
>>
>>>
>>>
>>>> + {
>>>> + .parent = PNV_CORE_TYPE_NAME("power10_v2.0"),
>>>> + .name = PNV_CORE_TYPE_NAME("power11"),
>>>> + }
>>>
>>> nope. please use DEFINE_PNV_CORE_TYPE()
>>
>> Okay, then, should I have a 'pnv_core_power11_class_init' call
>> 'pnv_core_power10_class_init' ?
>
> yes.
>
>
>>
>>>
>>>> };
>>>> DEFINE_TYPES(pnv_core_infos)
>>>> @@ -633,6 +642,11 @@ static const TypeInfo pnv_quad_infos[] = {
>>>> .parent = TYPE_PNV_QUAD,
>>>> .name = PNV_QUAD_TYPE_NAME("power10"),
>>>> .class_init = pnv_quad_power10_class_init,
>>>> + .class_base_init = pnv_quad_power10_class_init,
>>>> + },
>>>> + {
>>>> + .parent = PNV_QUAD_TYPE_NAME("power10"),
>>>> + .name = PNV_QUAD_TYPE_NAME("power11"),
>>>
>>> hmm, I'd rather introduce pnv_quad_power11_class_init.
>>
>> Same, in that case, I can have a 'pnv_quad_power11_class_init' which
>> just calls 'pnv_quad_power10_class_init'.
>
> yes.
>
>
> Thanks,
>
> C.
>
>
>>
>> Any comments ?
>>
>>>> <...snip...>
>>>>
>>>> +struct Pnv11Chip {
>>>> + /*< private >*/
>>>> + Pnv10Chip parent_obj;
>>>
>>> Can't you use a typedef instead ?
>>
>> Yes, makes sense. Thanks Cédric.
>>
>> - Aditya Gupta
>>
>>>
>>> Thanks,
>>>
>>> C.
>>>
>>>
>>>> +};
>>>> +
>>>> struct PnvChipClass {
>>>> /*< private >*/
>>>> SysBusDeviceClass parent_class;
>>>
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-29 1:44 ` David Gibson
@ 2024-05-01 13:29 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-05-01 13:29 UTC (permalink / raw)
To: David Gibson, Cédric Le Goater
Cc: Mahesh J Salgaonkar, Madhavan Srinivasan, Nicholas Piggin,
qemu-devel, qemu-ppc, Daniel Henrique Barboza,
Frédéric Barrat, Harsh Prateek Bora
Hello David,
On 29/04/24 07:14, David Gibson wrote:
> On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric le Goater wrote:
>> On 4/26/24 13:00, Aditya Gupta wrote:
>>> Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
>>> with Power11 being the newest supported Power processor in QEMU.
>> This is too early. We should merge Power11 support first, possibly in 9.1,
>> and then change default in a future release, 9.2, 10.0
> Additionally, changes to defaults in pseries must be versioned, so
> that the behaviour of existing machine types won't change.
Sure, will take care when pseries default changes in future.
Thanks,
- Aditya Gupta
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type
2024-05-01 13:22 ` Aditya Gupta
@ 2024-05-01 14:39 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-05-01 14:39 UTC (permalink / raw)
To: Cédric Le Goater, Mahesh J Salgaonkar
Cc: Madhavan Srinivasan, Nicholas Piggin, qemu-devel, qemu-ppc,
Daniel Henrique Barboza, David Gibson, Harsh Prateek Bora
Hi Cédric,
>>
>> Skiboot reports :
>>
>> [ 0.121234172,6] P11 DD1.00 detected
>>
> It is a DD2.0, with major revision = 0x2, and minor revision = 0.
> Might need some change in skiboot. Will post a v3 series with changes.
>
The issue was in QEMU, not skiboot.
QEMU sets CFAM id for Power10 as DD1.0 (hw/ppc/pnv.c: 2093):
k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
CFAM is same for Power11, and hence for both 'powernv10' and
'powernv11', skiboot shows DD1.0.
It should be `0x220da04980000000` for DD2.0.
Should I update the CFAM in a separate patch ?
Thanks,
Aditya Gupta
>
> Thanks,
>
> - Aditya Gupta
>
>>
>> C.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:40 ` Aditya Gupta
2024-04-29 1:44 ` David Gibson
@ 2024-05-03 4:52 ` Nicholas Piggin
2024-05-03 6:53 ` Aditya Gupta
2 siblings, 1 reply; 42+ messages in thread
From: Nicholas Piggin @ 2024-05-03 4:52 UTC (permalink / raw)
To: Cédric Le Goater, Aditya Gupta, Mahesh J Salgaonkar,
Madhavan Srinivasan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Frédéric Barrat, Harsh Prateek Bora
On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too early. We should merge Power11 support first, possibly in 9.1,
> and then change default in a future release, 9.2, 10.0
Agree. Since P10 is the released chip that is what users will want
to use. Developers can set -cpu by hand.
Thanks,
Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv'
2024-05-03 4:52 ` Nicholas Piggin
@ 2024-05-03 6:53 ` Aditya Gupta
0 siblings, 0 replies; 42+ messages in thread
From: Aditya Gupta @ 2024-05-03 6:53 UTC (permalink / raw)
To: Nicholas Piggin, Cédric Le Goater, Mahesh J Salgaonkar,
Madhavan Srinivasan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, David Gibson,
Frédéric Barrat, Harsh Prateek Bora
On 03/05/24 10:22, Nicholas Piggin wrote:
> On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
>> On 4/26/24 13:00, Aditya Gupta wrote:
>>> Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
>>> with Power11 being the newest supported Power processor in QEMU.
>> This is too early. We should merge Power11 support first, possibly in 9.1,
>> and then change default in a future release, 9.2, 10.0
> Agree. Since P10 is the released chip that is what users will want
> to use. Developers can set -cpu by hand.
Yes. I have dropped that patch from my v3.
About v3, I am blocked on a issue due to PCR values being same for P10 &
P11. Will post the series after that gets sorted out.
Thanks,
Aditya Gupta
> Thanks,
> Nick
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2024-05-03 7:19 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-26 11:00 [PATCH v2 00/10] Power11 support for QEMU Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 01/10] ppc/pseries: Add Power11 cpu type Aditya Gupta
2024-04-26 14:27 ` Cédric Le Goater
2024-04-26 17:05 ` Aditya Gupta
2024-04-26 17:41 ` Cédric Le Goater
2024-05-01 13:22 ` Aditya Gupta
2024-05-01 14:39 ` Aditya Gupta
2024-04-26 17:12 ` Aditya Gupta
2024-04-26 17:28 ` Cédric Le Goater
2024-04-26 17:44 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 02/10] ppc/pnv: Introduce 'PnvChipClass::chip_type' Aditya Gupta
2024-04-26 14:16 ` Cédric Le Goater
2024-04-26 17:18 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 03/10] ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine Aditya Gupta
2024-04-26 14:55 ` Cédric Le Goater
2024-04-26 17:34 ` Aditya Gupta
2024-04-26 17:53 ` Cédric Le Goater
2024-05-01 13:28 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 04/10] ppc/pnv: Add HOMER for POWER11 Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 05/10] ppc/pnv: Add a LPC controller " Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 06/10] ppc/pnv: Add OCC for Power11 Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:38 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 07/10] ppc/pnv: Add a PSI bridge model " Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:39 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 08/10] ppc/pnv: Add SBE " Aditya Gupta
2024-04-26 14:33 ` Cédric Le Goater
2024-04-26 17:39 ` Aditya Gupta
2024-04-26 11:00 ` [PATCH v2 09/10] ppc: Make Power11 as default cpu type for 'pseries' and 'powernv' Aditya Gupta
2024-04-26 14:32 ` Cédric Le Goater
2024-04-26 17:40 ` Aditya Gupta
2024-04-29 1:44 ` David Gibson
2024-05-01 13:29 ` Aditya Gupta
2024-05-03 4:52 ` Nicholas Piggin
2024-05-03 6:53 ` Aditya Gupta
[not found] ` <20240426110023.733309-11-adityag@linux.ibm.com>
2024-04-26 14:38 ` [PATCH v2 10/10] ppc/pnv: Update skiboot.lid to support Power11 Cédric Le Goater
2024-04-26 17:42 ` Aditya Gupta
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