[PATCH i-g-t v2 0/7] tests/perf: Enable i915 perf tests on CNL

[PATCH i-g-t v2 0/7] tests/perf: Enable i915 perf tests on CNL

[Lionel Landwerlin]

Adding a fix for make based builds.

Cheers,

Lionel Landwerlin (7):
  tools: make sure to include embedded drm-uapi headers
  include/drm-uapi: bump headers
  tests/perf: drop copied i915 defines/structs
  tests/perf: factorize max oa buffer size define
  tests/perf: query CS timestamp frequency if available
  tests/perf: enable testing on Coffelake GT3
  tests/perf: add test config uuid for Cannonlake

 include/drm-uapi/amdgpu_drm.h  |  12 ++++
 include/drm-uapi/armada_drm.h  |   1 +
 include/drm-uapi/etnaviv_drm.h |   1 +
 include/drm-uapi/exynos_drm.h  |   1 +
 include/drm-uapi/i810_drm.h    |   1 +
 include/drm-uapi/i915_drm.h    |  38 ++++++++++
 include/drm-uapi/omap_drm.h    |   1 +
 lib/igt_gt.h                   |  11 +--
 lib/meson.build                |   3 +-
 tests/perf.c                   | 160 +++++++++++------------------------------
 tools/Makefile.am              |   2 +-
 11 files changed, 103 insertions(+), 128 deletions(-)

--
2.15.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 1/7] tools: make sure to include embedded drm-uapi headers

[Lionel Landwerlin]

Headers from lib/ depend on drm uapi headers. Since we started
embedding them, make sure to pull them first, since we still depend on
libdrm, we don't want the system headers to be included first.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tools/Makefile.am | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/Makefile.am b/tools/Makefile.am
index a8196f07..dcf282ea 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -15,7 +15,7 @@ endif
 
 SUBDIRS = null_state_gen registers
 
-AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include/drm-uapi -I$(top_srcdir)/lib
 AM_CFLAGS = $(DEBUG_CFLAGS) $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) \
 	    $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) -DIGT_DATADIR=\"$(pkgdatadir)\" \
 	    $(WERROR_CFLAGS) -D_GNU_SOURCE
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 2/7] include/drm-uapi: bump headers

[Lionel Landwerlin]

Taken from drm-next :

commit 9c606cd4117a3c45e04a6616b1a0dbeb18eeee62
Merge: c5dd52f653fa 3997eea57caf
Author: Dave Airlie <airlied@redhat.com>
Date:   Thu Dec 7 06:28:22 2017 +1000

    Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 include/drm-uapi/amdgpu_drm.h  | 12 ++++++++++++
 include/drm-uapi/armada_drm.h  |  1 +
 include/drm-uapi/etnaviv_drm.h |  1 +
 include/drm-uapi/exynos_drm.h  |  1 +
 include/drm-uapi/i810_drm.h    |  1 +
 include/drm-uapi/i915_drm.h    | 38 ++++++++++++++++++++++++++++++++++++++
 include/drm-uapi/omap_drm.h    |  1 +
 lib/igt_gt.h                   | 11 ++---------
 lib/meson.build                |  3 ++-
 9 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 919248fb..4d21191a 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -160,6 +160,7 @@ union drm_amdgpu_bo_list {
 #define AMDGPU_CTX_OP_ALLOC_CTX	1
 #define AMDGPU_CTX_OP_FREE_CTX	2
 #define AMDGPU_CTX_OP_QUERY_STATE	3
+#define AMDGPU_CTX_OP_QUERY_STATE2	4
 
 /* GPU reset status */
 #define AMDGPU_CTX_NO_RESET		0
@@ -170,6 +171,13 @@ union drm_amdgpu_bo_list {
 /* unknown cause */
 #define AMDGPU_CTX_UNKNOWN_RESET	3
 
+/* indicate gpu reset occured after ctx created */
+#define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
+/* indicate vram lost occured after ctx created */
+#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
+/* indicate some job from this context once cause gpu hang */
+#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
+
 /* Context priority level */
 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
@@ -869,6 +877,10 @@ struct drm_amdgpu_info_device {
 	__u32 _pad1;
 	/* always on cu bitmap */
 	__u32 cu_ao_bitmap[4][4];
+	/** Starting high virtual address for UMDs. */
+	__u64 high_va_offset;
+	/** The maximum high virtual address */
+	__u64 high_va_max;
 };
 
 struct drm_amdgpu_info_hw_ip {
diff --git a/include/drm-uapi/armada_drm.h b/include/drm-uapi/armada_drm.h
index 0cb93241..af1c14c8 100644
--- a/include/drm-uapi/armada_drm.h
+++ b/include/drm-uapi/armada_drm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
  * Copyright (C) 2012 Russell King
  *  With inspiration from the i915 driver
diff --git a/include/drm-uapi/etnaviv_drm.h b/include/drm-uapi/etnaviv_drm.h
index 110cc73b..e9b997a0 100644
--- a/include/drm-uapi/etnaviv_drm.h
+++ b/include/drm-uapi/etnaviv_drm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
  * Copyright (C) 2015 Etnaviv Project
  *
diff --git a/include/drm-uapi/exynos_drm.h b/include/drm-uapi/exynos_drm.h
index 2a064d2b..76c34dd5 100644
--- a/include/drm-uapi/exynos_drm.h
+++ b/include/drm-uapi/exynos_drm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
 /* exynos_drm.h
  *
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
diff --git a/include/drm-uapi/i810_drm.h b/include/drm-uapi/i810_drm.h
index 6e6cf86b..d285d5e7 100644
--- a/include/drm-uapi/i810_drm.h
+++ b/include/drm-uapi/i810_drm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 #ifndef _I810_DRM_H_
 #define _I810_DRM_H_
 
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 890df227..7f28eea4 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -86,6 +86,22 @@ enum i915_mocs_table_index {
 	I915_MOCS_CACHED,
 };
 
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
+ * classification of the role of the engine, which may be used when requesting
+ * operations to be performed on a certain subset of engines, or for providing
+ * information about that group.
+ */
+enum drm_i915_gem_engine_class {
+	I915_ENGINE_CLASS_RENDER	= 0,
+	I915_ENGINE_CLASS_COPY		= 1,
+	I915_ENGINE_CLASS_VIDEO		= 2,
+	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
+
+	I915_ENGINE_CLASS_INVALID	= -1
+};
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255	/* table size 2k - maximum due to use
@@ -450,6 +466,27 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
 
+/*
+ * Query whether every context (both per-file default and user created) is
+ * isolated (insofar as HW supports). If this parameter is not true, then
+ * freshly created contexts may inherit values from an existing context,
+ * rather than default HW values. If true, it also ensures (insofar as HW
+ * supports) that all state set by this context will not leak to any other
+ * context.
+ *
+ * As not every engine across every gen support contexts, the returned
+ * value reports the support of context isolation for individual engines by
+ * returning a bitmask of each engine class set to true if that class supports
+ * isolation.
+ */
+#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
+
+/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
+ * registers. This used to be fixed per platform but from CNL onwards, this
+ * might vary depending on the parts.
+ */
+#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
+
 typedef struct drm_i915_getparam {
 	__s32 param;
 	/*
@@ -839,6 +876,7 @@ struct drm_i915_gem_exec_fence {
 
 #define I915_EXEC_FENCE_WAIT            (1<<0)
 #define I915_EXEC_FENCE_SIGNAL          (1<<1)
+#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
 	__u32 flags;
 };
 
diff --git a/include/drm-uapi/omap_drm.h b/include/drm-uapi/omap_drm.h
index fd5e3ea5..1fccffef 100644
--- a/include/drm-uapi/omap_drm.h
+++ b/include/drm-uapi/omap_drm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
  * include/uapi/drm/omap_drm.h
  *
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 48ed48af..68592410 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -27,6 +27,8 @@
 #include "igt_debugfs.h"
 #include "igt_core.h"
 
+#include "i915_drm.h"
+
 void igt_require_hang_ring(int fd, int ring);
 
 typedef struct igt_hang {
@@ -92,15 +94,6 @@ extern const struct intel_execution_engine2 {
 	     (e__)->name; \
 	     (e__)++)
 
-enum drm_i915_gem_engine_class {
-	I915_ENGINE_CLASS_RENDER 	= 0,
-	I915_ENGINE_CLASS_COPY		= 1,
-	I915_ENGINE_CLASS_VIDEO		= 2,
-	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
-
-	I915_ENGINE_CLASS_INVALID	= -1
-};
-
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
diff --git a/lib/meson.build b/lib/meson.build
index d06d85b4..42da7185 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -181,7 +181,8 @@ lib_igt = declare_dependency(link_with : lib_igt_build,
 igt_deps = [ lib_igt ] + lib_deps
 
 lib_igt_perf_build = static_library('igt_perf',
-	['igt_perf.c']
+	['igt_perf.c'],
+	include_directories : inc
 )
 
 lib_igt_perf = declare_dependency(link_with : lib_igt_perf_build,
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 3/7] tests/perf: drop copied i915 defines/structs

[Lionel Landwerlin]

Now that we have drm uapi headers in tree, we can drop this stuff.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 114 ++++-------------------------------------------------------
 1 file changed, 7 insertions(+), 107 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index a161c45d..08ac106a 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -81,106 +81,6 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming interface");
 #define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
 #define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
 
-/* Temporarily copy i915-perf uapi here to avoid a dependency on libdrm's
- * i915_drm.h copy being updated with the i915-perf interface before this
- * test can land in i-g-t.
- *
- * TODO: remove this once the interface lands in libdrm
- */
-#ifndef DRM_I915_PERF_OPEN
-#define DRM_I915_PERF_OPEN		0x36
-#define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
-
-enum drm_i915_oa_format {
-	I915_OA_FORMAT_A13 = 1,     /* HSW only */
-	I915_OA_FORMAT_A29,         /* HSW only */
-	I915_OA_FORMAT_A13_B8_C8,   /* HSW only */
-	I915_OA_FORMAT_B4_C8,       /* HSW only */
-	I915_OA_FORMAT_A45_B8_C8,   /* HSW only */
-	I915_OA_FORMAT_B4_C8_A16,   /* HSW only */
-	I915_OA_FORMAT_C4_B8,       /* HSW+ */
-
-	/* Gen8+ */
-	I915_OA_FORMAT_A12,
-	I915_OA_FORMAT_A12_B8_C8,
-	I915_OA_FORMAT_A32u40_A4u32_B8_C8,
-
-	I915_OA_FORMAT_MAX /* non-ABI */
-};
-
-enum drm_i915_perf_property_id {
-       DRM_I915_PERF_PROP_CTX_HANDLE = 1,
-       DRM_I915_PERF_PROP_SAMPLE_OA,
-       DRM_I915_PERF_PROP_OA_METRICS_SET,
-       DRM_I915_PERF_PROP_OA_FORMAT,
-       DRM_I915_PERF_PROP_OA_EXPONENT,
-
-       DRM_I915_PERF_PROP_MAX /* non-ABI */
-};
-
-struct drm_i915_perf_open_param {
-       __u32 flags;
-#define I915_PERF_FLAG_FD_CLOEXEC	(1<<0)
-#define I915_PERF_FLAG_FD_NONBLOCK	(1<<1)
-#define I915_PERF_FLAG_DISABLED		(1<<2)
-
-       __u32 num_properties;
-       __u64 properties_ptr;
-};
-
-#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
-#define I915_PERF_IOCTL_DISABLE	_IO('i', 0x1)
-
-struct drm_i915_perf_record_header {
-       __u32 type;
-       __u16 pad;
-       __u16 size;
-};
-
-enum drm_i915_perf_record_type {
-       DRM_I915_PERF_RECORD_SAMPLE = 1,
-       DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
-       DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
-
-       DRM_I915_PERF_RECORD_MAX /* non-ABI */
-};
-#endif /* !DRM_I915_PERF_OPEN */
-
-/* There is no ifdef we can use for those formats :( */
-enum {
-	local_I915_OA_FORMAT_A12 = I915_OA_FORMAT_C4_B8 + 1,
-	local_I915_OA_FORMAT_A12_B8_C8 = I915_OA_FORMAT_C4_B8 + 2,
-	local_I915_OA_FORMAT_A32u40_A4u32_B8_C8 = I915_OA_FORMAT_C4_B8 + 3,
-};
-
-#define local_I915_OA_FORMAT_MAX (local_I915_OA_FORMAT_A32u40_A4u32_B8_C8 + 1)
-
-#ifndef DRM_IOCTL_I915_PERF_ADD_CONFIG
-
-#define DRM_I915_PERF_ADD_CONFIG	0x37
-#define DRM_I915_PERF_REMOVE_CONFIG	0x38
-
-#define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
-#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
-
-/**
- * Structure to upload perf dynamic configuration into the kernel.
- */
-struct drm_i915_perf_oa_config {
-	/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
-	char uuid[36];
-
-	__u32 n_mux_regs;
-	__u32 n_boolean_regs;
-	__u32 n_flex_regs;
-
-	__u64 mux_regs_ptr;
-	__u64 boolean_regs_ptr;
-	__u64 flex_regs_ptr;
-};
-
-#endif /* !DRM_IOCTL_I915_PERF_ADD_CONFIG */
-
 struct accumulator {
 #define MAX_RAW_OA_COUNTERS 62
 	enum drm_i915_oa_format format;
@@ -203,7 +103,7 @@ struct oa_format {
 	int n_c;
 };
 
-static struct oa_format hsw_oa_formats[local_I915_OA_FORMAT_MAX] = {
+static struct oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = {
 	[I915_OA_FORMAT_A13] = { /* HSW only */
 		"A13", .size = 64,
 		.a_off = 12, .n_a = 13, },
@@ -235,16 +135,16 @@ static struct oa_format hsw_oa_formats[local_I915_OA_FORMAT_MAX] = {
 		.b_off = 28, .n_b = 8 },
 };
 
-static struct oa_format gen8_oa_formats[local_I915_OA_FORMAT_MAX] = {
-	[local_I915_OA_FORMAT_A12] = {
+static struct oa_format gen8_oa_formats[I915_OA_FORMAT_MAX] = {
+	[I915_OA_FORMAT_A12] = {
 		"A12", .size = 64,
 		.a_off = 12, .n_a = 12, .first_a = 7, },
-	[local_I915_OA_FORMAT_A12_B8_C8] = {
+	[I915_OA_FORMAT_A12_B8_C8] = {
 		"A12_B8_C8", .size = 128,
 		.a_off = 12, .n_a = 12,
 		.b_off = 64, .n_b = 8,
 		.c_off = 96, .n_c = 8, .first_a = 7, },
-	[local_I915_OA_FORMAT_A32u40_A4u32_B8_C8] = {
+	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = {
 		"A32u40_A4u32_B8_C8", .size = 256,
 		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
 		.a_off = 144, .n_a = 4, .first_a = 32,
@@ -368,7 +268,7 @@ __perf_open(int fd, struct drm_i915_perf_open_param *param, bool prevent_pm)
 static int
 lookup_format(int i915_perf_fmt_id)
 {
-	igt_assert(i915_perf_fmt_id < local_I915_OA_FORMAT_MAX);
+	igt_assert(i915_perf_fmt_id < I915_OA_FORMAT_MAX);
 	igt_assert(get_oa_format(i915_perf_fmt_id).name);
 
 	return i915_perf_fmt_id;
@@ -1104,7 +1004,7 @@ init_sys_info(void)
 		drm_i915_getparam_t gp;
 
 		test_set_name = "TestOa";
-		test_oa_format = local_I915_OA_FORMAT_A32u40_A4u32_B8_C8;
+		test_oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
 		undefined_a_counters = gen8_undefined_a_counters;
 		read_report_ticks = gen8_read_report_ticks;
 		sanity_check_reports = gen8_sanity_check_test_oa_reports;
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 4/7] tests/perf: factorize max oa buffer size define

[Lionel Landwerlin]

We use this value in several places.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 08ac106a..7f988d7c 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -81,6 +81,8 @@ IGT_TEST_DESCRIPTION("Test the i915 perf metrics streaming interface");
 #define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
 #define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
 
+#define MAX_OA_BUF_SIZE (16 * 1024 * 1024)
+
 struct accumulator {
 #define MAX_RAW_OA_COUNTERS 62
 	enum drm_i915_oa_format format;
@@ -1336,7 +1338,7 @@ read_2_oa_reports(int format_id,
 	 * to indicate that the OA unit may be over taxed if lots of reports
 	 * are being lost.
 	 */
-	int max_reports = (16 * 1024 * 1024) / format_size;
+	int max_reports = MAX_OA_BUF_SIZE / format_size;
 	int buf_size = sample_size * max_reports * 1.5;
 	uint8_t *buf = malloc(buf_size);
 	int n = 0;
@@ -2654,7 +2656,7 @@ test_buffer_fill(void)
 	int buf_size = 65536 * (256 + sizeof(struct drm_i915_perf_record_header));
 	uint8_t *buf = malloc(buf_size);
 	int len;
-	size_t oa_buf_size = 16 * 1024 * 1024;
+	size_t oa_buf_size = MAX_OA_BUF_SIZE;
 	size_t report_size = get_oa_format(test_oa_format).size;
 	int n_full_oa_reports = oa_buf_size / report_size;
 	uint64_t fill_duration = n_full_oa_reports * oa_period;
@@ -2823,7 +2825,7 @@ test_enable_disable(void)
 	};
 	int buf_size = 65536 * (256 + sizeof(struct drm_i915_perf_record_header));
 	uint8_t *buf = malloc(buf_size);
-	size_t oa_buf_size = 16 * 1024 * 1024;
+	size_t oa_buf_size = MAX_OA_BUF_SIZE;
 	size_t report_size = get_oa_format(test_oa_format).size;
 	int n_full_oa_reports = oa_buf_size / report_size;
 	uint64_t fill_duration = n_full_oa_reports * oa_period;
@@ -3518,7 +3520,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 	size_t format_size = get_oa_format(test_oa_format).size;
 	size_t sample_size = (sizeof(struct drm_i915_perf_record_header) +
 			      format_size);
-	int max_reports = (16 * 1024 * 1024) / format_size;
+	int max_reports = MAX_OA_BUF_SIZE / format_size;
 	int buf_size = sample_size * max_reports * 1.5;
 	int child_ret;
 	uint8_t *buf = malloc(buf_size);
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 5/7] tests/perf: query CS timestamp frequency if available

[Lionel Landwerlin]

On Cannonlake+ the CS timestamp frequency might vary from one part to
another. We have a new param to query this from the kernel (which
reads the value from registers).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 7f988d7c..ef37ceb3 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -969,6 +969,29 @@ gen8_sanity_check_test_oa_reports(uint32_t *oa_report0, uint32_t *oa_report1,
 	}
 }
 
+static uint64_t
+get_cs_timestamp_frequency(void)
+{
+	int cs_ts_freq = 0;
+	drm_i915_getparam_t gp;
+
+	gp.param = I915_PARAM_CS_TIMESTAMP_FREQUENCY;
+	gp.value = &cs_ts_freq;
+	if (igt_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp) == 0)
+		return cs_ts_freq;
+
+	igt_debug("Couldn't query CS timestamp frequency, trying to guess based on PCI-id\n");
+
+	if (IS_GEN7(devid) || IS_GEN8(devid))
+		return 12500000;
+	if (IS_SKYLAKE(devid) || IS_KABYLAKE(devid) || IS_COFFEELAKE(devid))
+		return 12000000;
+	if (IS_BROXTON(devid) || IS_GEMINILAKE(devid))
+		return 19200000;
+
+	igt_assert(!"You need to run this on a kernel with PARAM_CS_TIMESTAMP_FREQUENCY support\n");
+}
+
 static bool
 init_sys_info(void)
 {
@@ -979,7 +1002,8 @@ init_sys_info(void)
 	igt_assert_neq(card, -1);
 	igt_assert_neq(devid, 0);
 
-	timestamp_frequency = 12500000;
+	timestamp_frequency = get_cs_timestamp_frequency();
+	igt_assert_neq(timestamp_frequency, 0);
 
 	if (IS_HASWELL(devid)) {
 		/* We don't have a TestOa metric set for Haswell so use
@@ -1030,10 +1054,8 @@ init_sys_info(void)
 				igt_debug("unsupported Skylake GT size\n");
 				return false;
 			}
-			timestamp_frequency = 12000000;
 		} else if (IS_BROXTON(devid)) {
 			test_set_uuid = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
-			timestamp_frequency = 19200000;
 		} else if (IS_KABYLAKE(devid)) {
 			switch (intel_gt(devid)) {
 			case 1:
@@ -1046,10 +1068,8 @@ init_sys_info(void)
 				igt_debug("unsupported Kabylake GT size\n");
 				return false;
 			}
-			timestamp_frequency = 12000000;
 		} else if (IS_GEMINILAKE(devid)) {
 			test_set_uuid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
-			timestamp_frequency = 19200000;
 		} else if (IS_COFFEELAKE(devid)) {
 			switch (intel_gt(devid)) {
 			case 1:
@@ -1059,7 +1079,6 @@ init_sys_info(void)
 				igt_debug("unsupported Cannonlake GT size\n");
 				return false;
 			}
-			timestamp_frequency = 12000000;
 		} else {
 			igt_debug("unsupported GT\n");
 			return false;
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 6/7] tests/perf: enable testing on Coffelake GT3

[Lionel Landwerlin]

Add the test config uuid for GT3.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index ef37ceb3..cc0c21a1 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1075,8 +1075,11 @@ init_sys_info(void)
 			case 1:
 				test_set_uuid = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
 				break;
+			case 2:
+				test_set_uuid = "577e8e2c-3fa0-4875-8743-3538d585e3b0";
+				break;
 			default:
-				igt_debug("unsupported Cannonlake GT size\n");
+				igt_debug("unsupported Coffeelake GT size\n");
 				return false;
 			}
 		} else {
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t v2 7/7] tests/perf: add test config uuid for Cannonlake

[Lionel Landwerlin]

This will enable running the tests on Cannonlake.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index cc0c21a1..99bcdc72 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -1082,6 +1082,8 @@ init_sys_info(void)
 				igt_debug("unsupported Coffeelake GT size\n");
 				return false;
 			}
+		} else if (IS_CANNONLAKE(devid)) {
+			test_set_uuid = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
 		} else {
 			igt_debug("unsupported GT\n");
 			return false;
-- 
2.15.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for tests/perf: Enable i915 perf tests on CNL (rev2)

[Patchwork]

== Series Details ==

Series: tests/perf: Enable i915 perf tests on CNL (rev2)
URL   : https://patchwork.freedesktop.org/series/35067/
State : failure

== Summary ==

IGT patchset build failed on latest successful build
2fc64acf8a4465d5eab3d6cfec9b3c1b5df30d73 igt/perf_pmu: Tweak wait_for_rc6, yet again

Making all in .
make[3]: Nothing to be done for 'all-am'.
Making all in drm-uapi
make[3]: Nothing to be done for 'all'.
Making all in tests
Making all in intel-ci
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all-am'.
Making all in assembler
make  all-recursive
Making all in doc
make[4]: Nothing to be done for 'all'.
Making all in test
make[4]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all-am'.
Making all in overlay
  CC       gem-interrupts.o
In file included from ./../lib/igt_perf.h:32:0,
                 from gem-interrupts.c:34:
./../lib/igt_gt.h:99:16: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
           enum drm_i915_gem_engine_class class,
                ^~~~~~~~~~~~~~~~~~~~~~~~~
./../lib/igt_gt.h:103:12: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
       enum drm_i915_gem_engine_class class,
            ^~~~~~~~~~~~~~~~~~~~~~~~~
./../lib/igt_gt.h:108:9: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
    enum drm_i915_gem_engine_class class,
         ^~~~~~~~~~~~~~~~~~~~~~~~~
./../lib/igt_gt.h:108:35: error: parameter 2 (‘class’) has incomplete type
    enum drm_i915_gem_engine_class class,
                                   ^~~~~
./../lib/igt_gt.h:107:6: warning: function declaration isn’t a prototype [-Wstrict-prototypes]
 void gem_require_engine(int gem_fd,
      ^~~~~~~~~~~~~~~~~~
In file included from ./../lib/igt_gt.h:28:0,
                 from ./../lib/igt_perf.h:32,
                 from gem-interrupts.c:34:
./../lib/igt_gt.h: In function ‘gem_require_engine’:
./../lib/igt_gt.h:111:37: error: type of formal parameter 2 is incomplete
  igt_require(gem_has_engine(gem_fd, class, instance));
                                     ^
./../lib/igt_core.h:613:8: note: in definition of macro ‘igt_require’
  if (!(expr)) igt_skip_check(#expr , NULL); \
        ^~~~
Makefile:594: recipe for target 'gem-interrupts.o' failed
make[2]: *** [gem-interrupts.o] Error 1
Makefile:531: recipe for target 'all-recursive' failed
make[1]: *** [all-recursive] Error 1
Makefile:463: recipe for target 'all' failed
make: *** [all] Error 2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 4/7] tests/perf: factorize max oa buffer size define

[Matthew Auld]

On 8 December 2017 at 11:39, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> We use this value in several places.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.BAT: failure for tests/perf: Enable i915 perf tests on CNL (rev2)

[Lionel Landwerlin]

Apologies, I've fixed this locally and will send a v3 with the fix.

On 08/12/17 13:25, Patchwork wrote:
> == Series Details ==
>
> Series: tests/perf: Enable i915 perf tests on CNL (rev2)
> URL   : https://patchwork.freedesktop.org/series/35067/
> State : failure
>
> == Summary ==
>
> IGT patchset build failed on latest successful build
> 2fc64acf8a4465d5eab3d6cfec9b3c1b5df30d73 igt/perf_pmu: Tweak wait_for_rc6, yet again
>
> Making all in .
> make[3]: Nothing to be done for 'all-am'.
> Making all in drm-uapi
> make[3]: Nothing to be done for 'all'.
> Making all in tests
> Making all in intel-ci
> make[3]: Nothing to be done for 'all'.
> make[3]: Nothing to be done for 'all-am'.
> Making all in assembler
> make  all-recursive
> Making all in doc
> make[4]: Nothing to be done for 'all'.
> Making all in test
> make[4]: Nothing to be done for 'all'.
> make[4]: Nothing to be done for 'all-am'.
> Making all in overlay
>    CC       gem-interrupts.o
> In file included from ./../lib/igt_perf.h:32:0,
>                   from gem-interrupts.c:34:
> ./../lib/igt_gt.h:99:16: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
>             enum drm_i915_gem_engine_class class,
>                  ^~~~~~~~~~~~~~~~~~~~~~~~~
> ./../lib/igt_gt.h:103:12: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
>         enum drm_i915_gem_engine_class class,
>              ^~~~~~~~~~~~~~~~~~~~~~~~~
> ./../lib/igt_gt.h:108:9: warning: ‘enum drm_i915_gem_engine_class’ declared inside parameter list will not be visible outside of this definition or declaration
>      enum drm_i915_gem_engine_class class,
>           ^~~~~~~~~~~~~~~~~~~~~~~~~
> ./../lib/igt_gt.h:108:35: error: parameter 2 (‘class’) has incomplete type
>      enum drm_i915_gem_engine_class class,
>                                     ^~~~~
> ./../lib/igt_gt.h:107:6: warning: function declaration isn’t a prototype [-Wstrict-prototypes]
>   void gem_require_engine(int gem_fd,
>        ^~~~~~~~~~~~~~~~~~
> In file included from ./../lib/igt_gt.h:28:0,
>                   from ./../lib/igt_perf.h:32,
>                   from gem-interrupts.c:34:
> ./../lib/igt_gt.h: In function ‘gem_require_engine’:
> ./../lib/igt_gt.h:111:37: error: type of formal parameter 2 is incomplete
>    igt_require(gem_has_engine(gem_fd, class, instance));
>                                       ^
> ./../lib/igt_core.h:613:8: note: in definition of macro ‘igt_require’
>    if (!(expr)) igt_skip_check(#expr , NULL); \
>          ^~~~
> Makefile:594: recipe for target 'gem-interrupts.o' failed
> make[2]: *** [gem-interrupts.o] Error 1
> Makefile:531: recipe for target 'all-recursive' failed
> make[1]: *** [all-recursive] Error 1
> Makefile:463: recipe for target 'all' failed
> make: *** [all] Error 2
>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 5/7] tests/perf: query CS timestamp frequency if available

[Matthew Auld]

On 8 December 2017 at 11:39, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> On Cannonlake+ the CS timestamp frequency might vary from one part to
> another. We have a new param to query this from the kernel (which
> reads the value from registers).
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 6/7] tests/perf: enable testing on Coffelake GT3

[Matthew Auld]

On 8 December 2017 at 11:39, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> Add the test config uuid for GT3.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

s/Coffelake/Coffeelake/

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 7/7] tests/perf: add test config uuid for Cannonlake

[Matthew Auld]

On 8 December 2017 at 11:39, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> This will enable running the tests on Cannonlake.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Missing the CS timestamp frequency fallback for CNL in
get_cs_timestamp_frequency().

Otherwise:
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 7/7] tests/perf: add test config uuid for Cannonlake

[Lionel Landwerlin]

On 08/12/17 13:50, Matthew Auld wrote:
> On 8 December 2017 at 11:39, Lionel Landwerlin
> <lionel.g.landwerlin@intel.com> wrote:
>> This will enable running the tests on Cannonlake.
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Missing the CS timestamp frequency fallback for CNL in
> get_cs_timestamp_frequency().

The point is that if we can't read it from the kernel, the tests better 
fail.
It seems like 50% of the parts I've seen so far are clocked like BXT and 
the other 50% like SKL/KBL.
The tests will fail if we run with the wrong assumed frequency.

>
> Otherwise:
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t v2 7/7] tests/perf: add test config uuid for Cannonlake

[Lionel Landwerlin]

On 08/12/17 13:54, Lionel Landwerlin wrote:
> On 08/12/17 13:50, Matthew Auld wrote:
>> On 8 December 2017 at 11:39, Lionel Landwerlin
>> <lionel.g.landwerlin@intel.com> wrote:
>>> This will enable running the tests on Cannonlake.
>>>
>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Missing the CS timestamp frequency fallback for CNL in
>> get_cs_timestamp_frequency().
>
> The point is that if we can't read it from the kernel, the tests 
> better fail.
> It seems like 50% of the parts I've seen so far are clocked like BXT 
> and the other 50% like SKL/KBL.
> The tests will fail if we run with the wrong assumed frequency.

Actually I probably want to replace that assert with a skip!

>
>>
>> Otherwise:
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx