* [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes
@ 2022-01-28 14:56 Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
` (6 more replies)
0 siblings, 7 replies; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
In adding our first X-extension (i.e., vendor-defined) on RISC-V with
XVentanaCondOps, we need to add a few instructure improvements to make
it easier to add similar vendor-defined extensions in the future:
- refactor access to the cfg->ext_* fields by making a pointer to the
cfg structure (as cfg_ptr) available via DisasContext
- add a table-based list of decoders to invoke, each being guarded by
a guard/predicate-function, that can be used to either add vendor
extensions, large extensions or override (by listing the decoder
before the one for standard extensions) patterns to handle errata
Changes in v3:
- (new patch) refactor 'struct RISCVCPUConfig'
- (new patch) copy pointer to element cfg into DisasContext
- (new patch) test extension-availability through cfg_ptr in
DisasContext, removing the fields that have been copied into
DisasContext directly
- (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
into DisasContext) instead of going throuhg RISCV_CPU
- expose only the DisasContext* to predicate functions
- mark the table of decoder functions as static
- drop the inline from always_true_p, until the need arises (i.e.,
someone finds a use for it and calls it directly)
- rewrite to drop the 'handled' temporary in iterating over the
decoder table, removing the assignment in the condition of the if
- rename to trans_xventanacondops.c.inc (i.e. with the '.c')
- (in MATERIALISE_EXT_PREDICATE) don't annotate the predicate function
for testing the availability of individual extensions as 'inline'
and don't make CPURISCVState* visible to these predicate functions
- add a MAINTAINERS entry for XVentanaCondOps
Changes in v2:
- (new patch) iterate over a table of guarded decoder functions
- Split off decode table into XVentanaCondOps.decode
- Wire up XVentanaCondOps in the decoder-table
Philipp Tomsich (7):
target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct
RISCVCPUConfig'
target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into
cfg_ptr
target/riscv: access configuration through cfg_ptr in DisasContext
target/riscv: access cfg structure through DisasContext
target/riscv: iterate over a table of decoders
target/riscv: Add XVentanaCondOps custom extension
target/riscv: add a MAINTAINERS entry for XVentanaCondOps
MAINTAINERS | 7 ++
target/riscv/XVentanaCondOps.decode | 25 +++++
target/riscv/cpu.c | 3 +
target/riscv/cpu.h | 79 ++++++-------
target/riscv/insn_trans/trans_rvb.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++---------
target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-
.../insn_trans/trans_xventanacondops.c.inc | 39 +++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 62 +++++++----
11 files changed, 218 insertions(+), 116 deletions(-)
create mode 100644 target/riscv/XVentanaCondOps.decode
create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc
--
2.33.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 20:52 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
Changes in v3:
- (new patch) refactor 'struct RISCVCPUConfig'
target/riscv/cpu.h | 76 ++++++++++++++++++++++++----------------------
1 file changed, 39 insertions(+), 37 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..9c795089b6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -303,6 +303,44 @@ struct RISCVCPUClass {
DeviceReset parent_reset;
};
+struct RISCVCPUConfig {
+ bool ext_i;
+ bool ext_e;
+ bool ext_g;
+ bool ext_m;
+ bool ext_a;
+ bool ext_f;
+ bool ext_d;
+ bool ext_c;
+ bool ext_s;
+ bool ext_u;
+ bool ext_h;
+ bool ext_j;
+ bool ext_v;
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbs;
+ bool ext_counters;
+ bool ext_ifencei;
+ bool ext_icsr;
+ bool ext_zfh;
+ bool ext_zfhmin;
+ bool ext_zve32f;
+ bool ext_zve64f;
+
+ char *priv_spec;
+ char *user_spec;
+ char *bext_spec;
+ char *vext_spec;
+ uint16_t vlen;
+ uint16_t elen;
+ bool mmu;
+ bool pmp;
+ bool epmp;
+ uint64_t resetvec;
+};
+
/**
* RISCVCPU:
* @env: #CPURISCVState
@@ -320,43 +358,7 @@ struct RISCVCPU {
char *dyn_vreg_xml;
/* Configuration Settings */
- struct {
- bool ext_i;
- bool ext_e;
- bool ext_g;
- bool ext_m;
- bool ext_a;
- bool ext_f;
- bool ext_d;
- bool ext_c;
- bool ext_s;
- bool ext_u;
- bool ext_h;
- bool ext_j;
- bool ext_v;
- bool ext_zba;
- bool ext_zbb;
- bool ext_zbc;
- bool ext_zbs;
- bool ext_counters;
- bool ext_ifencei;
- bool ext_icsr;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zve32f;
- bool ext_zve64f;
-
- char *priv_spec;
- char *user_spec;
- char *bext_spec;
- char *vext_spec;
- uint16_t vlen;
- uint16_t elen;
- bool mmu;
- bool pmp;
- bool epmp;
- uint64_t resetvec;
- } cfg;
+ struct RISCVCPUConfig cfg;
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 20:53 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
Changes in v3:
- (new patch) copy pointer to element cfg into DisasContext
target/riscv/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..22d09af2df 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@ typedef struct DisasContext {
int frm;
RISCVMXL ol;
bool virt_enabled;
+ const struct RISCVCPUConfig *cfg_ptr;
bool ext_ifencei;
bool ext_zfh;
bool ext_zfhmin;
@@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#endif
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
+ ctx->cfg_ptr = &(cpu->cfg);
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
Changes in v3:
- (new patch) test extension-availability through cfg_ptr in
DisasContext, removing the fields that have been copied into
DisasContext directly
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++++-----------
target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-
target/riscv/translate.c | 14 ---
4 files changed, 55 insertions(+), 69 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 3cd1b3f877..f1342f30f8 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -806,7 +806,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
{
- if (!ctx->ext_ifencei) {
+ if (!ctx->cfg_ptr->ext_ifencei) {
return false;
}
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f85a9e83b4..ff09e345ad 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -74,7 +74,7 @@ static bool require_zve32f(DisasContext *s)
}
/* Zve32f doesn't support FP64. (Section 18.2) */
- return s->ext_zve32f ? s->sew <= MO_32 : true;
+ return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
}
static bool require_scale_zve32f(DisasContext *s)
@@ -85,7 +85,7 @@ static bool require_scale_zve32f(DisasContext *s)
}
/* Zve32f doesn't support FP64. (Section 18.2) */
- return s->ext_zve64f ? s->sew <= MO_16 : true;
+ return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
}
static bool require_zve64f(DisasContext *s)
@@ -96,7 +96,7 @@ static bool require_zve64f(DisasContext *s)
}
/* Zve64f doesn't support FP64. (Section 18.2) */
- return s->ext_zve64f ? s->sew <= MO_32 : true;
+ return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
}
static bool require_scale_zve64f(DisasContext *s)
@@ -107,7 +107,7 @@ static bool require_scale_zve64f(DisasContext *s)
}
/* Zve64f doesn't support FP64. (Section 18.2) */
- return s->ext_zve64f ? s->sew <= MO_16 : true;
+ return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
}
/* Destination vector register group cannot overlap source mask register. */
@@ -174,7 +174,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
TCGv s1, dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || s->cfg_ptr->ext_zve64f)) {
return false;
}
@@ -210,7 +210,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
TCGv dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || s->cfg_ptr->ext_zve64f)) {
return false;
}
@@ -248,7 +248,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{
- return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
+ return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8;
}
/* check functions */
@@ -318,7 +318,7 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
* when XLEN=32. (Section 18.2)
*/
if (get_xl(s) == MXL_RV32) {
- ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
+ ret &= (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
}
return ret;
@@ -454,7 +454,7 @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm)
{
return (s->lmul <= 2) &&
(s->sew < MO_64) &&
- ((s->sew + 1) <= (s->elen >> 4)) &&
+ ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
require_align(vd, s->lmul + 1) &&
require_vm(vm, vd);
}
@@ -482,7 +482,7 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
{
return (s->lmul <= 2) &&
(s->sew < MO_64) &&
- ((s->sew + 1) <= (s->elen >> 4)) &&
+ ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
require_align(vs2, s->lmul + 1) &&
require_align(vd, s->lmul) &&
require_vm(vm, vd);
@@ -661,7 +661,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
*/
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -819,7 +819,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
stride = get_gpr(s, rs2, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -925,7 +925,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
@@ -1065,7 +1065,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -1120,7 +1120,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -1185,7 +1185,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
static inline uint32_t MAXSZ(DisasContext *s)
{
int scale = s->lmul - 3;
- return scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+ return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -1220,7 +1220,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn);
}
mark_vs_dirty(s);
gen_set_label(over);
@@ -1262,7 +1262,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -1425,7 +1425,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -1508,7 +1508,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- cpu_env, s->vlen / 8, s->vlen / 8,
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
data, fn);
mark_vs_dirty(s);
gen_set_label(over);
@@ -1587,7 +1587,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
- cpu_env, s->vlen / 8, s->vlen / 8, data, fn);
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -1663,7 +1663,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -1843,7 +1843,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -1963,7 +1963,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
- (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
}
static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
@@ -1976,7 +1976,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
- (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
}
GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
@@ -2046,7 +2046,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, s->vlen / 8, s->vlen / 8, data,
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data,
fns[s->sew]);
gen_set_label(over);
}
@@ -2083,7 +2083,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
};
tcg_gen_ext_tl_i64(s1_i64, s1);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1_i64, cpu_env, desc);
@@ -2123,7 +2123,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
s1 = tcg_constant_i64(simm);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, cpu_env, desc);
@@ -2176,7 +2176,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
- (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
}
static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
@@ -2187,7 +2187,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
- (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
}
GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
@@ -2275,7 +2275,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2302,7 +2302,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -2391,7 +2391,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2464,7 +2464,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2583,7 +2583,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
- s->vlen / 8, s->vlen / 8, data, fn);
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -2696,7 +2696,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
do_nanbox(s, t1, cpu_fpr[a->rs1]);
dest = tcg_temp_new_ptr();
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, t1, cpu_env, desc);
@@ -2782,7 +2782,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2831,7 +2831,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2896,7 +2896,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2947,7 +2947,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -2986,7 +2986,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_check(s, a) && (s->sew < MO_64) &&
- ((s->sew + 1) <= (s->elen >> 4));
+ ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
}
GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
@@ -3034,7 +3034,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
- s->vlen / 8, s->vlen / 8, data, fn); \
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); \
mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
@@ -3067,7 +3067,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
dst = dest_gpr(s, a->rd);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -3099,7 +3099,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
dst = dest_gpr(s, a->rd);
- desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+ desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -3134,7 +3134,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
- cpu_env, s->vlen / 8, s->vlen / 8, \
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \
data, fn); \
mark_vs_dirty(s); \
gen_set_label(over); \
@@ -3174,7 +3174,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
};
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
- s->vlen / 8, s->vlen / 8, data, fns[s->sew]);
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
return true;
@@ -3200,7 +3200,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
gen_helper_vid_v_w, gen_helper_vid_v_d,
};
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
- cpu_env, s->vlen / 8, s->vlen / 8,
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,
data, fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
@@ -3554,7 +3554,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+ int vlmax = scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3586,7 +3586,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+ int vlmax = scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
@@ -3638,7 +3638,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
- cpu_env, s->vlen / 8, s->vlen / 8, data,
+ cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data,
fns[s->sew]);
mark_vs_dirty(s);
gen_set_label(over);
@@ -3657,7 +3657,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
if (require_rvv(s) && \
QEMU_IS_ALIGNED(a->rd, LEN) && \
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
- uint32_t maxsz = (s->vlen >> 3) * LEN; \
+ uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
if (s->vstart == 0) { \
/* EEW = 8 */ \
tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
@@ -3742,7 +3742,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
- s->vlen / 8, s->vlen / 8, data, fn);
+ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn);
mark_vs_dirty(s);
gen_set_label(over);
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 5a7cac8958..608c51da2c 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -17,13 +17,13 @@
*/
#define REQUIRE_ZFH(ctx) do { \
- if (!ctx->ext_zfh) { \
+ if (!ctx->cfg_ptr->ext_zfh) { \
return false; \
} \
} while (0)
#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
- if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \
+ if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
return false; \
} \
} while (0)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 22d09af2df..441690846c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -77,11 +77,6 @@ typedef struct DisasContext {
RISCVMXL ol;
bool virt_enabled;
const struct RISCVCPUConfig *cfg_ptr;
- bool ext_ifencei;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zve32f;
- bool ext_zve64f;
bool hlsx;
/* vector extension */
bool vill;
@@ -99,8 +94,6 @@ typedef struct DisasContext {
*/
int8_t lmul;
uint8_t sew;
- uint16_t vlen;
- uint16_t elen;
target_ulong vstart;
bool vl_eq_vlmax;
uint8_t ntemp;
@@ -910,13 +903,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->cfg_ptr = &(cpu->cfg);
- ctx->ext_ifencei = cpu->cfg.ext_ifencei;
- ctx->ext_zfh = cpu->cfg.ext_zfh;
- ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
- ctx->ext_zve32f = cpu->cfg.ext_zve32f;
- ctx->ext_zve64f = cpu->cfg.ext_zve64f;
- ctx->vlen = cpu->cfg.vlen;
- ctx->elen = cpu->cfg.elen;
ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
` (2 preceding siblings ...)
2022-01-28 14:56 ` [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
Changes in v3:
- (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
into DisasContext) instead of going throuhg RISCV_CPU
target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 810431a1d6..f9bd3b7ec4 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -19,25 +19,25 @@
*/
#define REQUIRE_ZBA(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
+ if (ctx->cfg_ptr->ext_zba) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBB(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
+ if (ctx->cfg_ptr->ext_zbb) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBC(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
+ if (ctx->cfg_ptr->ext_zbc) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBS(ctx) do { \
- if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
+ if (ctx->cfg_ptr->ext_zbs) { \
return false; \
} \
} while (0)
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/7] target/riscv: iterate over a table of decoders
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
` (3 preceding siblings ...)
2022-01-28 14:56 ` [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 20:56 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v3:
- expose only the DisasContext* to predicate functions
- mark the table of decoder functions as static
- drop the inline from always_true_p, until the need arises (i.e.,
someone finds a use for it and calls it directly)
- rewrite to drop the 'handled' temporary in iterating over the
decoder table, removing the assignment in the condition of the if
Changes in v2:
- (new patch) iterate over a table of guarded decoder functions
target/riscv/translate.c | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 441690846c..38fdec2fd9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -111,6 +111,11 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa_ext & ext;
}
+static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
+{
+ return true;
+}
+
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -855,16 +860,26 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
- /* check for compressed insn */
+ /*
+ * A table with predicate (i.e., guard) functions and decoder functions
+ * that are tested in-order until a decoder matches onto the opcode.
+ */
+ static const struct {
+ bool (*guard_func)(DisasContext *);
+ bool (*decode_func)(DisasContext *, uint32_t);
+ } decoders[] = {
+ { always_true_p, decode_insn32 },
+ };
+
+ /* Check for compressed insn */
if (extract16(opcode, 0, 2) != 3) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (!decode_insn16(ctx, opcode)) {
- gen_exception_illegal(ctx);
- }
+ if (decode_insn16(ctx, opcode))
+ return;
}
} else {
uint32_t opcode32 = opcode;
@@ -873,10 +888,17 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- if (!decode_insn32(ctx, opcode32)) {
- gen_exception_illegal(ctx);
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+ if (!decoders[i].guard_func(ctx))
+ continue;
+
+ if (decoders[i].decode_func(ctx, opcode32))
+ return;
}
}
+
+ gen_exception_illegal(ctx);
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
` (4 preceding siblings ...)
2022-01-28 14:56 ` [PATCH v3 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v3:
- rename to trans_xventanacondops.c.inc (i.e. with the '.c')
- (in MATERIALISE_EXT_PREDICATE) don't annotate the predicate function
for testing the availability of individual extensions as 'inline'
and don't make CPURISCVState* visible to these predicate functions
Changes in v2:
- Split off decode table into XVentanaCondOps.decode
- Wire up XVentanaCondOps in the decoder-table
target/riscv/XVentanaCondOps.decode | 25 ++++++++++++
target/riscv/cpu.c | 3 ++
target/riscv/cpu.h | 3 ++
.../insn_trans/trans_xventanacondops.c.inc | 39 +++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 12 ++++++
6 files changed, 83 insertions(+)
create mode 100644 target/riscv/XVentanaCondOps.decode
create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc
diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode
new file mode 100644
index 0000000000..5aef7c3d72
--- /dev/null
+++ b/target/riscv/XVentanaCondOps.decode
@@ -0,0 +1,25 @@
+#
+# RISC-V translation routines for the XVentanaCondOps extension
+#
+# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: VTx-family custom instructions
+# Custom ISA extensions for Ventana Micro Systems RISC-V cores
+# (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
+
+# Fields
+%rs2 20:5
+%rs1 15:5
+%rd 7:5
+
+# Argument sets
+&r rd rs1 rs2 !extern
+
+# Formats
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
+
+# *** RV64 Custom-3 Extension ***
+vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r
+vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1cb0436187..6df07b8289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -734,6 +734,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ /* Vendor-specific custom extensions */
+ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9c795089b6..ccf9ea9922 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,9 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+ /* Vendor-specific custom extensions */
+ bool ext_XVentanaCondOps;
+
char *priv_spec;
char *user_spec;
char *bext_spec;
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
new file mode 100644
index 0000000000..b8a5d031b5
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -0,0 +1,39 @@
+/*
+ * RISC-V translation routines for the XVentanaCondOps extension.
+ *
+ * Copyright (c) 2021-2022 VRULL GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
+{
+ return gen_condmask(ctx, a, TCG_COND_NE);
+}
+
+static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
+{
+ return gen_condmask(ctx, a, TCG_COND_EQ);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a3997ed580..91f0ac32ff 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -4,6 +4,7 @@ dir = meson.current_source_dir()
gen = [
decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
]
riscv_ss = ss.source_set()
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 38fdec2fd9..89cf96b2e6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -116,6 +116,14 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
return true;
}
+#define MATERIALISE_EXT_PREDICATE(ext) \
+ static bool has_ ## ext ## _p(DisasContext *ctx) \
+ { \
+ return ctx->cfg_ptr->ext_ ## ext ; \
+ }
+
+MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
+
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -854,9 +862,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_xventanacondops.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
+/* Include decoders for factored-out extensions */
+#include "decode-XVentanaCondOps.c.inc"
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
@@ -869,6 +880,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
bool (*decode_func)(DisasContext *, uint32_t);
} decoders[] = {
{ always_true_p, decode_insn32 },
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
};
/* Check for compressed insn */
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
` (5 preceding siblings ...)
2022-01-28 14:56 ` [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
@ 2022-01-28 14:56 ` Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
6 siblings, 1 reply; 15+ messages in thread
From: Philipp Tomsich @ 2022-01-28 14:56 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, Greg Favor, Alistair Francis, Kito Cheng,
Philipp Tomsich
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v3:
- add a MAINTAINERS entry for XVentanaCondOps
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e4b3a4bcdf..2ffcc5a87b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,13 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RISC-V XVentanaCondOps extension
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/XVentanaCondOps.decode
+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
S: Orphan
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
@ 2022-01-30 20:52 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 20:52 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> + struct RISCVCPUConfig cfg;
Coding style says use a typedef for the struct.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
2022-01-28 14:56 ` [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
@ 2022-01-30 20:53 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 20:53 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> As the number of extensions is growing, copying them individiually
> into the DisasContext will scale less and less... instead we populate
> a pointer to the RISCVCPUConfig structure in the DisasContext.
>
> This adds an extra indirection when checking for the availability of
> an extension (compared to copying the fields into DisasContext).
> While not a performance problem today, we can always (shallow) copy
> the entire structure into the DisasContext (instead of putting a
> pointer to it) if this is ever deemed necessary.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>
> ---
>
> Changes in v3:
> - (new patch) copy pointer to element cfg into DisasContext
>
> target/riscv/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext
2022-01-28 14:56 ` [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
@ 2022-01-30 20:54 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 20:54 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
> copies (in DisasContext) of some of the elements available in the
> RISCVCPUConfig structure. This commit redirects accesses to use the
> cfg_ptr copied into DisasContext and removes the shallow copies.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>
> ---
>
> Changes in v3:
> - (new patch) test extension-availability through cfg_ptr in
> DisasContext, removing the fields that have been copied into
> DisasContext directly
>
> target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++++-----------
> target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-
> target/riscv/translate.c | 14 ---
> 4 files changed, 55 insertions(+), 69 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext
2022-01-28 14:56 ` [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
@ 2022-01-30 20:54 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 20:54 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> The Zb[abcs] support code still uses the RISCV_CPU macros to access
> the configuration information (i.e., check whether an extension is
> available/enabled). Now that we provide this information directly
> from DisasContext, we can access this directly via the cfg_ptr field.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
>
> ---
>
> Changes in v3:
> - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied
> into DisasContext) instead of going throuhg RISCV_CPU
>
> target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 5/7] target/riscv: iterate over a table of decoders
2022-01-28 14:56 ` [PATCH v3 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
@ 2022-01-30 20:56 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 20:56 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> - if (!decode_insn16(ctx, opcode)) {
> - gen_exception_illegal(ctx);
> - }
> + if (decode_insn16(ctx, opcode))
> + return;
...
> - if (!decode_insn32(ctx, opcode32)) {
> - gen_exception_illegal(ctx);
> +
> + for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
> + if (!decoders[i].guard_func(ctx))
> + continue;
> +
> + if (decoders[i].decode_func(ctx, opcode32))
> + return;
Missing braces, per style. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension
2022-01-28 14:56 ` [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
@ 2022-01-30 21:06 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 21:06 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> This adds the decoder and translation for the XVentanaCondOps custom
> extension (vendor-defined by Ventana Micro Systems), which is
> documented athttps://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
>
> This commit then also adds a guard-function (has_XVentanaCondOps_p)
> and the decoder function to the table of decoders, enabling the
> support for the XVentanaCondOps extension.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps
2022-01-28 14:56 ` [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
@ 2022-01-30 21:06 ` Richard Henderson
0 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2022-01-30 21:06 UTC (permalink / raw)
To: Philipp Tomsich, qemu-devel; +Cc: Greg Favor, Alistair Francis, Kito Cheng
On 1/29/22 01:56, Philipp Tomsich wrote:
> The XVentanaCondOps extension is supported by VRULL on behalf of the
> Ventana Micro. Add myself as a point-of-contact.
>
> Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-01-30 21:08 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-28 14:56 [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Philipp Tomsich
2022-01-28 14:56 ` [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Philipp Tomsich
2022-01-30 20:52 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Philipp Tomsich
2022-01-30 20:53 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext Philipp Tomsich
2022-01-30 20:54 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 5/7] target/riscv: iterate over a table of decoders Philipp Tomsich
2022-01-30 20:56 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
2022-01-28 14:56 ` [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Philipp Tomsich
2022-01-30 21:06 ` Richard Henderson
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