* [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
@ 2022-12-07 14:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Several small corrections for the UBWC setup and related data.
Dmitry Baryshkov (3):
drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
drm/msm/dpu: correct the UBWC version on sm6115
drm/msm/dpu: add missing ubwc_swizzle setting to catalog
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
2 files changed, 9 insertions(+), 2 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
@ 2022-12-07 14:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Several small corrections for the UBWC setup and related data.
Dmitry Baryshkov (3):
drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
drm/msm/dpu: correct the UBWC version on sm6115
drm/msm/dpu: add missing ubwc_swizzle setting to catalog
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
2 files changed, 9 insertions(+), 2 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2022-12-07 14:28 ` Dmitry Baryshkov
-1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 691c471b08c2..4246ab0b3bee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
ctx->mdp->highest_bank_bit << 18);
switch (ctx->catalog->caps->ubwc_version) {
case DPU_HW_UBWC_VER_10:
- /* TODO: UBWC v1 case */
+ fast_clear = fmt->alpha_enable ? BIT(31) : 0;
+ DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
+ BIT(8) |
+ (ctx->mdp->highest_bank_bit << 4));
break;
case DPU_HW_UBWC_VER_20:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
@ 2022-12-07 14:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 691c471b08c2..4246ab0b3bee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
ctx->mdp->highest_bank_bit << 18);
switch (ctx->catalog->caps->ubwc_version) {
case DPU_HW_UBWC_VER_10:
- /* TODO: UBWC v1 case */
+ fast_clear = fmt->alpha_enable ? BIT(31) : 0;
+ DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
+ BIT(8) |
+ (ctx->mdp->highest_bank_bit << 4));
break;
case DPU_HW_UBWC_VER_20:
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] drm/msm/dpu: correct the UBWC version on sm6115
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2022-12-07 14:28 ` Dmitry Baryshkov
-1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0.
Change the catalog entry accordingly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..a1b52b9b16f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -335,7 +335,7 @@ static const struct dpu_caps sm6115_dpu_caps = {
.max_mixer_blendstages = 0x4,
.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
- .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_version = DPU_HW_UBWC_VER_10,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = 2160,
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] drm/msm/dpu: correct the UBWC version on sm6115
@ 2022-12-07 14:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0.
Change the catalog entry accordingly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..a1b52b9b16f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -335,7 +335,7 @@ static const struct dpu_caps sm6115_dpu_caps = {
.max_mixer_blendstages = 0x4,
.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
- .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_version = DPU_HW_UBWC_VER_10,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = 2160,
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] drm/msm/dpu: add missing ubwc_swizzle setting to catalog
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2022-12-07 14:28 ` Dmitry Baryshkov
-1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a1b52b9b16f1..b80cc11a9a83 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -516,6 +516,7 @@ static const struct dpu_mdp_cfg sm6115_mdp[] = {
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x7,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2ac, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
@@ -529,6 +530,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .ubwc_swizzle = 0x6,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -558,6 +560,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .ubwc_swizzle = 0x6,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] drm/msm/dpu: add missing ubwc_swizzle setting to catalog
@ 2022-12-07 14:28 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-12-07 14:28 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a1b52b9b16f1..b80cc11a9a83 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -516,6 +516,7 @@ static const struct dpu_mdp_cfg sm6115_mdp[] = {
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x1,
+ .ubwc_swizzle = 0x7,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2ac, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
@@ -529,6 +530,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .ubwc_swizzle = 0x6,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -558,6 +560,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
.base = 0x0, .len = 0x494,
.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .ubwc_swizzle = 0x6,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
--
2.35.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2023-01-13 21:43 ` Abhinav Kumar
-1 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-13 21:43 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Several small corrections for the UBWC setup and related data.
>
I am assuming this series will be dropped in favor of the RFC:
https://patchwork.freedesktop.org/series/111751/
Right?
> Dmitry Baryshkov (3):
> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
> drm/msm/dpu: correct the UBWC version on sm6115
> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
@ 2023-01-13 21:43 ` Abhinav Kumar
0 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-13 21:43 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Several small corrections for the UBWC setup and related data.
>
I am assuming this series will be dropped in favor of the RFC:
https://patchwork.freedesktop.org/series/111751/
Right?
> Dmitry Baryshkov (3):
> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
> drm/msm/dpu: correct the UBWC version on sm6115
> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
2023-01-13 21:43 ` Abhinav Kumar
@ 2023-01-15 14:06 ` Dmitry Baryshkov
-1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-01-15 14:06 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 13/01/2023 23:43, Abhinav Kumar wrote:
>
>
> On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
>> Several small corrections for the UBWC setup and related data.
>>
>
> I am assuming this series will be dropped in favor of the RFC:
>
> https://patchwork.freedesktop.org/series/111751/
>
> Right?
No, they cover different topics. One covers the way the DPU handles UBWC
setup, another one reworks MDSS.
>
>> Dmitry Baryshkov (3):
>> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
>> drm/msm/dpu: correct the UBWC version on sm6115
>> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>>
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
>> 2 files changed, 9 insertions(+), 2 deletions(-)
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
@ 2023-01-15 14:06 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-01-15 14:06 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 13/01/2023 23:43, Abhinav Kumar wrote:
>
>
> On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
>> Several small corrections for the UBWC setup and related data.
>>
>
> I am assuming this series will be dropped in favor of the RFC:
>
> https://patchwork.freedesktop.org/series/111751/
>
> Right?
No, they cover different topics. One covers the way the DPU handles UBWC
setup, another one reworks MDSS.
>
>> Dmitry Baryshkov (3):
>> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
>> drm/msm/dpu: correct the UBWC version on sm6115
>> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>>
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 ++++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
>> 2 files changed, 9 insertions(+), 2 deletions(-)
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2023-01-24 23:22 ` Abhinav Kumar
-1 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:22 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 691c471b08c2..4246ab0b3bee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> ctx->mdp->highest_bank_bit << 18);
> switch (ctx->catalog->caps->ubwc_version) {
> case DPU_HW_UBWC_VER_10:
> - /* TODO: UBWC v1 case */
> + fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> + DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> + fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
> + BIT(8) |
> + (ctx->mdp->highest_bank_bit << 4));
> break;
> case DPU_HW_UBWC_VER_20:
> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
@ 2023-01-24 23:22 ` Abhinav Kumar
0 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:22 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 691c471b08c2..4246ab0b3bee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -310,7 +310,11 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
> ctx->mdp->highest_bank_bit << 18);
> switch (ctx->catalog->caps->ubwc_version) {
> case DPU_HW_UBWC_VER_10:
> - /* TODO: UBWC v1 case */
> + fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> + DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
> + fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) |
> + BIT(8) |
> + (ctx->mdp->highest_bank_bit << 4));
> break;
> case DPU_HW_UBWC_VER_20:
> fast_clear = fmt->alpha_enable ? BIT(31) : 0;
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/3] drm/msm/dpu: correct the UBWC version on sm6115
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2023-01-24 23:23 ` Abhinav Kumar
-1 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:23 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0.
> Change the catalog entry accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b4ca123d8e69..a1b52b9b16f1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -335,7 +335,7 @@ static const struct dpu_caps sm6115_dpu_caps = {
> .max_mixer_blendstages = 0x4,
> .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> - .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_version = DPU_HW_UBWC_VER_10,
> .has_dim_layer = true,
> .has_idle_pc = true,
> .max_linewidth = 2160,
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/3] drm/msm/dpu: correct the UBWC version on sm6115
@ 2023-01-24 23:23 ` Abhinav Kumar
0 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:23 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0.
> Change the catalog entry accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b4ca123d8e69..a1b52b9b16f1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -335,7 +335,7 @@ static const struct dpu_caps sm6115_dpu_caps = {
> .max_mixer_blendstages = 0x4,
> .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> - .ubwc_version = DPU_HW_UBWC_VER_20,
> + .ubwc_version = DPU_HW_UBWC_VER_10,
> .has_dim_layer = true,
> .has_idle_pc = true,
> .max_linewidth = 2160,
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/3] drm/msm/dpu: add missing ubwc_swizzle setting to catalog
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2023-01-24 23:27 ` Abhinav Kumar
-1 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
I have already acked https://patchwork.freedesktop.org/patch/519662/
So this can be dropped from this series.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index a1b52b9b16f1..b80cc11a9a83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -516,6 +516,7 @@ static const struct dpu_mdp_cfg sm6115_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = 0,
> .highest_bank_bit = 0x1,
> + .ubwc_swizzle = 0x7,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2ac, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> @@ -529,6 +530,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = 0,
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .ubwc_swizzle = 0x6,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2AC, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> @@ -558,6 +560,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .ubwc_swizzle = 0x6,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2AC, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/3] drm/msm/dpu: add missing ubwc_swizzle setting to catalog
@ 2023-01-24 23:27 ` Abhinav Kumar
0 siblings, 0 replies; 20+ messages in thread
From: Abhinav Kumar @ 2023-01-24 23:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On 12/7/2022 6:28 AM, Dmitry Baryshkov wrote:
> Use the values from the vendor DTs to set ubwc_swizzle in the catalog.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
I have already acked https://patchwork.freedesktop.org/patch/519662/
So this can be dropped from this series.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index a1b52b9b16f1..b80cc11a9a83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -516,6 +516,7 @@ static const struct dpu_mdp_cfg sm6115_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = 0,
> .highest_bank_bit = 0x1,
> + .ubwc_swizzle = 0x7,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2ac, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> @@ -529,6 +530,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = 0,
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .ubwc_swizzle = 0x6,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2AC, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> @@ -558,6 +560,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
> .base = 0x0, .len = 0x494,
> .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> + .ubwc_swizzle = 0x6,
> .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> .reg_off = 0x2AC, .bit_off = 0},
> .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
2022-12-07 14:28 ` Dmitry Baryshkov
@ 2023-01-26 19:00 ` Dmitry Baryshkov
-1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-01-26 19:00 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno
On Wed, 07 Dec 2022 16:28:30 +0200, Dmitry Baryshkov wrote:
> Several small corrections for the UBWC setup and related data.
>
> Dmitry Baryshkov (3):
> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
> drm/msm/dpu: correct the UBWC version on sm6115
> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>
> [...]
Applied, thanks!
[1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
https://gitlab.freedesktop.org/lumag/msm/-/commit/975b86f8c2a8
[2/3] drm/msm/dpu: correct the UBWC version on sm6115
https://gitlab.freedesktop.org/lumag/msm/-/commit/7a9898ec3018
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup
@ 2023-01-26 19:00 ` Dmitry Baryshkov
0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-01-26 19:00 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar, Dmitry Baryshkov
Cc: freedreno, linux-arm-msm, Bjorn Andersson, dri-devel, Stephen Boyd
On Wed, 07 Dec 2022 16:28:30 +0200, Dmitry Baryshkov wrote:
> Several small corrections for the UBWC setup and related data.
>
> Dmitry Baryshkov (3):
> drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
> drm/msm/dpu: correct the UBWC version on sm6115
> drm/msm/dpu: add missing ubwc_swizzle setting to catalog
>
> [...]
Applied, thanks!
[1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format
https://gitlab.freedesktop.org/lumag/msm/-/commit/975b86f8c2a8
[2/3] drm/msm/dpu: correct the UBWC version on sm6115
https://gitlab.freedesktop.org/lumag/msm/-/commit/7a9898ec3018
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-01-26 19:01 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-07 14:28 [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup Dmitry Baryshkov
2022-12-07 14:28 ` Dmitry Baryshkov
2022-12-07 14:28 ` [PATCH 1/3] drm/msm/dpu: handle UBWC 1.0 in dpu_hw_sspp_setup_format Dmitry Baryshkov
2022-12-07 14:28 ` Dmitry Baryshkov
2023-01-24 23:22 ` Abhinav Kumar
2023-01-24 23:22 ` Abhinav Kumar
2022-12-07 14:28 ` [PATCH 2/3] drm/msm/dpu: correct the UBWC version on sm6115 Dmitry Baryshkov
2022-12-07 14:28 ` Dmitry Baryshkov
2023-01-24 23:23 ` Abhinav Kumar
2023-01-24 23:23 ` Abhinav Kumar
2022-12-07 14:28 ` [PATCH 3/3] drm/msm/dpu: add missing ubwc_swizzle setting to catalog Dmitry Baryshkov
2022-12-07 14:28 ` Dmitry Baryshkov
2023-01-24 23:27 ` Abhinav Kumar
2023-01-24 23:27 ` Abhinav Kumar
2023-01-13 21:43 ` [PATCH 0/3] drm/msm/dpu: several fixes for UBWC setup Abhinav Kumar
2023-01-13 21:43 ` Abhinav Kumar
2023-01-15 14:06 ` Dmitry Baryshkov
2023-01-15 14:06 ` Dmitry Baryshkov
2023-01-26 19:00 ` Dmitry Baryshkov
2023-01-26 19:00 ` Dmitry Baryshkov
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