[PATCH v4 00/19] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[PATCH v4 00/19] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[Simon Horman]

The aim of this series is to add common clock framework and in turn
multiplatform support to the r8a7779 SoC and marzen-reference.  It
subsequently removes non-multiplatform support from marzen-reference.

This is based on work for R-Car Gen2 by Laurent Pinchart and Magnus Damm.


This series is based on the renesas-devel-v3.14-rc6-20140313v3
tag of my renesas tree.

This series requires "spi: sh-hspi: Do not specifically request shyway_clk"
in order for HSPI to be initialised when booting using multiplatform.

This series is known not to work when
booting with SMP enabled and maxcpus not set to 1.

This series attempts to address the extensive review
received for v3 of this series. Changes are noted
in the changelog of individual patches.

Simon Horman (19):
  clk: shmobile: r8a7779: Add clocks support
  clk: shmobile: r8a7779: Add MSTP clock support
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  ARM: shmobile: r8a7779: Add clocks
  ARM: shmobile: Sync Marzen DTS with Marzen reference DTS
  ARM: shmobile: marzen: Specify external clock frequency in DT
  ARM: shmobile: r8a7779: Reference clocks
  ARM: shmobile: r8a7779: Add helper to read mode pins
  ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to
    clock-r8a7779.c
  ARM: shmobile: marzen-reference: Move clock and OF device
    initialisation into board code
  ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h
  ARM: shmobile: r8a7779: Initial multiplatform support
  ARM: shmobile: marzen-reference: Initialize CPG device
  ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
  ARM: shmobile: marzen: Add to shmobile defconfig
  ARM: shmobile: Remove non-multiplatform Marzen reference support
  ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
  ARM: shmobile: Remove Marzen reference DTS
  ARM: shmobile: marzen-reference: Remove legacy clock support

 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     | 120 --------------
 arch/arm/boot/dts/r8a7779-marzen.dts               |  97 +++++++++++
 arch/arm/boot/dts/r8a7779.dtsi                     | 163 +++++++++++++++++++
 arch/arm/configs/shmobile_defconfig                |   2 +
 arch/arm/mach-shmobile/Kconfig                     |  22 +--
 arch/arm/mach-shmobile/Makefile                    |   2 +-
 arch/arm/mach-shmobile/Makefile.boot               |   1 -
 arch/arm/mach-shmobile/board-marzen-reference.c    |  30 ++++
 arch/arm/mach-shmobile/clock-r8a7779.c             |  22 ++-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |  28 ++--
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 181 +++++++++++++++++++++
 include/dt-bindings/clock/r8a7779-clock.h          |  64 ++++++++
 include/linux/clk/shmobile.h                       |   3 +
 18 files changed, 609 insertions(+), 161 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

-- 
1.8.5.2

[PATCH v4 00/19] ARM: shmobile: r8a7779, marzen: CCF and multiplatform

[Simon Horman]

The aim of this series is to add common clock framework and in turn
multiplatform support to the r8a7779 SoC and marzen-reference.  It
subsequently removes non-multiplatform support from marzen-reference.

This is based on work for R-Car Gen2 by Laurent Pinchart and Magnus Damm.


This series is based on the renesas-devel-v3.14-rc6-20140313v3
tag of my renesas tree.

This series requires "spi: sh-hspi: Do not specifically request shyway_clk"
in order for HSPI to be initialised when booting using multiplatform.

This series is known not to work when
booting with SMP enabled and maxcpus not set to 1.

This series attempts to address the extensive review
received for v3 of this series. Changes are noted
in the changelog of individual patches.

Simon Horman (19):
  clk: shmobile: r8a7779: Add clocks support
  clk: shmobile: r8a7779: Add MSTP clock support
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  ARM: shmobile: r8a7779: Add clocks
  ARM: shmobile: Sync Marzen DTS with Marzen reference DTS
  ARM: shmobile: marzen: Specify external clock frequency in DT
  ARM: shmobile: r8a7779: Reference clocks
  ARM: shmobile: r8a7779: Add helper to read mode pins
  ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to
    clock-r8a7779.c
  ARM: shmobile: marzen-reference: Move clock and OF device
    initialisation into board code
  ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h
  ARM: shmobile: r8a7779: Initial multiplatform support
  ARM: shmobile: marzen-reference: Initialize CPG device
  ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
  ARM: shmobile: marzen: Add to shmobile defconfig
  ARM: shmobile: Remove non-multiplatform Marzen reference support
  ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
  ARM: shmobile: Remove Marzen reference DTS
  ARM: shmobile: marzen-reference: Remove legacy clock support

 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
 arch/arm/boot/dts/Makefile                         |   4 +-
 arch/arm/boot/dts/r8a7779-marzen-reference.dts     | 120 --------------
 arch/arm/boot/dts/r8a7779-marzen.dts               |  97 +++++++++++
 arch/arm/boot/dts/r8a7779.dtsi                     | 163 +++++++++++++++++++
 arch/arm/configs/shmobile_defconfig                |   2 +
 arch/arm/mach-shmobile/Kconfig                     |  22 +--
 arch/arm/mach-shmobile/Makefile                    |   2 +-
 arch/arm/mach-shmobile/Makefile.boot               |   1 -
 arch/arm/mach-shmobile/board-marzen-reference.c    |  30 ++++
 arch/arm/mach-shmobile/clock-r8a7779.c             |  22 ++-
 arch/arm/mach-shmobile/include/mach/r8a7779.h      |   2 +-
 arch/arm/mach-shmobile/setup-r8a7779.c             |  28 ++--
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 181 +++++++++++++++++++++
 include/dt-bindings/clock/r8a7779-clock.h          |  64 ++++++++
 include/linux/clk/shmobile.h                       |   3 +
 18 files changed, 609 insertions(+), 161 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

-- 
1.8.5.2

[PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks are all fixed rate clocks with multiplier and
divisor set according to boot mode configuration.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
Under discussion
* Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat string
  added. I am less enthusiastic.

v4
* As suggested by Geert Uytterhoeven
  - Remove double and from bindings documentation
  - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
  - Correct order of cpg_clk_configs entries
* As suggested by Laurent Pinchart
  - Update copyright to include 2014
  - Remove reference to non-existent divider clocks in changelog
  - Do not map cpg->reg as it is not accessed
  - Return an error for unknown name values in r8a7779_cpg_register_clock()
  - Expose clkb in binding
  - Do not include MSPT registers in register range in binding example
* Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
  (to me)
v3
* As suggested by Laurent Pinchart
  - Added external clock input
  - Use PLLA ratio set bu MD11 and MD12
  - Add _div suffixes of fields of struct cpt_clk_config
  - Register PLLA as a fixed factor clock
  - Use sizeof() instead of sizeof
  - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()

  - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
    binding which could be shared with other SoCs as I do not believe that
    the SoCs is are sufficiently similar.
---
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 181 +++++++++++++++++++++
 include/linux/clk/shmobile.h                       |   3 +
 4 files changed, 212 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 0000000..ed3c8cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "b", "out".
+
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks@ffc80000 {
+		compatible = "renesas,r8a7779-cpg-clocks";
+		reg = <0 0xffc80000 0 0x30>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
+		                     "b", "out";
+	};
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 9ecef14..2121ba0 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 0000000..8974a41
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,181 @@
+/*
+ * r8a7779 Core CPG Clocks
+ *
+ * Copyright (C) 2013, 2014 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/r8a7779-clock.h>
+
+#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
+
+struct r8a7779_cpg {
+	struct clk_onecell_data data;
+	spinlock_t lock;
+	void __iomem *reg;
+};
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *		MD1 = 1			MD1 = 0
+ *		(PLLA = 1500)		(PLLA = 1600)
+ *		(MHz)			(MHz)
+ *------------------------------------------------+--------------------
+ * clkz		1000   (2/3)		800   (1/2)
+ * clkzs	 250   (1/6)		200   (1/8)
+ * clki		 750   (1/2)		800   (1/2)
+ * clks		 250   (1/6)		200   (1/8)
+ * clks1	 125   (1/12)		100   (1/16)
+ * clks3	 187.5 (1/8)		200   (1/8)
+ * clks4	  93.7 (1/16)		100   (1/16)
+ * clkp		  62.5 (1/24)		 50   (1/32)
+ * clkg		  62.5 (1/24)		 66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
+ * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
+ */
+
+#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
+
+struct cpg_clk_config {
+	unsigned int z_mult;
+	unsigned int z_div;
+	unsigned int zs_and_s_div;
+	unsigned int s1_div;
+	unsigned int p_div;
+	unsigned int b_and_out_div;
+};
+
+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 2, 3, 6, 12, 24, 24 },
+	{ 1, 2, 8, 16, 32, 32 },
+	{ 2, 3, 6, 12, 24, 36 },
+};
+
+/*
+ *   MD		PLLA Ratio
+ * 12 11
+ *------------------------
+ * 0  0		x42
+ * 0  1		x48
+ * 1  0		x56
+ * 1  1		x64
+ */
+
+#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
+
+static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+			   const struct cpg_clk_config *config,
+			   unsigned int plla_mult, const char *name)
+{
+	const char *parent_name = "plla";
+	unsigned int mult = 1;
+	unsigned int div = 1;
+
+	if (!strcmp(name, "plla")) {
+		parent_name = of_clk_get_parent_name(np, 0);
+		mult = plla_mult;
+	} else if (!strcmp(name, "z")) {
+		div = config->z_div;
+		mult = config->z_mult;
+	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
+		div = config->zs_and_s_div;
+	} else if (!strcmp(name, "s1")) {
+		div = config->s1_div;
+	} else if (!strcmp(name, "p")) {
+		div = config->p_div;
+	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
+		div = config->b_and_out_div;
+	} else {
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+}
+
+static void __init r8a7779_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_clk_config *config;
+	struct r8a7779_cpg *cpg;
+	struct clk **clks;
+	unsigned int i, plla_mult;
+	int num_clks;
+
+	num_clks = of_property_count_strings(np, "clock-output-names");
+	if (num_clks < 0) {
+		pr_err("%s: failed to count clocks\n", __func__);
+		return;
+	}
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
+	if (cpg = NULL || clks = NULL) {
+		/* We're leaking memory on purpose, there's no point in cleaning
+		 * up as the system won't boot anyway.
+		 */
+		pr_err("%s: failed to allocate cpg\n", __func__);
+		return;
+	}
+
+	spin_lock_init(&cpg->lock);
+
+	cpg->data.clks = clks;
+	cpg->data.clk_num = num_clks;
+
+	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
+	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+
+	for (i = 0; i < num_clks; ++i) {
+		const char *name;
+		struct clk *clk;
+
+		of_property_read_string_index(np, "clock-output-names", i,
+					      &name);
+
+		clk = r8a7779_cpg_register_clock(np, cpg, config,
+						 plla_mult, name);
+		if (IS_ERR(clk))
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clk));
+		else
+			cpg->data.clks[i] = clk;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
+	       r8a7779_cpg_clocks_init);
+
+void __init r8a7779_clocks_init(u32 mode)
+{
+	cpg_mode = mode;
+
+	of_clk_init(NULL);
+}
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080..9f8a140 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013, 2014 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Contact: Simon Horman <horms@verge.net.au>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
-- 
1.8.5.2

[PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks are all fixed rate clocks with multiplier and
divisor set according to boot mode configuration.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>

---
Under discussion
* Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat string
  added. I am less enthusiastic.

v4
* As suggested by Geert Uytterhoeven
  - Remove double and from bindings documentation
  - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
  - Correct order of cpg_clk_configs entries
* As suggested by Laurent Pinchart
  - Update copyright to include 2014
  - Remove reference to non-existent divider clocks in changelog
  - Do not map cpg->reg as it is not accessed
  - Return an error for unknown name values in r8a7779_cpg_register_clock()
  - Expose clkb in binding
  - Do not include MSPT registers in register range in binding example
* Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
  (to me)
v3
* As suggested by Laurent Pinchart
  - Added external clock input
  - Use PLLA ratio set bu MD11 and MD12
  - Add _div suffixes of fields of struct cpt_clk_config
  - Register PLLA as a fixed factor clock
  - Use sizeof() instead of sizeof
  - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()

  - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
    binding which could be shared with other SoCs as I do not believe that
    the SoCs is are sufficiently similar.
---
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 181 +++++++++++++++++++++
 include/linux/clk/shmobile.h                       |   3 +
 4 files changed, 212 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 0000000..ed3c8cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "b", "out".
+
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks@ffc80000 {
+		compatible = "renesas,r8a7779-cpg-clocks";
+		reg = <0 0xffc80000 0 0x30>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
+		                     "b", "out";
+	};
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 9ecef14..2121ba0 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 0000000..8974a41
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,181 @@
+/*
+ * r8a7779 Core CPG Clocks
+ *
+ * Copyright (C) 2013, 2014 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/r8a7779-clock.h>
+
+#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
+
+struct r8a7779_cpg {
+	struct clk_onecell_data data;
+	spinlock_t lock;
+	void __iomem *reg;
+};
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *		MD1 = 1			MD1 = 0
+ *		(PLLA = 1500)		(PLLA = 1600)
+ *		(MHz)			(MHz)
+ *------------------------------------------------+--------------------
+ * clkz		1000   (2/3)		800   (1/2)
+ * clkzs	 250   (1/6)		200   (1/8)
+ * clki		 750   (1/2)		800   (1/2)
+ * clks		 250   (1/6)		200   (1/8)
+ * clks1	 125   (1/12)		100   (1/16)
+ * clks3	 187.5 (1/8)		200   (1/8)
+ * clks4	  93.7 (1/16)		100   (1/16)
+ * clkp		  62.5 (1/24)		 50   (1/32)
+ * clkg		  62.5 (1/24)		 66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
+ * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
+ */
+
+#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
+
+struct cpg_clk_config {
+	unsigned int z_mult;
+	unsigned int z_div;
+	unsigned int zs_and_s_div;
+	unsigned int s1_div;
+	unsigned int p_div;
+	unsigned int b_and_out_div;
+};
+
+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 2, 3, 6, 12, 24, 24 },
+	{ 1, 2, 8, 16, 32, 32 },
+	{ 2, 3, 6, 12, 24, 36 },
+};
+
+/*
+ *   MD		PLLA Ratio
+ * 12 11
+ *------------------------
+ * 0  0		x42
+ * 0  1		x48
+ * 1  0		x56
+ * 1  1		x64
+ */
+
+#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
+
+static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+			   const struct cpg_clk_config *config,
+			   unsigned int plla_mult, const char *name)
+{
+	const char *parent_name = "plla";
+	unsigned int mult = 1;
+	unsigned int div = 1;
+
+	if (!strcmp(name, "plla")) {
+		parent_name = of_clk_get_parent_name(np, 0);
+		mult = plla_mult;
+	} else if (!strcmp(name, "z")) {
+		div = config->z_div;
+		mult = config->z_mult;
+	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
+		div = config->zs_and_s_div;
+	} else if (!strcmp(name, "s1")) {
+		div = config->s1_div;
+	} else if (!strcmp(name, "p")) {
+		div = config->p_div;
+	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
+		div = config->b_and_out_div;
+	} else {
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+}
+
+static void __init r8a7779_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_clk_config *config;
+	struct r8a7779_cpg *cpg;
+	struct clk **clks;
+	unsigned int i, plla_mult;
+	int num_clks;
+
+	num_clks = of_property_count_strings(np, "clock-output-names");
+	if (num_clks < 0) {
+		pr_err("%s: failed to count clocks\n", __func__);
+		return;
+	}
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
+	if (cpg == NULL || clks == NULL) {
+		/* We're leaking memory on purpose, there's no point in cleaning
+		 * up as the system won't boot anyway.
+		 */
+		pr_err("%s: failed to allocate cpg\n", __func__);
+		return;
+	}
+
+	spin_lock_init(&cpg->lock);
+
+	cpg->data.clks = clks;
+	cpg->data.clk_num = num_clks;
+
+	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
+	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+
+	for (i = 0; i < num_clks; ++i) {
+		const char *name;
+		struct clk *clk;
+
+		of_property_read_string_index(np, "clock-output-names", i,
+					      &name);
+
+		clk = r8a7779_cpg_register_clock(np, cpg, config,
+						 plla_mult, name);
+		if (IS_ERR(clk))
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clk));
+		else
+			cpg->data.clks[i] = clk;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
+	       r8a7779_cpg_clocks_init);
+
+void __init r8a7779_clocks_init(u32 mode)
+{
+	cpg_mode = mode;
+
+	of_clk_init(NULL);
+}
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080..9f8a140 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013, 2014 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>
+ * Contact: Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
-- 
1.8.5.2

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[PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks are all fixed rate clocks with multiplier and
divisor set according to boot mode configuration.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: devicetree at vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
Under discussion
* Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat string
  added. I am less enthusiastic.

v4
* As suggested by Geert Uytterhoeven
  - Remove double and from bindings documentation
  - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
  - Correct order of cpg_clk_configs entries
* As suggested by Laurent Pinchart
  - Update copyright to include 2014
  - Remove reference to non-existent divider clocks in changelog
  - Do not map cpg->reg as it is not accessed
  - Return an error for unknown name values in r8a7779_cpg_register_clock()
  - Expose clkb in binding
  - Do not include MSPT registers in register range in binding example
* Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
  (to me)
v3
* As suggested by Laurent Pinchart
  - Added external clock input
  - Use PLLA ratio set bu MD11 and MD12
  - Add _div suffixes of fields of struct cpt_clk_config
  - Register PLLA as a fixed factor clock
  - Use sizeof() instead of sizeof
  - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()

  - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
    binding which could be shared with other SoCs as I do not believe that
    the SoCs is are sufficiently similar.
---
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
 drivers/clk/shmobile/Makefile                      |   1 +
 drivers/clk/shmobile/clk-r8a7779.c                 | 181 +++++++++++++++++++++
 include/linux/clk/shmobile.h                       |   3 +
 4 files changed, 212 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
 create mode 100644 drivers/clk/shmobile/clk-r8a7779.c

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 0000000..ed3c8cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "b", "out".
+
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks at ffc80000 {
+		compatible = "renesas,r8a7779-cpg-clocks";
+		reg = <0 0xffc80000 0 0x30>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
+		                     "b", "out";
+	};
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 9ecef14..2121ba0 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
new file mode 100644
index 0000000..8974a41
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -0,0 +1,181 @@
+/*
+ * r8a7779 Core CPG Clocks
+ *
+ * Copyright (C) 2013, 2014 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/r8a7779-clock.h>
+
+#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
+
+struct r8a7779_cpg {
+	struct clk_onecell_data data;
+	spinlock_t lock;
+	void __iomem *reg;
+};
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *		MD1 = 1			MD1 = 0
+ *		(PLLA = 1500)		(PLLA = 1600)
+ *		(MHz)			(MHz)
+ *------------------------------------------------+--------------------
+ * clkz		1000   (2/3)		800   (1/2)
+ * clkzs	 250   (1/6)		200   (1/8)
+ * clki		 750   (1/2)		800   (1/2)
+ * clks		 250   (1/6)		200   (1/8)
+ * clks1	 125   (1/12)		100   (1/16)
+ * clks3	 187.5 (1/8)		200   (1/8)
+ * clks4	  93.7 (1/16)		100   (1/16)
+ * clkp		  62.5 (1/24)		 50   (1/32)
+ * clkg		  62.5 (1/24)		 66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
+ * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
+ */
+
+#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
+
+struct cpg_clk_config {
+	unsigned int z_mult;
+	unsigned int z_div;
+	unsigned int zs_and_s_div;
+	unsigned int s1_div;
+	unsigned int p_div;
+	unsigned int b_and_out_div;
+};
+
+static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
+	{ 1, 2, 8, 16, 32, 24 },
+	{ 2, 3, 6, 12, 24, 24 },
+	{ 1, 2, 8, 16, 32, 32 },
+	{ 2, 3, 6, 12, 24, 36 },
+};
+
+/*
+ *   MD		PLLA Ratio
+ * 12 11
+ *------------------------
+ * 0  0		x42
+ * 0  1		x48
+ * 1  0		x56
+ * 1  1		x64
+ */
+
+#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
+
+static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static u32 cpg_mode __initdata;
+
+static struct clk * __init
+r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
+			   const struct cpg_clk_config *config,
+			   unsigned int plla_mult, const char *name)
+{
+	const char *parent_name = "plla";
+	unsigned int mult = 1;
+	unsigned int div = 1;
+
+	if (!strcmp(name, "plla")) {
+		parent_name = of_clk_get_parent_name(np, 0);
+		mult = plla_mult;
+	} else if (!strcmp(name, "z")) {
+		div = config->z_div;
+		mult = config->z_mult;
+	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
+		div = config->zs_and_s_div;
+	} else if (!strcmp(name, "s1")) {
+		div = config->s1_div;
+	} else if (!strcmp(name, "p")) {
+		div = config->p_div;
+	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
+		div = config->b_and_out_div;
+	} else {
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
+}
+
+static void __init r8a7779_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_clk_config *config;
+	struct r8a7779_cpg *cpg;
+	struct clk **clks;
+	unsigned int i, plla_mult;
+	int num_clks;
+
+	num_clks = of_property_count_strings(np, "clock-output-names");
+	if (num_clks < 0) {
+		pr_err("%s: failed to count clocks\n", __func__);
+		return;
+	}
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
+	if (cpg == NULL || clks == NULL) {
+		/* We're leaking memory on purpose, there's no point in cleaning
+		 * up as the system won't boot anyway.
+		 */
+		pr_err("%s: failed to allocate cpg\n", __func__);
+		return;
+	}
+
+	spin_lock_init(&cpg->lock);
+
+	cpg->data.clks = clks;
+	cpg->data.clk_num = num_clks;
+
+	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
+	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
+
+	for (i = 0; i < num_clks; ++i) {
+		const char *name;
+		struct clk *clk;
+
+		of_property_read_string_index(np, "clock-output-names", i,
+					      &name);
+
+		clk = r8a7779_cpg_register_clock(np, cpg, config,
+						 plla_mult, name);
+		if (IS_ERR(clk))
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clk));
+		else
+			cpg->data.clks[i] = clk;
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
+	       r8a7779_cpg_clocks_init);
+
+void __init r8a7779_clocks_init(u32 mode)
+{
+	cpg_mode = mode;
+
+	of_clk_init(NULL);
+}
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080..9f8a140 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013, 2014 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Contact: Simon Horman <horms@verge.net.au>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
-- 
1.8.5.2

[PATCH v4 02/19] clk: shmobile: r8a7779: Add MSTP clock support

[Simon Horman]

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add entry in numerical order
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 5992dce..0708937 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
-- 
1.8.5.2

[PATCH v4 02/19] clk: shmobile: r8a7779: Add MSTP clock support

[Simon Horman]

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add entry in numerical order
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 5992dce..0708937 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
-- 
1.8.5.2

[PATCH v4 02/19] clk: shmobile: r8a7779: Add MSTP clock support

[Simon Horman]

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: devicetree at vger.kernel.org
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* As suggested by Laurent Pinchart
  - Add entry in numerical order
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 5992dce..0708937 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
-- 
1.8.5.2

[PATCH v4 03/19] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Simon Horman]

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v4
* Add R8A7779_CLK_B

v3
* As suggested by Laurent Pinchart
  - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
  - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
  - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
  - Add ethernet, MMC and HSCIF entries
  - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5

* Add R8A7779_CLK_PCIE

v2
* No change
---
 include/dt-bindings/clock/r8a7779-clock.h | 64 +++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 0000000..381a611
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA	0
+#define R8A7779_CLK_Z		1
+#define R8A7779_CLK_ZS		2
+#define R8A7779_CLK_S		3
+#define R8A7779_CLK_S1		4
+#define R8A7779_CLK_P		5
+#define R8A7779_CLK_B		6
+#define R8A7779_CLK_OUT		7
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI	7
+#define R8A7779_CLK_TMU2	14
+#define R8A7779_CLK_TMU1	15
+#define R8A7779_CLK_TMU0	16
+#define R8A7779_CLK_HSCIF1	18
+#define R8A7779_CLK_HSCIF0	19
+#define R8A7779_CLK_SCIF5	21
+#define R8A7779_CLK_SCIF4	22
+#define R8A7779_CLK_SCIF3	23
+#define R8A7779_CLK_SCIF2	24
+#define R8A7779_CLK_SCIF1	25
+#define R8A7779_CLK_SCIF0	26
+#define R8A7779_CLK_I2C3	27
+#define R8A7779_CLK_I2C2	28
+#define R8A7779_CLK_I2C1	29
+#define R8A7779_CLK_I2C0	30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01	0
+#define R8A7779_CLK_USB2	1
+#define R8A7779_CLK_DU		3
+#define R8A7779_CLK_VIN2	8
+#define R8A7779_CLK_VIN1	9
+#define R8A7779_CLK_VIN0	10
+#define R8A7779_CLK_ETHER	14
+#define R8A7779_CLK_SATA	15
+#define R8A7779_CLK_PCIE	16
+#define R8A7779_CLK_VIN3	20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3	20
+#define R8A7779_CLK_SDHI2	21
+#define R8A7779_CLK_SDHI1	22
+#define R8A7779_CLK_SDHI0	23
+#define R8A7779_CLK_MMC1	30
+#define R8A7779_CLK_MMC0	31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
-- 
1.8.5.2

[PATCH v4 03/19] ARM: shmobile: r8a7779: Add clock index macros for DT sources

[Simon Horman]

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v4
* Add R8A7779_CLK_B

v3
* As suggested by Laurent Pinchart
  - Consolidate R8A7779_CLK_HSPI{0,1,2} into R8A7779_CLK_HSPI
  - Correct inverted indexes of R8A7779_CLK_TMU{1,2}
  - Consolidate R8A7779_CLK_{E,O}HCI{0,1} into R8A7779_CLK_USB{0,1}
  - Add ethernet, MMC and HSCIF entries
  - Replace R8A7779_SCIF6 with R8A7779_CLK_SCIF5

* Add R8A7779_CLK_PCIE

v2
* No change
---
 include/dt-bindings/clock/r8a7779-clock.h | 64 +++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7779-clock.h

diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 0000000..381a611
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA	0
+#define R8A7779_CLK_Z		1
+#define R8A7779_CLK_ZS		2
+#define R8A7779_CLK_S		3
+#define R8A7779_CLK_S1		4
+#define R8A7779_CLK_P		5
+#define R8A7779_CLK_B		6
+#define R8A7779_CLK_OUT		7
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI	7
+#define R8A7779_CLK_TMU2	14
+#define R8A7779_CLK_TMU1	15
+#define R8A7779_CLK_TMU0	16
+#define R8A7779_CLK_HSCIF1	18
+#define R8A7779_CLK_HSCIF0	19
+#define R8A7779_CLK_SCIF5	21
+#define R8A7779_CLK_SCIF4	22
+#define R8A7779_CLK_SCIF3	23
+#define R8A7779_CLK_SCIF2	24
+#define R8A7779_CLK_SCIF1	25
+#define R8A7779_CLK_SCIF0	26
+#define R8A7779_CLK_I2C3	27
+#define R8A7779_CLK_I2C2	28
+#define R8A7779_CLK_I2C1	29
+#define R8A7779_CLK_I2C0	30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01	0
+#define R8A7779_CLK_USB2	1
+#define R8A7779_CLK_DU		3
+#define R8A7779_CLK_VIN2	8
+#define R8A7779_CLK_VIN1	9
+#define R8A7779_CLK_VIN0	10
+#define R8A7779_CLK_ETHER	14
+#define R8A7779_CLK_SATA	15
+#define R8A7779_CLK_PCIE	16
+#define R8A7779_CLK_VIN3	20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3	20
+#define R8A7779_CLK_SDHI2	21
+#define R8A7779_CLK_SDHI1	22
+#define R8A7779_CLK_SDHI0	23
+#define R8A7779_CLK_MMC1	30
+#define R8A7779_CLK_MMC0	31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
-- 
1.8.5.2

[PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Declare all core and MSTP clocks currently used by r8a7779-based boards.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven
  - Wrap lines at < 80columns
  - Beef-up short lines towards 80 columns
* As suggested by Laurent Pinchart
  - Add HSCIF clocks
  - Correct many clock sources
  - Correct reg of cpg_clocks
* Add CPG clock "b" which is now part of the binding

v3
* As suggested by Laurent Pinchart
  - Add and use extal_clk
  - Fix bogus status register use for MSTP clocks
  - Fix bogus mstp3_cls to use its own entries rather than
    that of mstp1_clks

* Update to use "main" in cpg_clocks as per updated
  binding in previous patch
* Update for new, consolidated and renamed index macros
  - R8A7779_CLK_ETHER
  - R8A7779_CLK_HSCIF
  - R8A7779_CLK_HSPI
  - R8A7779_CLK_MMC0,1
  - R8A7779_CLK_PCIE
  - R8A7779_CLK_USB01,2
---
 arch/arm/boot/dts/r8a7779.dtsi | 151 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 151 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4..c0802aa 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -278,4 +279,154 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overriden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "extal";
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks@0xe6150000 {
+			compatible = "renesas,r8a7779-cpg-clocks";
+			reg = <0 0xffc80000 0 0x30>;
+			clocks = <&extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "plla", "z", "zs", "s",
+					     "s1", "p", "b", "out";
+		};
+
+		/* Fixed factor clocks */
+		i_clk: i_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "i";
+		};
+		s3_clk: s3_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "s3";
+		};
+		s4_clk: s4_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <16>;
+			clock-mult = <1>;
+			clock-output-names = "s4";
+		};
+		g_clk: g_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+			clock-output-names = "g";
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80030 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
+				R8A7779_CLK_HSPI R8A7779_CLK_TMU0
+				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
+				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0
+				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
+				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
+				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+			>;
+			clock-output-names +				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
+				"tmu2", "hscif1", "hscif0", "scif5", "scif4",
+				"scif3", "scif2", "scif1", "scif0", "i2c3",
+				"i2c2", "i2c1", "i2c0";
+		};
+		mstp1_clks: mstp1_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>,
+			         <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_USB01 R8A7779_CLK_USB01
+				R8A7779_CLK_USB2 R8A7779_CLK_USB2
+				R8A7779_CLK_DU R8A7779_CLK_VIN2
+				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+				R8A7779_CLK_ETHER R8A7779_CLK_SATA
+				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+			>;
+			clock-output-names +				"ehci0", "ohci0",
+				"ehci1", "ohci1",
+				"du", "vin2",
+				"vin1", "vin0",
+				"ether", "sata",
+				"pcie", "vin3";
+		};
+		mstp3_clks: mstp3_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc8003c 0 4>;
+			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
+				 <&s4_clk>, <&s4_clk>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+			>;
+			clock-output-names +				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
+				"mmc1", "mmc0";
+		};
+	};
 };
-- 
1.8.5.2

[PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Declare all core and MSTP clocks currently used by r8a7779-based boards.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven
  - Wrap lines at < 80columns
  - Beef-up short lines towards 80 columns
* As suggested by Laurent Pinchart
  - Add HSCIF clocks
  - Correct many clock sources
  - Correct reg of cpg_clocks
* Add CPG clock "b" which is now part of the binding

v3
* As suggested by Laurent Pinchart
  - Add and use extal_clk
  - Fix bogus status register use for MSTP clocks
  - Fix bogus mstp3_cls to use its own entries rather than
    that of mstp1_clks

* Update to use "main" in cpg_clocks as per updated
  binding in previous patch
* Update for new, consolidated and renamed index macros
  - R8A7779_CLK_ETHER
  - R8A7779_CLK_HSCIF
  - R8A7779_CLK_HSPI
  - R8A7779_CLK_MMC0,1
  - R8A7779_CLK_PCIE
  - R8A7779_CLK_USB01,2
---
 arch/arm/boot/dts/r8a7779.dtsi | 151 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 151 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4..c0802aa 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 
+#include <dt-bindings/clock/r8a7779-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -278,4 +279,154 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overriden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "extal";
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks at 0xe6150000 {
+			compatible = "renesas,r8a7779-cpg-clocks";
+			reg = <0 0xffc80000 0 0x30>;
+			clocks = <&extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "plla", "z", "zs", "s",
+					     "s1", "p", "b", "out";
+		};
+
+		/* Fixed factor clocks */
+		i_clk: i_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "i";
+		};
+		s3_clk: s3_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "s3";
+		};
+		s4_clk: s4_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <16>;
+			clock-mult = <1>;
+			clock-output-names = "s4";
+		};
+		g_clk: g_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+			clock-output-names = "g";
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80030 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_S>,
+			         <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_S1>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
+				R8A7779_CLK_HSPI R8A7779_CLK_TMU0
+				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
+				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0
+				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
+				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
+				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
+				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
+				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
+			>;
+			clock-output-names =
+				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
+				"tmu2", "hscif1", "hscif0", "scif5", "scif4",
+				"scif3", "scif2", "scif1", "scif0", "i2c3",
+				"i2c2", "i2c1", "i2c0";
+		};
+		mstp1_clks: mstp1_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
+			clocks = <&cpg_clocks R8A7779_CLK_P>,
+			         <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_S>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_P>,
+				 <&cpg_clocks R8A7779_CLK_S>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_USB01 R8A7779_CLK_USB01
+				R8A7779_CLK_USB2 R8A7779_CLK_USB2
+				R8A7779_CLK_DU R8A7779_CLK_VIN2
+				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
+				R8A7779_CLK_ETHER R8A7779_CLK_SATA
+				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
+			>;
+			clock-output-names =
+				"ehci0", "ohci0",
+				"ehci1", "ohci1",
+				"du", "vin2",
+				"vin1", "vin0",
+				"ether", "sata",
+				"pcie", "vin3";
+		};
+		mstp3_clks: mstp3_clks {
+			compatible = "renesas,r8a7779-mstp-clocks",
+			             "renesas,cpg-mstp-clocks";
+			reg = <0 0xffc8003c 0 4>;
+			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
+				 <&s4_clk>, <&s4_clk>;
+			#clock-cells = <1>;
+			renesas,clock-indices = <
+				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
+				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
+				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
+			>;
+			clock-output-names =
+				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
+				"mmc1", "mmc0";
+		};
+	};
 };
-- 
1.8.5.2

[PATCH v4 05/19] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Simon Horman]

Copy the device nodes from Marzen reference into the Marzen device tree
file. This will allow us to use a single DTS file regardless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
will be used.

Based on a similar change for the Lager board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Updated for recent changes to Marzen reference DTS
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 93 ++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2..eda6240 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "marzen";
@@ -24,4 +26,95 @@
 		device_type = "memory";
 		reg = <0x60000000 0x40000000>;
 	};
+
+	fixedregulator3v3: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	lan0@18000000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
+		phy-mode = "mii";
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		reg-io-width = <4>;
+		vddvario-supply = <&fixedregulator3v3>;
+		vdd33a-supply = <&fixedregulator3v3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		};
+		led3 {
+			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		};
+		led4 {
+			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&irqpin0 {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: serial2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: serial4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sd0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		renesas,function = "sdhi0";
+	};
+
+	hspi0_pins: hspi0 {
+		renesas,groups = "hspi0";
+		renesas,function = "hspi0";
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&fixedregulator3v3>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&hspi0 {
+	pinctrl-0 = <&hspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
 };
-- 
1.8.5.2

[PATCH v4 05/19] ARM: shmobile: Sync Marzen DTS with Marzen reference DTS

[Simon Horman]

Copy the device nodes from Marzen reference into the Marzen device tree
file. This will allow us to use a single DTS file regardless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
will be used.

Based on a similar change for the Lager board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Updated for recent changes to Marzen reference DTS
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 93 ++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a7af2c2..eda6240 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -11,6 +11,8 @@
 
 /dts-v1/;
 #include "r8a7779.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "marzen";
@@ -24,4 +26,95 @@
 		device_type = "memory";
 		reg = <0x60000000 0x40000000>;
 	};
+
+	fixedregulator3v3: fixedregulator at 0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	lan0 at 18000000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x18000000 0x100>;
+		pinctrl-0 = <&lan0_pins>;
+		pinctrl-names = "default";
+
+		phy-mode = "mii";
+		interrupt-parent = <&irqpin0>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		reg-io-width = <4>;
+		vddvario-supply = <&fixedregulator3v3>;
+		vdd33a-supply = <&fixedregulator3v3>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led2 {
+			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		};
+		led3 {
+			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		};
+		led4 {
+			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&irqpin0 {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif2_pins &scif4_pins>;
+	pinctrl-names = "default";
+
+	lan0_pins: lan0 {
+		intc {
+			renesas,groups = "intc_irq1_b";
+			renesas,function = "intc";
+		};
+		lbsc {
+			renesas,groups = "lbsc_ex_cs0";
+			renesas,function = "lbsc";
+		};
+	};
+
+	scif2_pins: serial2 {
+		renesas,groups = "scif2_data_c";
+		renesas,function = "scif2";
+	};
+
+	scif4_pins: serial4 {
+		renesas,groups = "scif4_data";
+		renesas,function = "scif4";
+	};
+
+	sdhi0_pins: sd0 {
+		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
+		renesas,function = "sdhi0";
+	};
+
+	hspi0_pins: hspi0 {
+		renesas,groups = "hspi0";
+		renesas,function = "hspi0";
+	};
+};
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-names = "default";
+
+	vmmc-supply = <&fixedregulator3v3>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&hspi0 {
+	pinctrl-0 = <&hspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
 };
-- 
1.8.5.2

[PATCH v4 06/19] ARM: shmobile: marzen: Specify external clock frequency in DT

[Simon Horman]

The external crystal frequency is 31.25 on the Marzen board.
Specify it in the device tree.

Based on work for the Lager board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index eda6240..2c727cd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -68,6 +68,10 @@
 	status = "okay";
 };
 
+&extal_clk {
+	clock-frequency = <31250000>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif2_pins &scif4_pins>;
 	pinctrl-names = "default";
-- 
1.8.5.2

[PATCH v4 06/19] ARM: shmobile: marzen: Specify external clock frequency in DT

[Simon Horman]

The external crystal frequency is 31.25 on the Marzen board.
Specify it in the device tree.

Based on work for the Lager board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Update r8a7779-marzen.dts instead of r8a7779-marzen-reference.dts
---
 arch/arm/boot/dts/r8a7779-marzen.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index eda6240..2c727cd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -68,6 +68,10 @@
 	status = "okay";
 };
 
+&extal_clk {
+	clock-frequency = <31250000>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif2_pins &scif4_pins>;
 	pinctrl-names = "default";
-- 
1.8.5.2

[PATCH v4 07/19] ARM: shmobile: r8a7779: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Also update the following nodes which are now present
  - hspi{0,1,2}
  - sata: Suggested by Laurent Pinchart
---
 arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index c0802aa..dbdc92d 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -166,6 +166,7 @@
 		reg = <0xffc70000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 		status = "disabled";
 	};
 
@@ -176,6 +177,7 @@
 		reg = <0xffc71000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 		status = "disabled";
 	};
 
@@ -186,6 +188,7 @@
 		reg = <0xffc72000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 		status = "disabled";
 	};
 
@@ -196,6 +199,7 @@
 		reg = <0xffc73000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 		status = "disabled";
 	};
 
@@ -214,6 +218,7 @@
 		reg = <0xfc600000 0x2000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 	};
 
 	sdhi0: sd@ffe4c000 {
@@ -221,6 +226,7 @@
 		reg = <0xffe4c000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -231,6 +237,7 @@
 		reg = <0xffe4d000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -241,6 +248,7 @@
 		reg = <0xffe4e000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -251,6 +259,7 @@
 		reg = <0xffe4f000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -261,6 +270,7 @@
 		reg = <0xfffc7000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -269,6 +279,7 @@
 		reg = <0xfffc8000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -277,6 +288,7 @@
 		reg = <0xfffc6000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
-- 
1.8.5.2

[PATCH v4 07/19] ARM: shmobile: r8a7779: Reference clocks

[Simon Horman]

Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.

Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoC.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Also update the following nodes which are now present
  - hspi{0,1,2}
  - sata: Suggested by Laurent Pinchart
---
 arch/arm/boot/dts/r8a7779.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index c0802aa..dbdc92d 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -166,6 +166,7 @@
 		reg = <0xffc70000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 		status = "disabled";
 	};
 
@@ -176,6 +177,7 @@
 		reg = <0xffc71000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 		status = "disabled";
 	};
 
@@ -186,6 +188,7 @@
 		reg = <0xffc72000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 		status = "disabled";
 	};
 
@@ -196,6 +199,7 @@
 		reg = <0xffc73000 0x1000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 		status = "disabled";
 	};
 
@@ -214,6 +218,7 @@
 		reg = <0xfc600000 0x2000>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 	};
 
 	sdhi0: sd at ffe4c000 {
@@ -221,6 +226,7 @@
 		reg = <0xffe4c000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -231,6 +237,7 @@
 		reg = <0xffe4d000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -241,6 +248,7 @@
 		reg = <0xffe4e000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -251,6 +259,7 @@
 		reg = <0xffe4f000 0x100>;
 		interrupt-parent = <&gic>;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -261,6 +270,7 @@
 		reg = <0xfffc7000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -269,6 +279,7 @@
 		reg = <0xfffc8000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
@@ -277,6 +288,7 @@
 		reg = <0xfffc6000 0x18>;
 		interrupt-controller = <&gic>;
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 		status = "disabled";
 	};
 
-- 
1.8.5.2

[PATCH v4 08/19] ARM: shmobile: r8a7779: Add helper to read mode pins

[Simon Horman]

Add and use helper to read mode pins.
This will be re-used when moving marzen-reference to
the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c        | 11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c        | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 8e403ae..b1a5065 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
 
 /*
  *		MD1 = 1			MD1 = 0
@@ -52,9 +53,6 @@
 #define MSTPCR3		IOMEM(0xffc8003c)
 #define MSTPSR1		IOMEM(0xffc80044)
 
-#define MODEMR		0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -209,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7779_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	if (mode & MD(1)) {
 		plla_clk.rate = 1500000000;
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 88eecea..d5ba2d8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -32,6 +32,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8e860b3..f6aeb7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -802,6 +802,20 @@ void __init r8a7779_add_standard_devices_dt(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
+#define MODEMR		0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 static const char *r8a7779_compat_dt[] __initdata = {
 	"renesas,r8a7779",
 	NULL,
-- 
1.8.5.2

[PATCH v4 08/19] ARM: shmobile: r8a7779: Add helper to read mode pins

[Simon Horman]

Add and use helper to read mode pins.
This will be re-used when moving marzen-reference to
the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c        | 11 ++---------
 arch/arm/mach-shmobile/include/mach/r8a7779.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7779.c        | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 8e403ae..b1a5065 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7779.h>
 
 /*
  *		MD1 = 1			MD1 = 0
@@ -52,9 +53,6 @@
 #define MSTPCR3		IOMEM(0xffc8003c)
 #define MSTPSR1		IOMEM(0xffc80044)
 
-#define MODEMR		0xffcc0020
-
-
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
  */
@@ -209,14 +207,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7779_clock_init(void)
 {
-	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-	u32 mode;
+	u32 mode = r8a7779_read_mode_pins();
 	int k, ret = 0;
 
-	BUG_ON(!modemr);
-	mode = ioread32(modemr);
-	iounmap(modemr);
-
 	if (mode & MD(1)) {
 		plla_clk.rate = 1500000000;
 
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 88eecea..d5ba2d8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -32,6 +32,7 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_init_late(void);
+extern u32 r8a7779_read_mode_pins(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8e860b3..f6aeb7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -802,6 +802,20 @@ void __init r8a7779_add_standard_devices_dt(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
+#define MODEMR		0xffcc0020
+
+u32 __init r8a7779_read_mode_pins(void)
+{
+	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+	u32 mode;
+
+	BUG_ON(!modemr);
+	mode = ioread32(modemr);
+	iounmap(modemr);
+
+	return mode;
+}
+
 static const char *r8a7779_compat_dt[] __initdata = {
 	"renesas,r8a7779",
 	NULL,
-- 
1.8.5.2

[PATCH v4 09/19] ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c

[Simon Horman]

r8a7779_earlytimer_init() calls r8a7779_clock_init() and
r8a7779_clock_init() is defined in clock-r8a7779.c.

If both CONFIG_COMMON_CLK and CONFIG_ARCH_R8A7779 are enabled,
as will be the case when marzen-reference moves to use
the common clock framework, then setup-r8a7779.c is compiled
but clock-r8a7779.c is not.

As r8a7779_earlytimer_init() is not used by marzen-reference
simply move it to clock-r8a7779.c.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 +++++++++++
 arch/arm/mach-shmobile/setup-r8a7779.c | 10 ----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b1a5065..e4fc7df 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <linux/sh_timer.h>
 #include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
@@ -263,3 +264,13 @@ void __init r8a7779_clock_init(void)
 	else
 		panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+	r8a7779_clock_init();
+	r8a7779_register_twd();
+	shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f6aeb7f..f28b8c7 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -714,16 +714,6 @@ void __init r8a7779_add_standard_devices(void)
 	r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-	r8a7779_clock_init();
-	r8a7779_register_twd();
-	shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
 	early_platform_add_devices(r8a7779_devices_dt,
-- 
1.8.5.2

[PATCH v4 09/19] ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c

[Simon Horman]

r8a7779_earlytimer_init() calls r8a7779_clock_init() and
r8a7779_clock_init() is defined in clock-r8a7779.c.

If both CONFIG_COMMON_CLK and CONFIG_ARCH_R8A7779 are enabled,
as will be the case when marzen-reference moves to use
the common clock framework, then setup-r8a7779.c is compiled
but clock-r8a7779.c is not.

As r8a7779_earlytimer_init() is not used by marzen-reference
simply move it to clock-r8a7779.c.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7779.c | 11 +++++++++++
 arch/arm/mach-shmobile/setup-r8a7779.c | 10 ----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b1a5065..e4fc7df 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <linux/sh_timer.h>
 #include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
@@ -263,3 +264,13 @@ void __init r8a7779_clock_init(void)
 	else
 		panic("failed to setup r8a7779 clocks\n");
 }
+
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
+
+void __init r8a7779_earlytimer_init(void)
+{
+	r8a7779_clock_init();
+	r8a7779_register_twd();
+	shmobile_earlytimer_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f6aeb7f..f28b8c7 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -714,16 +714,6 @@ void __init r8a7779_add_standard_devices(void)
 	r8a7779_register_hpb_dmae();
 }
 
-/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
-void __init __weak r8a7779_register_twd(void) { }
-
-void __init r8a7779_earlytimer_init(void)
-{
-	r8a7779_clock_init();
-	r8a7779_register_twd();
-	shmobile_earlytimer_init();
-}
-
 void __init r8a7779_add_early_devices(void)
 {
 	early_platform_add_devices(r8a7779_devices_dt,
-- 
1.8.5.2

[PATCH v4 10/19] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board

[Simon Horman]

Move the clock initialisation and OF device population from
SoC to board code. This is in keeping with the pattern used by Lager.
And the clock portion is part of decoupling clock initialisation
from SoC code in preparation for moving to the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 3 +++
 arch/arm/mach-shmobile/setup-r8a7779.c          | 4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936..c22e5c2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -27,7 +28,9 @@
 
 static void __init marzen_init(void)
 {
+	r8a7779_clock_init();
 	r8a7779_add_standard_devices_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f28b8c7..3471a9b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -784,12 +784,8 @@ void __init r8a7779_init_delay(void)
 
 void __init r8a7779_add_standard_devices_dt(void)
 {
-	/* clocks are setup late during boot in the case of DT */
-	r8a7779_clock_init();
-
 	platform_add_devices(r8a7779_devices_dt,
 			     ARRAY_SIZE(r8a7779_devices_dt));
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 #define MODEMR		0xffcc0020
-- 
1.8.5.2

[PATCH v4 10/19] ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board code

[Simon Horman]

Move the clock initialisation and OF device population from
SoC to board code. This is in keeping with the pattern used by Lager.
And the clock portion is part of decoupling clock initialisation
from SoC code in preparation for moving to the common clock framework.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 3 +++
 arch/arm/mach-shmobile/setup-r8a7779.c          | 4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 2773936..c22e5c2 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -27,7 +28,9 @@
 
 static void __init marzen_init(void)
 {
+	r8a7779_clock_init();
 	r8a7779_add_standard_devices_dt();
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
 }
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index f28b8c7..3471a9b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -784,12 +784,8 @@ void __init r8a7779_init_delay(void)
 
 void __init r8a7779_add_standard_devices_dt(void)
 {
-	/* clocks are setup late during boot in the case of DT */
-	r8a7779_clock_init();
-
 	platform_add_devices(r8a7779_devices_dt,
 			     ARRAY_SIZE(r8a7779_devices_dt));
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 #define MODEMR		0xffcc0020
-- 
1.8.5.2

[PATCH v4 11/19] ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h

[Simon Horman]

Do not include sh_clk.h in r8a7779.h as it is not necessary.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index d5ba2d8..757b903 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7779_H__
 #define __ASM_R8A7779_H__
 
-#include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <mach/pm-rcar.h>
 
-- 
1.8.5.2

[PATCH v4 11/19] ARM: shmobile: r8a7779: Do not include sh_clk.h in r8a7779.h

[Simon Horman]

Do not include sh_clk.h in r8a7779.h as it is not necessary.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7779.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index d5ba2d8..757b903 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -1,7 +1,6 @@
 #ifndef __ASM_R8A7779_H__
 #define __ASM_R8A7779_H__
 
-#include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <mach/pm-rcar.h>
 
-- 
1.8.5.2

[PATCH v4 12/19] ARM: shmobile: r8a7779: Initial multiplatform support

[Simon Horman]

Add Marzen and r8a7779 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.

Marzen board support exists in 3 flavours:
1) SHMOBILE_MULTI, MACH_MARZEN - board-marzen-reference.c (CCF + DT)
2) SHMOBILE, MACH_MARZEN_REFERENCE - board-marzen-reference.c (DT)
3) SHMOBILE, MACH_MARZEN - board-marzen.c (legacy C code)

When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.

Based on work for the Koelsch and r8a7791 by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Select RENESAS_INTC_IRQPIN
---
 arch/arm/boot/dts/Makefile                      | 3 ++-
 arch/arm/mach-shmobile/Kconfig                  | 9 +++++++++
 arch/arm/mach-shmobile/Makefile                 | 1 +
 arch/arm/mach-shmobile/board-marzen-reference.c | 5 +++++
 4 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 41927cc..f56e594 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -262,7 +262,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
-	r8a7790-lager.dtb
+	r8a7790-lager.dtb \
+	r8a7779-marzen-reference.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f7465a3..215c742 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,6 +23,10 @@ if ARCH_SHMOBILE_MULTI
 
 comment "Renesas ARM SoCs System Type"
 
+config ARCH_R8A7779
+	bool "R-Car H1 (R8A77790)"
+	select RENESAS_INTC_IRQPIN
+
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
 
@@ -53,6 +57,11 @@ config MACH_LAGER
 	depends on ARCH_R8A7790
 	select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+	bool "MARZEN board"
+	depends on ARCH_R8A7779
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 9c5cd8c..ed49315 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -59,6 +59,7 @@ ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)	+= board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)	+= board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)	+= board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)	+= board-ape6evm-reference.o
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index c22e5c2..d3e8319 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk-provider.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -28,7 +29,11 @@
 
 static void __init marzen_init(void)
 {
+#ifdef CONFIG_COMMON_CLK
+	of_clk_init(NULL);
+#else
 	r8a7779_clock_init();
+#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v4 12/19] ARM: shmobile: r8a7779: Initial multiplatform support

[Simon Horman]

Add Marzen and r8a7779 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.

Marzen board support exists in 3 flavours:
1) SHMOBILE_MULTI, MACH_MARZEN - board-marzen-reference.c (CCF + DT)
2) SHMOBILE, MACH_MARZEN_REFERENCE - board-marzen-reference.c (DT)
3) SHMOBILE, MACH_MARZEN - board-marzen.c (legacy C code)

When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.

Based on work for the Koelsch and r8a7791 by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v3
* Select RENESAS_INTC_IRQPIN
---
 arch/arm/boot/dts/Makefile                      | 3 ++-
 arch/arm/mach-shmobile/Kconfig                  | 9 +++++++++
 arch/arm/mach-shmobile/Makefile                 | 1 +
 arch/arm/mach-shmobile/board-marzen-reference.c | 5 +++++
 4 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 41927cc..f56e594 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -262,7 +262,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
-	r8a7790-lager.dtb
+	r8a7790-lager.dtb \
+	r8a7779-marzen-reference.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f7465a3..215c742 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,6 +23,10 @@ if ARCH_SHMOBILE_MULTI
 
 comment "Renesas ARM SoCs System Type"
 
+config ARCH_R8A7779
+	bool "R-Car H1 (R8A77790)"
+	select RENESAS_INTC_IRQPIN
+
 config ARCH_EMEV2
 	bool "Emma Mobile EV2"
 
@@ -53,6 +57,11 @@ config MACH_LAGER
 	depends on ARCH_R8A7790
 	select MICREL_PHY if SH_ETH
 
+config MACH_MARZEN
+	bool "MARZEN board"
+	depends on ARCH_R8A7779
+	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+
 comment "Renesas ARM SoCs System Configuration"
 endif
 
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 9c5cd8c..ed49315 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -59,6 +59,7 @@ ifdef CONFIG_ARCH_SHMOBILE_MULTI
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_KOELSCH)	+= board-koelsch-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager-reference.o
+obj-$(CONFIG_MACH_MARZEN)	+= board-marzen-reference.o
 else
 obj-$(CONFIG_MACH_APE6EVM)	+= board-ape6evm.o
 obj-$(CONFIG_MACH_APE6EVM_REFERENCE)	+= board-ape6evm-reference.o
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index c22e5c2..d3e8319 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/clk-provider.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -28,7 +29,11 @@
 
 static void __init marzen_init(void)
 {
+#ifdef CONFIG_COMMON_CLK
+	of_clk_init(NULL);
+#else
 	r8a7779_clock_init();
+#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v4 13/19] ARM: shmobile: marzen-reference: Initialize CPG device

[Simon Horman]

On multiplatform kernels clocks are handled by the CCF CPG driver. It
must be explicitly initialized by a call to r8a7779_clocks_init() with
the value of the boot mode pins.

Based on similar work for the Koelsch board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index d3e8319..e261431 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -27,11 +28,17 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static void __init marzen_init(void)
+static void __init marzen_init_timer(void)
 {
 #ifdef CONFIG_COMMON_CLK
-	of_clk_init(NULL);
-#else
+	r8a7779_clocks_init(r8a7779_read_mode_pins());
+#endif
+	clocksource_of_init();
+}
+
+static void __init marzen_init(void)
+{
+#ifndef CONFIG_COMMON_CLK
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
@@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
 	.smp		= smp_ops(r8a7779_smp_ops),
 	.map_io		= r8a7779_map_io,
 	.init_early	= r8a7779_init_delay,
+	.init_time	= marzen_init_timer,
 	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= r8a7779_init_irq_dt,
 	.init_machine	= marzen_init,
-- 
1.8.5.2

[PATCH v4 13/19] ARM: shmobile: marzen-reference: Initialize CPG device

[Simon Horman]

On multiplatform kernels clocks are handled by the CCF CPG driver. It
must be explicitly initialized by a call to r8a7779_clocks_init() with
the value of the boot mode pins.

Based on similar work for the Koelsch board by Laurent Pinchart.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index d3e8319..e261431 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,7 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -27,11 +28,17 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 
-static void __init marzen_init(void)
+static void __init marzen_init_timer(void)
 {
 #ifdef CONFIG_COMMON_CLK
-	of_clk_init(NULL);
-#else
+	r8a7779_clocks_init(r8a7779_read_mode_pins());
+#endif
+	clocksource_of_init();
+}
+
+static void __init marzen_init(void)
+{
+#ifndef CONFIG_COMMON_CLK
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
@@ -48,6 +55,7 @@ DT_MACHINE_START(MARZEN, "marzen")
 	.smp		= smp_ops(r8a7779_smp_ops),
 	.map_io		= r8a7779_map_io,
 	.init_early	= r8a7779_init_delay,
+	.init_time	= marzen_init_timer,
 	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= r8a7779_init_irq_dt,
 	.init_machine	= marzen_init,
-- 
1.8.5.2

[PATCH v4 14/19] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7779.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.

Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven and Magnus Damm
  - Make use of shmobile_clk_workaround()
  - This patch now depends on
    "ARM: shmobile: Introduce shmobile_clk_workaround()"

v3
* Initialise TMU clocks instead of CMT clocks
  - It is TMU that Marzen uses as a clocksource
* Refactor clock initialisation hack as per more recent mainline
  code for Koelsch
* Use IS_ERR to check the return value of clk_get()
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index e261431..5823c83 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -23,6 +23,7 @@
 #include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <asm/irq.h>
@@ -36,9 +37,29 @@ static void __init marzen_init_timer(void)
 	clocksource_of_init();
 }
 
+#ifdef CONFIG_COMMON_CLK
+/*
+ * This is a really crude hack to provide clkdev support to platform
+ * devices until they get moved to DT.
+ */
+static const struct clk_name clk_names[] __initconst = {
+	{ "scif0", NULL, "sh-sci.0" },
+	{ "scif1", NULL, "sh-sci.1" },
+	{ "scif2", NULL, "sh-sci.2" },
+	{ "scif3", NULL, "sh-sci.3" },
+	{ "scif4", NULL, "sh-sci.4" },
+	{ "scif5", NULL, "sh-sci.5" },
+	{ "tmu0", NULL, "sh_tmu.0" },
+	{ "tmu1", NULL, "sh_tmu.1" },
+	{ "tmu2", NULL, "sh_tmu.2" },
+};
+#endif
+
 static void __init marzen_init(void)
 {
-#ifndef CONFIG_COMMON_CLK
+#ifdef CONFIG_COMMON_CLK
+	shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
+#else
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
-- 
1.8.5.2

[PATCH v4 14/19] ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU

[Simon Horman]

Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7779.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.

Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven and Magnus Damm
  - Make use of shmobile_clk_workaround()
  - This patch now depends on
    "ARM: shmobile: Introduce shmobile_clk_workaround()"

v3
* Initialise TMU clocks instead of CMT clocks
  - It is TMU that Marzen uses as a clocksource
* Refactor clock initialisation hack as per more recent mainline
  code for Koelsch
* Use IS_ERR to check the return value of clk_get()
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index e261431..5823c83 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -23,6 +23,7 @@
 #include <linux/clocksource.h>
 #include <linux/of_platform.h>
 #include <mach/r8a7779.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <asm/irq.h>
@@ -36,9 +37,29 @@ static void __init marzen_init_timer(void)
 	clocksource_of_init();
 }
 
+#ifdef CONFIG_COMMON_CLK
+/*
+ * This is a really crude hack to provide clkdev support to platform
+ * devices until they get moved to DT.
+ */
+static const struct clk_name clk_names[] __initconst = {
+	{ "scif0", NULL, "sh-sci.0" },
+	{ "scif1", NULL, "sh-sci.1" },
+	{ "scif2", NULL, "sh-sci.2" },
+	{ "scif3", NULL, "sh-sci.3" },
+	{ "scif4", NULL, "sh-sci.4" },
+	{ "scif5", NULL, "sh-sci.5" },
+	{ "tmu0", NULL, "sh_tmu.0" },
+	{ "tmu1", NULL, "sh_tmu.1" },
+	{ "tmu2", NULL, "sh_tmu.2" },
+};
+#endif
+
 static void __init marzen_init(void)
 {
-#ifndef CONFIG_COMMON_CLK
+#ifdef CONFIG_COMMON_CLK
+	shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
+#else
 	r8a7779_clock_init();
 #endif
 	r8a7779_add_standard_devices_dt();
-- 
1.8.5.2

[PATCH v4 15/19] ARM: shmobile: marzen: Add to shmobile defconfig

[Simon Horman]

Add marzen to shmobile defconfig now that it supports multiplatform

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 2a27d46..1d8e10a 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -9,11 +9,13 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
+CONFIG_MACH_MARZEN=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_PL310_ERRATA_588369=y
-- 
1.8.5.2

[PATCH v4 15/19] ARM: shmobile: marzen: Add to shmobile defconfig

[Simon Horman]

Add marzen to shmobile defconfig now that it supports multiplatform

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 2a27d46..1d8e10a 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -9,11 +9,13 @@ CONFIG_EMBEDDED=y
 CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_ARCH_SHMOBILE_MULTI=y
+CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R8A7790=y
 CONFIG_ARCH_R8A7791=y
 CONFIG_MACH_KOELSCH=y
 CONFIG_MACH_LAGER=y
+CONFIG_MACH_MARZEN=y
 # CONFIG_SWP_EMULATE is not set
 CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_PL310_ERRATA_588369=y
-- 
1.8.5.2

[PATCH v4 16/19] ARM: shmobile: Remove non-multiplatform Marzen reference support

[Simon Horman]

Now that r8a7779 has CCF support remove the legacy Marzen reference
Kconfig bits CONFIG_MACH_MARZEN_REFERENCE for the non-multiplatform
case.

Starting from this commit Marzen board support is always enabled via
CONFIG_MACH_MARZEN, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-marzen.c and board-marzen-reference.c

The file board-marzen-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile           |  1 -
 arch/arm/mach-shmobile/Kconfig       | 13 -------------
 arch/arm/mach-shmobile/Makefile      |  1 -
 arch/arm/mach-shmobile/Makefile.boot |  1 -
 4 files changed, 16 deletions(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f56e594..69cd6b7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -251,7 +251,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
 	r8a7778-bockw-reference.dtb \
 	r8a7740-armadillo800eva-reference.dtb \
 	r8a7779-marzen.dtb \
-	r8a7779-marzen-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
 	sh73a0-kzm9g.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 215c742..d8abb4d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -249,19 +249,6 @@ config MACH_MARZEN
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	select USE_OF
 
-config MACH_MARZEN_REFERENCE
-	bool "MARZEN board - Reference Device Tree Implementation"
-	depends on ARCH_R8A7779
-	select ARCH_REQUIRE_GPIOLIB
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-	select USE_OF
-	---help---
-	   Use reference implementation of Marzen board support
-	   which makes use of device tree at the expense
-	   of not supporting a number of devices.
-
-	   This is intended to aid developers
-
 config MACH_LAGER
 	bool "Lager board"
 	depends on ARCH_R8A7790
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index ed49315..591966e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -69,7 +69,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE)	+= board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai.o
 obj-$(CONFIG_MACH_GENMAI_REFERENCE)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)	+= board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)	+= board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)	+= board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 99455ec..4200b94 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -14,7 +14,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR	:= $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
-- 
1.8.5.2

[PATCH v4 16/19] ARM: shmobile: Remove non-multiplatform Marzen reference support

[Simon Horman]

Now that r8a7779 has CCF support remove the legacy Marzen reference
Kconfig bits CONFIG_MACH_MARZEN_REFERENCE for the non-multiplatform
case.

Starting from this commit Marzen board support is always enabled via
CONFIG_MACH_MARZEN, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-marzen.c and board-marzen-reference.c

The file board-marzen-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile           |  1 -
 arch/arm/mach-shmobile/Kconfig       | 13 -------------
 arch/arm/mach-shmobile/Makefile      |  1 -
 arch/arm/mach-shmobile/Makefile.boot |  1 -
 4 files changed, 16 deletions(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f56e594..69cd6b7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -251,7 +251,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
 	r8a7778-bockw-reference.dtb \
 	r8a7740-armadillo800eva-reference.dtb \
 	r8a7779-marzen.dtb \
-	r8a7779-marzen-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
 	sh73a0-kzm9g.dtb \
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 215c742..d8abb4d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -249,19 +249,6 @@ config MACH_MARZEN
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
 	select USE_OF
 
-config MACH_MARZEN_REFERENCE
-	bool "MARZEN board - Reference Device Tree Implementation"
-	depends on ARCH_R8A7779
-	select ARCH_REQUIRE_GPIOLIB
-	select REGULATOR_FIXED_VOLTAGE if REGULATOR
-	select USE_OF
-	---help---
-	   Use reference implementation of Marzen board support
-	   which makes use of device tree at the expense
-	   of not supporting a number of devices.
-
-	   This is intended to aid developers
-
 config MACH_LAGER
 	bool "Lager board"
 	depends on ARCH_R8A7790
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index ed49315..591966e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -69,7 +69,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE)	+= board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)	+= board-genmai.o
 obj-$(CONFIG_MACH_GENMAI_REFERENCE)	+= board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)	+= board-marzen.o
-obj-$(CONFIG_MACH_MARZEN_REFERENCE)	+= board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)	+= board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)	+= board-armadillo800eva.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)	+= board-armadillo800eva-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 99455ec..4200b94 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -14,7 +14,6 @@ loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
 loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
 loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
 loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
-loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
 __ZRELADDR	:= $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
-- 
1.8.5.2

[PATCH v4 17/19] ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB

[Simon Horman]

Let the multiplatform Marzen support boot with the legacy DTS for
Marzen as well as the Marzen reference DTS.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile                      | 2 +-
 arch/arm/mach-shmobile/board-marzen-reference.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 69cd6b7..cbec54c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -262,7 +262,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
-	r8a7779-marzen-reference.dtb
+	r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 5823c83..741a076 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -68,6 +68,7 @@ static void __init marzen_init(void)
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+	"renesas,marzen",
 	"renesas,marzen-reference",
 	NULL,
 };
-- 
1.8.5.2

[PATCH v4 17/19] ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB

[Simon Horman]

Let the multiplatform Marzen support boot with the legacy DTS for
Marzen as well as the Marzen reference DTS.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/Makefile                      | 2 +-
 arch/arm/mach-shmobile/board-marzen-reference.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 69cd6b7..cbec54c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -262,7 +262,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
 	r7s72100-genmai-reference.dtb \
 	r8a7791-koelsch.dtb \
 	r8a7790-lager.dtb \
-	r8a7779-marzen-reference.dtb
+	r8a7779-marzen.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
 	socfpga_cyclone5_socdk.dtb \
 	socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 5823c83..741a076 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -68,6 +68,7 @@ static void __init marzen_init(void)
 }
 
 static const char *marzen_boards_compat_dt[] __initdata = {
+	"renesas,marzen",
 	"renesas,marzen-reference",
 	NULL,
 };
-- 
1.8.5.2

[PATCH v4 18/19] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

Now that the DTS file r8a7790-marzen.dts can be used with
board-marzen.c and board-marzen-reference.c, proceed with removing
r8a7790-marzen-reference.dts.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120 -------------------------
 1 file changed, 120 deletions(-)
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index 76f5eef..0000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "marzen";
-	compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-	chosen {
-		bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	fixedregulator3v3: fixedregulator@0 {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	lan0@18000000 {
-		compatible = "smsc,lan9220", "smsc,lan9115";
-		reg = <0x18000000 0x100>;
-		pinctrl-0 = <&lan0_pins>;
-		pinctrl-names = "default";
-
-		phy-mode = "mii";
-		interrupt-parent = <&irqpin0>;
-		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		reg-io-width = <4>;
-		vddvario-supply = <&fixedregulator3v3>;
-		vdd33a-supply = <&fixedregulator3v3>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led2 {
-			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-		};
-		led3 {
-			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-		};
-		led4 {
-			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&irqpin0 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif2_pins &scif4_pins>;
-	pinctrl-names = "default";
-
-	lan0_pins: lan0 {
-		intc {
-			renesas,groups = "intc_irq1_b";
-			renesas,function = "intc";
-		};
-		lbsc {
-			renesas,groups = "lbsc_ex_cs0";
-			renesas,function = "lbsc";
-		};
-	};
-
-	scif2_pins: serial2 {
-		renesas,groups = "scif2_data_c";
-		renesas,function = "scif2";
-	};
-
-	scif4_pins: serial4 {
-		renesas,groups = "scif4_data";
-		renesas,function = "scif4";
-	};
-
-	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
-	};
-
-	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0";
-		renesas,function = "hspi0";
-	};
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
-
-	vmmc-supply = <&fixedregulator3v3>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&hspi0 {
-	pinctrl-0 = <&hspi0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-- 
1.8.5.2

[PATCH v4 18/19] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

Now that the DTS file r8a7790-marzen.dts can be used with
board-marzen.c and board-marzen-reference.c, proceed with removing
r8a7790-marzen-reference.dts.

Based on work for the Koelsch board by Laurent Pinchart.

Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120 -------------------------
 1 file changed, 120 deletions(-)
 delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts

diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index 76f5eef..0000000
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-#include "r8a7779.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "marzen";
-	compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
-	chosen {
-		bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
-	};
-
-	memory {
-		device_type = "memory";
-		reg = <0x60000000 0x40000000>;
-	};
-
-	fixedregulator3v3: fixedregulator at 0 {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	lan0 at 18000000 {
-		compatible = "smsc,lan9220", "smsc,lan9115";
-		reg = <0x18000000 0x100>;
-		pinctrl-0 = <&lan0_pins>;
-		pinctrl-names = "default";
-
-		phy-mode = "mii";
-		interrupt-parent = <&irqpin0>;
-		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
-		reg-io-width = <4>;
-		vddvario-supply = <&fixedregulator3v3>;
-		vdd33a-supply = <&fixedregulator3v3>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led2 {
-			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
-		};
-		led3 {
-			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-		};
-		led4 {
-			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&irqpin0 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif2_pins &scif4_pins>;
-	pinctrl-names = "default";
-
-	lan0_pins: lan0 {
-		intc {
-			renesas,groups = "intc_irq1_b";
-			renesas,function = "intc";
-		};
-		lbsc {
-			renesas,groups = "lbsc_ex_cs0";
-			renesas,function = "lbsc";
-		};
-	};
-
-	scif2_pins: serial2 {
-		renesas,groups = "scif2_data_c";
-		renesas,function = "scif2";
-	};
-
-	scif4_pins: serial4 {
-		renesas,groups = "scif4_data";
-		renesas,function = "scif4";
-	};
-
-	sdhi0_pins: sd0 {
-		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
-		renesas,function = "sdhi0";
-	};
-
-	hspi0_pins: hspi0 {
-		renesas,groups = "hspi0";
-		renesas,function = "hspi0";
-	};
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
-
-	vmmc-supply = <&fixedregulator3v3>;
-	bus-width = <4>;
-	status = "okay";
-};
-
-&hspi0 {
-	pinctrl-0 = <&hspi0_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-- 
1.8.5.2

[PATCH v4 19/19] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

Marzen DT reference is now only built for multiplatform
which means that CCF comes with the package. Remove unused legacy
code ifdefs to clean up the code.

Based on similar work for the Koelsch board by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven
  - Remove bogus "these" from changelog
* Rebase
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 741a076..f96fe65 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -31,13 +31,10 @@
 
 static void __init marzen_init_timer(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	r8a7779_clocks_init(r8a7779_read_mode_pins());
-#endif
 	clocksource_of_init();
 }
 
-#ifdef CONFIG_COMMON_CLK
 /*
  * This is a really crude hack to provide clkdev support to platform
  * devices until they get moved to DT.
@@ -53,15 +50,10 @@ static const struct clk_name clk_names[] __initconst = {
 	{ "tmu1", NULL, "sh_tmu.1" },
 	{ "tmu2", NULL, "sh_tmu.2" },
 };
-#endif
 
 static void __init marzen_init(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-#else
-	r8a7779_clock_init();
-#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

[PATCH v4 19/19] ARM: shmobile: marzen-reference: Remove legacy clock support

[Simon Horman]

Marzen DT reference is now only built for multiplatform
which means that CCF comes with the package. Remove unused legacy
code ifdefs to clean up the code.

Based on similar work for the Koelsch board by Magnus Damm.

Cc: Magnus Damm <damm@opensource.se>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

---
v4
* As suggested by Geert Uytterhoeven
  - Remove bogus "these" from changelog
* Rebase
---
 arch/arm/mach-shmobile/board-marzen-reference.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 741a076..f96fe65 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -31,13 +31,10 @@
 
 static void __init marzen_init_timer(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	r8a7779_clocks_init(r8a7779_read_mode_pins());
-#endif
 	clocksource_of_init();
 }
 
-#ifdef CONFIG_COMMON_CLK
 /*
  * This is a really crude hack to provide clkdev support to platform
  * devices until they get moved to DT.
@@ -53,15 +50,10 @@ static const struct clk_name clk_names[] __initconst = {
 	{ "tmu1", NULL, "sh_tmu.1" },
 	{ "tmu2", NULL, "sh_tmu.2" },
 };
-#endif
 
 static void __init marzen_init(void)
 {
-#ifdef CONFIG_COMMON_CLK
 	shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
-#else
-	r8a7779_clock_init();
-#endif
 	r8a7779_add_standard_devices_dt();
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 	r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
-- 
1.8.5.2

Re: [PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> The R8A7779 SoC has several clocks that are too custom to be supported in a
> generic driver. Those clocks are all fixed rate clocks with multiplier and
> divisor set according to boot mode configuration.
> 
> Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> Under discussion
> * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> string added. I am less enthusiastic.

Apart from this I have just a small comment, please see below. All the rest 
looks good to me.

> v4
> * As suggested by Geert Uytterhoeven
>   - Remove double and from bindings documentation
>   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
>   - Correct order of cpg_clk_configs entries
> * As suggested by Laurent Pinchart
>   - Update copyright to include 2014
>   - Remove reference to non-existent divider clocks in changelog
>   - Do not map cpg->reg as it is not accessed
>   - Return an error for unknown name values in r8a7779_cpg_register_clock()
>   - Expose clkb in binding
>   - Do not include MSPT registers in register range in binding example
> * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
>   (to me)
> v3
> * As suggested by Laurent Pinchart
>   - Added external clock input
>   - Use PLLA ratio set bu MD11 and MD12
>   - Add _div suffixes of fields of struct cpt_clk_config
>   - Register PLLA as a fixed factor clock
>   - Use sizeof() instead of sizeof
>   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> 
>   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
>     binding which could be shared with other SoCs as I do not believe that
>     the SoCs is are sufficiently similar.
> ---
>  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
>  drivers/clk/shmobile/Makefile                      |   1 +
>  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
>  3 +
>  4 files changed, 212 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> new file mode 100644
> index 0000000..ed3c8cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,27 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +several fixed ratio dividers
> +
> +Required Properties:
> +
> +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> +  - reg: Base address and length of the memory resource used by the CPG
> +
> +  - clocks: Reference to the parent clock
> +  - #clock-cells: Must be 1
> +  - clock-output-names: The names of the clocks. Supported clocks are
> "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> +
> +
> +Example
> +-------
> +
> +	cpg_clocks: cpg_clocks@ffc80000 {
> +		compatible = "renesas,r8a7779-cpg-clocks";
> +		reg = <0 0xffc80000 0 0x30>;
> +		clocks = <&extal_clk>;
> +		#clock-cells = <1>;
> +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> +		                     "b", "out";
> +	};
> diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> index 9ecef14..2121ba0 100644
> --- a/drivers/clk/shmobile/Makefile
> +++ b/drivers/clk/shmobile/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
>  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> index 0000000..8974a41
> --- /dev/null
> +++ b/drivers/clk/shmobile/clk-r8a7779.c
> @@ -0,0 +1,181 @@
> +/*
> + * r8a7779 Core CPG Clocks
> + *
> + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/clock/r8a7779-clock.h>
> +
> +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> +
> +struct r8a7779_cpg {
> +	struct clk_onecell_data data;
> +	spinlock_t lock;
> +	void __iomem *reg;
> +};
> +
> +/*
> ---------------------------------------------------------------------------
> -- + * CPG Clock Data
> + */
> +
> +/*
> + *		MD1 = 1			MD1 = 0
> + *		(PLLA = 1500)		(PLLA = 1600)
> + *		(MHz)			(MHz)
> + *------------------------------------------------+--------------------
> + * clkz		1000   (2/3)		800   (1/2)
> + * clkzs	 250   (1/6)		200   (1/8)
> + * clki		 750   (1/2)		800   (1/2)
> + * clks		 250   (1/6)		200   (1/8)
> + * clks1	 125   (1/12)		100   (1/16)
> + * clks3	 187.5 (1/8)		200   (1/8)
> + * clks4	  93.7 (1/16)		100   (1/16)
> + * clkp		  62.5 (1/24)		 50   (1/32)
> + * clkg		  62.5 (1/24)		 66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> +
> +struct cpg_clk_config {
> +	unsigned int z_mult;
> +	unsigned int z_div;
> +	unsigned int zs_and_s_div;
> +	unsigned int s1_div;
> +	unsigned int p_div;
> +	unsigned int b_and_out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 2, 3, 6, 12, 24, 24 },
> +	{ 1, 2, 8, 16, 32, 32 },
> +	{ 2, 3, 6, 12, 24, 36 },
> +};
> +
> +/*
> + *   MD		PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0		x42
> + * 0  1		x48
> + * 1  0		x56
> + * 1  1		x64
> + */
> +
> +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> +
> +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> }; +
> +/*
> ---------------------------------------------------------------------------
> -- + * Initialization
> + */
> +
> +static u32 cpg_mode __initdata;
> +
> +static struct clk * __init
> +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> +			   const struct cpg_clk_config *config,
> +			   unsigned int plla_mult, const char *name)
> +{
> +	const char *parent_name = "plla";
> +	unsigned int mult = 1;
> +	unsigned int div = 1;
> +
> +	if (!strcmp(name, "plla")) {
> +		parent_name = of_clk_get_parent_name(np, 0);
> +		mult = plla_mult;
> +	} else if (!strcmp(name, "z")) {
> +		div = config->z_div;
> +		mult = config->z_mult;
> +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> +		div = config->zs_and_s_div;
> +	} else if (!strcmp(name, "s1")) {
> +		div = config->s1_div;
> +	} else if (!strcmp(name, "p")) {
> +		div = config->p_div;
> +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> +		div = config->b_and_out_div;
> +	} else {
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> +}
> +
> +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> +{
> +	const struct cpg_clk_config *config;
> +	struct r8a7779_cpg *cpg;
> +	struct clk **clks;
> +	unsigned int i, plla_mult;
> +	int num_clks;
> +
> +	num_clks = of_property_count_strings(np, "clock-output-names");
> +	if (num_clks < 0) {
> +		pr_err("%s: failed to count clocks\n", __func__);
> +		return;
> +	}
> +
> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg = NULL || clks = NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);

It has recently been pointed out to me that kzalloc failures print an OOM 
message to the kernel log, so there's no need to duplicate it.

> +		return;
> +	}
> +
> +	spin_lock_init(&cpg->lock);
> +
> +	cpg->data.clks = clks;
> +	cpg->data.clk_num = num_clks;
> +
> +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> +
> +	for (i = 0; i < num_clks; ++i) {
> +		const char *name;
> +		struct clk *clk;
> +
> +		of_property_read_string_index(np, "clock-output-names", i,
> +					      &name);
> +
> +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> +						 plla_mult, name);
> +		if (IS_ERR(clk))
> +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> +			       __func__, np->name, name, PTR_ERR(clk));
> +		else
> +			cpg->data.clks[i] = clk;
> +	}
> +
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> +}
> +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> +	       r8a7779_cpg_clocks_init);


-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> The R8A7779 SoC has several clocks that are too custom to be supported in a
> generic driver. Those clocks are all fixed rate clocks with multiplier and
> divisor set according to boot mode configuration.
> 
> Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> Under discussion
> * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> string added. I am less enthusiastic.

Apart from this I have just a small comment, please see below. All the rest 
looks good to me.

> v4
> * As suggested by Geert Uytterhoeven
>   - Remove double and from bindings documentation
>   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
>   - Correct order of cpg_clk_configs entries
> * As suggested by Laurent Pinchart
>   - Update copyright to include 2014
>   - Remove reference to non-existent divider clocks in changelog
>   - Do not map cpg->reg as it is not accessed
>   - Return an error for unknown name values in r8a7779_cpg_register_clock()
>   - Expose clkb in binding
>   - Do not include MSPT registers in register range in binding example
> * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
>   (to me)
> v3
> * As suggested by Laurent Pinchart
>   - Added external clock input
>   - Use PLLA ratio set bu MD11 and MD12
>   - Add _div suffixes of fields of struct cpt_clk_config
>   - Register PLLA as a fixed factor clock
>   - Use sizeof() instead of sizeof
>   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> 
>   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
>     binding which could be shared with other SoCs as I do not believe that
>     the SoCs is are sufficiently similar.
> ---
>  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
>  drivers/clk/shmobile/Makefile                      |   1 +
>  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
>  3 +
>  4 files changed, 212 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> new file mode 100644
> index 0000000..ed3c8cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,27 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +several fixed ratio dividers
> +
> +Required Properties:
> +
> +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> +  - reg: Base address and length of the memory resource used by the CPG
> +
> +  - clocks: Reference to the parent clock
> +  - #clock-cells: Must be 1
> +  - clock-output-names: The names of the clocks. Supported clocks are
> "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> +
> +
> +Example
> +-------
> +
> +	cpg_clocks: cpg_clocks@ffc80000 {
> +		compatible = "renesas,r8a7779-cpg-clocks";
> +		reg = <0 0xffc80000 0 0x30>;
> +		clocks = <&extal_clk>;
> +		#clock-cells = <1>;
> +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> +		                     "b", "out";
> +	};
> diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> index 9ecef14..2121ba0 100644
> --- a/drivers/clk/shmobile/Makefile
> +++ b/drivers/clk/shmobile/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
>  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> index 0000000..8974a41
> --- /dev/null
> +++ b/drivers/clk/shmobile/clk-r8a7779.c
> @@ -0,0 +1,181 @@
> +/*
> + * r8a7779 Core CPG Clocks
> + *
> + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/clock/r8a7779-clock.h>
> +
> +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> +
> +struct r8a7779_cpg {
> +	struct clk_onecell_data data;
> +	spinlock_t lock;
> +	void __iomem *reg;
> +};
> +
> +/*
> ---------------------------------------------------------------------------
> -- + * CPG Clock Data
> + */
> +
> +/*
> + *		MD1 = 1			MD1 = 0
> + *		(PLLA = 1500)		(PLLA = 1600)
> + *		(MHz)			(MHz)
> + *------------------------------------------------+--------------------
> + * clkz		1000   (2/3)		800   (1/2)
> + * clkzs	 250   (1/6)		200   (1/8)
> + * clki		 750   (1/2)		800   (1/2)
> + * clks		 250   (1/6)		200   (1/8)
> + * clks1	 125   (1/12)		100   (1/16)
> + * clks3	 187.5 (1/8)		200   (1/8)
> + * clks4	  93.7 (1/16)		100   (1/16)
> + * clkp		  62.5 (1/24)		 50   (1/32)
> + * clkg		  62.5 (1/24)		 66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> +
> +struct cpg_clk_config {
> +	unsigned int z_mult;
> +	unsigned int z_div;
> +	unsigned int zs_and_s_div;
> +	unsigned int s1_div;
> +	unsigned int p_div;
> +	unsigned int b_and_out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 2, 3, 6, 12, 24, 24 },
> +	{ 1, 2, 8, 16, 32, 32 },
> +	{ 2, 3, 6, 12, 24, 36 },
> +};
> +
> +/*
> + *   MD		PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0		x42
> + * 0  1		x48
> + * 1  0		x56
> + * 1  1		x64
> + */
> +
> +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> +
> +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> }; +
> +/*
> ---------------------------------------------------------------------------
> -- + * Initialization
> + */
> +
> +static u32 cpg_mode __initdata;
> +
> +static struct clk * __init
> +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> +			   const struct cpg_clk_config *config,
> +			   unsigned int plla_mult, const char *name)
> +{
> +	const char *parent_name = "plla";
> +	unsigned int mult = 1;
> +	unsigned int div = 1;
> +
> +	if (!strcmp(name, "plla")) {
> +		parent_name = of_clk_get_parent_name(np, 0);
> +		mult = plla_mult;
> +	} else if (!strcmp(name, "z")) {
> +		div = config->z_div;
> +		mult = config->z_mult;
> +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> +		div = config->zs_and_s_div;
> +	} else if (!strcmp(name, "s1")) {
> +		div = config->s1_div;
> +	} else if (!strcmp(name, "p")) {
> +		div = config->p_div;
> +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> +		div = config->b_and_out_div;
> +	} else {
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> +}
> +
> +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> +{
> +	const struct cpg_clk_config *config;
> +	struct r8a7779_cpg *cpg;
> +	struct clk **clks;
> +	unsigned int i, plla_mult;
> +	int num_clks;
> +
> +	num_clks = of_property_count_strings(np, "clock-output-names");
> +	if (num_clks < 0) {
> +		pr_err("%s: failed to count clocks\n", __func__);
> +		return;
> +	}
> +
> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg == NULL || clks == NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);

It has recently been pointed out to me that kzalloc failures print an OOM 
message to the kernel log, so there's no need to duplicate it.

> +		return;
> +	}
> +
> +	spin_lock_init(&cpg->lock);
> +
> +	cpg->data.clks = clks;
> +	cpg->data.clk_num = num_clks;
> +
> +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> +
> +	for (i = 0; i < num_clks; ++i) {
> +		const char *name;
> +		struct clk *clk;
> +
> +		of_property_read_string_index(np, "clock-output-names", i,
> +					      &name);
> +
> +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> +						 plla_mult, name);
> +		if (IS_ERR(clk))
> +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> +			       __func__, np->name, name, PTR_ERR(clk));
> +		else
> +			cpg->data.clks[i] = clk;
> +	}
> +
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> +}
> +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> +	       r8a7779_cpg_clocks_init);


-- 
Regards,

Laurent Pinchart

[PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> The R8A7779 SoC has several clocks that are too custom to be supported in a
> generic driver. Those clocks are all fixed rate clocks with multiplier and
> divisor set according to boot mode configuration.
> 
> Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> Under discussion
> * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> string added. I am less enthusiastic.

Apart from this I have just a small comment, please see below. All the rest 
looks good to me.

> v4
> * As suggested by Geert Uytterhoeven
>   - Remove double and from bindings documentation
>   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
>   - Correct order of cpg_clk_configs entries
> * As suggested by Laurent Pinchart
>   - Update copyright to include 2014
>   - Remove reference to non-existent divider clocks in changelog
>   - Do not map cpg->reg as it is not accessed
>   - Return an error for unknown name values in r8a7779_cpg_register_clock()
>   - Expose clkb in binding
>   - Do not include MSPT registers in register range in binding example
> * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
>   (to me)
> v3
> * As suggested by Laurent Pinchart
>   - Added external clock input
>   - Use PLLA ratio set bu MD11 and MD12
>   - Add _div suffixes of fields of struct cpt_clk_config
>   - Register PLLA as a fixed factor clock
>   - Use sizeof() instead of sizeof
>   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> 
>   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
>     binding which could be shared with other SoCs as I do not believe that
>     the SoCs is are sufficiently similar.
> ---
>  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
>  drivers/clk/shmobile/Makefile                      |   1 +
>  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
>  3 +
>  4 files changed, 212 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> 
> diff --git
> a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> new file mode 100644
> index 0000000..ed3c8cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> @@ -0,0 +1,27 @@
> +* Renesas R8A7779 Clock Pulse Generator (CPG)
> +
> +The CPG generates core clocks for the R8A7779. It includes one PLL and
> +several fixed ratio dividers
> +
> +Required Properties:
> +
> +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> +  - reg: Base address and length of the memory resource used by the CPG
> +
> +  - clocks: Reference to the parent clock
> +  - #clock-cells: Must be 1
> +  - clock-output-names: The names of the clocks. Supported clocks are
> "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> +
> +
> +Example
> +-------
> +
> +	cpg_clocks: cpg_clocks at ffc80000 {
> +		compatible = "renesas,r8a7779-cpg-clocks";
> +		reg = <0 0xffc80000 0 0x30>;
> +		clocks = <&extal_clk>;
> +		#clock-cells = <1>;
> +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> +		                     "b", "out";
> +	};
> diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> index 9ecef14..2121ba0 100644
> --- a/drivers/clk/shmobile/Makefile
> +++ b/drivers/clk/shmobile/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
>  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
>  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> index 0000000..8974a41
> --- /dev/null
> +++ b/drivers/clk/shmobile/clk-r8a7779.c
> @@ -0,0 +1,181 @@
> +/*
> + * r8a7779 Core CPG Clocks
> + *
> + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> + *
> + * Contact: Simon Horman <horms@verge.net.au>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/shmobile.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/clock/r8a7779-clock.h>
> +
> +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> +
> +struct r8a7779_cpg {
> +	struct clk_onecell_data data;
> +	spinlock_t lock;
> +	void __iomem *reg;
> +};
> +
> +/*
> ---------------------------------------------------------------------------
> -- + * CPG Clock Data
> + */
> +
> +/*
> + *		MD1 = 1			MD1 = 0
> + *		(PLLA = 1500)		(PLLA = 1600)
> + *		(MHz)			(MHz)
> + *------------------------------------------------+--------------------
> + * clkz		1000   (2/3)		800   (1/2)
> + * clkzs	 250   (1/6)		200   (1/8)
> + * clki		 750   (1/2)		800   (1/2)
> + * clks		 250   (1/6)		200   (1/8)
> + * clks1	 125   (1/12)		100   (1/16)
> + * clks3	 187.5 (1/8)		200   (1/8)
> + * clks4	  93.7 (1/16)		100   (1/16)
> + * clkp		  62.5 (1/24)		 50   (1/32)
> + * clkg		  62.5 (1/24)		 66.6 (1/24)
> + * clkb, CLKOUT
> + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> + */
> +
> +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> +
> +struct cpg_clk_config {
> +	unsigned int z_mult;
> +	unsigned int z_div;
> +	unsigned int zs_and_s_div;
> +	unsigned int s1_div;
> +	unsigned int p_div;
> +	unsigned int b_and_out_div;
> +};
> +
> +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> +	{ 1, 2, 8, 16, 32, 24 },
> +	{ 2, 3, 6, 12, 24, 24 },
> +	{ 1, 2, 8, 16, 32, 32 },
> +	{ 2, 3, 6, 12, 24, 36 },
> +};
> +
> +/*
> + *   MD		PLLA Ratio
> + * 12 11
> + *------------------------
> + * 0  0		x42
> + * 0  1		x48
> + * 1  0		x56
> + * 1  1		x64
> + */
> +
> +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> +
> +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> }; +
> +/*
> ---------------------------------------------------------------------------
> -- + * Initialization
> + */
> +
> +static u32 cpg_mode __initdata;
> +
> +static struct clk * __init
> +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> +			   const struct cpg_clk_config *config,
> +			   unsigned int plla_mult, const char *name)
> +{
> +	const char *parent_name = "plla";
> +	unsigned int mult = 1;
> +	unsigned int div = 1;
> +
> +	if (!strcmp(name, "plla")) {
> +		parent_name = of_clk_get_parent_name(np, 0);
> +		mult = plla_mult;
> +	} else if (!strcmp(name, "z")) {
> +		div = config->z_div;
> +		mult = config->z_mult;
> +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> +		div = config->zs_and_s_div;
> +	} else if (!strcmp(name, "s1")) {
> +		div = config->s1_div;
> +	} else if (!strcmp(name, "p")) {
> +		div = config->p_div;
> +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> +		div = config->b_and_out_div;
> +	} else {
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> +}
> +
> +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> +{
> +	const struct cpg_clk_config *config;
> +	struct r8a7779_cpg *cpg;
> +	struct clk **clks;
> +	unsigned int i, plla_mult;
> +	int num_clks;
> +
> +	num_clks = of_property_count_strings(np, "clock-output-names");
> +	if (num_clks < 0) {
> +		pr_err("%s: failed to count clocks\n", __func__);
> +		return;
> +	}
> +
> +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> +	if (cpg == NULL || clks == NULL) {
> +		/* We're leaking memory on purpose, there's no point in cleaning
> +		 * up as the system won't boot anyway.
> +		 */
> +		pr_err("%s: failed to allocate cpg\n", __func__);

It has recently been pointed out to me that kzalloc failures print an OOM 
message to the kernel log, so there's no need to duplicate it.

> +		return;
> +	}
> +
> +	spin_lock_init(&cpg->lock);
> +
> +	cpg->data.clks = clks;
> +	cpg->data.clk_num = num_clks;
> +
> +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> +
> +	for (i = 0; i < num_clks; ++i) {
> +		const char *name;
> +		struct clk *clk;
> +
> +		of_property_read_string_index(np, "clock-output-names", i,
> +					      &name);
> +
> +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> +						 plla_mult, name);
> +		if (IS_ERR(clk))
> +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> +			       __func__, np->name, name, PTR_ERR(clk));
> +		else
> +			cpg->data.clks[i] = clk;
> +	}
> +
> +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> +}
> +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> +	       r8a7779_cpg_clocks_init);


-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Thursday 13 March 2014 17:59:47 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v4
> * As suggested by Geert Uytterhoeven
>   - Wrap lines at < 80columns
>   - Beef-up short lines towards 80 columns
> * As suggested by Laurent Pinchart
>   - Add HSCIF clocks
>   - Correct many clock sources
>   - Correct reg of cpg_clocks
> * Add CPG clock "b" which is now part of the binding
> 
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 151 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 151 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..c0802aa 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,154 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks@0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xffc80000 0 0x30>;
> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "b", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
> +				R8A7779_CLK_HSPI

I would define a single HSPI clock and reference it from the three HSPI 
instances. Having three identical copies of a single clock will not work, the 
first clock to be disabled will disable the other two as they would all share 
the same register bit. Don't forget to remove two of the three CLK_S 
references above.

> 				R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0

Bad copy and paste ? This should be TMU2, TMU1 and TMU0.

> +				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0

HSCIF1 and HSCIF0 ?

> +				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
> +				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> +				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names > +				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
> +				"tmu2",

Following the comments above, this should become

"hspi", "tmu2", "tmu1", "tmu0".

> "hscif1", "hscif0", "scif5", "scif4",
> +				"scif3", "scif2", "scif1", "scif0", "i2c3",
> +				"i2c2", "i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> +			         <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01

Same as above, two instances of the same hardware clock won't fly.

> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2

Same here.

> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names > +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",

Following the comments above, this would become "usb01", "usb2".

> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
> +				 <&s4_clk>, <&s4_clk>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names > +				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

[PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Laurent Pinchart]

Hi Simon,

Thank you for the patch.

On Thursday 13 March 2014 17:59:47 Simon Horman wrote:
> Declare all core and MSTP clocks currently used by r8a7779-based boards.
> 
> Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> 
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> ---
> v4
> * As suggested by Geert Uytterhoeven
>   - Wrap lines at < 80columns
>   - Beef-up short lines towards 80 columns
> * As suggested by Laurent Pinchart
>   - Add HSCIF clocks
>   - Correct many clock sources
>   - Correct reg of cpg_clocks
> * Add CPG clock "b" which is now part of the binding
> 
> v3
> * As suggested by Laurent Pinchart
>   - Add and use extal_clk
>   - Fix bogus status register use for MSTP clocks
>   - Fix bogus mstp3_cls to use its own entries rather than
>     that of mstp1_clks
> 
> * Update to use "main" in cpg_clocks as per updated
>   binding in previous patch
> * Update for new, consolidated and renamed index macros
>   - R8A7779_CLK_ETHER
>   - R8A7779_CLK_HSCIF
>   - R8A7779_CLK_HSPI
>   - R8A7779_CLK_MMC0,1
>   - R8A7779_CLK_PCIE
>   - R8A7779_CLK_USB01,2
> ---
>  arch/arm/boot/dts/r8a7779.dtsi | 151 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 151 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> index d0561d4..c0802aa 100644
> --- a/arch/arm/boot/dts/r8a7779.dtsi
> +++ b/arch/arm/boot/dts/r8a7779.dtsi
> @@ -11,6 +11,7 @@
> 
>  /include/ "skeleton.dtsi"
> 
> +#include <dt-bindings/clock/r8a7779-clock.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> 
>  / {
> @@ -278,4 +279,154 @@
>  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> +
> +	clocks {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* External root clock */
> +		extal_clk: extal_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			/* This value must be overriden by the board. */
> +			clock-frequency = <0>;
> +			clock-output-names = "extal";
> +		};
> +
> +		/* Special CPG clocks */
> +		cpg_clocks: cpg_clocks at 0xe6150000 {
> +			compatible = "renesas,r8a7779-cpg-clocks";
> +			reg = <0 0xffc80000 0 0x30>;
> +			clocks = <&extal_clk>;
> +			#clock-cells = <1>;
> +			clock-output-names = "plla", "z", "zs", "s",
> +					     "s1", "p", "b", "out";
> +		};
> +
> +		/* Fixed factor clocks */
> +		i_clk: i_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <2>;
> +			clock-mult = <1>;
> +			clock-output-names = "i";
> +		};
> +		s3_clk: s3_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <8>;
> +			clock-mult = <1>;
> +			clock-output-names = "s3";
> +		};
> +		s4_clk: s4_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <16>;
> +			clock-mult = <1>;
> +			clock-output-names = "s4";
> +		};
> +		g_clk: g_clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> +			#clock-cells = <0>;
> +			clock-div = <24>;
> +			clock-mult = <1>;
> +			clock-output-names = "g";
> +		};
> +
> +		/* Gate clocks */
> +		mstp0_clks: mstp0_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc80030 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_S>,
> +			         <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_S1>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
> +				R8A7779_CLK_HSPI

I would define a single HSPI clock and reference it from the three HSPI 
instances. Having three identical copies of a single clock will not work, the 
first clock to be disabled will disable the other two as they would all share 
the same register bit. Don't forget to remove two of the three CLK_S 
references above.

> 				R8A7779_CLK_TMU0
> +				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0

Bad copy and paste ? This should be TMU2, TMU1 and TMU0.

> +				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0

HSCIF1 and HSCIF0 ?

> +				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
> +				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> +				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> +			>;
> +			clock-output-names =
> +				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
> +				"tmu2",

Following the comments above, this should become

"hspi", "tmu2", "tmu1", "tmu0".

> "hscif1", "hscif0", "scif5", "scif4",
> +				"scif3", "scif2", "scif1", "scif0", "i2c3",
> +				"i2c2", "i2c1", "i2c0";
> +		};
> +		mstp1_clks: mstp1_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> +			         <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_S>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_P>,
> +				 <&cpg_clocks R8A7779_CLK_S>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_USB01 R8A7779_CLK_USB01

Same as above, two instances of the same hardware clock won't fly.

> +				R8A7779_CLK_USB2 R8A7779_CLK_USB2

Same here.

> +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> +			>;
> +			clock-output-names =
> +				"ehci0", "ohci0",
> +				"ehci1", "ohci1",

Following the comments above, this would become "usb01", "usb2".

> +				"du", "vin2",
> +				"vin1", "vin0",
> +				"ether", "sata",
> +				"pcie", "vin3";
> +		};
> +		mstp3_clks: mstp3_clks {
> +			compatible = "renesas,r8a7779-mstp-clocks",
> +			             "renesas,cpg-mstp-clocks";
> +			reg = <0 0xffc8003c 0 4>;
> +			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
> +				 <&s4_clk>, <&s4_clk>;
> +			#clock-cells = <1>;
> +			renesas,clock-indices = <
> +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> +			>;
> +			clock-output-names =
> +				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
> +				"mmc1", "mmc0";
> +		};
> +	};
>  };

-- 
Regards,

Laurent Pinchart

Re: [PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Thu, Mar 13, 2014 at 10:34:07AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> > The R8A7779 SoC has several clocks that are too custom to be supported in a
> > generic driver. Those clocks are all fixed rate clocks with multiplier and
> > divisor set according to boot mode configuration.
> > 
> > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree@vger.kernel.org
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > Under discussion
> > * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> > string added. I am less enthusiastic.
> 
> Apart from this I have just a small comment, please see below. All the rest 
> looks good to me.
> 
> > v4
> > * As suggested by Geert Uytterhoeven
> >   - Remove double and from bindings documentation
> >   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
> >   - Correct order of cpg_clk_configs entries
> > * As suggested by Laurent Pinchart
> >   - Update copyright to include 2014
> >   - Remove reference to non-existent divider clocks in changelog
> >   - Do not map cpg->reg as it is not accessed
> >   - Return an error for unknown name values in r8a7779_cpg_register_clock()
> >   - Expose clkb in binding
> >   - Do not include MSPT registers in register range in binding example
> > * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
> >   (to me)
> > v3
> > * As suggested by Laurent Pinchart
> >   - Added external clock input
> >   - Use PLLA ratio set bu MD11 and MD12
> >   - Add _div suffixes of fields of struct cpt_clk_config
> >   - Register PLLA as a fixed factor clock
> >   - Use sizeof() instead of sizeof
> >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> > 
> >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> >     binding which could be shared with other SoCs as I do not believe that
> >     the SoCs is are sufficiently similar.
> > ---
> >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
> >  drivers/clk/shmobile/Makefile                      |   1 +
> >  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> > +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
> >  3 +
> >  4 files changed, 212 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > new file mode 100644
> > index 0000000..ed3c8cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,27 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +several fixed ratio dividers
> > +
> > +Required Properties:
> > +
> > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > +  - reg: Base address and length of the memory resource used by the CPG
> > +
> > +  - clocks: Reference to the parent clock
> > +  - #clock-cells: Must be 1
> > +  - clock-output-names: The names of the clocks. Supported clocks are
> > "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> > +
> > +
> > +Example
> > +-------
> > +
> > +	cpg_clocks: cpg_clocks@ffc80000 {
> > +		compatible = "renesas,r8a7779-cpg-clocks";
> > +		reg = <0 0xffc80000 0 0x30>;
> > +		clocks = <&extal_clk>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> > +		                     "b", "out";
> > +	};
> > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > index 9ecef14..2121ba0 100644
> > --- a/drivers/clk/shmobile/Makefile
> > +++ b/drivers/clk/shmobile/Makefile
> > @@ -1,4 +1,5 @@
> >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > index 0000000..8974a41
> > --- /dev/null
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > @@ -0,0 +1,181 @@
> > +/*
> > + * r8a7779 Core CPG Clocks
> > + *
> > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > + *
> > + * Contact: Simon Horman <horms@verge.net.au>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/clk/shmobile.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> > +
> > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > +
> > +struct r8a7779_cpg {
> > +	struct clk_onecell_data data;
> > +	spinlock_t lock;
> > +	void __iomem *reg;
> > +};
> > +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *		MD1 = 1			MD1 = 0
> > + *		(PLLA = 1500)		(PLLA = 1600)
> > + *		(MHz)			(MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz		1000   (2/3)		800   (1/2)
> > + * clkzs	 250   (1/6)		200   (1/8)
> > + * clki		 750   (1/2)		800   (1/2)
> > + * clks		 250   (1/6)		200   (1/8)
> > + * clks1	 125   (1/12)		100   (1/16)
> > + * clks3	 187.5 (1/8)		200   (1/8)
> > + * clks4	  93.7 (1/16)		100   (1/16)
> > + * clkp		  62.5 (1/24)		 50   (1/32)
> > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +	unsigned int z_mult;
> > +	unsigned int z_div;
> > +	unsigned int zs_and_s_div;
> > +	unsigned int s1_div;
> > +	unsigned int p_div;
> > +	unsigned int b_and_out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 2, 3, 6, 12, 24, 24 },
> > +	{ 1, 2, 8, 16, 32, 32 },
> > +	{ 2, 3, 6, 12, 24, 36 },
> > +};
> > +
> > +/*
> > + *   MD		PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0		x42
> > + * 0  1		x48
> > + * 1  0		x56
> > + * 1  1		x64
> > + */
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > +
> > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > }; +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * Initialization
> > + */
> > +
> > +static u32 cpg_mode __initdata;
> > +
> > +static struct clk * __init
> > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> > +			   const struct cpg_clk_config *config,
> > +			   unsigned int plla_mult, const char *name)
> > +{
> > +	const char *parent_name = "plla";
> > +	unsigned int mult = 1;
> > +	unsigned int div = 1;
> > +
> > +	if (!strcmp(name, "plla")) {
> > +		parent_name = of_clk_get_parent_name(np, 0);
> > +		mult = plla_mult;
> > +	} else if (!strcmp(name, "z")) {
> > +		div = config->z_div;
> > +		mult = config->z_mult;
> > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > +		div = config->zs_and_s_div;
> > +	} else if (!strcmp(name, "s1")) {
> > +		div = config->s1_div;
> > +	} else if (!strcmp(name, "p")) {
> > +		div = config->p_div;
> > +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> > +		div = config->b_and_out_div;
> > +	} else {
> > +		return ERR_PTR(-EINVAL);
> > +	}
> > +
> > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> > +}
> > +
> > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > +{
> > +	const struct cpg_clk_config *config;
> > +	struct r8a7779_cpg *cpg;
> > +	struct clk **clks;
> > +	unsigned int i, plla_mult;
> > +	int num_clks;
> > +
> > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > +	if (num_clks < 0) {
> > +		pr_err("%s: failed to count clocks\n", __func__);
> > +		return;
> > +	}
> > +
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg = NULL || clks = NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> 
> It has recently been pointed out to me that kzalloc failures print an OOM 
> message to the kernel log, so there's no need to duplicate it.

Thanks, I will remove the pr_err() line.

> 
> > +		return;
> > +	}
> > +
> > +	spin_lock_init(&cpg->lock);
> > +
> > +	cpg->data.clks = clks;
> > +	cpg->data.clk_num = num_clks;
> > +
> > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> > +
> > +	for (i = 0; i < num_clks; ++i) {
> > +		const char *name;
> > +		struct clk *clk;
> > +
> > +		of_property_read_string_index(np, "clock-output-names", i,
> > +					      &name);
> > +
> > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > +						 plla_mult, name);
> > +		if (IS_ERR(clk))
> > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > +			       __func__, np->name, name, PTR_ERR(clk));
> > +		else
> > +			cpg->data.clks[i] = clk;
> > +	}
> > +
> > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > +}
> > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > +	       r8a7779_cpg_clocks_init);
> 
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

Re: [PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Thu, Mar 13, 2014 at 10:34:07AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> > The R8A7779 SoC has several clocks that are too custom to be supported in a
> > generic driver. Those clocks are all fixed rate clocks with multiplier and
> > divisor set according to boot mode configuration.
> > 
> > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree@vger.kernel.org
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > Under discussion
> > * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> > string added. I am less enthusiastic.
> 
> Apart from this I have just a small comment, please see below. All the rest 
> looks good to me.
> 
> > v4
> > * As suggested by Geert Uytterhoeven
> >   - Remove double and from bindings documentation
> >   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
> >   - Correct order of cpg_clk_configs entries
> > * As suggested by Laurent Pinchart
> >   - Update copyright to include 2014
> >   - Remove reference to non-existent divider clocks in changelog
> >   - Do not map cpg->reg as it is not accessed
> >   - Return an error for unknown name values in r8a7779_cpg_register_clock()
> >   - Expose clkb in binding
> >   - Do not include MSPT registers in register range in binding example
> > * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
> >   (to me)
> > v3
> > * As suggested by Laurent Pinchart
> >   - Added external clock input
> >   - Use PLLA ratio set bu MD11 and MD12
> >   - Add _div suffixes of fields of struct cpt_clk_config
> >   - Register PLLA as a fixed factor clock
> >   - Use sizeof() instead of sizeof
> >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> > 
> >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> >     binding which could be shared with other SoCs as I do not believe that
> >     the SoCs is are sufficiently similar.
> > ---
> >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
> >  drivers/clk/shmobile/Makefile                      |   1 +
> >  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> > +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
> >  3 +
> >  4 files changed, 212 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > new file mode 100644
> > index 0000000..ed3c8cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,27 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +several fixed ratio dividers
> > +
> > +Required Properties:
> > +
> > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > +  - reg: Base address and length of the memory resource used by the CPG
> > +
> > +  - clocks: Reference to the parent clock
> > +  - #clock-cells: Must be 1
> > +  - clock-output-names: The names of the clocks. Supported clocks are
> > "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> > +
> > +
> > +Example
> > +-------
> > +
> > +	cpg_clocks: cpg_clocks@ffc80000 {
> > +		compatible = "renesas,r8a7779-cpg-clocks";
> > +		reg = <0 0xffc80000 0 0x30>;
> > +		clocks = <&extal_clk>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> > +		                     "b", "out";
> > +	};
> > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > index 9ecef14..2121ba0 100644
> > --- a/drivers/clk/shmobile/Makefile
> > +++ b/drivers/clk/shmobile/Makefile
> > @@ -1,4 +1,5 @@
> >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > index 0000000..8974a41
> > --- /dev/null
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > @@ -0,0 +1,181 @@
> > +/*
> > + * r8a7779 Core CPG Clocks
> > + *
> > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > + *
> > + * Contact: Simon Horman <horms@verge.net.au>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/clk/shmobile.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> > +
> > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > +
> > +struct r8a7779_cpg {
> > +	struct clk_onecell_data data;
> > +	spinlock_t lock;
> > +	void __iomem *reg;
> > +};
> > +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *		MD1 = 1			MD1 = 0
> > + *		(PLLA = 1500)		(PLLA = 1600)
> > + *		(MHz)			(MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz		1000   (2/3)		800   (1/2)
> > + * clkzs	 250   (1/6)		200   (1/8)
> > + * clki		 750   (1/2)		800   (1/2)
> > + * clks		 250   (1/6)		200   (1/8)
> > + * clks1	 125   (1/12)		100   (1/16)
> > + * clks3	 187.5 (1/8)		200   (1/8)
> > + * clks4	  93.7 (1/16)		100   (1/16)
> > + * clkp		  62.5 (1/24)		 50   (1/32)
> > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +	unsigned int z_mult;
> > +	unsigned int z_div;
> > +	unsigned int zs_and_s_div;
> > +	unsigned int s1_div;
> > +	unsigned int p_div;
> > +	unsigned int b_and_out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 2, 3, 6, 12, 24, 24 },
> > +	{ 1, 2, 8, 16, 32, 32 },
> > +	{ 2, 3, 6, 12, 24, 36 },
> > +};
> > +
> > +/*
> > + *   MD		PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0		x42
> > + * 0  1		x48
> > + * 1  0		x56
> > + * 1  1		x64
> > + */
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > +
> > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > }; +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * Initialization
> > + */
> > +
> > +static u32 cpg_mode __initdata;
> > +
> > +static struct clk * __init
> > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> > +			   const struct cpg_clk_config *config,
> > +			   unsigned int plla_mult, const char *name)
> > +{
> > +	const char *parent_name = "plla";
> > +	unsigned int mult = 1;
> > +	unsigned int div = 1;
> > +
> > +	if (!strcmp(name, "plla")) {
> > +		parent_name = of_clk_get_parent_name(np, 0);
> > +		mult = plla_mult;
> > +	} else if (!strcmp(name, "z")) {
> > +		div = config->z_div;
> > +		mult = config->z_mult;
> > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > +		div = config->zs_and_s_div;
> > +	} else if (!strcmp(name, "s1")) {
> > +		div = config->s1_div;
> > +	} else if (!strcmp(name, "p")) {
> > +		div = config->p_div;
> > +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> > +		div = config->b_and_out_div;
> > +	} else {
> > +		return ERR_PTR(-EINVAL);
> > +	}
> > +
> > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> > +}
> > +
> > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > +{
> > +	const struct cpg_clk_config *config;
> > +	struct r8a7779_cpg *cpg;
> > +	struct clk **clks;
> > +	unsigned int i, plla_mult;
> > +	int num_clks;
> > +
> > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > +	if (num_clks < 0) {
> > +		pr_err("%s: failed to count clocks\n", __func__);
> > +		return;
> > +	}
> > +
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg == NULL || clks == NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> 
> It has recently been pointed out to me that kzalloc failures print an OOM 
> message to the kernel log, so there's no need to duplicate it.

Thanks, I will remove the pr_err() line.

> 
> > +		return;
> > +	}
> > +
> > +	spin_lock_init(&cpg->lock);
> > +
> > +	cpg->data.clks = clks;
> > +	cpg->data.clk_num = num_clks;
> > +
> > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> > +
> > +	for (i = 0; i < num_clks; ++i) {
> > +		const char *name;
> > +		struct clk *clk;
> > +
> > +		of_property_read_string_index(np, "clock-output-names", i,
> > +					      &name);
> > +
> > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > +						 plla_mult, name);
> > +		if (IS_ERR(clk))
> > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > +			       __func__, np->name, name, PTR_ERR(clk));
> > +		else
> > +			cpg->data.clks[i] = clk;
> > +	}
> > +
> > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > +}
> > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > +	       r8a7779_cpg_clocks_init);
> 
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

[PATCH v4 01/19] clk: shmobile: r8a7779: Add clocks support

[Simon Horman]

On Thu, Mar 13, 2014 at 10:34:07AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.
> 
> On Thursday 13 March 2014 17:59:44 Simon Horman wrote:
> > The R8A7779 SoC has several clocks that are too custom to be supported in a
> > generic driver. Those clocks are all fixed rate clocks with multiplier and
> > divisor set according to boot mode configuration.
> > 
> > Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree at vger.kernel.org
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > Under discussion
> > * Laurent Pinchart would like an "renesas,rcar-gen1-cpg-clocks" compat
> > string added. I am less enthusiastic.
> 
> Apart from this I have just a small comment, please see below. All the rest 
> looks good to me.
> 
> > v4
> > * As suggested by Geert Uytterhoeven
> >   - Remove double and from bindings documentation
> >   - Remove unused CPG_PLL_CONFIG_INDEX and struct cpg_pll_config
> >   - Correct order of cpg_clk_configs entries
> > * As suggested by Laurent Pinchart
> >   - Update copyright to include 2014
> >   - Remove reference to non-existent divider clocks in changelog
> >   - Do not map cpg->reg as it is not accessed
> >   - Return an error for unknown name values in r8a7779_cpg_register_clock()
> >   - Expose clkb in binding
> >   - Do not include MSPT registers in register range in binding example
> > * Write (BIT(2)|BIT(1)) instead of (BIT(1)|BIT(2)) as it is less confusing
> >   (to me)
> > v3
> > * As suggested by Laurent Pinchart
> >   - Added external clock input
> >   - Use PLLA ratio set bu MD11 and MD12
> >   - Add _div suffixes of fields of struct cpt_clk_config
> >   - Register PLLA as a fixed factor clock
> >   - Use sizeof() instead of sizeof
> >   - Use num_clks instead of CPG_NUM_CLOCKS in r8a7779_cpg_clocks_init()
> > 
> >   - I kept this as r8a7779 binding rather than moving to a R-Car Gen1
> >     binding which could be shared with other SoCs as I do not believe that
> >     the SoCs is are sufficiently similar.
> > ---
> >  .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  |  27 +++
> >  drivers/clk/shmobile/Makefile                      |   1 +
> >  drivers/clk/shmobile/clk-r8a7779.c                 | 181
> > +++++++++++++++++++++ include/linux/clk/shmobile.h                       | 
> >  3 +
> >  4 files changed, 212 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > create mode 100644 drivers/clk/shmobile/clk-r8a7779.c
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > new file mode 100644
> > index 0000000..ed3c8cb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
> > @@ -0,0 +1,27 @@
> > +* Renesas R8A7779 Clock Pulse Generator (CPG)
> > +
> > +The CPG generates core clocks for the R8A7779. It includes one PLL and
> > +several fixed ratio dividers
> > +
> > +Required Properties:
> > +
> > +  - compatible: Must be "renesas,r8a7779-cpg-clocks"
> > +  - reg: Base address and length of the memory resource used by the CPG
> > +
> > +  - clocks: Reference to the parent clock
> > +  - #clock-cells: Must be 1
> > +  - clock-output-names: The names of the clocks. Supported clocks are
> > "plla", +    "z", "zs", "s", "s1", "p", "b", "out".
> > +
> > +
> > +Example
> > +-------
> > +
> > +	cpg_clocks: cpg_clocks at ffc80000 {
> > +		compatible = "renesas,r8a7779-cpg-clocks";
> > +		reg = <0 0xffc80000 0 0x30>;
> > +		clocks = <&extal_clk>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "plla", "z", "zs", "s", "s1", "p",
> > +		                     "b", "out";
> > +	};
> > diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
> > index 9ecef14..2121ba0 100644
> > --- a/drivers/clk/shmobile/Makefile
> > +++ b/drivers/clk/shmobile/Makefile
> > @@ -1,4 +1,5 @@
> >  obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
> > +obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
> >  obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
> >  obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
> > diff --git a/drivers/clk/shmobile/clk-r8a7779.c
> > b/drivers/clk/shmobile/clk-r8a7779.c new file mode 100644
> > index 0000000..8974a41
> > --- /dev/null
> > +++ b/drivers/clk/shmobile/clk-r8a7779.c
> > @@ -0,0 +1,181 @@
> > +/*
> > + * r8a7779 Core CPG Clocks
> > + *
> > + * Copyright (C) 2013, 2014 Horms Solutions Ltd.
> > + *
> > + * Contact: Simon Horman <horms@verge.net.au>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/clk/shmobile.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> > +
> > +#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)
> > +
> > +struct r8a7779_cpg {
> > +	struct clk_onecell_data data;
> > +	spinlock_t lock;
> > +	void __iomem *reg;
> > +};
> > +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * CPG Clock Data
> > + */
> > +
> > +/*
> > + *		MD1 = 1			MD1 = 0
> > + *		(PLLA = 1500)		(PLLA = 1600)
> > + *		(MHz)			(MHz)
> > + *------------------------------------------------+--------------------
> > + * clkz		1000   (2/3)		800   (1/2)
> > + * clkzs	 250   (1/6)		200   (1/8)
> > + * clki		 750   (1/2)		800   (1/2)
> > + * clks		 250   (1/6)		200   (1/8)
> > + * clks1	 125   (1/12)		100   (1/16)
> > + * clks3	 187.5 (1/8)		200   (1/8)
> > + * clks4	  93.7 (1/16)		100   (1/16)
> > + * clkp		  62.5 (1/24)		 50   (1/32)
> > + * clkg		  62.5 (1/24)		 66.6 (1/24)
> > + * clkb, CLKOUT
> > + * (MD2 = 0)	  62.5 (1/24)		 66.6 (1/24)
> > + * (MD2 = 1)	  41.6 (1/36)		 50   (1/32)
> > + */
> > +
> > +#define CPG_CLK_CONFIG_INDEX(md)	(((md) & (BIT(2)|BIT(1))) >> 1)
> > +
> > +struct cpg_clk_config {
> > +	unsigned int z_mult;
> > +	unsigned int z_div;
> > +	unsigned int zs_and_s_div;
> > +	unsigned int s1_div;
> > +	unsigned int p_div;
> > +	unsigned int b_and_out_div;
> > +};
> > +
> > +static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
> > +	{ 1, 2, 8, 16, 32, 24 },
> > +	{ 2, 3, 6, 12, 24, 24 },
> > +	{ 1, 2, 8, 16, 32, 32 },
> > +	{ 2, 3, 6, 12, 24, 36 },
> > +};
> > +
> > +/*
> > + *   MD		PLLA Ratio
> > + * 12 11
> > + *------------------------
> > + * 0  0		x42
> > + * 0  1		x48
> > + * 1  0		x56
> > + * 1  1		x64
> > + */
> > +
> > +#define CPG_PLLA_MULT_INDEX(md)	(((md) & (BIT(12)|BIT(11))) >> 11)
> > +
> > +static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64
> > }; +
> > +/*
> > ---------------------------------------------------------------------------
> > -- + * Initialization
> > + */
> > +
> > +static u32 cpg_mode __initdata;
> > +
> > +static struct clk * __init
> > +r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
> > +			   const struct cpg_clk_config *config,
> > +			   unsigned int plla_mult, const char *name)
> > +{
> > +	const char *parent_name = "plla";
> > +	unsigned int mult = 1;
> > +	unsigned int div = 1;
> > +
> > +	if (!strcmp(name, "plla")) {
> > +		parent_name = of_clk_get_parent_name(np, 0);
> > +		mult = plla_mult;
> > +	} else if (!strcmp(name, "z")) {
> > +		div = config->z_div;
> > +		mult = config->z_mult;
> > +	} else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
> > +		div = config->zs_and_s_div;
> > +	} else if (!strcmp(name, "s1")) {
> > +		div = config->s1_div;
> > +	} else if (!strcmp(name, "p")) {
> > +		div = config->p_div;
> > +	} else if (!strcmp(name, "b") || !strcmp(name, "out")) {
> > +		div = config->b_and_out_div;
> > +	} else {
> > +		return ERR_PTR(-EINVAL);
> > +	}
> > +
> > +	return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
> > +}
> > +
> > +static void __init r8a7779_cpg_clocks_init(struct device_node *np)
> > +{
> > +	const struct cpg_clk_config *config;
> > +	struct r8a7779_cpg *cpg;
> > +	struct clk **clks;
> > +	unsigned int i, plla_mult;
> > +	int num_clks;
> > +
> > +	num_clks = of_property_count_strings(np, "clock-output-names");
> > +	if (num_clks < 0) {
> > +		pr_err("%s: failed to count clocks\n", __func__);
> > +		return;
> > +	}
> > +
> > +	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
> > +	clks = kzalloc(CPG_NUM_CLOCKS * sizeof(*clks), GFP_KERNEL);
> > +	if (cpg == NULL || clks == NULL) {
> > +		/* We're leaking memory on purpose, there's no point in cleaning
> > +		 * up as the system won't boot anyway.
> > +		 */
> > +		pr_err("%s: failed to allocate cpg\n", __func__);
> 
> It has recently been pointed out to me that kzalloc failures print an OOM 
> message to the kernel log, so there's no need to duplicate it.

Thanks, I will remove the pr_err() line.

> 
> > +		return;
> > +	}
> > +
> > +	spin_lock_init(&cpg->lock);
> > +
> > +	cpg->data.clks = clks;
> > +	cpg->data.clk_num = num_clks;
> > +
> > +	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)];
> > +	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)];
> > +
> > +	for (i = 0; i < num_clks; ++i) {
> > +		const char *name;
> > +		struct clk *clk;
> > +
> > +		of_property_read_string_index(np, "clock-output-names", i,
> > +					      &name);
> > +
> > +		clk = r8a7779_cpg_register_clock(np, cpg, config,
> > +						 plla_mult, name);
> > +		if (IS_ERR(clk))
> > +			pr_err("%s: failed to register %s %s clock (%ld)\n",
> > +			       __func__, np->name, name, PTR_ERR(clk));
> > +		else
> > +			cpg->data.clks[i] = clk;
> > +	}
> > +
> > +	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
> > +}
> > +CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
> > +	       r8a7779_cpg_clocks_init);
> 
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

Re: [PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Hi Laurent,

On Thu, Mar 13, 2014 at 10:54:03AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.

Thanks for your review.
I will fix things up as you suggest.

> 
> On Thursday 13 March 2014 17:59:47 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v4
> > * As suggested by Geert Uytterhoeven
> >   - Wrap lines at < 80columns
> >   - Beef-up short lines towards 80 columns
> > * As suggested by Laurent Pinchart
> >   - Add HSCIF clocks
> >   - Correct many clock sources
> >   - Correct reg of cpg_clocks
> > * Add CPG clock "b" which is now part of the binding
> > 
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 151 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 151 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..c0802aa 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,154 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks@0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xffc80000 0 0x30>;
> > +			clocks = <&extal_clk>;
> > +			#clock-cells = <1>;
> > +			clock-output-names = "plla", "z", "zs", "s",
> > +					     "s1", "p", "b", "out";
> > +		};
> > +
> > +		/* Fixed factor clocks */
> > +		i_clk: i_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <2>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "i";
> > +		};
> > +		s3_clk: s3_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <8>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s3";
> > +		};
> > +		s4_clk: s4_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <16>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s4";
> > +		};
> > +		g_clk: g_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <24>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "g";
> > +		};
> > +
> > +		/* Gate clocks */
> > +		mstp0_clks: mstp0_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc80030 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
> > +				R8A7779_CLK_HSPI
> 
> I would define a single HSPI clock and reference it from the three HSPI 
> instances. Having three identical copies of a single clock will not work, the 
> first clock to be disabled will disable the other two as they would all share 
> the same register bit. Don't forget to remove two of the three CLK_S 
> references above.
> 
> > 				R8A7779_CLK_TMU0
> > +				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> 
> Bad copy and paste ? This should be TMU2, TMU1 and TMU0.
> 
> > +				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0
> 
> HSCIF1 and HSCIF0 ?
> 
> > +				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
> > +				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> > +				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> > +			>;
> > +			clock-output-names > > +				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
> > +				"tmu2",
> 
> Following the comments above, this should become
> 
> "hspi", "tmu2", "tmu1", "tmu0".
> 
> > "hscif1", "hscif0", "scif5", "scif4",
> > +				"scif3", "scif2", "scif1", "scif0", "i2c3",
> > +				"i2c2", "i2c1", "i2c0";
> > +		};
> > +		mstp1_clks: mstp1_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> > +			         <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> 
> Same as above, two instances of the same hardware clock won't fly.
> 
> > +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> 
> Same here.
> 
> > +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +			>;
> > +			clock-output-names > > +				"ehci0", "ohci0",
> > +				"ehci1", "ohci1",
> 
> Following the comments above, this would become "usb01", "usb2".
> 
> > +				"du", "vin2",
> > +				"vin1", "vin0",
> > +				"ether", "sata",
> > +				"pcie", "vin3";
> > +		};
> > +		mstp3_clks: mstp3_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc8003c 0 4>;
> > +			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
> > +				 <&s4_clk>, <&s4_clk>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> > +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> > +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> > +			>;
> > +			clock-output-names > > +				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
> > +				"mmc1", "mmc0";
> > +		};
> > +	};
> >  };
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

[PATCH v4 04/19] ARM: shmobile: r8a7779: Add clocks

[Simon Horman]

Hi Laurent,

On Thu, Mar 13, 2014 at 10:54:03AM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> Thank you for the patch.

Thanks for your review.
I will fix things up as you suggest.

> 
> On Thursday 13 March 2014 17:59:47 Simon Horman wrote:
> > Declare all core and MSTP clocks currently used by r8a7779-based boards.
> > 
> > Based on work by Laurent Pinchart for the r8a7790 and r8a7791 SoCs.
> > 
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > ---
> > v4
> > * As suggested by Geert Uytterhoeven
> >   - Wrap lines at < 80columns
> >   - Beef-up short lines towards 80 columns
> > * As suggested by Laurent Pinchart
> >   - Add HSCIF clocks
> >   - Correct many clock sources
> >   - Correct reg of cpg_clocks
> > * Add CPG clock "b" which is now part of the binding
> > 
> > v3
> > * As suggested by Laurent Pinchart
> >   - Add and use extal_clk
> >   - Fix bogus status register use for MSTP clocks
> >   - Fix bogus mstp3_cls to use its own entries rather than
> >     that of mstp1_clks
> > 
> > * Update to use "main" in cpg_clocks as per updated
> >   binding in previous patch
> > * Update for new, consolidated and renamed index macros
> >   - R8A7779_CLK_ETHER
> >   - R8A7779_CLK_HSCIF
> >   - R8A7779_CLK_HSPI
> >   - R8A7779_CLK_MMC0,1
> >   - R8A7779_CLK_PCIE
> >   - R8A7779_CLK_USB01,2
> > ---
> >  arch/arm/boot/dts/r8a7779.dtsi | 151 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 151 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
> > index d0561d4..c0802aa 100644
> > --- a/arch/arm/boot/dts/r8a7779.dtsi
> > +++ b/arch/arm/boot/dts/r8a7779.dtsi
> > @@ -11,6 +11,7 @@
> > 
> >  /include/ "skeleton.dtsi"
> > 
> > +#include <dt-bindings/clock/r8a7779-clock.h>
> >  #include <dt-bindings/interrupt-controller/irq.h>
> > 
> >  / {
> > @@ -278,4 +279,154 @@
> >  		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> >  		status = "disabled";
> >  	};
> > +
> > +	clocks {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* External root clock */
> > +		extal_clk: extal_clk {
> > +			compatible = "fixed-clock";
> > +			#clock-cells = <0>;
> > +			/* This value must be overriden by the board. */
> > +			clock-frequency = <0>;
> > +			clock-output-names = "extal";
> > +		};
> > +
> > +		/* Special CPG clocks */
> > +		cpg_clocks: cpg_clocks at 0xe6150000 {
> > +			compatible = "renesas,r8a7779-cpg-clocks";
> > +			reg = <0 0xffc80000 0 0x30>;
> > +			clocks = <&extal_clk>;
> > +			#clock-cells = <1>;
> > +			clock-output-names = "plla", "z", "zs", "s",
> > +					     "s1", "p", "b", "out";
> > +		};
> > +
> > +		/* Fixed factor clocks */
> > +		i_clk: i_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <2>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "i";
> > +		};
> > +		s3_clk: s3_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <8>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s3";
> > +		};
> > +		s4_clk: s4_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <16>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "s4";
> > +		};
> > +		g_clk: g_clk {
> > +			compatible = "fixed-factor-clock";
> > +			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
> > +			#clock-cells = <0>;
> > +			clock-div = <24>;
> > +			clock-mult = <1>;
> > +			clock-output-names = "g";
> > +		};
> > +
> > +		/* Gate clocks */
> > +		mstp0_clks: mstp0_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc80030 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_S>,
> > +			         <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_S1>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_HSPI R8A7779_CLK_HSPI
> > +				R8A7779_CLK_HSPI
> 
> I would define a single HSPI clock and reference it from the three HSPI 
> instances. Having three identical copies of a single clock will not work, the 
> first clock to be disabled will disable the other two as they would all share 
> the same register bit. Don't forget to remove two of the three CLK_S 
> references above.
> 
> > 				R8A7779_CLK_TMU0
> > +				R8A7779_CLK_TMU0 R8A7779_CLK_TMU0
> 
> Bad copy and paste ? This should be TMU2, TMU1 and TMU0.
> 
> > +				R8A7779_CLK_HSCIF0 R8A7779_CLK_HSCIF0
> 
> HSCIF1 and HSCIF0 ?
> 
> > +				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
> > +				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
> > +				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
> > +				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
> > +				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
> > +			>;
> > +			clock-output-names =
> > +				"hspi0", "hspi1", "hspi2", "tmu0", "tmu1",
> > +				"tmu2",
> 
> Following the comments above, this should become
> 
> "hspi", "tmu2", "tmu1", "tmu0".
> 
> > "hscif1", "hscif0", "scif5", "scif4",
> > +				"scif3", "scif2", "scif1", "scif0", "i2c3",
> > +				"i2c2", "i2c1", "i2c0";
> > +		};
> > +		mstp1_clks: mstp1_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
> > +			clocks = <&cpg_clocks R8A7779_CLK_P>,
> > +			         <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_S>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_P>,
> > +				 <&cpg_clocks R8A7779_CLK_S>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_USB01 R8A7779_CLK_USB01
> 
> Same as above, two instances of the same hardware clock won't fly.
> 
> > +				R8A7779_CLK_USB2 R8A7779_CLK_USB2
> 
> Same here.
> 
> > +				R8A7779_CLK_DU R8A7779_CLK_VIN2
> > +				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
> > +				R8A7779_CLK_ETHER R8A7779_CLK_SATA
> > +				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
> > +			>;
> > +			clock-output-names =
> > +				"ehci0", "ohci0",
> > +				"ehci1", "ohci1",
> 
> Following the comments above, this would become "usb01", "usb2".
> 
> > +				"du", "vin2",
> > +				"vin1", "vin0",
> > +				"ether", "sata",
> > +				"pcie", "vin3";
> > +		};
> > +		mstp3_clks: mstp3_clks {
> > +			compatible = "renesas,r8a7779-mstp-clocks",
> > +			             "renesas,cpg-mstp-clocks";
> > +			reg = <0 0xffc8003c 0 4>;
> > +			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
> > +				 <&s4_clk>, <&s4_clk>;
> > +			#clock-cells = <1>;
> > +			renesas,clock-indices = <
> > +				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
> > +				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
> > +				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
> > +			>;
> > +			clock-output-names =
> > +				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
> > +				"mmc1", "mmc0";
> > +		};
> > +	};
> >  };
> 
> -- 
> Regards,
> 
> Laurent Pinchart
> 

Re: [PATCH v4 18/19] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

On Fri, Mar 14, 2014 at 01:21:39PM +0900, Magnus Damm wrote:
> Hi Simon,
> 
> I think you want to update the commit message to use r8a7779 instead of
> r8a7790.

Thanks, I will fix that.

> 
> Thanks,
> 
> / magnus
>  On Mar 13, 2014 6:00 PM, "Simon Horman" <horms+renesas@verge.net.au> wrote:
> 
> > Now that the DTS file r8a7790-marzen.dts can be used with
> > board-marzen.c and board-marzen-reference.c, proceed with removing
> > r8a7790-marzen-reference.dts.
> >
> > Based on work for the Koelsch board by Laurent Pinchart.
> >
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120
> > -------------------------
> >  1 file changed, 120 deletions(-)
> >  delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
> >
> > diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > deleted file mode 100644
> > index 76f5eef..0000000
> > --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > +++ /dev/null
> > @@ -1,120 +0,0 @@
> > -/*
> > - * Reference Device Tree Source for the Marzen board
> > - *
> > - * Copyright (C) 2013 Renesas Solutions Corp.
> > - * Copyright (C) 2013 Simon Horman
> > - *
> > - * This file is licensed under the terms of the GNU General Public License
> > - * version 2.  This program is licensed "as is" without any warranty of
> > any
> > - * kind, whether express or implied.
> > - */
> > -
> > -/dts-v1/;
> > -#include "r8a7779.dtsi"
> > -#include <dt-bindings/gpio/gpio.h>
> > -#include <dt-bindings/interrupt-controller/irq.h>
> > -
> > -/ {
> > -       model = "marzen";
> > -       compatible = "renesas,marzen-reference", "renesas,r8a7779";
> > -
> > -       chosen {
> > -               bootargs = "console=ttySC2,115200
> > earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
> > -       };
> > -
> > -       memory {
> > -               device_type = "memory";
> > -               reg = <0x60000000 0x40000000>;
> > -       };
> > -
> > -       fixedregulator3v3: fixedregulator@0 {
> > -               compatible = "regulator-fixed";
> > -               regulator-name = "fixed-3.3V";
> > -               regulator-min-microvolt = <3300000>;
> > -               regulator-max-microvolt = <3300000>;
> > -               regulator-boot-on;
> > -               regulator-always-on;
> > -       };
> > -
> > -       lan0@18000000 {
> > -               compatible = "smsc,lan9220", "smsc,lan9115";
> > -               reg = <0x18000000 0x100>;
> > -               pinctrl-0 = <&lan0_pins>;
> > -               pinctrl-names = "default";
> > -
> > -               phy-mode = "mii";
> > -               interrupt-parent = <&irqpin0>;
> > -               interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> > -               reg-io-width = <4>;
> > -               vddvario-supply = <&fixedregulator3v3>;
> > -               vdd33a-supply = <&fixedregulator3v3>;
> > -       };
> > -
> > -       leds {
> > -               compatible = "gpio-leds";
> > -               led2 {
> > -                       gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> > -               };
> > -               led3 {
> > -                       gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
> > -               };
> > -               led4 {
> > -                       gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
> > -               };
> > -       };
> > -};
> > -
> > -&irqpin0 {
> > -       status = "okay";
> > -};
> > -
> > -&pfc {
> > -       pinctrl-0 = <&scif2_pins &scif4_pins>;
> > -       pinctrl-names = "default";
> > -
> > -       lan0_pins: lan0 {
> > -               intc {
> > -                       renesas,groups = "intc_irq1_b";
> > -                       renesas,function = "intc";
> > -               };
> > -               lbsc {
> > -                       renesas,groups = "lbsc_ex_cs0";
> > -                       renesas,function = "lbsc";
> > -               };
> > -       };
> > -
> > -       scif2_pins: serial2 {
> > -               renesas,groups = "scif2_data_c";
> > -               renesas,function = "scif2";
> > -       };
> > -
> > -       scif4_pins: serial4 {
> > -               renesas,groups = "scif4_data";
> > -               renesas,function = "scif4";
> > -       };
> > -
> > -       sdhi0_pins: sd0 {
> > -               renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
> > -               renesas,function = "sdhi0";
> > -       };
> > -
> > -       hspi0_pins: hspi0 {
> > -               renesas,groups = "hspi0";
> > -               renesas,function = "hspi0";
> > -       };
> > -};
> > -
> > -&sdhi0 {
> > -       pinctrl-0 = <&sdhi0_pins>;
> > -       pinctrl-names = "default";
> > -
> > -       vmmc-supply = <&fixedregulator3v3>;
> > -       bus-width = <4>;
> > -       status = "okay";
> > -};
> > -
> > -&hspi0 {
> > -       pinctrl-0 = <&hspi0_pins>;
> > -       pinctrl-names = "default";
> > -       status = "okay";
> > -};
> > --
> > 1.8.5.2
> >
> >

[PATCH v4 18/19] ARM: shmobile: Remove Marzen reference DTS

[Simon Horman]

On Fri, Mar 14, 2014 at 01:21:39PM +0900, Magnus Damm wrote:
> Hi Simon,
> 
> I think you want to update the commit message to use r8a7779 instead of
> r8a7790.

Thanks, I will fix that.

> 
> Thanks,
> 
> / magnus
>  On Mar 13, 2014 6:00 PM, "Simon Horman" <horms+renesas@verge.net.au> wrote:
> 
> > Now that the DTS file r8a7790-marzen.dts can be used with
> > board-marzen.c and board-marzen-reference.c, proceed with removing
> > r8a7790-marzen-reference.dts.
> >
> > Based on work for the Koelsch board by Laurent Pinchart.
> >
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm/boot/dts/r8a7779-marzen-reference.dts | 120
> > -------------------------
> >  1 file changed, 120 deletions(-)
> >  delete mode 100644 arch/arm/boot/dts/r8a7779-marzen-reference.dts
> >
> > diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > deleted file mode 100644
> > index 76f5eef..0000000
> > --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
> > +++ /dev/null
> > @@ -1,120 +0,0 @@
> > -/*
> > - * Reference Device Tree Source for the Marzen board
> > - *
> > - * Copyright (C) 2013 Renesas Solutions Corp.
> > - * Copyright (C) 2013 Simon Horman
> > - *
> > - * This file is licensed under the terms of the GNU General Public License
> > - * version 2.  This program is licensed "as is" without any warranty of
> > any
> > - * kind, whether express or implied.
> > - */
> > -
> > -/dts-v1/;
> > -#include "r8a7779.dtsi"
> > -#include <dt-bindings/gpio/gpio.h>
> > -#include <dt-bindings/interrupt-controller/irq.h>
> > -
> > -/ {
> > -       model = "marzen";
> > -       compatible = "renesas,marzen-reference", "renesas,r8a7779";
> > -
> > -       chosen {
> > -               bootargs = "console=ttySC2,115200
> > earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
> > -       };
> > -
> > -       memory {
> > -               device_type = "memory";
> > -               reg = <0x60000000 0x40000000>;
> > -       };
> > -
> > -       fixedregulator3v3: fixedregulator at 0 {
> > -               compatible = "regulator-fixed";
> > -               regulator-name = "fixed-3.3V";
> > -               regulator-min-microvolt = <3300000>;
> > -               regulator-max-microvolt = <3300000>;
> > -               regulator-boot-on;
> > -               regulator-always-on;
> > -       };
> > -
> > -       lan0 at 18000000 {
> > -               compatible = "smsc,lan9220", "smsc,lan9115";
> > -               reg = <0x18000000 0x100>;
> > -               pinctrl-0 = <&lan0_pins>;
> > -               pinctrl-names = "default";
> > -
> > -               phy-mode = "mii";
> > -               interrupt-parent = <&irqpin0>;
> > -               interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> > -               reg-io-width = <4>;
> > -               vddvario-supply = <&fixedregulator3v3>;
> > -               vdd33a-supply = <&fixedregulator3v3>;
> > -       };
> > -
> > -       leds {
> > -               compatible = "gpio-leds";
> > -               led2 {
> > -                       gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> > -               };
> > -               led3 {
> > -                       gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
> > -               };
> > -               led4 {
> > -                       gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
> > -               };
> > -       };
> > -};
> > -
> > -&irqpin0 {
> > -       status = "okay";
> > -};
> > -
> > -&pfc {
> > -       pinctrl-0 = <&scif2_pins &scif4_pins>;
> > -       pinctrl-names = "default";
> > -
> > -       lan0_pins: lan0 {
> > -               intc {
> > -                       renesas,groups = "intc_irq1_b";
> > -                       renesas,function = "intc";
> > -               };
> > -               lbsc {
> > -                       renesas,groups = "lbsc_ex_cs0";
> > -                       renesas,function = "lbsc";
> > -               };
> > -       };
> > -
> > -       scif2_pins: serial2 {
> > -               renesas,groups = "scif2_data_c";
> > -               renesas,function = "scif2";
> > -       };
> > -
> > -       scif4_pins: serial4 {
> > -               renesas,groups = "scif4_data";
> > -               renesas,function = "scif4";
> > -       };
> > -
> > -       sdhi0_pins: sd0 {
> > -               renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
> > -               renesas,function = "sdhi0";
> > -       };
> > -
> > -       hspi0_pins: hspi0 {
> > -               renesas,groups = "hspi0";
> > -               renesas,function = "hspi0";
> > -       };
> > -};
> > -
> > -&sdhi0 {
> > -       pinctrl-0 = <&sdhi0_pins>;
> > -       pinctrl-names = "default";
> > -
> > -       vmmc-supply = <&fixedregulator3v3>;
> > -       bus-width = <4>;
> > -       status = "okay";
> > -};
> > -
> > -&hspi0 {
> > -       pinctrl-0 = <&hspi0_pins>;
> > -       pinctrl-names = "default";
> > -       status = "okay";
> > -};
> > --
> > 1.8.5.2
> >
> >