* [U-Boot] [PATCH] powerpc/85xx: Add additional p4080 platform related defines/structs
@ 2010-07-15 5:05 Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
2010-07-21 5:42 ` [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
0 siblings, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
* Added PCIE4 address, offset, DEVDISR & LAW target ID
* Added new p4080 DDR registers and defines to immap
* Add missing corenet platform DEVDISR related defines
* Updated ccsr_gur to include LIODN registers
* Add RCWSR defines
* Added Basic qman, pme, bman immap structs
* Added SATA related offsets & addresses
* Added Frame Manager 1/2 offsets & addresses
* Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
* Added various offsets and addresses that where missing
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/include/asm/immap_85xx.h | 172 +++++++++++++++++++++++++++++----
1 files changed, 154 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index e65d665..a5e56d8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1646,6 +1646,8 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR_DDR2 0x00080000
#define FSL_CORENET_DEVDISR_DBG 0x00010000
#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_SATA1 0x00004000
+#define FSL_CORENET_DEVDISR_SATA2 0x00002000
#define FSL_CORENET_DEVDISR_ELBC 0x00001000
#define FSL_CORENET_DEVDISR_USB1 0x00000800
#define FSL_CORENET_DEVDISR_USB2 0x00000400
@@ -1666,12 +1668,14 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
#define FSL_CORENET_DEVDISR2_FM2 0x00020000
#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
u8 res8[12];
@@ -1700,9 +1704,18 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
+#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
u8 res18[192];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res19[240];
@@ -1726,10 +1739,15 @@ typedef struct ccsr_gur {
u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
- u32 rmuliodnr; /* RIO Message Unit LIODN */
- u32 rduliodnr; /* RIO Doorbell Unit LIODN */
- u32 rpwuliodnr; /* RIO Port Write Unit LIODN */
- u8 res22[52];
+ u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
+ u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
+ u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
+ u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
+ u32 sata1liodnr; /* SATA 1 LIODN */
+ u32 sata2liodnr; /* SATA 2 LIODN */
+ u32 sata3liodnr; /* SATA 3 LIODN */
+ u32 sata4liodnr; /* SATA 4 LIODN */
+ u8 res22[32];
u32 dma1liodnr; /* DMA 1 LIODN */
u32 dma2liodnr; /* DMA 2 LIODN */
u32 dma3liodnr; /* DMA 3 LIODN */
@@ -1764,6 +1782,12 @@ typedef struct ccsr_gur {
u8 res37[380];
} ccsr_gur_t;
+/*
+ * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
+ * everything after has RMan thus msg unit LIODN is used for maintenance
+ */
+#define rmuliodnr rio1maintliodnr
+
typedef struct ccsr_clk {
u32 clkc0csr; /* Core 0 Clock control/status */
u8 res1[0x1c];
@@ -2032,38 +2056,125 @@ enum {
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec {
- u8 res1[0xfa0];
+ u32 res0;
+ u32 mcfgr; /* Master CFG Register */
+ u8 res1[0x8];
+ struct {
+ u32 ms; /* Job Ring LIODN Register, MS */
+ u32 ls; /* Job Ring LIODN Register, LS */
+ } jqliodnr[4];
+ u8 res2[0x30];
+ struct {
+ u32 ms; /* RTIC LIODN Register, MS */
+ u32 ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ u8 res3[0x1c];
+ u32 decorr; /* DECO Request Register */
+ struct {
+ u32 ms; /* DECO LIODN Register, MS */
+ u32 ls; /* DECO LIODN Register, LS */
+ } decoliodnr[5];
+ u8 res4[0x58];
+ u32 dar; /* DECO Avail Register */
+ u32 drr; /* DECO Reset Register */
+ u8 res5[0xe78];
u32 crnr_ms; /* CHA Revision Number Register, MS */
u32 crnr_ls; /* CHA Revision Number Register, LS */
u32 ctpr_ms; /* Compile Time Parameters Register, MS */
-#define SEC_CTPR_MS_AXI_LIODN 0x08000000
-#define SEC_CTPR_MS_QI 0x02000000
u32 ctpr_ls; /* Compile Time Parameters Register, LS */
- u8 res2[0x10];
+ u8 res6[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
- u8 res3[0x4];
+ u8 res7[0x4];
u32 csta; /* CAAM Status Register */
- u8 res4[0x8];
+ u8 res8[0x8];
u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
-#define SEC_RVID_MA 0x0f000000
u32 ccbvid; /* CHA Cluster Block Version ID Register */
u32 chavid_ms; /* CHA Version ID Register, MS */
u32 chavid_ls; /* CHA Version ID Register, LS */
u32 chanum_ms; /* CHA Number Register, MS */
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 secvid_ms; /* SEC Version ID Register, MS */
+ u32 secvid_ls; /* SEC Version ID Register, LS */
+ u8 res9[0x6020];
+ u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ u8 res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN 0x08000000
+#define SEC_CTPR_MS_QI 0x02000000
+#define SEC_RVID_MA 0x0f000000
#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JQNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
- u32 chanum_ls; /* CHA Number Register, LS */
- u32 caamvid_ms; /* CAAM Version ID Register, MS */
- u32 caamvid_ls; /* CAAM Version ID Register, LS */
- u8 res5[0xf000];
-} ccsr_sec_t;
#endif
+typedef struct ccsr_qman {
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
+ } qcsp[32];
+
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8 - 0x200];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fqd_bare; /* FQD Extended Base Addr Register */
+ u32 fqd_bar; /* FQD Base Addr Register */
+ u8 res1[0x8];
+ u32 fqd_ar; /* FQD Attributes Register */
+ u8 res2[0xc];
+ u32 pfdr_bare; /* PFDR Extended Base Addr Register */
+ u32 pfdr_bar; /* PFDR Base Addr Register */
+ u8 res3[0x8];
+ u32 pfdr_ar; /* PFDR Attributes Register */
+ u8 res4[0x4c];
+ u32 qcsp_bare; /* QCSP Extended Base Addr Register */
+ u32 qcsp_bar; /* QCSP Base Addr Register */
+ u8 res5[0x78];
+ u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res6[4];
+ u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
+ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
+ u8 res7[0x2e8];
+} ccsr_qman_t;
+
+typedef struct ccsr_bman {
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fbpr_bare; /* FBPR Extended Base Addr Register */
+ u32 fbpr_bar; /* FBPR Base Addr Register */
+ u8 res1[0x8];
+ u32 fbpr_ar; /* FBPR Attributes Register */
+ u8 res2[0xf0];
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res7[0x2f4];
+} ccsr_bman_t;
+
+typedef struct ccsr_pme {
+ u8 res0[0x804];
+ u32 liodnbr; /* LIODN Base Register */
+ u8 res1[0x1f8];
+ u32 srcidr; /* Source ID Register */
+ u8 res2[8];
+ u32 liodnr; /* LIODN Register */
+ u8 res3[0x1e8];
+ u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
+ u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
+ u8 res4[0x400];
+} ccsr_pme_t;
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@@ -2072,20 +2183,41 @@ typedef struct ccsr_sec {
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
+#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
+#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
+#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
@@ -2130,6 +2262,8 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
@@ -2195,6 +2329,8 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_PCIE3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+#define CONFIG_SYS_PCIE4_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures
2010-07-15 5:05 [U-Boot] [PATCH] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
2010-07-26 13:50 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
2010-07-21 5:42 ` [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
1 sibling, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
Add basic structures for Frame Manager on P4080/P3041/P5020 devices
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/include/asm/fsl_fman.h | 212 +++++++++++++++++++++++++++++++++
arch/powerpc/include/asm/immap_85xx.h | 1 +
2 files changed, 213 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_fman.h
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
new file mode 100644
index 0000000..6c01ffc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -0,0 +1,212 @@
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_FMAN_H__
+#define __FSL_FMAN_H__
+
+#include <asm/types.h>
+
+typedef struct fm_bmi_common {
+ u32 fmbm_init; /* BMI initialization */
+ u32 fmbm_cfg1; /* BMI configuration1 */
+ u32 fmbm_cfg2; /* BMI configuration2 */
+ u32 res0[0x5];
+ u32 fmbm_ievr; /* interrupt event register */
+ u32 fmbm_ier; /* interrupt enable register */
+ u32 fmbm_ifr; /* interrupt force register */
+ u32 res1[0x5];
+ u32 fmbm_arb[0x8]; /* BMI arbitration */
+ u32 res2[0x28];
+ u32 fmbm_gde; /* global debug enable */
+ u32 fmbm_pp[0x3f]; /* BMI port parameters */
+ u32 res3;
+ u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */
+ u32 res4;
+ u32 fmbm_ppid[0x3f];/* port partition ID */
+} fm_bmi_common_t;
+
+typedef struct fm_qmi_common {
+ u32 fmqm_gc; /* general configuration register */
+ u32 res0;
+ u32 fmqm_eie; /* error interrupt event register */
+ u32 fmqm_eien; /* error interrupt enable register */
+ u32 fmqm_eif; /* error interrupt force register */
+ u32 fmqm_ie; /* interrupt event register */
+ u32 fmqm_ien; /* interrupt enable register */
+ u32 fmqm_if; /* interrupt force register */
+ u32 fmqm_gs; /* global status register */
+ u32 fmqm_ts; /* task status register */
+ u32 fmqm_etfc; /* enqueue total frame counter */
+ u32 fmqm_dtfc; /* dequeue total frame counter */
+ u32 fmqm_dc0; /* dequeue counter 0 */
+ u32 fmqm_dc1; /* dequeue counter 1 */
+ u32 fmqm_dc2; /* dequeue counter 2 */
+ u32 fmqm_dc3; /* dequeue counter 3 */
+ u32 fmqm_dfnoc; /* dequeue FQID not override counter */
+ u32 fmqm_dfcc; /* dequeue FQID from context counter */
+ u32 fmqm_dffc; /* dequeue FQID from FD counter */
+ u32 fmqm_dcc; /* dequeue confirm counter */
+ u32 res1[0xc];
+ u32 fmqm_dtrc; /* debug trap configuration register */
+ u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */
+ u32 res3[0x2];
+ u32 res4[0xdc]; /* missing debug regs */
+} fm_qmi_common_t;
+
+typedef struct fm_bmi {
+ u8 res[1024];
+} fm_bmi_t;
+
+typedef struct fm_qmi {
+ u8 res[1024];
+} fm_qmi_t;
+
+typedef struct fm_parser {
+ u8 res[1024];
+} fm_parser_t;
+
+typedef struct fm_policer {
+ u8 res[4*1024];
+} fm_policer_t;
+
+typedef struct fm_keygen {
+ u8 res[4*1024];
+} fm_keygen_t;
+
+typedef struct fm_dma {
+ u32 fmdmsr; /* status register */
+ u32 fmdmmr; /* mode register */
+ u32 fmdmtr; /* bus threshold register */
+ u32 fmdmhy; /* bus hysteresis register */
+ u32 fmdmsetr; /* SOS emergency threshold register */
+ u32 fmdmtah; /* transfer bus address high register */
+ u32 fmdmtal; /* transfer bus address low register */
+ u32 fmdmtcid; /* transfer bus communication ID register */
+ u32 fmdmra; /* DMA bus internal ram address register */
+ u32 fmdmrd; /* DMA bus internal ram data register */
+ u32 res0[0xb];
+ u32 fmdmdcr; /* debug counter */
+ u32 fmdmemsr; /* emrgency smoother register */
+ u32 res1;
+ u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */
+ u32 res[0x3c8];
+} fm_dma_t;
+
+typedef struct fm_fpm {
+ u32 fpmtnc; /* TNUM control */
+ u32 fpmprc; /* Port_ID control */
+ u32 res0;
+ u32 fpmflc; /* flush control */
+ u32 fpmdis1; /* dispatch thresholds1 */
+ u32 fpmdis2; /* dispatch thresholds2 */
+ u32 fmepi; /* error pending interrupts */
+ u32 fmrie; /* rams interrupt enable */
+ u32 fpmfcevent[0x4];/* FMan controller event 0-3 */
+ u32 res1[0x4];
+ u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */
+ u32 res2[0x4];
+ u32 fpmtsc1; /* timestamp control1 */
+ u32 fpmtsc2; /* timestamp control2 */
+ u32 fpmtsp; /* time stamp */
+ u32 fpmtsf; /* time stamp fraction */
+ u32 fpmrcr; /* rams control and event */
+ u32 res3[0x3];
+ u32 fpmdrd[0x4]; /* data_ram data 0-3 */
+ u32 res4[0xc];
+ u32 fpmdra; /* data ram access */
+ u32 fm_ip_rev_1; /* IP block revision 1 */
+ u32 fm_ip_rev_2; /* IP block revision 2 */
+ u32 fmrstc; /* reset command */
+ u32 fmcld; /* classifier debug control */
+ u32 fmnpi; /* normal pending interrupts */
+ u32 res5;
+ u32 fmnee; /* event and enable */
+ u32 fpmcev[0x4]; /* CPU event 0-3 */
+ u32 res6[0x4];
+ u32 fmfp_ps[0x40]; /* port status */
+ u32 res7[0x260];
+ u32 fpmts[0x80]; /* task status */
+ u32 res8[0xa0];
+} fm_fpm_t;
+
+typedef struct fm_imem {
+ u8 res[4*1024];
+} fm_imem_t;
+
+typedef struct fm_soft_parser {
+ u8 res[4*1024];
+} fm_soft_parser_t;
+
+typedef struct fm_dtesc {
+ u8 res[4*1024];
+} fm_dtsec_t;
+
+typedef struct fm_mdio {
+ u8 res[4*1024];
+} fm_mdio_t;
+
+typedef struct fm_10gec {
+ u8 res[4*1024];
+} fm_10gec_t;
+
+typedef struct fm_10gec_mdio {
+ u8 res[4*1024];
+} fm_10gec_mdio_t;
+
+typedef struct fm_1588 {
+ u8 res[4*1024];
+} fm_1588_t;
+
+typedef struct ccsr_fman {
+ u8 muram[0x80000];
+ fm_bmi_common_t fm_bmi_common;
+ fm_qmi_common_t fm_qmi_common;
+ u8 res0[2048];
+ struct {
+ fm_bmi_t fm_bmi;
+ fm_qmi_t fm_qmi;
+ fm_parser_t fm_parser;
+ u8 res[1024];
+ } port[63];
+ fm_policer_t fm_policer;
+ fm_keygen_t fm_keygen;
+ fm_dma_t fm_dma;
+ fm_fpm_t fm_fpm;
+ fm_imem_t fm_imem;
+ u8 res1[8*1024];
+ fm_soft_parser_t fm_soft_parser;
+ u8 res2[96*1024];
+ struct {
+ fm_dtsec_t fm_dtesc;
+ fm_mdio_t fm_mdio;
+ } mac[4];
+ u8 res3[32*1024];
+ fm_10gec_t fm_10gec;
+ fm_10gec_mdio_t fm_10gec_mdio;
+ u8 res4[48*1024];
+ fm_1588_t fm_1588;
+ u8 res5[4*1024];
+} ccsr_fman_t;
+
+#endif /*__FSL_FMAN_H__*/
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index a5e56d8..f109e8c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -32,6 +32,7 @@
#include <asm/fsl_dma.h>
#include <asm/fsl_i2c.h>
#include <asm/fsl_lbc.h>
+#include <asm/fsl_fman.h>
typedef struct ccsr_local {
u32 ccsrbarh; /* CCSR Base Addr High */
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
2010-07-26 13:50 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
1 sibling, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/fdt.c | 19 +++++++++++--------
1 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 2628cc5..b4354f9 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -298,17 +298,17 @@ void fdt_add_enet_stashing(void *fdt)
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
-static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
+ unsigned long freq)
{
- const char *path = fdt_get_alias(blob, alias);
-
- int off = fdt_path_offset(blob, path);
+ phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
+ int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
if (off > 0)
printf("WARNING enable to set clock-frequency "
- "for %s: %s\n", alias, fdt_strerror(off));
+ "for %s: %s\n", compat, fdt_strerror(off));
}
}
@@ -317,14 +317,17 @@ static void ft_fixup_dpaa_clks(void *blob)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ sysinfo.freqFMan[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+ ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ sysinfo.freqFMan[1]);
#endif
#ifdef CONFIG_SYS_DPAA_PME
- ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+ do_fixup_by_compat_u32(blob, "fsl,pme",
+ "clock-frequency", sysinfo.freqPME, 1);
#endif
}
#else
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
1 sibling, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
On QorIQ CoreNet based devices we have a global clocking block. We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index b4354f9..932466e 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -403,6 +403,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", bd->bi_brgfreq, 1);
#endif
+#ifdef CONFIG_FSL_CORENET
+ do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+#endif
+
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#ifdef CONFIG_MP
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
1 sibling, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
From: Emil Medve <Emilian.Medve@freescale.com>
The user manual refers to FMAN1 and FMAN2 not 0 and 1.
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/cpu.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index fe2b52d..f15d43c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -179,7 +179,7 @@ int checkcpu (void)
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
- printf(" FMAN%d: %s MHz\n", i,
+ printf(" FMAN%d: %s MHz\n", i + 1,
strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010)
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
1 sibling, 2 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/cpu.c | 4 ++++
arch/powerpc/include/asm/config.h | 2 ++
arch/powerpc/include/asm/processor.h | 4 ++++
drivers/misc/fsl_law.c | 2 +-
5 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 4ee0e9a..2656dde 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -59,6 +59,7 @@ COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 22f3423..570ddb6 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -84,6 +84,10 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P4080, P4080_E, 8),
+ CPU_TYPE_ENTRY(P5010, P5010, 1),
+ CPU_TYPE_ENTRY(P5010, P5010_E, 1),
+ CPU_TYPE_ENTRY(P5020, P5020, 2),
+ CPU_TYPE_ENTRY(P5020, P5020_E, 2),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index d88c282..f2f4188 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -46,6 +46,8 @@
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
+#elif defined(CONFIG_PPC_P5020)
+#define CONFIG_MAX_CPUS 2
#else
#define CONFIG_MAX_CPUS 1
#endif
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 844552c..5e6364a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1056,6 +1056,10 @@
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
#define SVR_P4080_E 0x820800
+#define SVR_P5010 0x822100
+#define SVR_P5010_E 0x822900
+#define SVR_P5020 0x822000
+#define SVR_P5020_E 0x822800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 628bd59..22270f1 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
-#elif defined(CONFIG_PPC_P4080)
+#elif defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020)
#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
@ 2010-07-15 5:05 ` Kumar Gala
2010-07-21 5:37 ` Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
1 sibling, 1 reply; 15+ messages in thread
From: Kumar Gala @ 2010-07-15 5:05 UTC (permalink / raw)
To: u-boot
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
arch/powerpc/include/asm/config.h | 2 ++
arch/powerpc/include/asm/processor.h | 2 ++
drivers/misc/fsl_law.c | 3 ++-
5 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 2656dde..fe851f1 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -58,6 +58,7 @@ COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 570ddb6..dc3da16 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -80,6 +80,8 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+ CPU_TYPE_ENTRY(P3041, P3041, 4),
+ CPU_TYPE_ENTRY(P3041, P3041_E, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index f2f4188..f70699d 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -44,6 +44,8 @@
defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
#elif defined(CONFIG_PPC_P5020)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 5e6364a..89f283a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1052,6 +1052,8 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
+#define SVR_P3041 0x821103
+#define SVR_P3041_E 0x821903
#define SVR_P4040 0x820100
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 22270f1..6589076 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -43,7 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
-#elif defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020)
+#elif defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P4080) || \
+ defined(CONFIG_PPC_P5020)
#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
@ 2010-07-21 5:36 ` Kumar Gala
1 sibling, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:36 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> Move to using fdt_node_offset_by_compat_reg to find the node offsets we
> want to update instead of using aliases.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/fdt.c | 19 +++++++++++--------
> 1 files changed, 11 insertions(+), 8 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
@ 2010-07-21 5:36 ` Kumar Gala
1 sibling, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:36 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> On QorIQ CoreNet based devices we have a global clocking block. We want
> to keep track of SYSCLK frequency as it is what is used to derive all
> other frequencies in the SoC
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010)
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines Kumar Gala
@ 2010-07-21 5:37 ` Kumar Gala
1 sibling, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:37 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> There are various locations that we have chip specific info:
>
> * Makefile for which ddr code to build
> * Added p5020 & p5010 to cpu_type_list and SVR list
> * Added number of LAWs for p5020
> * Set CONFIG_MAX_CPUS to 2 for p5020
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/Makefile | 1 +
> arch/powerpc/cpu/mpc8xxx/cpu.c | 4 ++++
> arch/powerpc/include/asm/config.h | 2 ++
> arch/powerpc/include/asm/processor.h | 4 ++++
> drivers/misc/fsl_law.c | 2 +-
> 5 files changed, 12 insertions(+), 1 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines Kumar Gala
@ 2010-07-21 5:37 ` Kumar Gala
0 siblings, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:37 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> There are various locations that we have chip specific info:
>
> * Makefile for which ddr code to build
> * Added p3041 to cpu_type_list and SVR list
> * Added number of LAWs for p3041
> * Set CONFIG_MAX_CPUS to 4 for p3041
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/Makefile | 1 +
> arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
> arch/powerpc/include/asm/config.h | 2 ++
> arch/powerpc/include/asm/processor.h | 2 ++
> drivers/misc/fsl_law.c | 3 ++-
> 5 files changed, 9 insertions(+), 1 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
@ 2010-07-21 5:37 ` Kumar Gala
1 sibling, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:37 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> From: Emil Medve <Emilian.Medve@freescale.com>
>
> The user manual refers to FMAN1 and FMAN2 not 0 and 1.
>
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/cpu.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs
2010-07-15 5:05 [U-Boot] [PATCH] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
@ 2010-07-21 5:42 ` Kumar Gala
2010-07-26 13:50 ` Kumar Gala
1 sibling, 1 reply; 15+ messages in thread
From: Kumar Gala @ 2010-07-21 5:42 UTC (permalink / raw)
To: u-boot
* Added PCIE4 address, offset, DEVDISR & LAW target ID
* Added new p4080 DDR registers and defines to immap
* Add missing corenet platform DEVDISR related defines
* Updated ccsr_gur to include LIODN registers
* Add RCWSR defines
* Added Basic qman, pme, bman immap structs
* Added SATA related offsets & addresses
* Added Frame Manager 1/2 offsets & addresses
* Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
* Added various offsets and addresses that where missing
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Previous version wasn't complete
arch/powerpc/include/asm/fsl_law.h | 3 +-
arch/powerpc/include/asm/immap_85xx.h | 216 +++++++++++++++++++++++++++++---
2 files changed, 197 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 12ba1a6..0e255ff 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -54,6 +54,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PCIE_1 = 0x00,
LAW_TRGT_IF_PCIE_2 = 0x01,
LAW_TRGT_IF_PCIE_3 = 0x02,
+ LAW_TRGT_IF_PCIE_4 = 0x03,
LAW_TRGT_IF_RIO_1 = 0x08,
LAW_TRGT_IF_RIO_2 = 0x09,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b1d219b..a5e56d8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -172,7 +172,17 @@ typedef struct ccsr_ddr {
u32 ddr_sr_cntr; /* self refresh counter */
u32 ddr_sdram_rcw_1; /* Control Words 1 */
u32 ddr_sdram_rcw_2; /* Control Words 2 */
- u8 res8_1b[2456];
+ u8 reg_1ab[8];
+ u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ u8 res8_1b[104];
+ u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ u8 res8_1ba[0x908];
u32 ddr_dsr1; /* Debug Status 1 */
u32 ddr_dsr2; /* Debug Status 2 */
u32 ddr_cdr1; /* Control Driver 1 */
@@ -180,7 +190,21 @@ typedef struct ccsr_ddr {
u8 res8_1c[200];
u32 ip_rev1; /* IP Block Revision 1 */
u32 ip_rev2; /* IP Block Revision 2 */
- u8 res8_2[512];
+ u32 eor; /* Enhanced Optimization Register */
+ u8 res8_2[252];
+ u32 mtcr; /* Memory Test Control Register */
+ u8 res8_3[28];
+ u32 mtp1; /* Memory Test Pattern 1 */
+ u32 mtp2; /* Memory Test Pattern 2 */
+ u32 mtp3; /* Memory Test Pattern 3 */
+ u32 mtp4; /* Memory Test Pattern 4 */
+ u32 mtp5; /* Memory Test Pattern 5 */
+ u32 mtp6; /* Memory Test Pattern 6 */
+ u32 mtp7; /* Memory Test Pattern 7 */
+ u32 mtp8; /* Memory Test Pattern 8 */
+ u32 mtp9; /* Memory Test Pattern 9 */
+ u32 mtp10; /* Memory Test Pattern 10 */
+ u8 res8_4[184];
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
@@ -218,6 +242,9 @@ typedef struct ccsr_ddr {
u8 res12[184];
} ccsr_ddr_t;
+#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
+#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
+
/* I2C Registers */
typedef struct ccsr_i2c {
struct fsl_i2c i2c[1];
@@ -1609,6 +1636,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
#define FSL_CORENET_DEVDISR_RMU 0x08000000
#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
@@ -1618,6 +1646,8 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR_DDR2 0x00080000
#define FSL_CORENET_DEVDISR_DBG 0x00010000
#define FSL_CORENET_DEVDISR_NAL 0x00008000
+#define FSL_CORENET_DEVDISR_SATA1 0x00004000
+#define FSL_CORENET_DEVDISR_SATA2 0x00002000
#define FSL_CORENET_DEVDISR_ELBC 0x00001000
#define FSL_CORENET_DEVDISR_USB1 0x00000800
#define FSL_CORENET_DEVDISR_USB2 0x00000400
@@ -1638,12 +1668,14 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
#define FSL_CORENET_DEVDISR2_FM2 0x00020000
#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
u8 res8[12];
@@ -1672,9 +1704,18 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
+#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
+#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
u8 res18[192];
u32 scratchrw[4]; /* Scratch Read/Write */
u8 res19[240];
@@ -1698,10 +1739,15 @@ typedef struct ccsr_gur {
u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
- u32 rmuliodnr; /* RIO Message Unit LIODN */
- u32 rduliodnr; /* RIO Doorbell Unit LIODN */
- u32 rpwuliodnr; /* RIO Port Write Unit LIODN */
- u8 res22[52];
+ u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
+ u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
+ u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
+ u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
+ u32 sata1liodnr; /* SATA 1 LIODN */
+ u32 sata2liodnr; /* SATA 2 LIODN */
+ u32 sata3liodnr; /* SATA 3 LIODN */
+ u32 sata4liodnr; /* SATA 4 LIODN */
+ u8 res22[32];
u32 dma1liodnr; /* DMA 1 LIODN */
u32 dma2liodnr; /* DMA 2 LIODN */
u32 dma3liodnr; /* DMA 3 LIODN */
@@ -1736,6 +1782,12 @@ typedef struct ccsr_gur {
u8 res37[380];
} ccsr_gur_t;
+/*
+ * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
+ * everything after has RMan thus msg unit LIODN is used for maintenance
+ */
+#define rmuliodnr rio1maintliodnr
+
typedef struct ccsr_clk {
u32 clkc0csr; /* Core 0 Clock control/status */
u8 res1[0x1c];
@@ -2004,38 +2056,125 @@ enum {
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec {
- u8 res1[0xfa0];
+ u32 res0;
+ u32 mcfgr; /* Master CFG Register */
+ u8 res1[0x8];
+ struct {
+ u32 ms; /* Job Ring LIODN Register, MS */
+ u32 ls; /* Job Ring LIODN Register, LS */
+ } jqliodnr[4];
+ u8 res2[0x30];
+ struct {
+ u32 ms; /* RTIC LIODN Register, MS */
+ u32 ls; /* RTIC LIODN Register, LS */
+ } rticliodnr[4];
+ u8 res3[0x1c];
+ u32 decorr; /* DECO Request Register */
+ struct {
+ u32 ms; /* DECO LIODN Register, MS */
+ u32 ls; /* DECO LIODN Register, LS */
+ } decoliodnr[5];
+ u8 res4[0x58];
+ u32 dar; /* DECO Avail Register */
+ u32 drr; /* DECO Reset Register */
+ u8 res5[0xe78];
u32 crnr_ms; /* CHA Revision Number Register, MS */
u32 crnr_ls; /* CHA Revision Number Register, LS */
u32 ctpr_ms; /* Compile Time Parameters Register, MS */
-#define SEC_CTPR_MS_AXI_LIODN 0x08000000
-#define SEC_CTPR_MS_QI 0x02000000
u32 ctpr_ls; /* Compile Time Parameters Register, LS */
- u8 res2[0x10];
+ u8 res6[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
- u8 res3[0x4];
+ u8 res7[0x4];
u32 csta; /* CAAM Status Register */
- u8 res4[0x8];
+ u8 res8[0x8];
u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
-#define SEC_RVID_MA 0x0f000000
u32 ccbvid; /* CHA Cluster Block Version ID Register */
u32 chavid_ms; /* CHA Version ID Register, MS */
u32 chavid_ls; /* CHA Version ID Register, LS */
u32 chanum_ms; /* CHA Number Register, MS */
+ u32 chanum_ls; /* CHA Number Register, LS */
+ u32 secvid_ms; /* SEC Version ID Register, MS */
+ u32 secvid_ls; /* SEC Version ID Register, LS */
+ u8 res9[0x6020];
+ u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
+ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
+ u8 res10[0x8fd8];
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN 0x08000000
+#define SEC_CTPR_MS_QI 0x02000000
+#define SEC_RVID_MA 0x0f000000
#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JQNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
- u32 chanum_ls; /* CHA Number Register, LS */
- u32 caamvid_ms; /* CAAM Version ID Register, MS */
- u32 caamvid_ls; /* CAAM Version ID Register, LS */
- u8 res5[0xf000];
-} ccsr_sec_t;
#endif
+typedef struct ccsr_qman {
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
+ } qcsp[32];
+
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8 - 0x200];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fqd_bare; /* FQD Extended Base Addr Register */
+ u32 fqd_bar; /* FQD Base Addr Register */
+ u8 res1[0x8];
+ u32 fqd_ar; /* FQD Attributes Register */
+ u8 res2[0xc];
+ u32 pfdr_bare; /* PFDR Extended Base Addr Register */
+ u32 pfdr_bar; /* PFDR Base Addr Register */
+ u8 res3[0x8];
+ u32 pfdr_ar; /* PFDR Attributes Register */
+ u8 res4[0x4c];
+ u32 qcsp_bare; /* QCSP Extended Base Addr Register */
+ u32 qcsp_bar; /* QCSP Base Addr Register */
+ u8 res5[0x78];
+ u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res6[4];
+ u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
+ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
+ u8 res7[0x2e8];
+} ccsr_qman_t;
+
+typedef struct ccsr_bman {
+ /* Not actually reserved, but irrelevant to u-boot */
+ u8 res[0xbf8];
+ u32 ip_rev_1;
+ u32 ip_rev_2;
+ u32 fbpr_bare; /* FBPR Extended Base Addr Register */
+ u32 fbpr_bar; /* FBPR Base Addr Register */
+ u8 res1[0x8];
+ u32 fbpr_ar; /* FBPR Attributes Register */
+ u8 res2[0xf0];
+ u32 srcidr; /* Source ID Register */
+ u32 liodnr; /* LIODN Register */
+ u8 res7[0x2f4];
+} ccsr_bman_t;
+
+typedef struct ccsr_pme {
+ u8 res0[0x804];
+ u32 liodnbr; /* LIODN Base Register */
+ u8 res1[0x1f8];
+ u32 srcidr; /* Source ID Register */
+ u8 res2[8];
+ u32 liodnr; /* LIODN Register */
+ u8 res3[0x1e8];
+ u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
+ u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
+ u8 res4[0x400];
+} ccsr_pme_t;
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@@ -2044,16 +2183,41 @@ typedef struct ccsr_sec {
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
+#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
-#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
+#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
+#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
-#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1 at DTSEC0 */
+#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
+#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
+#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
@@ -2098,6 +2262,8 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
@@ -2146,6 +2312,12 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_FM2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
@@ -2157,6 +2329,8 @@ typedef struct ccsr_sec {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_PCIE3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+#define CONFIG_SYS_PCIE4_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
--
1.6.0.6
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs
2010-07-21 5:42 ` [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
@ 2010-07-26 13:50 ` Kumar Gala
0 siblings, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-26 13:50 UTC (permalink / raw)
To: u-boot
On Jul 21, 2010, at 12:42 AM, Kumar Gala wrote:
> * Added PCIE4 address, offset, DEVDISR & LAW target ID
> * Added new p4080 DDR registers and defines to immap
> * Add missing corenet platform DEVDISR related defines
> * Updated ccsr_gur to include LIODN registers
> * Add RCWSR defines
> * Added Basic qman, pme, bman immap structs
> * Added SATA related offsets & addresses
> * Added Frame Manager 1/2 offsets & addresses
> * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
> * Added various offsets and addresses that where missing
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * Previous version wasn't complete
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
@ 2010-07-26 13:50 ` Kumar Gala
1 sibling, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2010-07-26 13:50 UTC (permalink / raw)
To: u-boot
On Jul 15, 2010, at 12:05 AM, Kumar Gala wrote:
> Add basic structures for Frame Manager on P4080/P3041/P5020 devices
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/include/asm/fsl_fman.h | 212 +++++++++++++++++++++++++++++++++
> arch/powerpc/include/asm/immap_85xx.h | 1 +
> 2 files changed, 213 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/include/asm/fsl_fman.h
applied to 85xx
- k
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2010-07-26 13:50 UTC | newest]
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2010-07-15 5:05 [U-Boot] [PATCH] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
2010-07-15 5:05 ` [U-Boot] [PATCH] powerpc/p3041: Add various p3041 related defines Kumar Gala
2010-07-21 5:37 ` Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/p5020: Add various p5020 related defines (and p5010) Kumar Gala
2010-07-21 5:37 ` [U-Boot] [PATCH] powerpc/mpc85xx: Report FMAN # to match user manual Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/p4080: Add setting of clock-frequency for clockgen node Kumar Gala
2010-07-21 5:36 ` [U-Boot] [PATCH] powerpc/85xx: Use fdt_node_offset_by_compat_reg for clock-frequency updates Kumar Gala
2010-07-26 13:50 ` [U-Boot] [PATCH] powerpc/fsl_fman: Add initial fman immap structures Kumar Gala
2010-07-21 5:42 ` [U-Boot] [PATCH v2] powerpc/85xx: Add additional p4080 platform related defines/structs Kumar Gala
2010-07-26 13:50 ` Kumar Gala
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