[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
is its DMA driver, which is completely platform-specific and provides
private API (s3c-dma), not even saying that its design is completely
against multiplatform-awareness.

The DMA controller present on this SoC series is a custom variant
of ARM PrimeCell PL080 modified by Samsung to add some extra features.
It is mostly compatible with original PL080, except:
 - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
 - offset of CH_CONFIG register is different,
 - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
 - transfer size field is extended to 24 bits, allowing much bigger
     single transfer,
 - LLI consists of one more word, to account for CH_CONTROL2 register.

Since all the rest is fully compatible with standard PL080 there is no
point in having separate driver just for this single variant, so I decided
to look into adding support for it to the amba-pl08x driver.

There was already some attempt to achieve this before, but this was before
Russel's big rework of the driver to use virtual channels, making the old
patches being not much of use.

This RFC series is a proof of concept that I managed to make during last
days of hacking. Except one patch adding clkdev lookup to clock driver
(which is being replaced with a CCF-compliant driver ATM), this is enough
to get memcpy and slave transfers to work on S3C64xx.

I have tested this on Mini6410 and SMDK6410 boards using dmatest for
memcpy and Samsung I2S with madplay/aplay for slave transfers.
Unfortunately I do not have access to other platforms with PL08x so
I could not test for any regressions introduced on them.

Credits for two patches go to Alban Bedel, who made a series fixing this
driver to make it usable with audio drivers. I rebased his patches on top
of mine and corrected coding style a bit.

OK, that's all. Any comments are welcome. Feel free to start throwing eggs
and tomatoes if you find this awful, but I won't be upset if I get some
Tested-by or Acked-by as well. ;)

Alban Bedel (2):
  dmaengine: PL08x: Fix reading the byte count in cctl
  dmaengine: PL08x: Add cyclic transfer support

Tomasz Figa (9):
  dma: amba-pl08x: Use bitmap to pass variant specific quirks
  dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation
  dma: amba-pl08x: Add support for different offset of CONFIG register
  dma: amba-pl08x: Add support for PL080S variant
  dma: amba-pl08x: Add support for different maximum transfer size
  dma: amba-pl08x: Keep LLIs aligned to 4-word boundary
  spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX
  ASoC: samsung: Do not require legacy DMA API in case of S3C64XX
  ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 +++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++
 drivers/dma/amba-pl08x.c                 | 399 ++++++++++++++++++++++---------
 drivers/spi/Kconfig                      |   2 +-
 include/linux/amba/pl080.h               |   1 +
 sound/soc/samsung/Kconfig                |   2 +-
 10 files changed, 613 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

-- 
1.8.2.1

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
is its DMA driver, which is completely platform-specific and provides
private API (s3c-dma), not even saying that its design is completely
against multiplatform-awareness.

The DMA controller present on this SoC series is a custom variant
of ARM PrimeCell PL080 modified by Samsung to add some extra features.
It is mostly compatible with original PL080, except:
 - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
 - offset of CH_CONFIG register is different,
 - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
 - transfer size field is extended to 24 bits, allowing much bigger
     single transfer,
 - LLI consists of one more word, to account for CH_CONTROL2 register.

Since all the rest is fully compatible with standard PL080 there is no
point in having separate driver just for this single variant, so I decided
to look into adding support for it to the amba-pl08x driver.

There was already some attempt to achieve this before, but this was before
Russel's big rework of the driver to use virtual channels, making the old
patches being not much of use.

This RFC series is a proof of concept that I managed to make during last
days of hacking. Except one patch adding clkdev lookup to clock driver
(which is being replaced with a CCF-compliant driver ATM), this is enough
to get memcpy and slave transfers to work on S3C64xx.

I have tested this on Mini6410 and SMDK6410 boards using dmatest for
memcpy and Samsung I2S with madplay/aplay for slave transfers.
Unfortunately I do not have access to other platforms with PL08x so
I could not test for any regressions introduced on them.

Credits for two patches go to Alban Bedel, who made a series fixing this
driver to make it usable with audio drivers. I rebased his patches on top
of mine and corrected coding style a bit.

OK, that's all. Any comments are welcome. Feel free to start throwing eggs
and tomatoes if you find this awful, but I won't be upset if I get some
Tested-by or Acked-by as well. ;)

Alban Bedel (2):
  dmaengine: PL08x: Fix reading the byte count in cctl
  dmaengine: PL08x: Add cyclic transfer support

Tomasz Figa (9):
  dma: amba-pl08x: Use bitmap to pass variant specific quirks
  dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation
  dma: amba-pl08x: Add support for different offset of CONFIG register
  dma: amba-pl08x: Add support for PL080S variant
  dma: amba-pl08x: Add support for different maximum transfer size
  dma: amba-pl08x: Keep LLIs aligned to 4-word boundary
  spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX
  ASoC: samsung: Do not require legacy DMA API in case of S3C64XX
  ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 +++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++
 drivers/dma/amba-pl08x.c                 | 399 ++++++++++++++++++++++---------
 drivers/spi/Kconfig                      |   2 +-
 include/linux/amba/pl080.h               |   1 +
 sound/soc/samsung/Kconfig                |   2 +-
 10 files changed, 613 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

-- 
1.8.2.1

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
is its DMA driver, which is completely platform-specific and provides
private API (s3c-dma), not even saying that its design is completely
against multiplatform-awareness.

The DMA controller present on this SoC series is a custom variant
of ARM PrimeCell PL080 modified by Samsung to add some extra features.
It is mostly compatible with original PL080, except:
 - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
 - offset of CH_CONFIG register is different,
 - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
 - transfer size field is extended to 24 bits, allowing much bigger
     single transfer,
 - LLI consists of one more word, to account for CH_CONTROL2 register.

Since all the rest is fully compatible with standard PL080 there is no
point in having separate driver just for this single variant, so I decided
to look into adding support for it to the amba-pl08x driver.

There was already some attempt to achieve this before, but this was before
Russel's big rework of the driver to use virtual channels, making the old
patches being not much of use.

This RFC series is a proof of concept that I managed to make during last
days of hacking. Except one patch adding clkdev lookup to clock driver
(which is being replaced with a CCF-compliant driver ATM), this is enough
to get memcpy and slave transfers to work on S3C64xx.

I have tested this on Mini6410 and SMDK6410 boards using dmatest for
memcpy and Samsung I2S with madplay/aplay for slave transfers.
Unfortunately I do not have access to other platforms with PL08x so
I could not test for any regressions introduced on them.

Credits for two patches go to Alban Bedel, who made a series fixing this
driver to make it usable with audio drivers. I rebased his patches on top
of mine and corrected coding style a bit.

OK, that's all. Any comments are welcome. Feel free to start throwing eggs
and tomatoes if you find this awful, but I won't be upset if I get some
Tested-by or Acked-by as well. ;)

Alban Bedel (2):
  dmaengine: PL08x: Fix reading the byte count in cctl
  dmaengine: PL08x: Add cyclic transfer support

Tomasz Figa (9):
  dma: amba-pl08x: Use bitmap to pass variant specific quirks
  dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation
  dma: amba-pl08x: Add support for different offset of CONFIG register
  dma: amba-pl08x: Add support for PL080S variant
  dma: amba-pl08x: Add support for different maximum transfer size
  dma: amba-pl08x: Keep LLIs aligned to 4-word boundary
  spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX
  ASoC: samsung: Do not require legacy DMA API in case of S3C64XX
  ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 +++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++
 drivers/dma/amba-pl08x.c                 | 399 ++++++++++++++++++++++---------
 drivers/spi/Kconfig                      |   2 +-
 include/linux/amba/pl080.h               |   1 +
 sound/soc/samsung/Kconfig                |   2 +-
 10 files changed, 613 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

-- 
1.8.2.1

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

Instead of defining new bool field in vendor_data struct for each quirk,
it is more reasonable to use a single flags field and make each quirk
use single bits.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 8bad254..d443a68 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -93,18 +93,22 @@
 static struct amba_driver pl08x_amba_driver;
 struct pl08x_driver_data;
 
+/** Controller supports dual AHB masters. */
+#define PL08X_IS_DUALMASTER	(1 << 0)
+/**
+ * Controller has Nomadik security extension bits that need to be checked
+ * for permission before use and some registers are missing.
+ */
+#define PL08X_IS_NOMADIK	(1 << 1)
+
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
  * @channels: the number of channels available in this variant
- * @dualmaster: whether this version supports dual AHB masters or not.
- * @nomadik: whether the channels have Nomadik security extension bits
- *	that need to be checked for permission before use and some registers are
- *	missing
+ * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
 	u8 channels;
-	bool dualmaster;
-	bool nomadik;
+	u32 flags;
 };
 
 /*
@@ -1391,7 +1395,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	/* Both to be incremented or the code will break */
 	txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
 
-	if (pl08x->vd->dualmaster)
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER)
 		txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
 					      pl08x->mem_buses);
 
@@ -1612,7 +1616,7 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
 {
 	/* The Nomadik variant does not have the config register */
-	if (pl08x->vd->nomadik)
+	if (pl08x->vd->flags & PL08X_IS_NOMADIK)
 		return;
 	writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
 }
@@ -1897,7 +1901,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	/* By default, AHB1 only.  If dualmaster, from platform */
 	pl08x->lli_buses = PL08X_AHB1;
 	pl08x->mem_buses = PL08X_AHB1;
-	if (pl08x->vd->dualmaster) {
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER) {
 		pl08x->lli_buses = pl08x->pd->lli_buses;
 		pl08x->mem_buses = pl08x->pd->mem_buses;
 	}
@@ -1954,7 +1958,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		 * down for the secure world only. Lock up these channels
 		 * by perpetually serving a dummy virtual channel.
 		 */
-		if (vd->nomadik) {
+		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
 			val = readl(ch->base + PL080_CH_CONFIG);
@@ -2039,18 +2043,17 @@ out_no_pl08x:
 /* PL080 has 8 channels and the PL080 have just 2 */
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
-	.dualmaster = true,
+	.flags = PL08X_IS_DUALMASTER,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
-	.dualmaster = true,
-	.nomadik = true,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
-	.dualmaster = false,
+	.flags = 0,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

Instead of defining new bool field in vendor_data struct for each quirk,
it is more reasonable to use a single flags field and make each quirk
use single bits.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 8bad254..d443a68 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -93,18 +93,22 @@
 static struct amba_driver pl08x_amba_driver;
 struct pl08x_driver_data;
 
+/** Controller supports dual AHB masters. */
+#define PL08X_IS_DUALMASTER	(1 << 0)
+/**
+ * Controller has Nomadik security extension bits that need to be checked
+ * for permission before use and some registers are missing.
+ */
+#define PL08X_IS_NOMADIK	(1 << 1)
+
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
  * @channels: the number of channels available in this variant
- * @dualmaster: whether this version supports dual AHB masters or not.
- * @nomadik: whether the channels have Nomadik security extension bits
- *	that need to be checked for permission before use and some registers are
- *	missing
+ * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
 	u8 channels;
-	bool dualmaster;
-	bool nomadik;
+	u32 flags;
 };
 
 /*
@@ -1391,7 +1395,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	/* Both to be incremented or the code will break */
 	txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
 
-	if (pl08x->vd->dualmaster)
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER)
 		txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
 					      pl08x->mem_buses);
 
@@ -1612,7 +1616,7 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
 {
 	/* The Nomadik variant does not have the config register */
-	if (pl08x->vd->nomadik)
+	if (pl08x->vd->flags & PL08X_IS_NOMADIK)
 		return;
 	writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
 }
@@ -1897,7 +1901,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	/* By default, AHB1 only.  If dualmaster, from platform */
 	pl08x->lli_buses = PL08X_AHB1;
 	pl08x->mem_buses = PL08X_AHB1;
-	if (pl08x->vd->dualmaster) {
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER) {
 		pl08x->lli_buses = pl08x->pd->lli_buses;
 		pl08x->mem_buses = pl08x->pd->mem_buses;
 	}
@@ -1954,7 +1958,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		 * down for the secure world only. Lock up these channels
 		 * by perpetually serving a dummy virtual channel.
 		 */
-		if (vd->nomadik) {
+		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
 			val = readl(ch->base + PL080_CH_CONFIG);
@@ -2039,18 +2043,17 @@ out_no_pl08x:
 /* PL080 has 8 channels and the PL080 have just 2 */
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
-	.dualmaster = true,
+	.flags = PL08X_IS_DUALMASTER,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
-	.dualmaster = true,
-	.nomadik = true,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
-	.dualmaster = false,
+	.flags = 0,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

Instead of defining new bool field in vendor_data struct for each quirk,
it is more reasonable to use a single flags field and make each quirk
use single bits.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 8bad254..d443a68 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -93,18 +93,22 @@
 static struct amba_driver pl08x_amba_driver;
 struct pl08x_driver_data;
 
+/** Controller supports dual AHB masters. */
+#define PL08X_IS_DUALMASTER	(1 << 0)
+/**
+ * Controller has Nomadik security extension bits that need to be checked
+ * for permission before use and some registers are missing.
+ */
+#define PL08X_IS_NOMADIK	(1 << 1)
+
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
  * @channels: the number of channels available in this variant
- * @dualmaster: whether this version supports dual AHB masters or not.
- * @nomadik: whether the channels have Nomadik security extension bits
- *	that need to be checked for permission before use and some registers are
- *	missing
+ * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
 	u8 channels;
-	bool dualmaster;
-	bool nomadik;
+	u32 flags;
 };
 
 /*
@@ -1391,7 +1395,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	/* Both to be incremented or the code will break */
 	txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
 
-	if (pl08x->vd->dualmaster)
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER)
 		txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
 					      pl08x->mem_buses);
 
@@ -1612,7 +1616,7 @@ bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
 {
 	/* The Nomadik variant does not have the config register */
-	if (pl08x->vd->nomadik)
+	if (pl08x->vd->flags & PL08X_IS_NOMADIK)
 		return;
 	writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
 }
@@ -1897,7 +1901,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	/* By default, AHB1 only.  If dualmaster, from platform */
 	pl08x->lli_buses = PL08X_AHB1;
 	pl08x->mem_buses = PL08X_AHB1;
-	if (pl08x->vd->dualmaster) {
+	if (pl08x->vd->flags & PL08X_IS_DUALMASTER) {
 		pl08x->lli_buses = pl08x->pd->lli_buses;
 		pl08x->mem_buses = pl08x->pd->mem_buses;
 	}
@@ -1954,7 +1958,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		 * down for the secure world only. Lock up these channels
 		 * by perpetually serving a dummy virtual channel.
 		 */
-		if (vd->nomadik) {
+		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
 			val = readl(ch->base + PL080_CH_CONFIG);
@@ -2039,18 +2043,17 @@ out_no_pl08x:
 /* PL080 has 8 channels and the PL080 have just 2 */
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
-	.dualmaster = true,
+	.flags = PL08X_IS_DUALMASTER,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
-	.dualmaster = true,
-	.nomadik = true,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
-	.dualmaster = false,
+	.flags = 0,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 02/11] dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation

[Tomasz Figa]

Further patch will introduce support for PL080S, which requires some
things to be done conditionally, thus increasing indentation level of
some functions even more.

This patch reduces indentation level of pl08x_getbytes_chan() function
by inverting several conditions and returning from function wherever
possible.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d443a68..1e57ded 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -473,47 +473,52 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
+	dma_addr_t llis_bus;
 	struct pl08x_txd *txd;
 	size_t bytes = 0;
+	int index;
+	u32 clli;
 
 	ch = plchan->phychan;
 	txd = plchan->at;
 
+	if (!ch || !txd)
+		return bytes;
+
 	/*
 	 * Follow the LLIs to get the number of remaining
 	 * bytes in the currently active transaction.
 	 */
-	if (ch && txd) {
-		u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+
+	/* First get the remaining bytes in the active transfer */
+	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
-		/* First get the remaining bytes in the active transfer */
-		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (!clli)
+		return bytes;
 
-		if (clli) {
-			struct pl08x_lli *llis_va = txd->llis_va;
-			dma_addr_t llis_bus = txd->llis_bus;
-			int index;
+	llis_va = txd->llis_va;
+	llis_bus = txd->llis_bus;
 
-			BUG_ON(clli < llis_bus || clli >= llis_bus +
+	BUG_ON(clli < llis_bus || clli >= llis_bus +
 				sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 
-			/*
-			 * Locate the next LLI - as this is an array,
-			 * it's simple maths to find.
-			 */
-			index = (clli - llis_bus) / sizeof(struct pl08x_lli);
+	/*
+	 * Locate the next LLI - as this is an array,
+	 * it's simple maths to find.
+	 */
+	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
-			for (; index < MAX_NUM_TSFR_LLIS; index++) {
-				bytes += get_bytes_in_cctl(llis_va[index].cctl);
+	for (; index < MAX_NUM_TSFR_LLIS; index++) {
+		bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
-				/*
-				 * A LLI pointer of 0 terminates the LLI list
-				 */
-				if (!llis_va[index].lli)
-					break;
-			}
-		}
+		/*
+		 * A LLI pointer of 0 terminates the LLI list
+		 */
+		if (!llis_va[index].lli)
+			break;
 	}
 
 	return bytes;
-- 
1.8.2.1

[RFC PATCH 02/11] dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation

[Tomasz Figa]

Further patch will introduce support for PL080S, which requires some
things to be done conditionally, thus increasing indentation level of
some functions even more.

This patch reduces indentation level of pl08x_getbytes_chan() function
by inverting several conditions and returning from function wherever
possible.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d443a68..1e57ded 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -473,47 +473,52 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
+	dma_addr_t llis_bus;
 	struct pl08x_txd *txd;
 	size_t bytes = 0;
+	int index;
+	u32 clli;
 
 	ch = plchan->phychan;
 	txd = plchan->at;
 
+	if (!ch || !txd)
+		return bytes;
+
 	/*
 	 * Follow the LLIs to get the number of remaining
 	 * bytes in the currently active transaction.
 	 */
-	if (ch && txd) {
-		u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+
+	/* First get the remaining bytes in the active transfer */
+	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
-		/* First get the remaining bytes in the active transfer */
-		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (!clli)
+		return bytes;
 
-		if (clli) {
-			struct pl08x_lli *llis_va = txd->llis_va;
-			dma_addr_t llis_bus = txd->llis_bus;
-			int index;
+	llis_va = txd->llis_va;
+	llis_bus = txd->llis_bus;
 
-			BUG_ON(clli < llis_bus || clli >= llis_bus +
+	BUG_ON(clli < llis_bus || clli >= llis_bus +
 				sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 
-			/*
-			 * Locate the next LLI - as this is an array,
-			 * it's simple maths to find.
-			 */
-			index = (clli - llis_bus) / sizeof(struct pl08x_lli);
+	/*
+	 * Locate the next LLI - as this is an array,
+	 * it's simple maths to find.
+	 */
+	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
-			for (; index < MAX_NUM_TSFR_LLIS; index++) {
-				bytes += get_bytes_in_cctl(llis_va[index].cctl);
+	for (; index < MAX_NUM_TSFR_LLIS; index++) {
+		bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
-				/*
-				 * A LLI pointer of 0 terminates the LLI list
-				 */
-				if (!llis_va[index].lli)
-					break;
-			}
-		}
+		/*
+		 * A LLI pointer of 0 terminates the LLI list
+		 */
+		if (!llis_va[index].lli)
+			break;
 	}
 
 	return bytes;
-- 
1.8.2.1

[RFC PATCH 02/11] dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation

[Tomasz Figa]

Further patch will introduce support for PL080S, which requires some
things to be done conditionally, thus increasing indentation level of
some functions even more.

This patch reduces indentation level of pl08x_getbytes_chan() function
by inverting several conditions and returning from function wherever
possible.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d443a68..1e57ded 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -473,47 +473,52 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
+	dma_addr_t llis_bus;
 	struct pl08x_txd *txd;
 	size_t bytes = 0;
+	int index;
+	u32 clli;
 
 	ch = plchan->phychan;
 	txd = plchan->at;
 
+	if (!ch || !txd)
+		return bytes;
+
 	/*
 	 * Follow the LLIs to get the number of remaining
 	 * bytes in the currently active transaction.
 	 */
-	if (ch && txd) {
-		u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
+
+	/* First get the remaining bytes in the active transfer */
+	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
-		/* First get the remaining bytes in the active transfer */
-		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (!clli)
+		return bytes;
 
-		if (clli) {
-			struct pl08x_lli *llis_va = txd->llis_va;
-			dma_addr_t llis_bus = txd->llis_bus;
-			int index;
+	llis_va = txd->llis_va;
+	llis_bus = txd->llis_bus;
 
-			BUG_ON(clli < llis_bus || clli >= llis_bus +
+	BUG_ON(clli < llis_bus || clli >= llis_bus +
 				sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
 
-			/*
-			 * Locate the next LLI - as this is an array,
-			 * it's simple maths to find.
-			 */
-			index = (clli - llis_bus) / sizeof(struct pl08x_lli);
+	/*
+	 * Locate the next LLI - as this is an array,
+	 * it's simple maths to find.
+	 */
+	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
-			for (; index < MAX_NUM_TSFR_LLIS; index++) {
-				bytes += get_bytes_in_cctl(llis_va[index].cctl);
+	for (; index < MAX_NUM_TSFR_LLIS; index++) {
+		bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
-				/*
-				 * A LLI pointer of 0 terminates the LLI list
-				 */
-				if (!llis_va[index].lli)
-					break;
-			}
-		}
+		/*
+		 * A LLI pointer of 0 terminates the LLI list
+		 */
+		if (!llis_va[index].lli)
+			break;
 	}
 
 	return bytes;
-- 
1.8.2.1

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
have CONFIG register at different offset. This patch makes the driver
use offset from vendor data struct.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++++--------------------
 1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 1e57ded..93913b4 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -107,6 +107,7 @@ struct pl08x_driver_data;
  * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
+	u8 config_offset;
 	u8 channels;
 	u32 flags;
 };
@@ -334,11 +335,12 @@ static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
  */
 
 /* Whether a certain channel is busy or not */
-static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
+static int pl08x_phy_channel_busy(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	unsigned int val;
 
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	return val & PL080_CONFIG_ACTIVE;
 }
 
@@ -362,7 +364,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	plchan->at = txd;
 
 	/* Wait for channel inactive */
-	while (pl08x_phy_channel_busy(phychan))
+	while (pl08x_phy_channel_busy(pl08x, phychan))
 		cpu_relax();
 
 	lli = &txd->llis_va[0];
@@ -377,7 +379,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
 	writel(lli->lli, phychan->base + PL080_CH_LLI);
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
-	writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
+	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
@@ -385,11 +387,13 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 		cpu_relax();
 
 	/* Do not access config register until channel shows as inactive */
-	val = readl(phychan->base + PL080_CH_CONFIG);
+
+	val = readl(phychan->base + pl08x->vd->config_offset);
 	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
-		val = readl(phychan->base + PL080_CH_CONFIG);
+		val = readl(phychan->base + pl08x->vd->config_offset);
 
-	writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
+	writel(val | PL080_CONFIG_ENABLE,
+				phychan->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -402,34 +406,36 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
  * For P->M transfers, disable the peripheral first to stop it filling
  * the DMAC FIFO, and then pause the DMAC.
  */
-static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_pause_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 	int timeout;
 
 	/* Set the HALT bit and wait for the FIFO to drain */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val |= PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	/* Wait for channel inactive */
 	for (timeout = 1000; timeout; timeout--) {
-		if (!pl08x_phy_channel_busy(ch))
+		if (!pl08x_phy_channel_busy(pl08x, ch))
 			break;
 		udelay(1);
 	}
-	if (pl08x_phy_channel_busy(ch))
+	if (pl08x_phy_channel_busy(pl08x, ch))
 		pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
 }
 
-static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_resume_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 
 	/* Clear the HALT bit */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val &= ~PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -441,12 +447,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 	struct pl08x_phy_chan *ch)
 {
-	u32 val = readl(ch->base + PL080_CH_CONFIG);
+	u32 val = readl(ch->base + pl08x->vd->config_offset);
 
 	val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
 	         PL080_CONFIG_TC_IRQ_MASK);
 
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
 	writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
@@ -1576,11 +1582,11 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		pl08x_free_txd_list(pl08x, plchan);
 		break;
 	case DMA_PAUSE:
-		pl08x_pause_phy_chan(plchan->phychan);
+		pl08x_pause_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_PAUSED;
 		break;
 	case DMA_RESUME:
-		pl08x_resume_phy_chan(plchan->phychan);
+		pl08x_resume_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_RUNNING;
 		break;
 	default:
@@ -1966,7 +1972,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
-			val = readl(ch->base + PL080_CH_CONFIG);
+			val = readl(ch->base + vd->config_offset);
 			if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
 				dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
 				ch->locked = true;
@@ -1974,7 +1980,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		}
 
 		dev_dbg(&adev->dev, "physical channel %d is %s\n",
-			i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+			i, pl08x_phy_channel_busy(pl08x, ch) ? "BUSY" : "FREE");
 	}
 
 	/* Register as many memcpy channels as there are physical channels */
@@ -2049,16 +2055,19 @@ out_no_pl08x:
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
have CONFIG register at different offset. This patch makes the driver
use offset from vendor data struct.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++++--------------------
 1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 1e57ded..93913b4 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -107,6 +107,7 @@ struct pl08x_driver_data;
  * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
+	u8 config_offset;
 	u8 channels;
 	u32 flags;
 };
@@ -334,11 +335,12 @@ static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
  */
 
 /* Whether a certain channel is busy or not */
-static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
+static int pl08x_phy_channel_busy(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	unsigned int val;
 
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	return val & PL080_CONFIG_ACTIVE;
 }
 
@@ -362,7 +364,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	plchan->at = txd;
 
 	/* Wait for channel inactive */
-	while (pl08x_phy_channel_busy(phychan))
+	while (pl08x_phy_channel_busy(pl08x, phychan))
 		cpu_relax();
 
 	lli = &txd->llis_va[0];
@@ -377,7 +379,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
 	writel(lli->lli, phychan->base + PL080_CH_LLI);
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
-	writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
+	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
@@ -385,11 +387,13 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 		cpu_relax();
 
 	/* Do not access config register until channel shows as inactive */
-	val = readl(phychan->base + PL080_CH_CONFIG);
+
+	val = readl(phychan->base + pl08x->vd->config_offset);
 	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
-		val = readl(phychan->base + PL080_CH_CONFIG);
+		val = readl(phychan->base + pl08x->vd->config_offset);
 
-	writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
+	writel(val | PL080_CONFIG_ENABLE,
+				phychan->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -402,34 +406,36 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
  * For P->M transfers, disable the peripheral first to stop it filling
  * the DMAC FIFO, and then pause the DMAC.
  */
-static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_pause_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 	int timeout;
 
 	/* Set the HALT bit and wait for the FIFO to drain */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val |= PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	/* Wait for channel inactive */
 	for (timeout = 1000; timeout; timeout--) {
-		if (!pl08x_phy_channel_busy(ch))
+		if (!pl08x_phy_channel_busy(pl08x, ch))
 			break;
 		udelay(1);
 	}
-	if (pl08x_phy_channel_busy(ch))
+	if (pl08x_phy_channel_busy(pl08x, ch))
 		pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
 }
 
-static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_resume_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 
 	/* Clear the HALT bit */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val &= ~PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -441,12 +447,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 	struct pl08x_phy_chan *ch)
 {
-	u32 val = readl(ch->base + PL080_CH_CONFIG);
+	u32 val = readl(ch->base + pl08x->vd->config_offset);
 
 	val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
 	         PL080_CONFIG_TC_IRQ_MASK);
 
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
 	writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
@@ -1576,11 +1582,11 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		pl08x_free_txd_list(pl08x, plchan);
 		break;
 	case DMA_PAUSE:
-		pl08x_pause_phy_chan(plchan->phychan);
+		pl08x_pause_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_PAUSED;
 		break;
 	case DMA_RESUME:
-		pl08x_resume_phy_chan(plchan->phychan);
+		pl08x_resume_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_RUNNING;
 		break;
 	default:
@@ -1966,7 +1972,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
-			val = readl(ch->base + PL080_CH_CONFIG);
+			val = readl(ch->base + vd->config_offset);
 			if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
 				dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
 				ch->locked = true;
@@ -1974,7 +1980,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		}
 
 		dev_dbg(&adev->dev, "physical channel %d is %s\n",
-			i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+			i, pl08x_phy_channel_busy(pl08x, ch) ? "BUSY" : "FREE");
 	}
 
 	/* Register as many memcpy channels as there are physical channels */
@@ -2049,16 +2055,19 @@ out_no_pl08x:
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
have CONFIG register at different offset. This patch makes the driver
use offset from vendor data struct.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++++--------------------
 1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 1e57ded..93913b4 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -107,6 +107,7 @@ struct pl08x_driver_data;
  * @flags: Vendor-specific flags, see PL08X_IS_*
  */
 struct vendor_data {
+	u8 config_offset;
 	u8 channels;
 	u32 flags;
 };
@@ -334,11 +335,12 @@ static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
  */
 
 /* Whether a certain channel is busy or not */
-static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
+static int pl08x_phy_channel_busy(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	unsigned int val;
 
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	return val & PL080_CONFIG_ACTIVE;
 }
 
@@ -362,7 +364,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	plchan->at = txd;
 
 	/* Wait for channel inactive */
-	while (pl08x_phy_channel_busy(phychan))
+	while (pl08x_phy_channel_busy(pl08x, phychan))
 		cpu_relax();
 
 	lli = &txd->llis_va[0];
@@ -377,7 +379,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
 	writel(lli->lli, phychan->base + PL080_CH_LLI);
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
-	writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
+	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
@@ -385,11 +387,13 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 		cpu_relax();
 
 	/* Do not access config register until channel shows as inactive */
-	val = readl(phychan->base + PL080_CH_CONFIG);
+
+	val = readl(phychan->base + pl08x->vd->config_offset);
 	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
-		val = readl(phychan->base + PL080_CH_CONFIG);
+		val = readl(phychan->base + pl08x->vd->config_offset);
 
-	writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
+	writel(val | PL080_CONFIG_ENABLE,
+				phychan->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -402,34 +406,36 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
  * For P->M transfers, disable the peripheral first to stop it filling
  * the DMAC FIFO, and then pause the DMAC.
  */
-static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_pause_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 	int timeout;
 
 	/* Set the HALT bit and wait for the FIFO to drain */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val |= PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	/* Wait for channel inactive */
 	for (timeout = 1000; timeout; timeout--) {
-		if (!pl08x_phy_channel_busy(ch))
+		if (!pl08x_phy_channel_busy(pl08x, ch))
 			break;
 		udelay(1);
 	}
-	if (pl08x_phy_channel_busy(ch))
+	if (pl08x_phy_channel_busy(pl08x, ch))
 		pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
 }
 
-static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
+static void pl08x_resume_phy_chan(struct pl08x_driver_data *pl08x,
+						struct pl08x_phy_chan *ch)
 {
 	u32 val;
 
 	/* Clear the HALT bit */
-	val = readl(ch->base + PL080_CH_CONFIG);
+	val = readl(ch->base + pl08x->vd->config_offset);
 	val &= ~PL080_CONFIG_HALT;
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 }
 
 /*
@@ -441,12 +447,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 	struct pl08x_phy_chan *ch)
 {
-	u32 val = readl(ch->base + PL080_CH_CONFIG);
+	u32 val = readl(ch->base + pl08x->vd->config_offset);
 
 	val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
 	         PL080_CONFIG_TC_IRQ_MASK);
 
-	writel(val, ch->base + PL080_CH_CONFIG);
+	writel(val, ch->base + pl08x->vd->config_offset);
 
 	writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
 	writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
@@ -1576,11 +1582,11 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		pl08x_free_txd_list(pl08x, plchan);
 		break;
 	case DMA_PAUSE:
-		pl08x_pause_phy_chan(plchan->phychan);
+		pl08x_pause_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_PAUSED;
 		break;
 	case DMA_RESUME:
-		pl08x_resume_phy_chan(plchan->phychan);
+		pl08x_resume_phy_chan(pl08x, plchan->phychan);
 		plchan->state = PL08X_CHAN_RUNNING;
 		break;
 	default:
@@ -1966,7 +1972,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		if (vd->flags & PL08X_IS_NOMADIK) {
 			u32 val;
 
-			val = readl(ch->base + PL080_CH_CONFIG);
+			val = readl(ch->base + vd->config_offset);
 			if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
 				dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
 				ch->locked = true;
@@ -1974,7 +1980,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 		}
 
 		dev_dbg(&adev->dev, "physical channel %d is %s\n",
-			i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+			i, pl08x_phy_channel_busy(pl08x, ch) ? "BUSY" : "FREE");
 	}
 
 	/* Register as many memcpy channels as there are physical channels */
@@ -2049,16 +2055,19 @@ out_no_pl08x:
 static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
+	.config_offset = PL080_CH_CONFIG,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Tomasz Figa]

PL080S is a modified version of PL080 that can be found on Samsung SoCs,
such as S3C6400 and S3C6410.

It has different offset of CONFIG register, separate CONTROL1 register
that holds transfer size and larger maximum transfer size.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c   | 68 +++++++++++++++++++++++++++++++++++++++-------
 include/linux/amba/pl080.h |  1 +
 2 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 93913b4..d1f1333 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -100,6 +100,8 @@ struct pl08x_driver_data;
  * for permission before use and some registers are missing.
  */
 #define PL08X_IS_NOMADIK	(1 << 1)
+/** Controller is PL080S (PL080 modified by Samsung) */
+#define PL08X_IS_PL080S		(1 << 2)
 
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
@@ -123,6 +125,7 @@ struct pl08x_lli {
 	u32 dst;
 	u32 lli;
 	u32 cctl;
+	u32 cctl1;
 };
 
 /**
@@ -381,6 +384,9 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
 	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		writel(lli->cctl1, phychan->base + PL080S_CH_CONTROL2);
+
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
 	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
@@ -476,9 +482,28 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	return bytes;
 }
 
+static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
+{
+	/* The source width defines the number of bytes */
+	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
+
+	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
+	case PL080_WIDTH_8BIT:
+		break;
+	case PL080_WIDTH_16BIT:
+		bytes *= 2;
+		break;
+	case PL080_WIDTH_32BIT:
+		bytes *= 4;
+		break;
+	}
+	return bytes;
+}
+
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
 	dma_addr_t llis_bus;
@@ -500,7 +525,12 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 
 	/* First get the remaining bytes in the active transfer */
-	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		bytes = get_bytes_in_cctl_pl080s(
+				readl(ch->base + PL080_CH_CONTROL),
+				readl(ch->base + PL080S_CH_CONTROL2));
+	else
+		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
 	if (!clli)
 		return bytes;
@@ -518,7 +548,11 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
 	for (; index < MAX_NUM_TSFR_LLIS; index++) {
-		bytes += get_bytes_in_cctl(llis_va[index].cctl);
+		if (pl08x->vd->flags & PL08X_IS_PL080S)
+			bytes += get_bytes_in_cctl_pl080s(llis_va[index].cctl,
+						llis_va[index].cctl1);
+		else
+			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
 		 * A LLI pointer of 0 terminates the LLI list
@@ -780,7 +814,7 @@ static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
  * Fills in one LLI for a certain transfer descriptor and advance the counter
  */
 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
-	int num_llis, int len, u32 cctl)
+	int num_llis, int len, u32 cctl, u32 cctl1)
 {
 	struct pl08x_lli *llis_va = bd->txd->llis_va;
 	dma_addr_t llis_bus = bd->txd->llis_bus;
@@ -788,6 +822,7 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 
 	llis_va[num_llis].cctl = cctl;
+	llis_va[num_llis].cctl1 = cctl1;
 	llis_va[num_llis].src = bd->srcbus.addr;
 	llis_va[num_llis].dst = bd->dstbus.addr;
 	llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
@@ -804,11 +839,12 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	bd->remainder -= len;
 }
 
-static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
+static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
+		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
 	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
-	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
+	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
 
@@ -912,7 +948,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 
 			cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, 0);
-			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
+			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl, 0);
 			break;
 		}
 
@@ -934,7 +970,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			dev_vdbg(&pl08x->adev->dev,
 				"%s byte width LLIs (remain 0x%08x)\n",
 				__func__, bd.remainder);
-			prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
+			prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, num_llis++,
 				&total_bytes);
 		}
 
@@ -992,7 +1028,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
-						lli_len, cctl);
+						lli_len, cctl, tsize);
 				total_bytes += lli_len;
 			}
 
@@ -1003,8 +1039,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				dev_vdbg(&pl08x->adev->dev,
 					"%s align with boundary, send odd bytes (remain %zu)\n",
 					__func__, bd.remainder);
-				prep_byte_width_lli(&bd, &cctl, bd.remainder,
-						num_llis++, &total_bytes);
+				prep_byte_width_lli(pl08x, &bd, &cctl,
+					bd.remainder, num_llis++, &total_bytes);
 			}
 		}
 
@@ -2064,6 +2100,12 @@ static struct vendor_data vendor_nomadik = {
 	.config_offset = PL080_CH_CONFIG,
 };
 
+static struct vendor_data vendor_pl080s = {
+	.channels = 8,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
+	.config_offset = PL080S_CH_CONFIG,
+};
+
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
@@ -2071,6 +2113,12 @@ static struct vendor_data vendor_pl081 = {
 };
 
 static struct amba_id pl08x_ids[] = {
+	/* Samsung PL080S variant */
+	{
+		.id	= 0x0a141080,
+		.mask	= 0xffffffff,
+		.data	= &vendor_pl080s,
+	},
 	/* PL080 */
 	{
 		.id	= 0x00041080,
diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 3e7b62f..ef36a0a 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -87,6 +87,7 @@
 #define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)
 #define PL080_CONTROL_SB_SIZE_SHIFT		(12)
 #define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)
+#define PL080S_CONTROL_TRANSFER_SIZE_MASK	(0xffffff << 0)
 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)
 
 #define PL080_BSIZE_1				(0x0)
-- 
1.8.2.1

[RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Tomasz Figa]

PL080S is a modified version of PL080 that can be found on Samsung SoCs,
such as S3C6400 and S3C6410.

It has different offset of CONFIG register, separate CONTROL1 register
that holds transfer size and larger maximum transfer size.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c   | 68 +++++++++++++++++++++++++++++++++++++++-------
 include/linux/amba/pl080.h |  1 +
 2 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 93913b4..d1f1333 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -100,6 +100,8 @@ struct pl08x_driver_data;
  * for permission before use and some registers are missing.
  */
 #define PL08X_IS_NOMADIK	(1 << 1)
+/** Controller is PL080S (PL080 modified by Samsung) */
+#define PL08X_IS_PL080S		(1 << 2)
 
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
@@ -123,6 +125,7 @@ struct pl08x_lli {
 	u32 dst;
 	u32 lli;
 	u32 cctl;
+	u32 cctl1;
 };
 
 /**
@@ -381,6 +384,9 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
 	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		writel(lli->cctl1, phychan->base + PL080S_CH_CONTROL2);
+
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
 	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
@@ -476,9 +482,28 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	return bytes;
 }
 
+static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
+{
+	/* The source width defines the number of bytes */
+	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
+
+	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
+	case PL080_WIDTH_8BIT:
+		break;
+	case PL080_WIDTH_16BIT:
+		bytes *= 2;
+		break;
+	case PL080_WIDTH_32BIT:
+		bytes *= 4;
+		break;
+	}
+	return bytes;
+}
+
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
 	dma_addr_t llis_bus;
@@ -500,7 +525,12 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 
 	/* First get the remaining bytes in the active transfer */
-	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		bytes = get_bytes_in_cctl_pl080s(
+				readl(ch->base + PL080_CH_CONTROL),
+				readl(ch->base + PL080S_CH_CONTROL2));
+	else
+		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
 	if (!clli)
 		return bytes;
@@ -518,7 +548,11 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
 	for (; index < MAX_NUM_TSFR_LLIS; index++) {
-		bytes += get_bytes_in_cctl(llis_va[index].cctl);
+		if (pl08x->vd->flags & PL08X_IS_PL080S)
+			bytes += get_bytes_in_cctl_pl080s(llis_va[index].cctl,
+						llis_va[index].cctl1);
+		else
+			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
 		 * A LLI pointer of 0 terminates the LLI list
@@ -780,7 +814,7 @@ static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
  * Fills in one LLI for a certain transfer descriptor and advance the counter
  */
 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
-	int num_llis, int len, u32 cctl)
+	int num_llis, int len, u32 cctl, u32 cctl1)
 {
 	struct pl08x_lli *llis_va = bd->txd->llis_va;
 	dma_addr_t llis_bus = bd->txd->llis_bus;
@@ -788,6 +822,7 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 
 	llis_va[num_llis].cctl = cctl;
+	llis_va[num_llis].cctl1 = cctl1;
 	llis_va[num_llis].src = bd->srcbus.addr;
 	llis_va[num_llis].dst = bd->dstbus.addr;
 	llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
@@ -804,11 +839,12 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	bd->remainder -= len;
 }
 
-static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
+static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
+		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
 	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
-	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
+	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
 
@@ -912,7 +948,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 
 			cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, 0);
-			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
+			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl, 0);
 			break;
 		}
 
@@ -934,7 +970,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			dev_vdbg(&pl08x->adev->dev,
 				"%s byte width LLIs (remain 0x%08x)\n",
 				__func__, bd.remainder);
-			prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
+			prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, num_llis++,
 				&total_bytes);
 		}
 
@@ -992,7 +1028,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
-						lli_len, cctl);
+						lli_len, cctl, tsize);
 				total_bytes += lli_len;
 			}
 
@@ -1003,8 +1039,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				dev_vdbg(&pl08x->adev->dev,
 					"%s align with boundary, send odd bytes (remain %zu)\n",
 					__func__, bd.remainder);
-				prep_byte_width_lli(&bd, &cctl, bd.remainder,
-						num_llis++, &total_bytes);
+				prep_byte_width_lli(pl08x, &bd, &cctl,
+					bd.remainder, num_llis++, &total_bytes);
 			}
 		}
 
@@ -2064,6 +2100,12 @@ static struct vendor_data vendor_nomadik = {
 	.config_offset = PL080_CH_CONFIG,
 };
 
+static struct vendor_data vendor_pl080s = {
+	.channels = 8,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
+	.config_offset = PL080S_CH_CONFIG,
+};
+
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
@@ -2071,6 +2113,12 @@ static struct vendor_data vendor_pl081 = {
 };
 
 static struct amba_id pl08x_ids[] = {
+	/* Samsung PL080S variant */
+	{
+		.id	= 0x0a141080,
+		.mask	= 0xffffffff,
+		.data	= &vendor_pl080s,
+	},
 	/* PL080 */
 	{
 		.id	= 0x00041080,
diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 3e7b62f..ef36a0a 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -87,6 +87,7 @@
 #define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)
 #define PL080_CONTROL_SB_SIZE_SHIFT		(12)
 #define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)
+#define PL080S_CONTROL_TRANSFER_SIZE_MASK	(0xffffff << 0)
 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)
 
 #define PL080_BSIZE_1				(0x0)
-- 
1.8.2.1

[RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Tomasz Figa]

PL080S is a modified version of PL080 that can be found on Samsung SoCs,
such as S3C6400 and S3C6410.

It has different offset of CONFIG register, separate CONTROL1 register
that holds transfer size and larger maximum transfer size.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c   | 68 +++++++++++++++++++++++++++++++++++++++-------
 include/linux/amba/pl080.h |  1 +
 2 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 93913b4..d1f1333 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -100,6 +100,8 @@ struct pl08x_driver_data;
  * for permission before use and some registers are missing.
  */
 #define PL08X_IS_NOMADIK	(1 << 1)
+/** Controller is PL080S (PL080 modified by Samsung) */
+#define PL08X_IS_PL080S		(1 << 2)
 
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
@@ -123,6 +125,7 @@ struct pl08x_lli {
 	u32 dst;
 	u32 lli;
 	u32 cctl;
+	u32 cctl1;
 };
 
 /**
@@ -381,6 +384,9 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 	writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
 	writel(txd->ccfg, phychan->base + pl08x->vd->config_offset);
 
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		writel(lli->cctl1, phychan->base + PL080S_CH_CONTROL2);
+
 	/* Enable the DMA channel */
 	/* Do not access config register until channel shows as disabled */
 	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
@@ -476,9 +482,28 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	return bytes;
 }
 
+static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
+{
+	/* The source width defines the number of bytes */
+	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
+
+	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
+	case PL080_WIDTH_8BIT:
+		break;
+	case PL080_WIDTH_16BIT:
+		bytes *= 2;
+		break;
+	case PL080_WIDTH_32BIT:
+		bytes *= 4;
+		break;
+	}
+	return bytes;
+}
+
 /* The channel should be paused when calling this */
 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 {
+	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_lli *llis_va;
 	struct pl08x_phy_chan *ch;
 	dma_addr_t llis_bus;
@@ -500,7 +525,12 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
 
 	/* First get the remaining bytes in the active transfer */
-	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		bytes = get_bytes_in_cctl_pl080s(
+				readl(ch->base + PL080_CH_CONTROL),
+				readl(ch->base + PL080S_CH_CONTROL2));
+	else
+		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
 
 	if (!clli)
 		return bytes;
@@ -518,7 +548,11 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 	index = (clli - llis_bus) / sizeof(struct pl08x_lli);
 
 	for (; index < MAX_NUM_TSFR_LLIS; index++) {
-		bytes += get_bytes_in_cctl(llis_va[index].cctl);
+		if (pl08x->vd->flags & PL08X_IS_PL080S)
+			bytes += get_bytes_in_cctl_pl080s(llis_va[index].cctl,
+						llis_va[index].cctl1);
+		else
+			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
 		 * A LLI pointer of 0 terminates the LLI list
@@ -780,7 +814,7 @@ static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
  * Fills in one LLI for a certain transfer descriptor and advance the counter
  */
 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
-	int num_llis, int len, u32 cctl)
+	int num_llis, int len, u32 cctl, u32 cctl1)
 {
 	struct pl08x_lli *llis_va = bd->txd->llis_va;
 	dma_addr_t llis_bus = bd->txd->llis_bus;
@@ -788,6 +822,7 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
 
 	llis_va[num_llis].cctl = cctl;
+	llis_va[num_llis].cctl1 = cctl1;
 	llis_va[num_llis].src = bd->srcbus.addr;
 	llis_va[num_llis].dst = bd->dstbus.addr;
 	llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
@@ -804,11 +839,12 @@ static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
 	bd->remainder -= len;
 }
 
-static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
+static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
+		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
 	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
-	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
+	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
 
@@ -912,7 +948,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 
 			cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, 0);
-			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
+			pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl, 0);
 			break;
 		}
 
@@ -934,7 +970,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			dev_vdbg(&pl08x->adev->dev,
 				"%s byte width LLIs (remain 0x%08x)\n",
 				__func__, bd.remainder);
-			prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
+			prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, num_llis++,
 				&total_bytes);
 		}
 
@@ -992,7 +1028,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
 					bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
-						lli_len, cctl);
+						lli_len, cctl, tsize);
 				total_bytes += lli_len;
 			}
 
@@ -1003,8 +1039,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 				dev_vdbg(&pl08x->adev->dev,
 					"%s align with boundary, send odd bytes (remain %zu)\n",
 					__func__, bd.remainder);
-				prep_byte_width_lli(&bd, &cctl, bd.remainder,
-						num_llis++, &total_bytes);
+				prep_byte_width_lli(pl08x, &bd, &cctl,
+					bd.remainder, num_llis++, &total_bytes);
 			}
 		}
 
@@ -2064,6 +2100,12 @@ static struct vendor_data vendor_nomadik = {
 	.config_offset = PL080_CH_CONFIG,
 };
 
+static struct vendor_data vendor_pl080s = {
+	.channels = 8,
+	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
+	.config_offset = PL080S_CH_CONFIG,
+};
+
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
@@ -2071,6 +2113,12 @@ static struct vendor_data vendor_pl081 = {
 };
 
 static struct amba_id pl08x_ids[] = {
+	/* Samsung PL080S variant */
+	{
+		.id	= 0x0a141080,
+		.mask	= 0xffffffff,
+		.data	= &vendor_pl080s,
+	},
 	/* PL080 */
 	{
 		.id	= 0x00041080,
diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 3e7b62f..ef36a0a 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -87,6 +87,7 @@
 #define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)
 #define PL080_CONTROL_SB_SIZE_SHIFT		(12)
 #define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)
+#define PL080S_CONTROL_TRANSFER_SIZE_MASK	(0xffffff << 0)
 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)
 
 #define PL080_BSIZE_1				(0x0)
-- 
1.8.2.1

[RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Tomasz Figa]

PL080S has separate register to store transfer size in, allowing single
transfer to be much larger than in standard PL080.

This patch makes the amba-pl08x driver aware of this and removes writing
transfer size to reserved bits of CH_CONTROL register on PL080S, which
was not a problem witn transfer sizes fitting the original bitfield
of PL080, but now would overwrite other fields.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d1f1333..eb10eb8 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -112,6 +112,7 @@ struct vendor_data {
 	u8 config_offset;
 	u8 channels;
 	u32 flags;
+	u32 max_transfer_size;
 };
 
 /*
@@ -843,7 +844,10 @@ static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
 		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
-	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, 0);
+	else
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
 	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
@@ -992,7 +996,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			 * MIN(buswidths)
 			 */
 			max_bytes_per_lli = bd.srcbus.buswidth *
-				PL080_CONTROL_TRANSFER_SIZE_MASK;
+						pl08x->vd->max_transfer_size;
 			dev_vdbg(&pl08x->adev->dev,
 				"%s max bytes per lli = %zu\n",
 				__func__, max_bytes_per_lli);
@@ -1025,8 +1029,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 					"size 0x%08zx (remainder 0x%08zx)\n",
 					__func__, lli_len, bd.remainder);
 
-				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
-					bd.dstbus.buswidth, tsize);
+				if (pl08x->vd->flags & PL08X_IS_PL080S)
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, 0);
+				else
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
 						lli_len, cctl, tsize);
 				total_bytes += lli_len;
@@ -2092,24 +2102,28 @@ static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl080s = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
 	.config_offset = PL080S_CH_CONFIG,
+	.max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Tomasz Figa]

PL080S has separate register to store transfer size in, allowing single
transfer to be much larger than in standard PL080.

This patch makes the amba-pl08x driver aware of this and removes writing
transfer size to reserved bits of CH_CONTROL register on PL080S, which
was not a problem witn transfer sizes fitting the original bitfield
of PL080, but now would overwrite other fields.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d1f1333..eb10eb8 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -112,6 +112,7 @@ struct vendor_data {
 	u8 config_offset;
 	u8 channels;
 	u32 flags;
+	u32 max_transfer_size;
 };
 
 /*
@@ -843,7 +844,10 @@ static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
 		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
-	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, 0);
+	else
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
 	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
@@ -992,7 +996,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			 * MIN(buswidths)
 			 */
 			max_bytes_per_lli = bd.srcbus.buswidth *
-				PL080_CONTROL_TRANSFER_SIZE_MASK;
+						pl08x->vd->max_transfer_size;
 			dev_vdbg(&pl08x->adev->dev,
 				"%s max bytes per lli = %zu\n",
 				__func__, max_bytes_per_lli);
@@ -1025,8 +1029,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 					"size 0x%08zx (remainder 0x%08zx)\n",
 					__func__, lli_len, bd.remainder);
 
-				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
-					bd.dstbus.buswidth, tsize);
+				if (pl08x->vd->flags & PL08X_IS_PL080S)
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, 0);
+				else
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
 						lli_len, cctl, tsize);
 				total_bytes += lli_len;
@@ -2092,24 +2102,28 @@ static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl080s = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
 	.config_offset = PL080S_CH_CONFIG,
+	.max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Tomasz Figa]

PL080S has separate register to store transfer size in, allowing single
transfer to be much larger than in standard PL080.

This patch makes the amba-pl08x driver aware of this and removes writing
transfer size to reserved bits of CH_CONTROL register on PL080S, which
was not a problem witn transfer sizes fitting the original bitfield
of PL080, but now would overwrite other fields.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index d1f1333..eb10eb8 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -112,6 +112,7 @@ struct vendor_data {
 	u8 config_offset;
 	u8 channels;
 	u32 flags;
+	u32 max_transfer_size;
 };
 
 /*
@@ -843,7 +844,10 @@ static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
 		struct pl08x_lli_build_data *bd,
 		u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
 {
-	*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
+	if (pl08x->vd->flags & PL08X_IS_PL080S)
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, 0);
+	else
+		*cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
 	pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl, len);
 	(*total_bytes) += len;
 }
@@ -992,7 +996,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 			 * MIN(buswidths)
 			 */
 			max_bytes_per_lli = bd.srcbus.buswidth *
-				PL080_CONTROL_TRANSFER_SIZE_MASK;
+						pl08x->vd->max_transfer_size;
 			dev_vdbg(&pl08x->adev->dev,
 				"%s max bytes per lli = %zu\n",
 				__func__, max_bytes_per_lli);
@@ -1025,8 +1029,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 					"size 0x%08zx (remainder 0x%08zx)\n",
 					__func__, lli_len, bd.remainder);
 
-				cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
-					bd.dstbus.buswidth, tsize);
+				if (pl08x->vd->flags & PL08X_IS_PL080S)
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, 0);
+				else
+					cctl = pl08x_cctl_bits(cctl,
+						bd.srcbus.buswidth,
+						bd.dstbus.buswidth, tsize);
 				pl08x_fill_lli_for_desc(&bd, num_llis++,
 						lli_len, cctl, tsize);
 				total_bytes += lli_len;
@@ -2092,24 +2102,28 @@ static struct vendor_data vendor_pl080 = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_nomadik = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl080s = {
 	.channels = 8,
 	.flags = PL08X_IS_DUALMASTER | PL08X_IS_PL080S,
 	.config_offset = PL080S_CH_CONFIG,
+	.max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct vendor_data vendor_pl081 = {
 	.channels = 2,
 	.flags = 0,
 	.config_offset = PL080_CH_CONFIG,
+	.max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
 };
 
 static struct amba_id pl08x_ids[] = {
-- 
1.8.2.1

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Tomasz Figa]

PL080 reference manual states that to LLI entries should be aligned
to 4-word boundary to make LLI fetches more efficient. This patch adds
a 3-word padding to the LLi struct to make this condition true.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index eb10eb8..0da5539 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -127,6 +127,7 @@ struct pl08x_lli {
 	u32 lli;
 	u32 cctl;
 	u32 cctl1;
+	u32 dummy[3];
 };
 
 /**
-- 
1.8.2.1

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Tomasz Figa]

PL080 reference manual states that to LLI entries should be aligned
to 4-word boundary to make LLI fetches more efficient. This patch adds
a 3-word padding to the LLi struct to make this condition true.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index eb10eb8..0da5539 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -127,6 +127,7 @@ struct pl08x_lli {
 	u32 lli;
 	u32 cctl;
 	u32 cctl1;
+	u32 dummy[3];
 };
 
 /**
-- 
1.8.2.1

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Tomasz Figa]

PL080 reference manual states that to LLI entries should be aligned
to 4-word boundary to make LLI fetches more efficient. This patch adds
a 3-word padding to the LLi struct to make this condition true.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index eb10eb8..0da5539 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -127,6 +127,7 @@ struct pl08x_lli {
 	u32 lli;
 	u32 cctl;
 	u32 cctl1;
+	u32 dummy[3];
 };
 
 /**
-- 
1.8.2.1

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 0da5539..bb3b36b 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -471,6 +471,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
@@ -489,6 +491,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
-- 
1.8.2.1

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 0da5539..bb3b36b 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -471,6 +471,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
@@ -489,6 +491,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
-- 
1.8.2.1

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 0da5539..bb3b36b 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -471,6 +471,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
@@ -489,6 +491,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
-- 
1.8.2.1

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

Many audio interface drivers require support of cyclic transfers to work
correctly, for example Samsung ASoC DMA driver. This patch adds support
for cyclic transfers to the amba-pl08x driver.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 181 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 136 insertions(+), 45 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index bb3b36b..210a893 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -184,6 +184,7 @@ struct pl08x_sg {
  * @ccfg: config reg values for current txd
  * @done: this marks completed descriptors, which should not have their
  *   mux released.
+ * @cyclic: indicate cyclic transfers
  */
 struct pl08x_txd {
 	struct virt_dma_desc vd;
@@ -198,6 +199,8 @@ struct pl08x_txd {
 	 */
 	u32 ccfg;
 	bool done;
+
+	bool cyclic;
 };
 
 /**
@@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
-		 * A LLI pointer of 0 terminates the LLI list
++		 * A LLI pointer going backward terminates the LLI list
 		 */
-		if (!llis_va[index].lli)
+		if (llis_va[index].lli <= clli)
 			break;
 	}
 
@@ -1075,10 +1078,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 	}
 
 	llis_va = txd->llis_va;
-	/* The final LLI terminates the LLI. */
-	llis_va[num_llis - 1].lli = 0;
-	/* The final LLI element shall also fire an interrupt. */
-	llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	if (txd->cyclic) {
+		/* Link back to the first LLI. */
+		llis_va[num_llis - 1].lli = txd->llis_bus | bd.lli_bus;
+	} else {
+		/* The final LLI terminates the LLI. */
+		llis_va[num_llis - 1].lli = 0;
+		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	}
 
 #ifdef VERBOSE_DEBUG
 	{
@@ -1470,25 +1477,19 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
 }
 
-static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
-		struct dma_chan *chan, struct scatterlist *sgl,
-		unsigned int sg_len, enum dma_transfer_direction direction,
-		unsigned long flags, void *context)
+static struct pl08x_txd *pl08x_init_txd(
+		struct dma_chan *chan,
+		enum dma_transfer_direction direction,
+		dma_addr_t *slave_addr)
 {
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
 	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_txd *txd;
-	struct pl08x_sg *dsg;
-	struct scatterlist *sg;
 	enum dma_slave_buswidth addr_width;
-	dma_addr_t slave_addr;
 	int ret, tmp;
 	u8 src_buses, dst_buses;
 	u32 maxburst, cctl;
 
-	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
-			__func__, sg_dma_len(sgl), plchan->name);
-
 	txd = pl08x_get_txd(plchan);
 	if (!txd) {
 		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
@@ -1502,14 +1503,14 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	 */
 	if (direction == DMA_MEM_TO_DEV) {
 		cctl = PL080_CONTROL_SRC_INCR;
-		slave_addr = plchan->cfg.dst_addr;
+		*slave_addr = plchan->cfg.dst_addr;
 		addr_width = plchan->cfg.dst_addr_width;
 		maxburst = plchan->cfg.dst_maxburst;
 		src_buses = pl08x->mem_buses;
 		dst_buses = plchan->cd->periph_buses;
 	} else if (direction == DMA_DEV_TO_MEM) {
 		cctl = PL080_CONTROL_DST_INCR;
-		slave_addr = plchan->cfg.src_addr;
+		*slave_addr = plchan->cfg.src_addr;
 		addr_width = plchan->cfg.src_addr_width;
 		maxburst = plchan->cfg.src_maxburst;
 		src_buses = plchan->cd->periph_buses;
@@ -1558,24 +1559,107 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	else
 		txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
 
+	return txd;
+}
+
+static int pl08x_tx_add_sg(struct pl08x_txd *txd,
+			   enum dma_transfer_direction direction,
+			   dma_addr_t slave_addr,
+			   dma_addr_t buf_addr,
+			   unsigned int len)
+{
+	struct pl08x_sg *dsg;
+
+	dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
+	if (!dsg)
+		return -ENOMEM;
+
+	list_add_tail(&dsg->node, &txd->dsg_list);
+
+	dsg->len = len;
+	if (direction == DMA_MEM_TO_DEV) {
+		dsg->src_addr = buf_addr;
+		dsg->dst_addr = slave_addr;
+	} else {
+		dsg->src_addr = slave_addr;
+		dsg->dst_addr = buf_addr;
+	}
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	struct scatterlist *sg;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
+			__func__, sg_dma_len(sgl), plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
 	for_each_sg(sgl, sg, sg_len, tmp) {
-		dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
-		if (!dsg) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      sg_dma_address(sg),
+				      sg_dma_len(sg));
+		if (ret) {
 			pl08x_release_mux(plchan);
 			pl08x_free_txd(pl08x, txd);
 			dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
 					__func__);
 			return NULL;
 		}
-		list_add_tail(&dsg->node, &txd->dsg_list);
+	}
 
-		dsg->len = sg_dma_len(sg);
-		if (direction == DMA_MEM_TO_DEV) {
-			dsg->src_addr = sg_dma_address(sg);
-			dsg->dst_addr = slave_addr;
-		} else {
-			dsg->src_addr = slave_addr;
-			dsg->dst_addr = sg_dma_address(sg);
+	ret = pl08x_fill_llis_for_desc(plchan->host, txd);
+	if (!ret) {
+		pl08x_release_mux(plchan);
+		pl08x_free_txd(pl08x, txd);
+		return NULL;
+	}
+
+	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev,
+		"%s prepare cyclic transaction of %d/%d bytes %s %s\n",
+		__func__, period_len, buf_len,
+		direction == DMA_MEM_TO_DEV ? "to" : "from",
+		plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
+	txd->cyclic = true;
+	txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
+	for (tmp = 0 ; tmp < buf_len ; tmp += period_len) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      buf_addr + tmp, period_len);
+		if (ret) {
+			pl08x_release_mux(plchan);
+			pl08x_free_txd(pl08x, txd);
+			return NULL;
 		}
 	}
 
@@ -1719,23 +1803,28 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
 			spin_lock(&plchan->vc.lock);
 			tx = plchan->at;
 			if (tx) {
-				plchan->at = NULL;
-				/*
-				 * This descriptor is done, release its mux
-				 * reservation.
-				 */
-				pl08x_release_mux(plchan);
-				tx->done = true;
-				vchan_cookie_complete(&tx->vd);
-
-				/*
-				 * And start the next descriptor (if any),
-				 * otherwise free this channel.
-				 */
-				if (vchan_next_desc(&plchan->vc))
-					pl08x_start_next_txd(plchan);
-				else
-					pl08x_phy_free(plchan);
+				if (tx->cyclic) {
+					vchan_cyclic_callback(&tx->vd);
+				} else {
+					plchan->at = NULL;
+					/*
+					 * This descriptor is done, release
+					 * its mux reservation.
+					 */
+					pl08x_release_mux(plchan);
+					tx->done = true;
+					vchan_cookie_complete(&tx->vd);
+
+					/*
+					 * And start the next descriptor
+					 * (if any), otherwise free this
+					 * channel.
+					 */
+					if (vchan_next_desc(&plchan->vc))
+						pl08x_start_next_txd(plchan);
+					else
+						pl08x_phy_free(plchan);
+				}
 			}
 			spin_unlock(&plchan->vc.lock);
 
@@ -1939,6 +2028,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 
 	/* Initialize slave engine */
 	dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
+	dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
 	pl08x->slave.dev = &adev->dev;
 	pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
 	pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
@@ -1946,6 +2036,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	pl08x->slave.device_tx_status = pl08x_dma_tx_status;
 	pl08x->slave.device_issue_pending = pl08x_issue_pending;
 	pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
+	pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
 	pl08x->slave.device_control = pl08x_control;
 
 	/* Get the platform data */
-- 
1.8.2.1

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

Many audio interface drivers require support of cyclic transfers to work
correctly, for example Samsung ASoC DMA driver. This patch adds support
for cyclic transfers to the amba-pl08x driver.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 181 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 136 insertions(+), 45 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index bb3b36b..210a893 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -184,6 +184,7 @@ struct pl08x_sg {
  * @ccfg: config reg values for current txd
  * @done: this marks completed descriptors, which should not have their
  *   mux released.
+ * @cyclic: indicate cyclic transfers
  */
 struct pl08x_txd {
 	struct virt_dma_desc vd;
@@ -198,6 +199,8 @@ struct pl08x_txd {
 	 */
 	u32 ccfg;
 	bool done;
+
+	bool cyclic;
 };
 
 /**
@@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
-		 * A LLI pointer of 0 terminates the LLI list
++		 * A LLI pointer going backward terminates the LLI list
 		 */
-		if (!llis_va[index].lli)
+		if (llis_va[index].lli <= clli)
 			break;
 	}
 
@@ -1075,10 +1078,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 	}
 
 	llis_va = txd->llis_va;
-	/* The final LLI terminates the LLI. */
-	llis_va[num_llis - 1].lli = 0;
-	/* The final LLI element shall also fire an interrupt. */
-	llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	if (txd->cyclic) {
+		/* Link back to the first LLI. */
+		llis_va[num_llis - 1].lli = txd->llis_bus | bd.lli_bus;
+	} else {
+		/* The final LLI terminates the LLI. */
+		llis_va[num_llis - 1].lli = 0;
+		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	}
 
 #ifdef VERBOSE_DEBUG
 	{
@@ -1470,25 +1477,19 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
 }
 
-static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
-		struct dma_chan *chan, struct scatterlist *sgl,
-		unsigned int sg_len, enum dma_transfer_direction direction,
-		unsigned long flags, void *context)
+static struct pl08x_txd *pl08x_init_txd(
+		struct dma_chan *chan,
+		enum dma_transfer_direction direction,
+		dma_addr_t *slave_addr)
 {
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
 	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_txd *txd;
-	struct pl08x_sg *dsg;
-	struct scatterlist *sg;
 	enum dma_slave_buswidth addr_width;
-	dma_addr_t slave_addr;
 	int ret, tmp;
 	u8 src_buses, dst_buses;
 	u32 maxburst, cctl;
 
-	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
-			__func__, sg_dma_len(sgl), plchan->name);
-
 	txd = pl08x_get_txd(plchan);
 	if (!txd) {
 		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
@@ -1502,14 +1503,14 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	 */
 	if (direction == DMA_MEM_TO_DEV) {
 		cctl = PL080_CONTROL_SRC_INCR;
-		slave_addr = plchan->cfg.dst_addr;
+		*slave_addr = plchan->cfg.dst_addr;
 		addr_width = plchan->cfg.dst_addr_width;
 		maxburst = plchan->cfg.dst_maxburst;
 		src_buses = pl08x->mem_buses;
 		dst_buses = plchan->cd->periph_buses;
 	} else if (direction == DMA_DEV_TO_MEM) {
 		cctl = PL080_CONTROL_DST_INCR;
-		slave_addr = plchan->cfg.src_addr;
+		*slave_addr = plchan->cfg.src_addr;
 		addr_width = plchan->cfg.src_addr_width;
 		maxburst = plchan->cfg.src_maxburst;
 		src_buses = plchan->cd->periph_buses;
@@ -1558,24 +1559,107 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	else
 		txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
 
+	return txd;
+}
+
+static int pl08x_tx_add_sg(struct pl08x_txd *txd,
+			   enum dma_transfer_direction direction,
+			   dma_addr_t slave_addr,
+			   dma_addr_t buf_addr,
+			   unsigned int len)
+{
+	struct pl08x_sg *dsg;
+
+	dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
+	if (!dsg)
+		return -ENOMEM;
+
+	list_add_tail(&dsg->node, &txd->dsg_list);
+
+	dsg->len = len;
+	if (direction == DMA_MEM_TO_DEV) {
+		dsg->src_addr = buf_addr;
+		dsg->dst_addr = slave_addr;
+	} else {
+		dsg->src_addr = slave_addr;
+		dsg->dst_addr = buf_addr;
+	}
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	struct scatterlist *sg;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
+			__func__, sg_dma_len(sgl), plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
 	for_each_sg(sgl, sg, sg_len, tmp) {
-		dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
-		if (!dsg) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      sg_dma_address(sg),
+				      sg_dma_len(sg));
+		if (ret) {
 			pl08x_release_mux(plchan);
 			pl08x_free_txd(pl08x, txd);
 			dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
 					__func__);
 			return NULL;
 		}
-		list_add_tail(&dsg->node, &txd->dsg_list);
+	}
 
-		dsg->len = sg_dma_len(sg);
-		if (direction == DMA_MEM_TO_DEV) {
-			dsg->src_addr = sg_dma_address(sg);
-			dsg->dst_addr = slave_addr;
-		} else {
-			dsg->src_addr = slave_addr;
-			dsg->dst_addr = sg_dma_address(sg);
+	ret = pl08x_fill_llis_for_desc(plchan->host, txd);
+	if (!ret) {
+		pl08x_release_mux(plchan);
+		pl08x_free_txd(pl08x, txd);
+		return NULL;
+	}
+
+	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev,
+		"%s prepare cyclic transaction of %d/%d bytes %s %s\n",
+		__func__, period_len, buf_len,
+		direction == DMA_MEM_TO_DEV ? "to" : "from",
+		plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
+	txd->cyclic = true;
+	txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
+	for (tmp = 0 ; tmp < buf_len ; tmp += period_len) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      buf_addr + tmp, period_len);
+		if (ret) {
+			pl08x_release_mux(plchan);
+			pl08x_free_txd(pl08x, txd);
+			return NULL;
 		}
 	}
 
@@ -1719,23 +1803,28 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
 			spin_lock(&plchan->vc.lock);
 			tx = plchan->at;
 			if (tx) {
-				plchan->at = NULL;
-				/*
-				 * This descriptor is done, release its mux
-				 * reservation.
-				 */
-				pl08x_release_mux(plchan);
-				tx->done = true;
-				vchan_cookie_complete(&tx->vd);
-
-				/*
-				 * And start the next descriptor (if any),
-				 * otherwise free this channel.
-				 */
-				if (vchan_next_desc(&plchan->vc))
-					pl08x_start_next_txd(plchan);
-				else
-					pl08x_phy_free(plchan);
+				if (tx->cyclic) {
+					vchan_cyclic_callback(&tx->vd);
+				} else {
+					plchan->at = NULL;
+					/*
+					 * This descriptor is done, release
+					 * its mux reservation.
+					 */
+					pl08x_release_mux(plchan);
+					tx->done = true;
+					vchan_cookie_complete(&tx->vd);
+
+					/*
+					 * And start the next descriptor
+					 * (if any), otherwise free this
+					 * channel.
+					 */
+					if (vchan_next_desc(&plchan->vc))
+						pl08x_start_next_txd(plchan);
+					else
+						pl08x_phy_free(plchan);
+				}
 			}
 			spin_unlock(&plchan->vc.lock);
 
@@ -1939,6 +2028,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 
 	/* Initialize slave engine */
 	dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
+	dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
 	pl08x->slave.dev = &adev->dev;
 	pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
 	pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
@@ -1946,6 +2036,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	pl08x->slave.device_tx_status = pl08x_dma_tx_status;
 	pl08x->slave.device_issue_pending = pl08x_issue_pending;
 	pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
+	pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
 	pl08x->slave.device_control = pl08x_control;
 
 	/* Get the platform data */
-- 
1.8.2.1

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Tomasz Figa]

From: Alban Bedel <alban.bedel@avionic-design.de>

Many audio interface drivers require support of cyclic transfers to work
correctly, for example Samsung ASoC DMA driver. This patch adds support
for cyclic transfers to the amba-pl08x driver.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/dma/amba-pl08x.c | 181 +++++++++++++++++++++++++++++++++++------------
 1 file changed, 136 insertions(+), 45 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index bb3b36b..210a893 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -184,6 +184,7 @@ struct pl08x_sg {
  * @ccfg: config reg values for current txd
  * @done: this marks completed descriptors, which should not have their
  *   mux released.
+ * @cyclic: indicate cyclic transfers
  */
 struct pl08x_txd {
 	struct virt_dma_desc vd;
@@ -198,6 +199,8 @@ struct pl08x_txd {
 	 */
 	u32 ccfg;
 	bool done;
+
+	bool cyclic;
 };
 
 /**
@@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 			bytes += get_bytes_in_cctl(llis_va[index].cctl);
 
 		/*
-		 * A LLI pointer of 0 terminates the LLI list
++		 * A LLI pointer going backward terminates the LLI list
 		 */
-		if (!llis_va[index].lli)
+		if (llis_va[index].lli <= clli)
 			break;
 	}
 
@@ -1075,10 +1078,14 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
 	}
 
 	llis_va = txd->llis_va;
-	/* The final LLI terminates the LLI. */
-	llis_va[num_llis - 1].lli = 0;
-	/* The final LLI element shall also fire an interrupt. */
-	llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	if (txd->cyclic) {
+		/* Link back to the first LLI. */
+		llis_va[num_llis - 1].lli = txd->llis_bus | bd.lli_bus;
+	} else {
+		/* The final LLI terminates the LLI. */
+		llis_va[num_llis - 1].lli = 0;
+		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	}
 
 #ifdef VERBOSE_DEBUG
 	{
@@ -1470,25 +1477,19 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
 	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
 }
 
-static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
-		struct dma_chan *chan, struct scatterlist *sgl,
-		unsigned int sg_len, enum dma_transfer_direction direction,
-		unsigned long flags, void *context)
+static struct pl08x_txd *pl08x_init_txd(
+		struct dma_chan *chan,
+		enum dma_transfer_direction direction,
+		dma_addr_t *slave_addr)
 {
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
 	struct pl08x_driver_data *pl08x = plchan->host;
 	struct pl08x_txd *txd;
-	struct pl08x_sg *dsg;
-	struct scatterlist *sg;
 	enum dma_slave_buswidth addr_width;
-	dma_addr_t slave_addr;
 	int ret, tmp;
 	u8 src_buses, dst_buses;
 	u32 maxburst, cctl;
 
-	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
-			__func__, sg_dma_len(sgl), plchan->name);
-
 	txd = pl08x_get_txd(plchan);
 	if (!txd) {
 		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
@@ -1502,14 +1503,14 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	 */
 	if (direction == DMA_MEM_TO_DEV) {
 		cctl = PL080_CONTROL_SRC_INCR;
-		slave_addr = plchan->cfg.dst_addr;
+		*slave_addr = plchan->cfg.dst_addr;
 		addr_width = plchan->cfg.dst_addr_width;
 		maxburst = plchan->cfg.dst_maxburst;
 		src_buses = pl08x->mem_buses;
 		dst_buses = plchan->cd->periph_buses;
 	} else if (direction == DMA_DEV_TO_MEM) {
 		cctl = PL080_CONTROL_DST_INCR;
-		slave_addr = plchan->cfg.src_addr;
+		*slave_addr = plchan->cfg.src_addr;
 		addr_width = plchan->cfg.src_addr_width;
 		maxburst = plchan->cfg.src_maxburst;
 		src_buses = plchan->cd->periph_buses;
@@ -1558,24 +1559,107 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
 	else
 		txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
 
+	return txd;
+}
+
+static int pl08x_tx_add_sg(struct pl08x_txd *txd,
+			   enum dma_transfer_direction direction,
+			   dma_addr_t slave_addr,
+			   dma_addr_t buf_addr,
+			   unsigned int len)
+{
+	struct pl08x_sg *dsg;
+
+	dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
+	if (!dsg)
+		return -ENOMEM;
+
+	list_add_tail(&dsg->node, &txd->dsg_list);
+
+	dsg->len = len;
+	if (direction == DMA_MEM_TO_DEV) {
+		dsg->src_addr = buf_addr;
+		dsg->dst_addr = slave_addr;
+	} else {
+		dsg->src_addr = slave_addr;
+		dsg->dst_addr = buf_addr;
+	}
+
+	return 0;
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	struct scatterlist *sg;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
+			__func__, sg_dma_len(sgl), plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
 	for_each_sg(sgl, sg, sg_len, tmp) {
-		dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
-		if (!dsg) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      sg_dma_address(sg),
+				      sg_dma_len(sg));
+		if (ret) {
 			pl08x_release_mux(plchan);
 			pl08x_free_txd(pl08x, txd);
 			dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
 					__func__);
 			return NULL;
 		}
-		list_add_tail(&dsg->node, &txd->dsg_list);
+	}
 
-		dsg->len = sg_dma_len(sg);
-		if (direction == DMA_MEM_TO_DEV) {
-			dsg->src_addr = sg_dma_address(sg);
-			dsg->dst_addr = slave_addr;
-		} else {
-			dsg->src_addr = slave_addr;
-			dsg->dst_addr = sg_dma_address(sg);
+	ret = pl08x_fill_llis_for_desc(plchan->host, txd);
+	if (!ret) {
+		pl08x_release_mux(plchan);
+		pl08x_free_txd(pl08x, txd);
+		return NULL;
+	}
+
+	return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
+		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
+		size_t period_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+	int ret, tmp;
+	dma_addr_t slave_addr;
+
+	dev_dbg(&pl08x->adev->dev,
+		"%s prepare cyclic transaction of %d/%d bytes %s %s\n",
+		__func__, period_len, buf_len,
+		direction == DMA_MEM_TO_DEV ? "to" : "from",
+		plchan->name);
+
+	txd = pl08x_init_txd(chan, direction, &slave_addr);
+	if (!txd)
+		return NULL;
+
+	txd->cyclic = true;
+	txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
+	for (tmp = 0 ; tmp < buf_len ; tmp += period_len) {
+		ret = pl08x_tx_add_sg(txd, direction, slave_addr,
+				      buf_addr + tmp, period_len);
+		if (ret) {
+			pl08x_release_mux(plchan);
+			pl08x_free_txd(pl08x, txd);
+			return NULL;
 		}
 	}
 
@@ -1719,23 +1803,28 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
 			spin_lock(&plchan->vc.lock);
 			tx = plchan->at;
 			if (tx) {
-				plchan->at = NULL;
-				/*
-				 * This descriptor is done, release its mux
-				 * reservation.
-				 */
-				pl08x_release_mux(plchan);
-				tx->done = true;
-				vchan_cookie_complete(&tx->vd);
-
-				/*
-				 * And start the next descriptor (if any),
-				 * otherwise free this channel.
-				 */
-				if (vchan_next_desc(&plchan->vc))
-					pl08x_start_next_txd(plchan);
-				else
-					pl08x_phy_free(plchan);
+				if (tx->cyclic) {
+					vchan_cyclic_callback(&tx->vd);
+				} else {
+					plchan->at = NULL;
+					/*
+					 * This descriptor is done, release
+					 * its mux reservation.
+					 */
+					pl08x_release_mux(plchan);
+					tx->done = true;
+					vchan_cookie_complete(&tx->vd);
+
+					/*
+					 * And start the next descriptor
+					 * (if any), otherwise free this
+					 * channel.
+					 */
+					if (vchan_next_desc(&plchan->vc))
+						pl08x_start_next_txd(plchan);
+					else
+						pl08x_phy_free(plchan);
+				}
 			}
 			spin_unlock(&plchan->vc.lock);
 
@@ -1939,6 +2028,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 
 	/* Initialize slave engine */
 	dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
+	dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
 	pl08x->slave.dev = &adev->dev;
 	pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
 	pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
@@ -1946,6 +2036,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
 	pl08x->slave.device_tx_status = pl08x_dma_tx_status;
 	pl08x->slave.device_issue_pending = pl08x_issue_pending;
 	pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
+	pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
 	pl08x->slave.device_control = pl08x_control;
 
 	/* Get the platform data */
-- 
1.8.2.1

[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2015897..8da1c22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_S3C24XX_FIQ
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
 	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
 
-- 
1.8.2.1

[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2015897..8da1c22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_S3C24XX_FIQ
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
 	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
 
-- 
1.8.2.1

[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2015897..8da1c22 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_S3C24XX_FIQ
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
 	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
 
-- 
1.8.2.1

[RFC PATCH 10/11] ASoC: samsung: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 sound/soc/samsung/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index ae0ea87..dbced1e 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,7 +1,7 @@
 config SND_SOC_SAMSUNG
 	tristate "ASoC support for Samsung"
 	depends on PLAT_SAMSUNG
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	select S3C2410_DMA if ARCH_S3C24XX
 	help
 	  Say Y or M if you want to add support for codecs attached to
-- 
1.8.2.1

[RFC PATCH 10/11] ASoC: samsung: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 sound/soc/samsung/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index ae0ea87..dbced1e 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,7 +1,7 @@
 config SND_SOC_SAMSUNG
 	tristate "ASoC support for Samsung"
 	depends on PLAT_SAMSUNG
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	select S3C2410_DMA if ARCH_S3C24XX
 	help
 	  Say Y or M if you want to add support for codecs attached to
-- 
1.8.2.1

[RFC PATCH 10/11] ASoC: samsung: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
can be used instead of the private s3c-dma interface.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 sound/soc/samsung/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
index ae0ea87..dbced1e 100644
--- a/sound/soc/samsung/Kconfig
+++ b/sound/soc/samsung/Kconfig
@@ -1,7 +1,7 @@
 config SND_SOC_SAMSUNG
 	tristate "ASoC support for Samsung"
 	depends on PLAT_SAMSUNG
-	select S3C64XX_DMA if ARCH_S3C64XX
+	select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
 	select S3C2410_DMA if ARCH_S3C24XX
 	help
 	  Say Y or M if you want to add support for codecs attached to
-- 
1.8.2.1

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Tomasz Figa]

This patch adds all required platform-specific data and initialization
code to support the generic amba-pl08x driver on S3C64xx SoCs.

Also some compatibility definitions are added to make the transition from
legacy API to DMA engine easier. The biggest hack here is passing const
char * pointers through DMA resource, casted to unsigned long, but this
is how Samsung DMA wrappers (used to support both s3c-dma and DMA engine
in drivers) is designed.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 ++++++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++++++++++++++
 6 files changed, 323 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42d6ea2..fab8f3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,7 @@ config ARCH_S3C64XX
 	bool "Samsung S3C64XX"
 	select ARCH_HAS_CPUFREQ
 	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
 	select ARM_VIC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2057853..704c5e4 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -28,9 +28,15 @@ config CPU_S3C6410
 	help
 	  Enable S3C6410 CPU support
 
+config S3C64XX_PL080
+	bool "S3C64XX DMA using generic PL08x driver"
+	select AMBA_PL08X
+	select SAMSUNG_DMADEV
+
 config S3C64XX_DMA
-	bool "S3C64XX DMA"
+	bool "S3C64XX DMA using legacy S3C DMA API"
 	select S3C_DMA
+	depends on !S3C64XX_PL080
 
 config S3C64XX_SETUP_SDHCI
 	bool
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c91..4e3326a 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 # DMA support
 
 obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
+obj-$(CONFIG_S3C64XX_PL080)	+= pl080.o
 
 # Device support
 
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..60a667a 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void);
 static inline int s3c64xx_pm_late_initcall(void) { return 0; }
 #endif
 
+#ifdef CONFIG_S3C64XX_PL080
+extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
+extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98c..6f88965 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
+#ifdef CONFIG_S3C64XX_DMA
+
 #define S3C_DMA_CHANNELS	(16)
 
 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
@@ -128,4 +130,67 @@ struct s3c2410_dma_chan {
 
 #include <plat/dma-core.h>
 
+#else
+
+#define S3C64XX_DMA_CHAN(name)		((unsigned long)(name))
+
+/* DMA0/SDMA0 */
+#define DMACH_UART0		S3C64XX_DMA_CHAN("uart0_tx")
+#define DMACH_UART0_SRC2	S3C64XX_DMA_CHAN("uart0_rx")
+#define DMACH_UART1		S3C64XX_DMA_CHAN("uart1_tx")
+#define DMACH_UART1_SRC2	S3C64XX_DMA_CHAN("uart1_rx")
+#define DMACH_UART2		S3C64XX_DMA_CHAN("uart2_tx")
+#define DMACH_UART2_SRC2	S3C64XX_DMA_CHAN("uart2_rx")
+#define DMACH_UART3		S3C64XX_DMA_CHAN("uart3_tx")
+#define DMACH_UART3_SRC2	S3C64XX_DMA_CHAN("uart3_rx")
+#define DMACH_PCM0_TX		S3C64XX_DMA_CHAN("pcm0_tx")
+#define DMACH_PCM0_RX		S3C64XX_DMA_CHAN("pcm0_rx")
+#define DMACH_I2S0_OUT		S3C64XX_DMA_CHAN("i2s0_tx")
+#define DMACH_I2S0_IN		S3C64XX_DMA_CHAN("i2s0_rx")
+#define DMACH_SPI0_TX		S3C64XX_DMA_CHAN("spi0_tx")
+#define DMACH_SPI0_RX		S3C64XX_DMA_CHAN("spi0_rx")
+#define DMACH_HSI_I2SV40_TX	S3C64XX_DMA_CHAN("i2s2_tx")
+#define DMACH_HSI_I2SV40_RX	S3C64XX_DMA_CHAN("i2s2_rx")
+
+/* DMA1/SDMA1 */
+#define DMACH_PCM1_TX		S3C64XX_DMA_CHAN("pcm1_tx")
+#define DMACH_PCM1_RX		S3C64XX_DMA_CHAN("pcm1_rx")
+#define DMACH_I2S1_OUT		S3C64XX_DMA_CHAN("i2s1_tx")
+#define DMACH_I2S1_IN		S3C64XX_DMA_CHAN("i2s1_rx")
+#define DMACH_SPI1_TX		S3C64XX_DMA_CHAN("spi1_tx")
+#define DMACH_SPI1_RX		S3C64XX_DMA_CHAN("spi1_rx")
+#define DMACH_AC97_PCMOUT	S3C64XX_DMA_CHAN("ac97_out")
+#define DMACH_AC97_PCMIN	S3C64XX_DMA_CHAN("ac97_in")
+#define DMACH_AC97_MICIN	S3C64XX_DMA_CHAN("ac97_mic")
+#define DMACH_PWM		S3C64XX_DMA_CHAN("pwm")
+#define DMACH_IRDA		S3C64XX_DMA_CHAN("irda")
+#define DMACH_EXTERNAL		S3C64XX_DMA_CHAN("external")
+#define DMACH_SECURITY_RX	S3C64XX_DMA_CHAN("sec_rx")
+#define DMACH_SECURITY_TX	S3C64XX_DMA_CHAN("sec_tx")
+
+enum dma_ch {
+	DMACH_MAX = 32
+};
+
+struct s3c2410_dma_client {
+	char	*name;
+};
+
+static inline bool samsung_dma_has_circular(void)
+{
+	return true;
+}
+
+static inline bool samsung_dma_is_dmadev(void)
+{
+	return true;
+}
+
+#define pl330_filter pl08x_filter_id
+
+#include <linux/amba/pl08x.h>
+#include <plat/dma-ops.h>
+
+#endif
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c
new file mode 100644
index 0000000..734b79f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/pl080.c
@@ -0,0 +1,244 @@
+/*
+ * Samsung's S3C64XX generic DMA support using amba-pl08x driver.
+ *
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl080.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include "regs-sys.h"
+
+static int pl08x_get_signal(const struct pl08x_channel_data *cd)
+{
+	return cd->min_signal;
+}
+
+static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
+{
+}
+
+/*
+ * DMA0
+ */
+
+static struct pl08x_channel_data s3c64xx_dma0_info[] = {
+	{
+		.bus_id = "uart0_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_tx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_rx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_tx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_rx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_tx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_rx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_tx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_rx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_tx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_rx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.periph_buses = PL08X_AHB2,
+	}
+};
+
+struct pl08x_platform_data s3c64xx_dma0_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma0_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
+			0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
+
+/*
+ * DMA1
+ */
+
+static struct pl08x_channel_data s3c64xx_dma1_info[] = {
+	{
+		.bus_id = "pcm1_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm1_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_out",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_in",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_mic",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pwm",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "external",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data s3c64xx_dma1_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma1_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
+			0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
+
+static int __init s3c64xx_pl080_init(void)
+{
+	/* Set all DMA configuration to be DMA, not SDMA */
+	writel(0xffffff, S3C64XX_SDMA_SEL);
+
+	if (of_have_populated_dt())
+		return 0;
+
+	amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
+	amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
+
+	return 0;
+}
+arch_initcall(s3c64xx_pl080_init);
-- 
1.8.2.1

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Tomasz Figa]

This patch adds all required platform-specific data and initialization
code to support the generic amba-pl08x driver on S3C64xx SoCs.

Also some compatibility definitions are added to make the transition from
legacy API to DMA engine easier. The biggest hack here is passing const
char * pointers through DMA resource, casted to unsigned long, but this
is how Samsung DMA wrappers (used to support both s3c-dma and DMA engine
in drivers) is designed.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 ++++++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++++++++++++++
 6 files changed, 323 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42d6ea2..fab8f3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,7 @@ config ARCH_S3C64XX
 	bool "Samsung S3C64XX"
 	select ARCH_HAS_CPUFREQ
 	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
 	select ARM_VIC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2057853..704c5e4 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -28,9 +28,15 @@ config CPU_S3C6410
 	help
 	  Enable S3C6410 CPU support
 
+config S3C64XX_PL080
+	bool "S3C64XX DMA using generic PL08x driver"
+	select AMBA_PL08X
+	select SAMSUNG_DMADEV
+
 config S3C64XX_DMA
-	bool "S3C64XX DMA"
+	bool "S3C64XX DMA using legacy S3C DMA API"
 	select S3C_DMA
+	depends on !S3C64XX_PL080
 
 config S3C64XX_SETUP_SDHCI
 	bool
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c91..4e3326a 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 # DMA support
 
 obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
+obj-$(CONFIG_S3C64XX_PL080)	+= pl080.o
 
 # Device support
 
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..60a667a 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void);
 static inline int s3c64xx_pm_late_initcall(void) { return 0; }
 #endif
 
+#ifdef CONFIG_S3C64XX_PL080
+extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
+extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98c..6f88965 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
+#ifdef CONFIG_S3C64XX_DMA
+
 #define S3C_DMA_CHANNELS	(16)
 
 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
@@ -128,4 +130,67 @@ struct s3c2410_dma_chan {
 
 #include <plat/dma-core.h>
 
+#else
+
+#define S3C64XX_DMA_CHAN(name)		((unsigned long)(name))
+
+/* DMA0/SDMA0 */
+#define DMACH_UART0		S3C64XX_DMA_CHAN("uart0_tx")
+#define DMACH_UART0_SRC2	S3C64XX_DMA_CHAN("uart0_rx")
+#define DMACH_UART1		S3C64XX_DMA_CHAN("uart1_tx")
+#define DMACH_UART1_SRC2	S3C64XX_DMA_CHAN("uart1_rx")
+#define DMACH_UART2		S3C64XX_DMA_CHAN("uart2_tx")
+#define DMACH_UART2_SRC2	S3C64XX_DMA_CHAN("uart2_rx")
+#define DMACH_UART3		S3C64XX_DMA_CHAN("uart3_tx")
+#define DMACH_UART3_SRC2	S3C64XX_DMA_CHAN("uart3_rx")
+#define DMACH_PCM0_TX		S3C64XX_DMA_CHAN("pcm0_tx")
+#define DMACH_PCM0_RX		S3C64XX_DMA_CHAN("pcm0_rx")
+#define DMACH_I2S0_OUT		S3C64XX_DMA_CHAN("i2s0_tx")
+#define DMACH_I2S0_IN		S3C64XX_DMA_CHAN("i2s0_rx")
+#define DMACH_SPI0_TX		S3C64XX_DMA_CHAN("spi0_tx")
+#define DMACH_SPI0_RX		S3C64XX_DMA_CHAN("spi0_rx")
+#define DMACH_HSI_I2SV40_TX	S3C64XX_DMA_CHAN("i2s2_tx")
+#define DMACH_HSI_I2SV40_RX	S3C64XX_DMA_CHAN("i2s2_rx")
+
+/* DMA1/SDMA1 */
+#define DMACH_PCM1_TX		S3C64XX_DMA_CHAN("pcm1_tx")
+#define DMACH_PCM1_RX		S3C64XX_DMA_CHAN("pcm1_rx")
+#define DMACH_I2S1_OUT		S3C64XX_DMA_CHAN("i2s1_tx")
+#define DMACH_I2S1_IN		S3C64XX_DMA_CHAN("i2s1_rx")
+#define DMACH_SPI1_TX		S3C64XX_DMA_CHAN("spi1_tx")
+#define DMACH_SPI1_RX		S3C64XX_DMA_CHAN("spi1_rx")
+#define DMACH_AC97_PCMOUT	S3C64XX_DMA_CHAN("ac97_out")
+#define DMACH_AC97_PCMIN	S3C64XX_DMA_CHAN("ac97_in")
+#define DMACH_AC97_MICIN	S3C64XX_DMA_CHAN("ac97_mic")
+#define DMACH_PWM		S3C64XX_DMA_CHAN("pwm")
+#define DMACH_IRDA		S3C64XX_DMA_CHAN("irda")
+#define DMACH_EXTERNAL		S3C64XX_DMA_CHAN("external")
+#define DMACH_SECURITY_RX	S3C64XX_DMA_CHAN("sec_rx")
+#define DMACH_SECURITY_TX	S3C64XX_DMA_CHAN("sec_tx")
+
+enum dma_ch {
+	DMACH_MAX = 32
+};
+
+struct s3c2410_dma_client {
+	char	*name;
+};
+
+static inline bool samsung_dma_has_circular(void)
+{
+	return true;
+}
+
+static inline bool samsung_dma_is_dmadev(void)
+{
+	return true;
+}
+
+#define pl330_filter pl08x_filter_id
+
+#include <linux/amba/pl08x.h>
+#include <plat/dma-ops.h>
+
+#endif
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c
new file mode 100644
index 0000000..734b79f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/pl080.c
@@ -0,0 +1,244 @@
+/*
+ * Samsung's S3C64XX generic DMA support using amba-pl08x driver.
+ *
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl080.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include "regs-sys.h"
+
+static int pl08x_get_signal(const struct pl08x_channel_data *cd)
+{
+	return cd->min_signal;
+}
+
+static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
+{
+}
+
+/*
+ * DMA0
+ */
+
+static struct pl08x_channel_data s3c64xx_dma0_info[] = {
+	{
+		.bus_id = "uart0_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_tx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_rx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_tx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_rx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_tx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_rx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_tx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_rx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_tx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_rx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.periph_buses = PL08X_AHB2,
+	}
+};
+
+struct pl08x_platform_data s3c64xx_dma0_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma0_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
+			0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
+
+/*
+ * DMA1
+ */
+
+static struct pl08x_channel_data s3c64xx_dma1_info[] = {
+	{
+		.bus_id = "pcm1_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm1_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_out",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_in",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_mic",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pwm",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "external",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data s3c64xx_dma1_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma1_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
+			0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
+
+static int __init s3c64xx_pl080_init(void)
+{
+	/* Set all DMA configuration to be DMA, not SDMA */
+	writel(0xffffff, S3C64XX_SDMA_SEL);
+
+	if (of_have_populated_dt())
+		return 0;
+
+	amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
+	amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
+
+	return 0;
+}
+arch_initcall(s3c64xx_pl080_init);
-- 
1.8.2.1

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Tomasz Figa]

This patch adds all required platform-specific data and initialization
code to support the generic amba-pl08x driver on S3C64xx SoCs.

Also some compatibility definitions are added to make the transition from
legacy API to DMA engine easier. The biggest hack here is passing const
char * pointers through DMA resource, casted to unsigned long, but this
is how Samsung DMA wrappers (used to support both s3c-dma and DMA engine
in drivers) is designed.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
 arch/arm/Kconfig                         |   1 +
 arch/arm/mach-s3c64xx/Kconfig            |   8 +-
 arch/arm/mach-s3c64xx/Makefile           |   1 +
 arch/arm/mach-s3c64xx/common.h           |   5 +
 arch/arm/mach-s3c64xx/include/mach/dma.h |  65 ++++++++
 arch/arm/mach-s3c64xx/pl080.c            | 244 +++++++++++++++++++++++++++++++
 6 files changed, 323 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-s3c64xx/pl080.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42d6ea2..fab8f3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,7 @@ config ARCH_S3C64XX
 	bool "Samsung S3C64XX"
 	select ARCH_HAS_CPUFREQ
 	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
 	select ARM_VIC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 2057853..704c5e4 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -28,9 +28,15 @@ config CPU_S3C6410
 	help
 	  Enable S3C6410 CPU support
 
+config S3C64XX_PL080
+	bool "S3C64XX DMA using generic PL08x driver"
+	select AMBA_PL08X
+	select SAMSUNG_DMADEV
+
 config S3C64XX_DMA
-	bool "S3C64XX DMA"
+	bool "S3C64XX DMA using legacy S3C DMA API"
 	select S3C_DMA
+	depends on !S3C64XX_PL080
 
 config S3C64XX_SETUP_SDHCI
 	bool
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c91..4e3326a 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 # DMA support
 
 obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
+obj-$(CONFIG_S3C64XX_PL080)	+= pl080.o
 
 # Device support
 
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 6cfc99b..60a667a 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void);
 static inline int s3c64xx_pm_late_initcall(void) { return 0; }
 #endif
 
+#ifdef CONFIG_S3C64XX_PL080
+extern struct pl08x_platform_data s3c64xx_dma0_plat_data;
+extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
+#endif
+
 #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98c..6f88965 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -11,6 +11,8 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
+#ifdef CONFIG_S3C64XX_DMA
+
 #define S3C_DMA_CHANNELS	(16)
 
 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
@@ -128,4 +130,67 @@ struct s3c2410_dma_chan {
 
 #include <plat/dma-core.h>
 
+#else
+
+#define S3C64XX_DMA_CHAN(name)		((unsigned long)(name))
+
+/* DMA0/SDMA0 */
+#define DMACH_UART0		S3C64XX_DMA_CHAN("uart0_tx")
+#define DMACH_UART0_SRC2	S3C64XX_DMA_CHAN("uart0_rx")
+#define DMACH_UART1		S3C64XX_DMA_CHAN("uart1_tx")
+#define DMACH_UART1_SRC2	S3C64XX_DMA_CHAN("uart1_rx")
+#define DMACH_UART2		S3C64XX_DMA_CHAN("uart2_tx")
+#define DMACH_UART2_SRC2	S3C64XX_DMA_CHAN("uart2_rx")
+#define DMACH_UART3		S3C64XX_DMA_CHAN("uart3_tx")
+#define DMACH_UART3_SRC2	S3C64XX_DMA_CHAN("uart3_rx")
+#define DMACH_PCM0_TX		S3C64XX_DMA_CHAN("pcm0_tx")
+#define DMACH_PCM0_RX		S3C64XX_DMA_CHAN("pcm0_rx")
+#define DMACH_I2S0_OUT		S3C64XX_DMA_CHAN("i2s0_tx")
+#define DMACH_I2S0_IN		S3C64XX_DMA_CHAN("i2s0_rx")
+#define DMACH_SPI0_TX		S3C64XX_DMA_CHAN("spi0_tx")
+#define DMACH_SPI0_RX		S3C64XX_DMA_CHAN("spi0_rx")
+#define DMACH_HSI_I2SV40_TX	S3C64XX_DMA_CHAN("i2s2_tx")
+#define DMACH_HSI_I2SV40_RX	S3C64XX_DMA_CHAN("i2s2_rx")
+
+/* DMA1/SDMA1 */
+#define DMACH_PCM1_TX		S3C64XX_DMA_CHAN("pcm1_tx")
+#define DMACH_PCM1_RX		S3C64XX_DMA_CHAN("pcm1_rx")
+#define DMACH_I2S1_OUT		S3C64XX_DMA_CHAN("i2s1_tx")
+#define DMACH_I2S1_IN		S3C64XX_DMA_CHAN("i2s1_rx")
+#define DMACH_SPI1_TX		S3C64XX_DMA_CHAN("spi1_tx")
+#define DMACH_SPI1_RX		S3C64XX_DMA_CHAN("spi1_rx")
+#define DMACH_AC97_PCMOUT	S3C64XX_DMA_CHAN("ac97_out")
+#define DMACH_AC97_PCMIN	S3C64XX_DMA_CHAN("ac97_in")
+#define DMACH_AC97_MICIN	S3C64XX_DMA_CHAN("ac97_mic")
+#define DMACH_PWM		S3C64XX_DMA_CHAN("pwm")
+#define DMACH_IRDA		S3C64XX_DMA_CHAN("irda")
+#define DMACH_EXTERNAL		S3C64XX_DMA_CHAN("external")
+#define DMACH_SECURITY_RX	S3C64XX_DMA_CHAN("sec_rx")
+#define DMACH_SECURITY_TX	S3C64XX_DMA_CHAN("sec_tx")
+
+enum dma_ch {
+	DMACH_MAX = 32
+};
+
+struct s3c2410_dma_client {
+	char	*name;
+};
+
+static inline bool samsung_dma_has_circular(void)
+{
+	return true;
+}
+
+static inline bool samsung_dma_is_dmadev(void)
+{
+	return true;
+}
+
+#define pl330_filter pl08x_filter_id
+
+#include <linux/amba/pl08x.h>
+#include <plat/dma-ops.h>
+
+#endif
+
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c
new file mode 100644
index 0000000..734b79f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/pl080.c
@@ -0,0 +1,244 @@
+/*
+ * Samsung's S3C64XX generic DMA support using amba-pl08x driver.
+ *
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl080.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include "regs-sys.h"
+
+static int pl08x_get_signal(const struct pl08x_channel_data *cd)
+{
+	return cd->min_signal;
+}
+
+static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
+{
+}
+
+/*
+ * DMA0
+ */
+
+static struct pl08x_channel_data s3c64xx_dma0_info[] = {
+	{
+		.bus_id = "uart0_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_tx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart3_rx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_tx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm0_rx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_tx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s0_rx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_tx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi0_rx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_tx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s2_rx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.periph_buses = PL08X_AHB2,
+	}
+};
+
+struct pl08x_platform_data s3c64xx_dma0_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma0_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
+			0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
+
+/*
+ * DMA1
+ */
+
+static struct pl08x_channel_data s3c64xx_dma1_info[] = {
+	{
+		.bus_id = "pcm1_tx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pcm1_rx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_tx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s1_rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "spi1_rx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_out",
+		.min_signal = 6,
+		.max_signal = 6,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_in",
+		.min_signal = 7,
+		.max_signal = 7,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ac97_mic",
+		.min_signal = 8,
+		.max_signal = 8,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "pwm",
+		.min_signal = 9,
+		.max_signal = 9,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 10,
+		.max_signal = 10,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "external",
+		.min_signal = 11,
+		.max_signal = 11,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data s3c64xx_dma1_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl_memcpy =
+			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl08x_get_signal,
+	.put_signal = pl08x_put_signal,
+	.slave_channels = s3c64xx_dma1_info,
+	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
+};
+
+static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
+			0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
+
+static int __init s3c64xx_pl080_init(void)
+{
+	/* Set all DMA configuration to be DMA, not SDMA */
+	writel(0xffffff, S3C64XX_SDMA_SEL);
+
+	if (of_have_populated_dt())
+		return 0;
+
+	amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
+	amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
+
+	return 0;
+}
+arch_initcall(s3c64xx_pl080_init);
-- 
1.8.2.1

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Instead of defining new bool field in vendor_data struct for each quirk,
> it is more reasonable to use a single flags field and make each quirk
> use single bits.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Not that I see the point, but I have no strong preference so:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Instead of defining new bool field in vendor_data struct for each quirk,
> it is more reasonable to use a single flags field and make each quirk
> use single bits.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Not that I see the point, but I have no strong preference so:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [RFC PATCH 02/11] dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Further patch will introduce support for PL080S, which requires some
> things to be done conditionally, thus increasing indentation level of
> some functions even more.
>
> This patch reduces indentation level of pl08x_getbytes_chan() function
> by inverting several conditions and returning from function wherever
> possible.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Nice refactoring and a patch that should be applied immediately
no matter what happens with the rest.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

PS:

> +       if (!ch || !txd)
> +               return bytes;

Just return 0; is even clearer in this case but who cares.

Yours,
Linus Walleij

[RFC PATCH 02/11] dma: amba-pl08x: Refactor pl08x_getbytes_chan() to lower indentation

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Further patch will introduce support for PL080S, which requires some
> things to be done conditionally, thus increasing indentation level of
> some functions even more.
>
> This patch reduces indentation level of pl08x_getbytes_chan() function
> by inverting several conditions and returning from function wherever
> possible.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Nice refactoring and a patch that should be applied immediately
no matter what happens with the rest.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

PS:

> +       if (!ch || !txd)
> +               return bytes;

Just return 0; is even clearer in this case but who cares.

Yours,
Linus Walleij

Re: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> have CONFIG register at different offset. This patch makes the driver
> use offset from vendor data struct.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Looks good to me:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> have CONFIG register at different offset. This patch makes the driver
> use offset from vendor data struct.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Looks good to me:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080S is a modified version of PL080 that can be found on Samsung SoCs,
> such as S3C6400 and S3C6410.
>
> It has different offset of CONFIG register, separate CONTROL1 register
> that holds transfer size and larger maximum transfer size.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

(I would have done some smallish things differently but it
is only a matter of taste.)

>  static struct amba_id pl08x_ids[] = {
> +       /* Samsung PL080S variant */
> +       {
> +               .id     = 0x0a141080,
> +               .mask   = 0xffffffff,
> +               .data   = &vendor_pl080s,
> +       },

Interesting that Samsung claim to be vendor 0x41
(ARM). Well ARM never made revision no 0x0a so
this works.

Yours,
Linus Walleij

[RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080S is a modified version of PL080 that can be found on Samsung SoCs,
> such as S3C6400 and S3C6410.
>
> It has different offset of CONFIG register, separate CONTROL1 register
> that holds transfer size and larger maximum transfer size.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

(I would have done some smallish things differently but it
is only a matter of taste.)

>  static struct amba_id pl08x_ids[] = {
> +       /* Samsung PL080S variant */
> +       {
> +               .id     = 0x0a141080,
> +               .mask   = 0xffffffff,
> +               .data   = &vendor_pl080s,
> +       },

Interesting that Samsung claim to be vendor 0x41
(ARM). Well ARM never made revision no 0x0a so
this works.

Yours,
Linus Walleij

Re: [RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080S has separate register to store transfer size in, allowing single
> transfer to be much larger than in standard PL080.
>
> This patch makes the amba-pl08x driver aware of this and removes writing
> transfer size to reserved bits of CH_CONTROL register on PL080S, which
> was not a problem witn transfer sizes fitting the original bitfield
> of PL080, but now would overwrite other fields.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Very straight-forward.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080S has separate register to store transfer size in, allowing single
> transfer to be much larger than in standard PL080.
>
> This patch makes the amba-pl08x driver aware of this and removes writing
> transfer size to reserved bits of CH_CONTROL register on PL080S, which
> was not a problem witn transfer sizes fitting the original bitfield
> of PL080, but now would overwrite other fields.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Very straight-forward.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080 reference manual states that to LLI entries should be aligned
> to 4-word boundary to make LLI fetches more efficient. This patch adds
> a 3-word padding to the LLi struct to make this condition true.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> ---
>  drivers/dma/amba-pl08x.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index eb10eb8..0da5539 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -127,6 +127,7 @@ struct pl08x_lli {
>         u32 lli;
>         u32 cctl;
>         u32 cctl1;
> +       u32 dummy[3];

Atleast put a comment into the code explaining what this is all
about. Or someone will add another member to the struct and
all is lost. Call it "padding" rather than dummy.

>  };

So it used to be like this before you added cctl1:

struct pl08x_lli {
        u32 src;
        u32 dst;
        u32 lli;
        u32 cctl;
};

Meaning it was 3 words.

And now you make it take 8 words for everyone.

Atleast this patch should be squashed into the patch
adding cctl1.

But I really don't like this fragile way of casting structs right
into memory, and I don't like that teh other PL080's also have
to waste 8 words when their LLIs fit so nicely into 4.

I would have solved this problem by creating a
marshalling function that just allocate the number of bytes the
LLI entry shall have and fill it in by assigning directly to the
precise target memory cell. This way the LLIs will take
4 words on the original variants and you can use some
nice logic to pad out to 8 words on the PL080S variant.

Yours,
Linus Walleij

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> PL080 reference manual states that to LLI entries should be aligned
> to 4-word boundary to make LLI fetches more efficient. This patch adds
> a 3-word padding to the LLi struct to make this condition true.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> ---
>  drivers/dma/amba-pl08x.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index eb10eb8..0da5539 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -127,6 +127,7 @@ struct pl08x_lli {
>         u32 lli;
>         u32 cctl;
>         u32 cctl1;
> +       u32 dummy[3];

Atleast put a comment into the code explaining what this is all
about. Or someone will add another member to the struct and
all is lost. Call it "padding" rather than dummy.

>  };

So it used to be like this before you added cctl1:

struct pl08x_lli {
        u32 src;
        u32 dst;
        u32 lli;
        u32 cctl;
};

Meaning it was 3 words.

And now you make it take 8 words for everyone.

Atleast this patch should be squashed into the patch
adding cctl1.

But I really don't like this fragile way of casting structs right
into memory, and I don't like that teh other PL080's also have
to waste 8 words when their LLIs fit so nicely into 4.

I would have solved this problem by creating a
marshalling function that just allocate the number of bytes the
LLI entry shall have and fill it in by assigning directly to the
precise target memory cell. This way the LLIs will take
4 words on the original variants and you can use some
nice logic to pad out to 8 words on the PL080S variant.

Yours,
Linus Walleij

Re: [RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> From: Alban Bedel <alban.bedel@avionic-design.de>
>
> There are more fields than just SWIDTH in CH_CONTROL register, so read
> register value must be masked in addition to shifting.
>
> Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Are we just lucky on current variants such that all unmasked bits
happen to be zero on them?

Yours,
Linus Walleij

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> From: Alban Bedel <alban.bedel@avionic-design.de>
>
> There are more fields than just SWIDTH in CH_CONTROL register, so read
> register value must be masked in addition to shifting.
>
> Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Are we just lucky on current variants such that all unmasked bits
happen to be zero on them?

Yours,
Linus Walleij

Re: [RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> From: Alban Bedel <alban.bedel@avionic-design.de>
>
> Many audio interface drivers require support of cyclic transfers to work
> correctly, for example Samsung ASoC DMA driver. This patch adds support
> for cyclic transfers to the amba-pl08x driver.
>
> Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Nice! This is useful for others as well.

> @@ -198,6 +199,8 @@ struct pl08x_txd {
>          */
>         u32 ccfg;
>         bool done;
> +
> +       bool cyclic;
>  };

You can never have enough whitespace right?

>  /**
> @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
>                         bytes += get_bytes_in_cctl(llis_va[index].cctl);
>
>                 /*
> -                * A LLI pointer of 0 terminates the LLI list
> ++               * A LLI pointer going backward terminates the LLI list

++? Really?

This looks like a merge leftover being merged in.

> -               if (!llis_va[index].lli)
> +               if (llis_va[index].lli <= clli)

This was clever.

The rest of the code looks nice.

Yours,
Linus Walleij

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> From: Alban Bedel <alban.bedel@avionic-design.de>
>
> Many audio interface drivers require support of cyclic transfers to work
> correctly, for example Samsung ASoC DMA driver. This patch adds support
> for cyclic transfers to the amba-pl08x driver.
>
> Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Nice! This is useful for others as well.

> @@ -198,6 +199,8 @@ struct pl08x_txd {
>          */
>         u32 ccfg;
>         bool done;
> +
> +       bool cyclic;
>  };

You can never have enough whitespace right?

>  /**
> @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
>                         bytes += get_bytes_in_cctl(llis_va[index].cctl);
>
>                 /*
> -                * A LLI pointer of 0 terminates the LLI list
> ++               * A LLI pointer going backward terminates the LLI list

++? Really?

This looks like a merge leftover being merged in.

> -               if (!llis_va[index].lli)
> +               if (llis_va[index].lli <= clli)

This was clever.

The rest of the code looks nice.

Yours,
Linus Walleij

Re: [RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
> can be used instead of the private s3c-dma interface.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
(...)
> -       select S3C64XX_DMA if ARCH_S3C64XX
> +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080

I guess this means the SPI driver does not work without DMA.
But is the SPI driver already augmented to handle generic DMA engine?
Anyway:

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
> can be used instead of the private s3c-dma interface.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
(...)
> -       select S3C64XX_DMA if ARCH_S3C64XX
> +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080

I guess this means the SPI driver does not work without DMA.
But is the SPI driver already augmented to handle generic DMA engine?
Anyway:

Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [RFC PATCH 10/11] ASoC: samsung: Do not require legacy DMA API in case of S3C64XX

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
> can be used instead of the private s3c-dma interface.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
(...)
> -       select S3C64XX_DMA if ARCH_S3C64XX
> +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
>         select S3C2410_DMA if ARCH_S3C24XX

I hope it will look nicer (like just selecting the real PL080 driver)
in the end. OK can live with this:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[RFC PATCH 10/11] ASoC: samsung: Do not require legacy DMA API in case of S3C64XX

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> With support for amba-pl08x driver, on S3C64xx the generic DMA engine API
> can be used instead of the private s3c-dma interface.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
(...)
> -       select S3C64XX_DMA if ARCH_S3C64XX
> +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
>         select S3C2410_DMA if ARCH_S3C24XX

I hope it will look nicer (like just selecting the real PL080 driver)
in the end. OK can live with this:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> This patch adds all required platform-specific data and initialization
> code to support the generic amba-pl08x driver on S3C64xx SoCs.
>
> Also some compatibility definitions are added to make the transition from
> legacy API to DMA engine easier. The biggest hack here is passing const
> char * pointers through DMA resource, casted to unsigned long, but this
> is how Samsung DMA wrappers (used to support both s3c-dma and DMA engine
> in drivers) is designed.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Patch looks like an OK stepping stone.

> +static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
> +                       0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
(...)
> +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
> +                       0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);

Ah, does this mean the device does not have any AMBA PrimeCell ID
contents?

Then use the ID 0x00053080 instead of 0x0a141080

0x53 is "S" for Samsung. Variant 0.

Yours,
Linus Walleij

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> This patch adds all required platform-specific data and initialization
> code to support the generic amba-pl08x driver on S3C64xx SoCs.
>
> Also some compatibility definitions are added to make the transition from
> legacy API to DMA engine easier. The biggest hack here is passing const
> char * pointers through DMA resource, casted to unsigned long, but this
> is how Samsung DMA wrappers (used to support both s3c-dma and DMA engine
> in drivers) is designed.
>
> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>

Patch looks like an OK stepping stone.

> +static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
> +                       0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
(...)
> +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
> +                       0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);

Ah, does this mean the device does not have any AMBA PrimeCell ID
contents?

Then use the ID 0x00053080 instead of 0x0a141080

0x53 is "S" for Samsung. Variant 0.

Yours,
Linus Walleij

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
> is its DMA driver, which is completely platform-specific and provides
> private API (s3c-dma), not even saying that its design is completely
> against multiplatform-awareness.
>
> The DMA controller present on this SoC series is a custom variant
> of ARM PrimeCell PL080 modified by Samsung to add some extra features.
> It is mostly compatible with original PL080, except:
>  - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
>  - offset of CH_CONFIG register is different,
>  - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
>  - transfer size field is extended to 24 bits, allowing much bigger
>      single transfer,
>  - LLI consists of one more word, to account for CH_CONTROL2 register.
>
> Since all the rest is fully compatible with standard PL080 there is no
> point in having separate driver just for this single variant, so I decided
> to look into adding support for it to the amba-pl08x driver.
>
> There was already some attempt to achieve this before, but this was before
> Russel's big rework of the driver to use virtual channels, making the old
> patches being not much of use.
>
> This RFC series is a proof of concept that I managed to make during last
> days of hacking. Except one patch adding clkdev lookup to clock driver
> (which is being replaced with a CCF-compliant driver ATM), this is enough
> to get memcpy and slave transfers to work on S3C64xx.
>
> I have tested this on Mini6410 and SMDK6410 boards using dmatest for
> memcpy and Samsung I2S with madplay/aplay for slave transfers.
> Unfortunately I do not have access to other platforms with PL08x so
> I could not test for any regressions introduced on them.
>
> Credits for two patches go to Alban Bedel, who made a series fixing this
> driver to make it usable with audio drivers. I rebased his patches on top
> of mine and corrected coding style a bit.
>
> OK, that's all. Any comments are welcome. Feel free to start throwing eggs
> and tomatoes if you find this awful, but I won't be upset if I get some
> Tested-by or Acked-by as well. ;)

I've waited for a long time for this to happen, thank you very much for
doing this.

Yours,
Linus Walleij

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Linus Walleij]

On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
> is its DMA driver, which is completely platform-specific and provides
> private API (s3c-dma), not even saying that its design is completely
> against multiplatform-awareness.
>
> The DMA controller present on this SoC series is a custom variant
> of ARM PrimeCell PL080 modified by Samsung to add some extra features.
> It is mostly compatible with original PL080, except:
>  - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
>  - offset of CH_CONFIG register is different,
>  - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
>  - transfer size field is extended to 24 bits, allowing much bigger
>      single transfer,
>  - LLI consists of one more word, to account for CH_CONTROL2 register.
>
> Since all the rest is fully compatible with standard PL080 there is no
> point in having separate driver just for this single variant, so I decided
> to look into adding support for it to the amba-pl08x driver.
>
> There was already some attempt to achieve this before, but this was before
> Russel's big rework of the driver to use virtual channels, making the old
> patches being not much of use.
>
> This RFC series is a proof of concept that I managed to make during last
> days of hacking. Except one patch adding clkdev lookup to clock driver
> (which is being replaced with a CCF-compliant driver ATM), this is enough
> to get memcpy and slave transfers to work on S3C64xx.
>
> I have tested this on Mini6410 and SMDK6410 boards using dmatest for
> memcpy and Samsung I2S with madplay/aplay for slave transfers.
> Unfortunately I do not have access to other platforms with PL08x so
> I could not test for any regressions introduced on them.
>
> Credits for two patches go to Alban Bedel, who made a series fixing this
> driver to make it usable with audio drivers. I rebased his patches on top
> of mine and corrected coding style a bit.
>
> OK, that's all. Any comments are welcome. Feel free to start throwing eggs
> and tomatoes if you find this awful, but I won't be upset if I get some
> Tested-by or Acked-by as well. ;)

I've waited for a long time for this to happen, thank you very much for
doing this.

Yours,
Linus Walleij

Re: [RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Mark Brown]

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On Mon, Jun 17, 2013 at 03:59:39PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> > -       select S3C64XX_DMA if ARCH_S3C64XX
> > +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080

> I guess this means the SPI driver does not work without DMA.
> But is the SPI driver already augmented to handle generic DMA engine?
> Anyway:

Yes, the driver currently relies on DMA.  There are some pending patches
for non-DMA operation that I need to test.  To be honest for both this
and the ASoC driver I'd be more inclined to just either select or depend
on the DMA controller rather than leaving the option of using the old
code.

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[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Mark Brown]

On Mon, Jun 17, 2013 at 03:59:39PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:

> > -       select S3C64XX_DMA if ARCH_S3C64XX
> > +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080

> I guess this means the SPI driver does not work without DMA.
> But is the SPI driver already augmented to handle generic DMA engine?
> Anyway:

Yes, the driver currently relies on DMA.  There are some pending patches
for non-DMA operation that I need to test.  To be honest for both this
and the ASoC driver I'd be more inclined to just either select or depend
on the DMA controller rather than leaving the option of using the old
code.
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Re: [RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Tomasz Figa]

On Monday 17 of June 2013 15:39:34 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080S is a modified version of PL080 that can be found on Samsung
> > SoCs, such as S3C6400 and S3C6410.
> > 
> > It has different offset of CONFIG register, separate CONTROL1 register
> > that holds transfer size and larger maximum transfer size.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> (I would have done some smallish things differently but it
> is only a matter of taste.)
> 
> >  static struct amba_id pl08x_ids[] = {
> > 
> > +       /* Samsung PL080S variant */
> > +       {
> > +               .id     = 0x0a141080,
> > +               .mask   = 0xffffffff,
> > +               .data   = &vendor_pl080s,
> > +       },
> 
> Interesting that Samsung claim to be vendor 0x41
> (ARM).

Yeah, I had identical thought when I saw it first time.

> Well ARM never made revision no 0x0a so
> this works.

Good, this is exactly what I wanted to read! ;)

I was afraid that this ID might conflict with some revision of normal 
PL080, but fortunately it is not the case.

Best refards,
Tomasz

[RFC PATCH 04/11] dma: amba-pl08x: Add support for PL080S variant

[Tomasz Figa]

On Monday 17 of June 2013 15:39:34 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080S is a modified version of PL080 that can be found on Samsung
> > SoCs, such as S3C6400 and S3C6410.
> > 
> > It has different offset of CONFIG register, separate CONTROL1 register
> > that holds transfer size and larger maximum transfer size.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> (I would have done some smallish things differently but it
> is only a matter of taste.)
> 
> >  static struct amba_id pl08x_ids[] = {
> > 
> > +       /* Samsung PL080S variant */
> > +       {
> > +               .id     = 0x0a141080,
> > +               .mask   = 0xffffffff,
> > +               .data   = &vendor_pl080s,
> > +       },
> 
> Interesting that Samsung claim to be vendor 0x41
> (ARM).

Yeah, I had identical thought when I saw it first time.

> Well ARM never made revision no 0x0a so
> this works.

Good, this is exactly what I wanted to read! ;)

I was afraid that this ID might conflict with some revision of normal 
PL080, but fortunately it is not the case.

Best refards,
Tomasz

Re: [RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Tomasz Figa]

On Monday 17 of June 2013 15:42:15 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080S has separate register to store transfer size in, allowing
> > single
> > transfer to be much larger than in standard PL080.
> > 
> > This patch makes the amba-pl08x driver aware of this and removes
> > writing transfer size to reserved bits of CH_CONTROL register on
> > PL080S, which was not a problem witn transfer sizes fitting the
> > original bitfield of PL080, but now would overwrite other fields.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Very straight-forward.
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Thanks.

Actually today I found another way of doing this, which wouldn't require 
checking PL08X_IS_PL080S flag at all.

Simply masking the transfer size in pl08x_cctl_bits() with mask of the 
original bitfield would be enough I think, as writes to those bits seem to 
be ignored on PL080S.

Best regards,
Tomasz

[RFC PATCH 05/11] dma: amba-pl08x: Add support for different maximum transfer size

[Tomasz Figa]

On Monday 17 of June 2013 15:42:15 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080S has separate register to store transfer size in, allowing
> > single
> > transfer to be much larger than in standard PL080.
> > 
> > This patch makes the amba-pl08x driver aware of this and removes
> > writing transfer size to reserved bits of CH_CONTROL register on
> > PL080S, which was not a problem witn transfer sizes fitting the
> > original bitfield of PL080, but now would overwrite other fields.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Very straight-forward.
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Thanks.

Actually today I found another way of doing this, which wouldn't require 
checking PL08X_IS_PL080S flag at all.

Simply masking the transfer size in pl08x_cctl_bits() with mask of the 
original bitfield would be enough I think, as writes to those bits seem to 
be ignored on PL080S.

Best regards,
Tomasz

Re: [RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Tomasz Figa]

On Monday 17 of June 2013 15:51:20 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080 reference manual states that to LLI entries should be aligned
> > to 4-word boundary to make LLI fetches more efficient. This patch adds
> > a 3-word padding to the LLi struct to make this condition true.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> > ---
> > 
> >  drivers/dma/amba-pl08x.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index eb10eb8..0da5539 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -127,6 +127,7 @@ struct pl08x_lli {
> > 
> >         u32 lli;
> >         u32 cctl;
> >         u32 cctl1;
> > 
> > +       u32 dummy[3];
> 
> Atleast put a comment into the code explaining what this is all
> about. Or someone will add another member to the struct and
> all is lost. Call it "padding" rather than dummy.
> 
> >  };
> 
> So it used to be like this before you added cctl1:
> 
> struct pl08x_lli {
>         u32 src;
>         u32 dst;
>         u32 lli;
>         u32 cctl;
> };
> 
> Meaning it was 3 words.
> 
> And now you make it take 8 words for everyone.
> 
> Atleast this patch should be squashed into the patch
> adding cctl1.
> 
> But I really don't like this fragile way of casting structs right
> into memory, and I don't like that teh other PL080's also have
> to waste 8 words when their LLIs fit so nicely into 4.
> 
> I would have solved this problem by creating a
> marshalling function that just allocate the number of bytes the
> LLI entry shall have and fill it in by assigning directly to the
> precise target memory cell. This way the LLIs will take
> 4 words on the original variants and you can use some
> nice logic to pad out to 8 words on the PL080S variant.

Definitely a valid point. I'll see what I can do about it.

I was thinking about it originally, but I couldn't find any really good 
solution for this so I just went with this extremely simple approach as a 
proof of concept and to show the problem. :)

Best regards,
Tomasz

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Tomasz Figa]

On Monday 17 of June 2013 15:51:20 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > PL080 reference manual states that to LLI entries should be aligned
> > to 4-word boundary to make LLI fetches more efficient. This patch adds
> > a 3-word padding to the LLi struct to make this condition true.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> > ---
> > 
> >  drivers/dma/amba-pl08x.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index eb10eb8..0da5539 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -127,6 +127,7 @@ struct pl08x_lli {
> > 
> >         u32 lli;
> >         u32 cctl;
> >         u32 cctl1;
> > 
> > +       u32 dummy[3];
> 
> Atleast put a comment into the code explaining what this is all
> about. Or someone will add another member to the struct and
> all is lost. Call it "padding" rather than dummy.
> 
> >  };
> 
> So it used to be like this before you added cctl1:
> 
> struct pl08x_lli {
>         u32 src;
>         u32 dst;
>         u32 lli;
>         u32 cctl;
> };
> 
> Meaning it was 3 words.
> 
> And now you make it take 8 words for everyone.
> 
> Atleast this patch should be squashed into the patch
> adding cctl1.
> 
> But I really don't like this fragile way of casting structs right
> into memory, and I don't like that teh other PL080's also have
> to waste 8 words when their LLIs fit so nicely into 4.
> 
> I would have solved this problem by creating a
> marshalling function that just allocate the number of bytes the
> LLI entry shall have and fill it in by assigning directly to the
> precise target memory cell. This way the LLIs will take
> 4 words on the original variants and you can use some
> nice logic to pad out to 8 words on the PL080S variant.

Definitely a valid point. I'll see what I can do about it.

I was thinking about it originally, but I couldn't find any really good 
solution for this so I just went with this extremely simple approach as a 
proof of concept and to show the problem. :)

Best regards,
Tomasz

Re: [RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

On Monday 17 of June 2013 15:53:14 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> > 
> > There are more fields than just SWIDTH in CH_CONTROL register, so read
> > register value must be masked in addition to shifting.
> > 
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> Are we just lucky on current variants such that all unmasked bits
> happen to be zero on them?

This is really interesting, because if you look at the bit layout, there 
is a lot of other bitfields above the SWIDTH field, like DWIDTH, src and 
dest AHB master selection, src and dest incerement setting, protection and 
terminal count interrupt enable bits.

Best regards,
Tomasz

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Tomasz Figa]

On Monday 17 of June 2013 15:53:14 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> > 
> > There are more fields than just SWIDTH in CH_CONTROL register, so read
> > register value must be masked in addition to shifting.
> > 
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> Are we just lucky on current variants such that all unmasked bits
> happen to be zero on them?

This is really interesting, because if you look at the bit layout, there 
is a lot of other bitfields above the SWIDTH field, like DWIDTH, src and 
dest AHB master selection, src and dest incerement setting, protection and 
terminal count interrupt enable bits.

Best regards,
Tomasz

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> Instead of defining new bool field in vendor_data struct for each quirk,
> it is more reasonable to use a single flags field and make each quirk
> use single bits.

Please explain why this is better over the existing system, and why it is
not just churn for code modification's sake.

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> Instead of defining new bool field in vendor_data struct for each quirk,
> it is more reasonable to use a single flags field and make each quirk
> use single bits.

Please explain why this is better over the existing system, and why it is
not just churn for code modification's sake.

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> Instead of defining new bool field in vendor_data struct for each quirk,
> it is more reasonable to use a single flags field and make each quirk
> use single bits.

Please explain why this is better over the existing system, and why it is
not just churn for code modification's sake.

Re: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> have CONFIG register at different offset. This patch makes the driver
> use offset from vendor data struct.

I'd suggest doing this a different way.  Instead of having to pass around
two pointers everywhere in order to access this register, add to
struct pl08x_phy_chan a void __iomem *reg_config; member, and initialize
that to base + vd->config_offset.  Then use ch->reg_cfg instead of
ch->base + PL080_CH_CONFIG.

This has the benefit that you won't have to modify a whole load of
functions to pass another argument, which costs not only an additional
register, but also storage to keep it around.

Re: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> have CONFIG register at different offset. This patch makes the driver
> use offset from vendor data struct.

I'd suggest doing this a different way.  Instead of having to pass around
two pointers everywhere in order to access this register, add to
struct pl08x_phy_chan a void __iomem *reg_config; member, and initialize
that to base + vd->config_offset.  Then use ch->reg_cfg instead of
ch->base + PL080_CH_CONFIG.

This has the benefit that you won't have to modify a whole load of
functions to pass another argument, which costs not only an additional
register, but also storage to keep it around.

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> have CONFIG register at different offset. This patch makes the driver
> use offset from vendor data struct.

I'd suggest doing this a different way.  Instead of having to pass around
two pointers everywhere in order to access this register, add to
struct pl08x_phy_chan a void __iomem *reg_config; member, and initialize
that to base + vd->config_offset.  Then use ch->reg_cfg instead of
ch->base + PL080_CH_CONFIG.

This has the benefit that you won't have to modify a whole load of
functions to pass another argument, which costs not only an additional
register, but also storage to keep it around.

Re: [RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Tomasz Figa]

On Monday 17 of June 2013 15:57:38 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> > 
> > Many audio interface drivers require support of cyclic transfers to
> > work correctly, for example Samsung ASoC DMA driver. This patch adds
> > support for cyclic transfers to the amba-pl08x driver.
> > 
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Nice! This is useful for others as well.
> 
> > @@ -198,6 +199,8 @@ struct pl08x_txd {
> > 
> >          */
> >         
> >         u32 ccfg;
> >         bool done;
> > 
> > +
> > +       bool cyclic;
> > 
> >  };
> 
> You can never have enough whitespace right?
> 
> >  /**
> > 
> > @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct
> > pl08x_dma_chan *plchan)> 
> >                         bytes +=
> >                         get_bytes_in_cctl(llis_va[index].cctl);
> >                 
> >                 /*
> > 
> > -                * A LLI pointer of 0 terminates the LLI list
> > ++               * A LLI pointer going backward terminates the LLI
> > list
> 
> ++? Really?
> 
> This looks like a merge leftover being merged in.

I think it's a copy/paste error when applying some hunks of the original 
patch manually.

> > -               if (!llis_va[index].lli)
> > +               if (llis_va[index].lli <= clli)
> 
> This was clever.
> 
> The rest of the code looks nice.

OK. I will fix the issues you mentioned in next version.

Best regards,
Tomasz

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Tomasz Figa]

On Monday 17 of June 2013 15:57:38 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> > 
> > Many audio interface drivers require support of cyclic transfers to
> > work correctly, for example Samsung ASoC DMA driver. This patch adds
> > support for cyclic transfers to the amba-pl08x driver.
> > 
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Nice! This is useful for others as well.
> 
> > @@ -198,6 +199,8 @@ struct pl08x_txd {
> > 
> >          */
> >         
> >         u32 ccfg;
> >         bool done;
> > 
> > +
> > +       bool cyclic;
> > 
> >  };
> 
> You can never have enough whitespace right?
> 
> >  /**
> > 
> > @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct
> > pl08x_dma_chan *plchan)> 
> >                         bytes +=
> >                         get_bytes_in_cctl(llis_va[index].cctl);
> >                 
> >                 /*
> > 
> > -                * A LLI pointer of 0 terminates the LLI list
> > ++               * A LLI pointer going backward terminates the LLI
> > list
> 
> ++? Really?
> 
> This looks like a merge leftover being merged in.

I think it's a copy/paste error when applying some hunks of the original 
patch manually.

> > -               if (!llis_va[index].lli)
> > +               if (llis_va[index].lli <= clli)
> 
> This was clever.
> 
> The rest of the code looks nice.

OK. I will fix the issues you mentioned in next version.

Best regards,
Tomasz

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

On Monday 17 of June 2013 19:48:56 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> > Instead of defining new bool field in vendor_data struct for each
> > quirk, it is more reasonable to use a single flags field and make
> > each quirk use single bits.
> 
> Please explain why this is better over the existing system, and why it
> is not just churn for code modification's sake.

It isn't anything important. I just thought that this is a better solution 
to store more than just two flags. Initially I had more of them added in 
further patches, but final version ended with just one, so this can be 
dropped.

Best regards,
Tomasz

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

On Monday 17 of June 2013 19:48:56 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> > Instead of defining new bool field in vendor_data struct for each
> > quirk, it is more reasonable to use a single flags field and make
> > each quirk use single bits.
> 
> Please explain why this is better over the existing system, and why it
> is not just churn for code modification's sake.

It isn't anything important. I just thought that this is a better solution 
to store more than just two flags. Initially I had more of them added in 
further patches, but final version ended with just one, so this can be 
dropped.

Best regards,
Tomasz

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Tomasz Figa]

On Monday 17 of June 2013 19:48:56 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
> > Instead of defining new bool field in vendor_data struct for each
> > quirk, it is more reasonable to use a single flags field and make
> > each quirk use single bits.
> 
> Please explain why this is better over the existing system, and why it
> is not just churn for code modification's sake.

It isn't anything important. I just thought that this is a better solution 
to store more than just two flags. Initially I had more of them added in 
further patches, but final version ended with just one, so this can be 
dropped.

Best regards,
Tomasz

Re: [RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:15PM +0200, Tomasz Figa wrote:
> @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
>  			bytes += get_bytes_in_cctl(llis_va[index].cctl);
>  
>  		/*
> -		 * A LLI pointer of 0 terminates the LLI list
> ++		 * A LLI pointer going backward terminates the LLI list

Spot the unfixed up merge error...

Re: [RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:15PM +0200, Tomasz Figa wrote:
> @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
>  			bytes += get_bytes_in_cctl(llis_va[index].cctl);
>  
>  		/*
> -		 * A LLI pointer of 0 terminates the LLI list
> ++		 * A LLI pointer going backward terminates the LLI list

Spot the unfixed up merge error...

[RFC PATCH 08/11] dmaengine: PL08x: Add cyclic transfer support

[Russell King - ARM Linux]

On Sun, Jun 16, 2013 at 10:54:15PM +0200, Tomasz Figa wrote:
> @@ -561,9 +564,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
>  			bytes += get_bytes_in_cctl(llis_va[index].cctl);
>  
>  		/*
> -		 * A LLI pointer of 0 terminates the LLI list
> ++		 * A LLI pointer going backward terminates the LLI list

Spot the unfixed up merge error...

Re: [RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Russell King - ARM Linux]

On Mon, Jun 17, 2013 at 03:51:20PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index eb10eb8..0da5539 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -127,6 +127,7 @@ struct pl08x_lli {
> >         u32 lli;
> >         u32 cctl;
> >         u32 cctl1;
> > +       u32 dummy[3];
> 
> Atleast put a comment into the code explaining what this is all
> about. Or someone will add another member to the struct and
> all is lost. Call it "padding" rather than dummy.

Another solution to that is to use __attribute__((__aligned__(16)))
if you want it aligned to 16 byte boundaries.

[RFC PATCH 06/11] dma: amba-pl08x: Keep LLIs aligned to 4-word boundary

[Russell King - ARM Linux]

On Mon, Jun 17, 2013 at 03:51:20PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index eb10eb8..0da5539 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -127,6 +127,7 @@ struct pl08x_lli {
> >         u32 lli;
> >         u32 cctl;
> >         u32 cctl1;
> > +       u32 dummy[3];
> 
> Atleast put a comment into the code explaining what this is all
> about. Or someone will add another member to the struct and
> all is lost. Call it "padding" rather than dummy.

Another solution to that is to use __attribute__((__aligned__(16)))
if you want it aligned to 16 byte boundaries.

Re: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

On Monday 17 of June 2013 19:52:23 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> > Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> > have CONFIG register at different offset. This patch makes the driver
> > use offset from vendor data struct.
> 
> I'd suggest doing this a different way.  Instead of having to pass
> around two pointers everywhere in order to access this register, add to
> struct pl08x_phy_chan a void __iomem *reg_config; member, and
> initialize that to base + vd->config_offset.  Then use ch->reg_cfg
> instead of ch->base + PL080_CH_CONFIG.
> 
> This has the benefit that you won't have to modify a whole load of
> functions to pass another argument, which costs not only an additional
> register, but also storage to keep it around.

OK. Let me do it this way and see how it turns out. However keep in mind 
that next patch adds further dependencies on access to vendor_data struct, 
so there is nothing sure.

Best regards,
Tomasz

Re: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

On Monday 17 of June 2013 19:52:23 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> > Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> > have CONFIG register at different offset. This patch makes the driver
> > use offset from vendor data struct.
> 
> I'd suggest doing this a different way.  Instead of having to pass
> around two pointers everywhere in order to access this register, add to
> struct pl08x_phy_chan a void __iomem *reg_config; member, and
> initialize that to base + vd->config_offset.  Then use ch->reg_cfg
> instead of ch->base + PL080_CH_CONFIG.
> 
> This has the benefit that you won't have to modify a whole load of
> functions to pass another argument, which costs not only an additional
> register, but also storage to keep it around.

OK. Let me do it this way and see how it turns out. However keep in mind 
that next patch adds further dependencies on access to vendor_data struct, 
so there is nothing sure.

Best regards,
Tomasz

[RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register

[Tomasz Figa]

On Monday 17 of June 2013 19:52:23 Russell King - ARM Linux wrote:
> On Sun, Jun 16, 2013 at 10:54:10PM +0200, Tomasz Figa wrote:
> > Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
> > have CONFIG register at different offset. This patch makes the driver
> > use offset from vendor data struct.
> 
> I'd suggest doing this a different way.  Instead of having to pass
> around two pointers everywhere in order to access this register, add to
> struct pl08x_phy_chan a void __iomem *reg_config; member, and
> initialize that to base + vd->config_offset.  Then use ch->reg_cfg
> instead of ch->base + PL080_CH_CONFIG.
> 
> This has the benefit that you won't have to modify a whole load of
> functions to pass another argument, which costs not only an additional
> register, but also storage to keep it around.

OK. Let me do it this way and see how it turns out. However keep in mind 
that next patch adds further dependencies on access to vendor_data struct, 
so there is nothing sure.

Best regards,
Tomasz

Re: [RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Russell King - ARM Linux]

On Mon, Jun 17, 2013 at 03:53:14PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> 
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> >
> > There are more fields than just SWIDTH in CH_CONTROL register, so read
> > register value must be masked in addition to shifting.
> >
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> Are we just lucky on current variants such that all unmasked bits
> happen to be zero on them?

It's probably that all the places which this gets used, the transfers
are 8-bit (like the UART) so it "just works" irrespective of that.

[RFC PATCH 07/11] dmaengine: PL08x: Fix reading the byte count in cctl

[Russell King - ARM Linux]

On Mon, Jun 17, 2013 at 03:53:14PM +0200, Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> 
> > From: Alban Bedel <alban.bedel@avionic-design.de>
> >
> > There are more fields than just SWIDTH in CH_CONTROL register, so read
> > register value must be masked in addition to shifting.
> >
> > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> 
> Are we just lucky on current variants such that all unmasked bits
> happen to be zero on them?

It's probably that all the places which this gets used, the transfers
are 8-bit (like the UART) so it "just works" irrespective of that.

Re: [RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

On Monday 17 of June 2013 17:06:30 Mark Brown wrote:
> On Mon, Jun 17, 2013 at 03:59:39PM +0200, Linus Walleij wrote:
> > On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > > -       select S3C64XX_DMA if ARCH_S3C64XX
> > > +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
> > 
> > I guess this means the SPI driver does not work without DMA.
> > But is the SPI driver already augmented to handle generic DMA engine?
> 
> > Anyway:
> Yes, the driver currently relies on DMA.  There are some pending patches
> for non-DMA operation that I need to test.  To be honest for both this
> and the ASoC driver I'd be more inclined to just either select or
> depend on the DMA controller rather than leaving the option of using
> the old code.

Well, I just left this for the purpose of this RFC, so testing things on 
both drivers would be possible (to see if any problems are caused by new 
driver or just by things that don't work).

If this driver turns out to be working correctly, I will happily remove 
the old private one and after s3c24xx moves to Heiko's DMA engine driver 
(or as it already moved?) we will be able to completely drop the private 
s3c-dma API.

Best regards,
Tomasz

[RFC PATCH 09/11] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX

[Tomasz Figa]

On Monday 17 of June 2013 17:06:30 Mark Brown wrote:
> On Mon, Jun 17, 2013 at 03:59:39PM +0200, Linus Walleij wrote:
> > On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > > -       select S3C64XX_DMA if ARCH_S3C64XX
> > > +       select S3C64XX_DMA if ARCH_S3C64XX && !S3C64XX_PL080
> > 
> > I guess this means the SPI driver does not work without DMA.
> > But is the SPI driver already augmented to handle generic DMA engine?
> 
> > Anyway:
> Yes, the driver currently relies on DMA.  There are some pending patches
> for non-DMA operation that I need to test.  To be honest for both this
> and the ASoC driver I'd be more inclined to just either select or
> depend on the DMA controller rather than leaving the option of using
> the old code.

Well, I just left this for the purpose of this RFC, so testing things on 
both drivers would be possible (to see if any problems are caused by new 
driver or just by things that don't work).

If this driver turns out to be working correctly, I will happily remove 
the old private one and after s3c24xx moves to Heiko's DMA engine driver 
(or as it already moved?) we will be able to completely drop the private 
s3c-dma API.

Best regards,
Tomasz

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Monday 17 of June 2013 16:06:25 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > support is its DMA driver, which is completely platform-specific and
> > provides private API (s3c-dma), not even saying that its design is
> > completely against multiplatform-awareness.
> > 
> > The DMA controller present on this SoC series is a custom variant
> > of ARM PrimeCell PL080 modified by Samsung to add some extra features.
> > 
> > It is mostly compatible with original PL080, except:
> >  - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
> >  - offset of CH_CONFIG register is different,
> >  - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
> >  - transfer size field is extended to 24 bits, allowing much bigger
> >  
> >      single transfer,
> >  
> >  - LLI consists of one more word, to account for CH_CONTROL2 register.
> > 
> > Since all the rest is fully compatible with standard PL080 there is no
> > point in having separate driver just for this single variant, so I
> > decided to look into adding support for it to the amba-pl08x driver.
> > 
> > There was already some attempt to achieve this before, but this was
> > before Russel's big rework of the driver to use virtual channels,
> > making the old patches being not much of use.
> > 
> > This RFC series is a proof of concept that I managed to make during
> > last days of hacking. Except one patch adding clkdev lookup to clock
> > driver (which is being replaced with a CCF-compliant driver ATM),
> > this is enough to get memcpy and slave transfers to work on S3C64xx.
> > 
> > I have tested this on Mini6410 and SMDK6410 boards using dmatest for
> > memcpy and Samsung I2S with madplay/aplay for slave transfers.
> > Unfortunately I do not have access to other platforms with PL08x so
> > I could not test for any regressions introduced on them.
> > 
> > Credits for two patches go to Alban Bedel, who made a series fixing
> > this driver to make it usable with audio drivers. I rebased his
> > patches on top of mine and corrected coding style a bit.
> > 
> > OK, that's all. Any comments are welcome. Feel free to start throwing
> > eggs and tomatoes if you find this awful, but I won't be upset if I
> > get some Tested-by or Acked-by as well. ;)
> 
> I've waited for a long time for this to happen, thank you very much for
> doing this.

You're welcome. Thanks for your review.

Best regards,
Tomasz

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Monday 17 of June 2013 16:06:25 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > support is its DMA driver, which is completely platform-specific and
> > provides private API (s3c-dma), not even saying that its design is
> > completely against multiplatform-awareness.
> > 
> > The DMA controller present on this SoC series is a custom variant
> > of ARM PrimeCell PL080 modified by Samsung to add some extra features.
> > 
> > It is mostly compatible with original PL080, except:
> >  - CH_CONTROL2 register is added between CH_CONTROL and CH_CONFIG,
> >  - offset of CH_CONFIG register is different,
> >  - transfer size field is moved from CH_CONTROL to CH_CONTROL2,
> >  - transfer size field is extended to 24 bits, allowing much bigger
> >  
> >      single transfer,
> >  
> >  - LLI consists of one more word, to account for CH_CONTROL2 register.
> > 
> > Since all the rest is fully compatible with standard PL080 there is no
> > point in having separate driver just for this single variant, so I
> > decided to look into adding support for it to the amba-pl08x driver.
> > 
> > There was already some attempt to achieve this before, but this was
> > before Russel's big rework of the driver to use virtual channels,
> > making the old patches being not much of use.
> > 
> > This RFC series is a proof of concept that I managed to make during
> > last days of hacking. Except one patch adding clkdev lookup to clock
> > driver (which is being replaced with a CCF-compliant driver ATM),
> > this is enough to get memcpy and slave transfers to work on S3C64xx.
> > 
> > I have tested this on Mini6410 and SMDK6410 boards using dmatest for
> > memcpy and Samsung I2S with madplay/aplay for slave transfers.
> > Unfortunately I do not have access to other platforms with PL08x so
> > I could not test for any regressions introduced on them.
> > 
> > Credits for two patches go to Alban Bedel, who made a series fixing
> > this driver to make it usable with audio drivers. I rebased his
> > patches on top of mine and corrected coding style a bit.
> > 
> > OK, that's all. Any comments are welcome. Feel free to start throwing
> > eggs and tomatoes if you find this awful, but I won't be upset if I
> > get some Tested-by or Acked-by as well. ;)
> 
> I've waited for a long time for this to happen, thank you very much for
> doing this.

You're welcome. Thanks for your review.

Best regards,
Tomasz

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Linus Walleij]

On Mon, Jun 17, 2013 at 8:56 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Monday 17 of June 2013 19:48:56 Russell King - ARM Linux wrote:
>> On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
>> > Instead of defining new bool field in vendor_data struct for each
>> > quirk, it is more reasonable to use a single flags field and make
>> > each quirk use single bits.
>>
>> Please explain why this is better over the existing system, and why it
>> is not just churn for code modification's sake.
>
> It isn't anything important. I just thought that this is a better solution
> to store more than just two flags. Initially I had more of them added in
> further patches, but final version ended with just one, so this can be
> dropped.

I thought about it yesterday and it basically looks to me that
it tries to outsmart the compiler on how to stuff the flags to save
struct space on the heap and hint that they can be determined
quickly by a & operation, this is like premature optimization.

So please go back to the old system.

Yours,
Linus Walleij

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Linus Walleij]

On Mon, Jun 17, 2013 at 8:56 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Monday 17 of June 2013 19:48:56 Russell King - ARM Linux wrote:
>> On Sun, Jun 16, 2013 at 10:54:08PM +0200, Tomasz Figa wrote:
>> > Instead of defining new bool field in vendor_data struct for each
>> > quirk, it is more reasonable to use a single flags field and make
>> > each quirk use single bits.
>>
>> Please explain why this is better over the existing system, and why it
>> is not just churn for code modification's sake.
>
> It isn't anything important. I just thought that this is a better solution
> to store more than just two flags. Initially I had more of them added in
> further patches, but final version ended with just one, so this can be
> dropped.

I thought about it yesterday and it basically looks to me that
it tries to outsmart the compiler on how to stuff the flags to save
struct space on the heap and hint that they can be determined
quickly by a & operation, this is like premature optimization.

So please go back to the old system.

Yours,
Linus Walleij

Re: [RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Arnd Bergmann]

On Tuesday 18 June 2013, Linus Walleij wrote:
> I thought about it yesterday and it basically looks to me that
> it tries to outsmart the compiler on how to stuff the flags to save
> struct space on the heap and hint that they can be determined
> quickly by a & operation, this is like premature optimization.
> 
> So please go back to the old system.

Note that a 'bool' is typically stored as a 32-bit field, so there
would be some space saving if there are a lot of flags.

I agree with the conclusion though, the previous state was more
readable, which outweighs any benefits.

	Arnd

[RFC PATCH 01/11] dma: amba-pl08x: Use bitmap to pass variant specific quirks

[Arnd Bergmann]

On Tuesday 18 June 2013, Linus Walleij wrote:
> I thought about it yesterday and it basically looks to me that
> it tries to outsmart the compiler on how to stuff the flags to save
> struct space on the heap and hint that they can be determined
> quickly by a & operation, this is like premature optimization.
> 
> So please go back to the old system.

Note that a 'bool' is typically stored as a 32-bit field, so there
would be some space saving if there are a lot of flags.

I agree with the conclusion though, the previous state was more
readable, which outweighs any benefits.

	Arnd

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
> is its DMA driver, which is completely platform-specific and provides
> private API (s3c-dma), not even saying that its design is completely
> against multiplatform-awareness.

I tried to test this on my s3c64xx based system but it gave me a kernel
that didn't boot far enough to give console output (there's some early
init stuff that uses SPI...).  That said, I needed:

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 210a893..0f49707 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
 	int ret;
 
 	if (plchan->mux_use++ == 0 && pd->get_signal) {
-		ret = pd->get_signal(plchan->cd);
+		ret = (pd->get_signal)(plchan->cd);
 		if (ret < 0) {
 			plchan->mux_use = 0;
 			return ret;

to get it to build which makes me suspect the compiler a bit as well...
the system has audio, SPI and MMC enabled.

I was applying this to -next, are there any other dependencies I need or
anything?

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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
> is its DMA driver, which is completely platform-specific and provides
> private API (s3c-dma), not even saying that its design is completely
> against multiplatform-awareness.

I tried to test this on my s3c64xx based system but it gave me a kernel
that didn't boot far enough to give console output (there's some early
init stuff that uses SPI...).  That said, I needed:

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 210a893..0f49707 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
 	int ret;
 
 	if (plchan->mux_use++ == 0 && pd->get_signal) {
-		ret = pd->get_signal(plchan->cd);
+		ret = (pd->get_signal)(plchan->cd);
 		if (ret < 0) {
 			plchan->mux_use = 0;
 			return ret;

to get it to build which makes me suspect the compiler a bit as well...
the system has audio, SPI and MMC enabled.

I was applying this to -next, are there any other dependencies I need or
anything?

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> One of the biggest roadblocks on the way of S3C64xx to DeviceTree support
> is its DMA driver, which is completely platform-specific and provides
> private API (s3c-dma), not even saying that its design is completely
> against multiplatform-awareness.

I tried to test this on my s3c64xx based system but it gave me a kernel
that didn't boot far enough to give console output (there's some early
init stuff that uses SPI...).  That said, I needed:

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 210a893..0f49707 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
 	int ret;
 
 	if (plchan->mux_use++ == 0 && pd->get_signal) {
-		ret = pd->get_signal(plchan->cd);
+		ret = (pd->get_signal)(plchan->cd);
 		if (ret < 0) {
 			plchan->mux_use = 0;
 			return ret;

to get it to build which makes me suspect the compiler a bit as well...
the system has audio, SPI and MMC enabled.

I was applying this to -next, are there any other dependencies I need or
anything?
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Re: [RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Tomasz Figa]

On Monday 17 of June 2013 16:04:47 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > This patch adds all required platform-specific data and initialization
> > code to support the generic amba-pl08x driver on S3C64xx SoCs.
> > 
> > Also some compatibility definitions are added to make the transition
> > from legacy API to DMA engine easier. The biggest hack here is
> > passing const char * pointers through DMA resource, casted to
> > unsigned long, but this is how Samsung DMA wrappers (used to support
> > both s3c-dma and DMA engine in drivers) is designed.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Patch looks like an OK stepping stone.
> 
> > +static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
> > +                       0x75000000, {IRQ_DMA0},
> > &s3c64xx_dma0_plat_data);
> (...)
> 
> > +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
> > +                       0x75100000, {IRQ_DMA1},
> > &s3c64xx_dma1_plat_data);
> Ah, does this mean the device does not have any AMBA PrimeCell ID
> contents?

Hmm, not really. The ID here is what I copied from PrimeCell ID registers 
and the method of registration is taken from S5PV210. If I remove the 
override, it will read the same value from registers.

> Then use the ID 0x00053080 instead of 0x0a141080
> 
> 0x53 is "S" for Samsung. Variant 0.

Well, that's kind of solution to make sure that it won't conflict with any 
future variant manufactured by ARM, I guess.

Best regards,
Tomasz

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Tomasz Figa]

On Monday 17 of June 2013 16:04:47 Linus Walleij wrote:
> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> 
wrote:
> > This patch adds all required platform-specific data and initialization
> > code to support the generic amba-pl08x driver on S3C64xx SoCs.
> > 
> > Also some compatibility definitions are added to make the transition
> > from legacy API to DMA engine easier. The biggest hack here is
> > passing const char * pointers through DMA resource, casted to
> > unsigned long, but this is how Samsung DMA wrappers (used to support
> > both s3c-dma and DMA engine in drivers) is designed.
> > 
> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
> 
> Patch looks like an OK stepping stone.
> 
> > +static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0x0a141080,
> > +                       0x75000000, {IRQ_DMA0},
> > &s3c64xx_dma0_plat_data);
> (...)
> 
> > +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
> > +                       0x75100000, {IRQ_DMA1},
> > &s3c64xx_dma1_plat_data);
> Ah, does this mean the device does not have any AMBA PrimeCell ID
> contents?

Hmm, not really. The ID here is what I copied from PrimeCell ID registers 
and the method of registration is taken from S5PV210. If I remove the 
override, it will read the same value from registers.

> Then use the ID 0x00053080 instead of 0x0a141080
> 
> 0x53 is "S" for Samsung. Variant 0.

Well, that's kind of solution to make sure that it won't conflict with any 
future variant manufactured by ARM, I guess.

Best regards,
Tomasz

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > support is its DMA driver, which is completely platform-specific and
> > provides private API (s3c-dma), not even saying that its design is
> > completely against multiplatform-awareness.
> 
> I tried to test this on my s3c64xx based system but it gave me a kernel
> that didn't boot far enough to give console output (there's some early
> init stuff that uses SPI...).  That said, I needed:
> 
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index 210a893..0f49707 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> *plchan) int ret;
> 
>  	if (plchan->mux_use++ == 0 && pd->get_signal) {
> -		ret = pd->get_signal(plchan->cd);
> +		ret = (pd->get_signal)(plchan->cd);

Hmm, that's strange. The former is a completely valid piece of code...

>  		if (ret < 0) {
>  			plchan->mux_use = 0;
>  			return ret;
> 
> to get it to build which makes me suspect the compiler a bit as well...
> the system has audio, SPI and MMC enabled.
> 
> I was applying this to -next, are there any other dependencies I need or
> anything?

Hmm, I've been testing this on top of my common clock framework and device 
tree patches, but I don't think this had any effect. Did you add necessary 
clkdev lookups to the clock driver?

In Samsung CCF alias notation it looks like this:

+       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
+       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

Not sure how hard it will be to add such lookups to the old clock driver, 
though.

I will test this applied directly on top of current linux-next when I find 
some time, but for now you might check out my v3.11-devel branch on my 
github:

https://github.com/tom3q/linux.git

Best regards,
Tomasz

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > support is its DMA driver, which is completely platform-specific and
> > provides private API (s3c-dma), not even saying that its design is
> > completely against multiplatform-awareness.
> 
> I tried to test this on my s3c64xx based system but it gave me a kernel
> that didn't boot far enough to give console output (there's some early
> init stuff that uses SPI...).  That said, I needed:
> 
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index 210a893..0f49707 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> *plchan) int ret;
> 
>  	if (plchan->mux_use++ == 0 && pd->get_signal) {
> -		ret = pd->get_signal(plchan->cd);
> +		ret = (pd->get_signal)(plchan->cd);

Hmm, that's strange. The former is a completely valid piece of code...

>  		if (ret < 0) {
>  			plchan->mux_use = 0;
>  			return ret;
> 
> to get it to build which makes me suspect the compiler a bit as well...
> the system has audio, SPI and MMC enabled.
> 
> I was applying this to -next, are there any other dependencies I need or
> anything?

Hmm, I've been testing this on top of my common clock framework and device 
tree patches, but I don't think this had any effect. Did you add necessary 
clkdev lookups to the clock driver?

In Samsung CCF alias notation it looks like this:

+       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
+       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

Not sure how hard it will be to add such lookups to the old clock driver, 
though.

I will test this applied directly on top of current linux-next when I find 
some time, but for now you might check out my v3.11-devel branch on my 
github:

https://github.com/tom3q/linux.git

Best regards,
Tomasz

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > support is its DMA driver, which is completely platform-specific and
> > provides private API (s3c-dma), not even saying that its design is
> > completely against multiplatform-awareness.
> 
> I tried to test this on my s3c64xx based system but it gave me a kernel
> that didn't boot far enough to give console output (there's some early
> init stuff that uses SPI...).  That said, I needed:
> 
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index 210a893..0f49707 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> *plchan) int ret;
> 
>  	if (plchan->mux_use++ == 0 && pd->get_signal) {
> -		ret = pd->get_signal(plchan->cd);
> +		ret = (pd->get_signal)(plchan->cd);

Hmm, that's strange. The former is a completely valid piece of code...

>  		if (ret < 0) {
>  			plchan->mux_use = 0;
>  			return ret;
> 
> to get it to build which makes me suspect the compiler a bit as well...
> the system has audio, SPI and MMC enabled.
> 
> I was applying this to -next, are there any other dependencies I need or
> anything?

Hmm, I've been testing this on top of my common clock framework and device 
tree patches, but I don't think this had any effect. Did you add necessary 
clkdev lookups to the clock driver?

In Samsung CCF alias notation it looks like this:

+       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
+       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

Not sure how hard it will be to add such lookups to the old clock driver, 
though.

I will test this applied directly on top of current linux-next when I find 
some time, but for now you might check out my v3.11-devel branch on my 
github:

https://github.com/tom3q/linux.git

Best regards,
Tomasz

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Arnd Bergmann]

On Wednesday 19 June 2013, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > > support is its DMA driver, which is completely platform-specific and
> > > provides private API (s3c-dma), not even saying that its design is
> > > completely against multiplatform-awareness.
> > 
> > I tried to test this on my s3c64xx based system but it gave me a kernel
> > that didn't boot far enough to give console output (there's some early
> > init stuff that uses SPI...).  That said, I needed:
> > 
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index 210a893..0f49707 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> > *plchan) int ret;
> > 
> >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > -             ret = pd->get_signal(plchan->cd);
> > +             ret = (pd->get_signal)(plchan->cd);
> 
> Hmm, that's strange. The former is a completely valid piece of code...

get_signal is a macro defined in include/linux/signal.h. If that header
gets included, neither of the two is valid.

	Arnd

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Arnd Bergmann]

On Wednesday 19 June 2013, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > > support is its DMA driver, which is completely platform-specific and
> > > provides private API (s3c-dma), not even saying that its design is
> > > completely against multiplatform-awareness.
> > 
> > I tried to test this on my s3c64xx based system but it gave me a kernel
> > that didn't boot far enough to give console output (there's some early
> > init stuff that uses SPI...).  That said, I needed:
> > 
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index 210a893..0f49707 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> > *plchan) int ret;
> > 
> >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > -             ret = pd->get_signal(plchan->cd);
> > +             ret = (pd->get_signal)(plchan->cd);
> 
> Hmm, that's strange. The former is a completely valid piece of code...

get_signal is a macro defined in include/linux/signal.h. If that header
gets included, neither of the two is valid.

	Arnd

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Arnd Bergmann]

On Wednesday 19 June 2013, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > On Sun, Jun 16, 2013 at 10:54:07PM +0200, Tomasz Figa wrote:
> > > One of the biggest roadblocks on the way of S3C64xx to DeviceTree
> > > support is its DMA driver, which is completely platform-specific and
> > > provides private API (s3c-dma), not even saying that its design is
> > > completely against multiplatform-awareness.
> > 
> > I tried to test this on my s3c64xx based system but it gave me a kernel
> > that didn't boot far enough to give console output (there's some early
> > init stuff that uses SPI...).  That said, I needed:
> > 
> > diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> > index 210a893..0f49707 100644
> > --- a/drivers/dma/amba-pl08x.c
> > +++ b/drivers/dma/amba-pl08x.c
> > @@ -313,7 +313,7 @@ static int pl08x_request_mux(struct pl08x_dma_chan
> > *plchan) int ret;
> > 
> >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > -             ret = pd->get_signal(plchan->cd);
> > +             ret = (pd->get_signal)(plchan->cd);
> 
> Hmm, that's strange. The former is a completely valid piece of code...

get_signal is a macro defined in include/linux/signal.h. If that header
gets included, neither of the two is valid.

	Arnd

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1448 bytes --]

On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:

> > -		ret = pd->get_signal(plchan->cd);
> > +		ret = (pd->get_signal)(plchan->cd);

> Hmm, that's strange. The former is a completely valid piece of code...

I know, hence...

> > to get it to build which makes me suspect the compiler a bit as well...

...my comment about suspecting the compiler.

> > I was applying this to -next, are there any other dependencies I need or
> > anything?

> Hmm, I've been testing this on top of my common clock framework and device 
> tree patches, but I don't think this had any effect. Did you add necessary 
> clkdev lookups to the clock driver?

No, I didn't - that's most likely it, I didn't really investigate.  I
didn't test the watchdog stuff as the clocks didn't get sent to me.

> In Samsung CCF alias notation it looks like this:

> +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

> Not sure how hard it will be to add such lookups to the old clock driver, 
> though.

It's pretty much the same providing you know which clock needs to be
used.

> I will test this applied directly on top of current linux-next when I find 
> some time, but for now you might check out my v3.11-devel branch on my 
> github:

> https://github.com/tom3q/linux.git

Will try to get round to it.

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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1448 bytes --]

On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:

> > -		ret = pd->get_signal(plchan->cd);
> > +		ret = (pd->get_signal)(plchan->cd);

> Hmm, that's strange. The former is a completely valid piece of code...

I know, hence...

> > to get it to build which makes me suspect the compiler a bit as well...

...my comment about suspecting the compiler.

> > I was applying this to -next, are there any other dependencies I need or
> > anything?

> Hmm, I've been testing this on top of my common clock framework and device 
> tree patches, but I don't think this had any effect. Did you add necessary 
> clkdev lookups to the clock driver?

No, I didn't - that's most likely it, I didn't really investigate.  I
didn't test the watchdog stuff as the clocks didn't get sent to me.

> In Samsung CCF alias notation it looks like this:

> +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

> Not sure how hard it will be to add such lookups to the old clock driver, 
> though.

It's pretty much the same providing you know which clock needs to be
used.

> I will test this applied directly on top of current linux-next when I find 
> some time, but for now you might check out my v3.11-devel branch on my 
> github:

> https://github.com/tom3q/linux.git

Will try to get round to it.

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:

> > -		ret = pd->get_signal(plchan->cd);
> > +		ret = (pd->get_signal)(plchan->cd);

> Hmm, that's strange. The former is a completely valid piece of code...

I know, hence...

> > to get it to build which makes me suspect the compiler a bit as well...

...my comment about suspecting the compiler.

> > I was applying this to -next, are there any other dependencies I need or
> > anything?

> Hmm, I've been testing this on top of my common clock framework and device 
> tree patches, but I don't think this had any effect. Did you add necessary 
> clkdev lookups to the clock driver?

No, I didn't - that's most likely it, I didn't really investigate.  I
didn't test the watchdog stuff as the clocks didn't get sent to me.

> In Samsung CCF alias notation it looks like this:

> +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),

> Not sure how hard it will be to add such lookups to the old clock driver, 
> though.

It's pretty much the same providing you know which clock needs to be
used.

> I will test this applied directly on top of current linux-next when I find 
> some time, but for now you might check out my v3.11-devel branch on my 
> github:

> https://github.com/tom3q/linux.git

Will try to get round to it.
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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Wed, Jun 19, 2013 at 09:01:33PM +0200, Arnd Bergmann wrote:
> On Wednesday 19 June 2013, Tomasz Figa wrote:

> > >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > > -             ret = pd->get_signal(plchan->cd);
> > > +             ret = (pd->get_signal)(plchan->cd);

> > Hmm, that's strange. The former is a completely valid piece of code...

> get_signal is a macro defined in include/linux/signal.h. If that header
> gets included, neither of the two is valid.

Ah, that'll be it.  I'll post a patch to rename...

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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Wed, Jun 19, 2013 at 09:01:33PM +0200, Arnd Bergmann wrote:
> On Wednesday 19 June 2013, Tomasz Figa wrote:

> > >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > > -             ret = pd->get_signal(plchan->cd);
> > > +             ret = (pd->get_signal)(plchan->cd);

> > Hmm, that's strange. The former is a completely valid piece of code...

> get_signal is a macro defined in include/linux/signal.h. If that header
> gets included, neither of the two is valid.

Ah, that'll be it.  I'll post a patch to rename...

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Wed, Jun 19, 2013 at 09:01:33PM +0200, Arnd Bergmann wrote:
> On Wednesday 19 June 2013, Tomasz Figa wrote:

> > >       if (plchan->mux_use++ == 0 && pd->get_signal) {
> > > -             ret = pd->get_signal(plchan->cd);
> > > +             ret = (pd->get_signal)(plchan->cd);

> > Hmm, that's strange. The former is a completely valid piece of code...

> get_signal is a macro defined in include/linux/signal.h. If that header
> gets included, neither of the two is valid.

Ah, that'll be it.  I'll post a patch to rename...
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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:
> On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > > -		ret = pd->get_signal(plchan->cd);
> > > +		ret = (pd->get_signal)(plchan->cd);
> > 
> > Hmm, that's strange. The former is a completely valid piece of code...
> 
> I know, hence...
> 
> > > to get it to build which makes me suspect the compiler a bit as
> > > well...
> 
> ...my comment about suspecting the compiler.
> 
> > > I was applying this to -next, are there any other dependencies I
> > > need or anything?
> > 
> > Hmm, I've been testing this on top of my common clock framework and
> > device tree patches, but I don't think this had any effect. Did you
> > add necessary clkdev lookups to the clock driver?
> 
> No, I didn't - that's most likely it, I didn't really investigate.  I
> didn't test the watchdog stuff as the clocks didn't get sent to me.

I always try to keep you on Cc of my patches for s3c64xx, as you are the 
most active user of this platform (if not the only one other than me) and 
this was the case for clock patches as well, just checked that.

Seems like I forgot to add you to watchdog patches, sorry. But you didn't 
miss anything, since they were rather trivial ones.

> > In Samsung CCF alias notation it looks like this:
> > 
> > +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> > +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
> > 
> > Not sure how hard it will be to add such lookups to the old clock
> > driver, though.
> 
> It's pretty much the same providing you know which clock needs to be
> used.
> 
> > I will test this applied directly on top of current linux-next when I
> > find some time, but for now you might check out my v3.11-devel branch
> > on my github:
> > 
> > https://github.com/tom3q/linux.git
> 
> Will try to get round to it.

OK.

Best regards,
Tomasz

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:
> On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > > -		ret = pd->get_signal(plchan->cd);
> > > +		ret = (pd->get_signal)(plchan->cd);
> > 
> > Hmm, that's strange. The former is a completely valid piece of code...
> 
> I know, hence...
> 
> > > to get it to build which makes me suspect the compiler a bit as
> > > well...
> 
> ...my comment about suspecting the compiler.
> 
> > > I was applying this to -next, are there any other dependencies I
> > > need or anything?
> > 
> > Hmm, I've been testing this on top of my common clock framework and
> > device tree patches, but I don't think this had any effect. Did you
> > add necessary clkdev lookups to the clock driver?
> 
> No, I didn't - that's most likely it, I didn't really investigate.  I
> didn't test the watchdog stuff as the clocks didn't get sent to me.

I always try to keep you on Cc of my patches for s3c64xx, as you are the 
most active user of this platform (if not the only one other than me) and 
this was the case for clock patches as well, just checked that.

Seems like I forgot to add you to watchdog patches, sorry. But you didn't 
miss anything, since they were rather trivial ones.

> > In Samsung CCF alias notation it looks like this:
> > 
> > +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> > +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
> > 
> > Not sure how hard it will be to add such lookups to the old clock
> > driver, though.
> 
> It's pretty much the same providing you know which clock needs to be
> used.
> 
> > I will test this applied directly on top of current linux-next when I
> > find some time, but for now you might check out my v3.11-devel branch
> > on my github:
> > 
> > https://github.com/tom3q/linux.git
> 
> Will try to get round to it.

OK.

Best regards,
Tomasz

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Tomasz Figa]

On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:
> On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> > > -		ret = pd->get_signal(plchan->cd);
> > > +		ret = (pd->get_signal)(plchan->cd);
> > 
> > Hmm, that's strange. The former is a completely valid piece of code...
> 
> I know, hence...
> 
> > > to get it to build which makes me suspect the compiler a bit as
> > > well...
> 
> ...my comment about suspecting the compiler.
> 
> > > I was applying this to -next, are there any other dependencies I
> > > need or anything?
> > 
> > Hmm, I've been testing this on top of my common clock framework and
> > device tree patches, but I don't think this had any effect. Did you
> > add necessary clkdev lookups to the clock driver?
> 
> No, I didn't - that's most likely it, I didn't really investigate.  I
> didn't test the watchdog stuff as the clocks didn't get sent to me.

I always try to keep you on Cc of my patches for s3c64xx, as you are the 
most active user of this platform (if not the only one other than me) and 
this was the case for clock patches as well, just checked that.

Seems like I forgot to add you to watchdog patches, sorry. But you didn't 
miss anything, since they were rather trivial ones.

> > In Samsung CCF alias notation it looks like this:
> > 
> > +       ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
> > +       ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
> > 
> > Not sure how hard it will be to add such lookups to the old clock
> > driver, though.
> 
> It's pretty much the same providing you know which clock needs to be
> used.
> 
> > I will test this applied directly on top of current linux-next when I
> > find some time, but for now you might check out my v3.11-devel branch
> > on my github:
> > 
> > https://github.com/tom3q/linux.git
> 
> Will try to get round to it.

OK.

Best regards,
Tomasz

Re: [RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Linus Walleij]

On Wed, Jun 19, 2013 at 8:23 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Monday 17 of June 2013 16:04:47 Linus Walleij wrote:
>> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com>
> wrote:
>> > +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
>> > +                       0x75100000, {IRQ_DMA1},
>> > &s3c64xx_dma1_plat_data);
>> Ah, does this mean the device does not have any AMBA PrimeCell ID
>> contents?
>
> Hmm, not really. The ID here is what I copied from PrimeCell ID registers
> and the method of registration is taken from S5PV210. If I remove the
> override, it will read the same value from registers.

OK then don't override. Overriding is for hardware which is all zeroes
in these registers.

>> Then use the ID 0x00053080 instead of 0x0a141080
>>
>> 0x53 is "S" for Samsung. Variant 0.
>
> Well, that's kind of solution to make sure that it won't conflict with any
> future variant manufactured by ARM, I guess.

Yeah, but as stated, if the hardware has proper IDs (these are
probably inspired by the PCI vendor/device/revision fields)
then rely on those.

Yours,
Linus Walleij

[RFC PATCH 11/11] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver

[Linus Walleij]

On Wed, Jun 19, 2013 at 8:23 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On Monday 17 of June 2013 16:04:47 Linus Walleij wrote:
>> On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com>
> wrote:
>> > +static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0x0a141080,
>> > +                       0x75100000, {IRQ_DMA1},
>> > &s3c64xx_dma1_plat_data);
>> Ah, does this mean the device does not have any AMBA PrimeCell ID
>> contents?
>
> Hmm, not really. The ID here is what I copied from PrimeCell ID registers
> and the method of registration is taken from S5PV210. If I remove the
> override, it will read the same value from registers.

OK then don't override. Overriding is for hardware which is all zeroes
in these registers.

>> Then use the ID 0x00053080 instead of 0x0a141080
>>
>> 0x53 is "S" for Samsung. Variant 0.
>
> Well, that's kind of solution to make sure that it won't conflict with any
> future variant manufactured by ARM, I guess.

Yeah, but as stated, if the hardware has proper IDs (these are
probably inspired by the PCI vendor/device/revision fields)
then rely on those.

Yours,
Linus Walleij

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 762 bytes --]

On Wed, Jun 19, 2013 at 09:32:44PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:

> > No, I didn't - that's most likely it, I didn't really investigate.  I
> > didn't test the watchdog stuff as the clocks didn't get sent to me.

> I always try to keep you on Cc of my patches for s3c64xx, as you are the 
> most active user of this platform (if not the only one other than me) and 
> this was the case for clock patches as well, just checked that.

Yes, I had the clock patches but they depended on something or other I
think.  I did test a previous verion IIRC.  There are other users I'm
aware of (you can probably take a wild guess where from the board)
though they tend not to be terribly active upstream.

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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 762 bytes --]

On Wed, Jun 19, 2013 at 09:32:44PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:

> > No, I didn't - that's most likely it, I didn't really investigate.  I
> > didn't test the watchdog stuff as the clocks didn't get sent to me.

> I always try to keep you on Cc of my patches for s3c64xx, as you are the 
> most active user of this platform (if not the only one other than me) and 
> this was the case for clock patches as well, just checked that.

Yes, I had the clock patches but they depended on something or other I
think.  I did test a previous verion IIRC.  There are other users I'm
aware of (you can probably take a wild guess where from the board)
though they tend not to be terribly active upstream.

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Wed, Jun 19, 2013 at 09:32:44PM +0200, Tomasz Figa wrote:
> On Wednesday 19 of June 2013 20:22:11 Mark Brown wrote:

> > No, I didn't - that's most likely it, I didn't really investigate.  I
> > didn't test the watchdog stuff as the clocks didn't get sent to me.

> I always try to keep you on Cc of my patches for s3c64xx, as you are the 
> most active user of this platform (if not the only one other than me) and 
> this was the case for clock patches as well, just checked that.

Yes, I had the clock patches but they depended on something or other I
think.  I did test a previous verion IIRC.  There are other users I'm
aware of (you can probably take a wild guess where from the board)
though they tend not to be terribly active upstream.
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RE: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Phil Carmody]

(Apologies if this is mangled, fighting both Outlook and remote desktop :-(
)

linux-kernel-owner@vger.kernel.org wrote on Behalf Of Mark Brown
> On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> 
> > > -		ret = pd->get_signal(plchan->cd);
> > > +		ret = (pd->get_signal)(plchan->cd);
> 
> > Hmm, that's strange. The former is a completely valid piece of
> code...
> 
> I know, hence...
> 
> > > to get it to build which makes me suspect the compiler a bit as
> well...
> 
> ...my comment about suspecting the compiler.

Can you just make that minimal change, and diff the objdump of the two .o's?
It would be worth a bug-report against the toolchain if different code was
being generated. If objdump spews huge numbers of diffs (due to one address
changing and pushing everything else out of kilter), then feel free to
forward both .o's or both objdumps to me, and I can run a script over them,
which knows to ignore unimportant address changes. 

Praying that this mail is readable to you, as it's not readable as I write
it,
Phil

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Phil Carmody]

(Apologies if this is mangled, fighting both Outlook and remote desktop :-(
)

linux-kernel-owner at vger.kernel.org wrote on Behalf Of Mark Brown
> On Wed, Jun 19, 2013 at 08:26:12PM +0200, Tomasz Figa wrote:
> > On Wednesday 19 of June 2013 18:40:47 Mark Brown wrote:
> 
> > > -		ret = pd->get_signal(plchan->cd);
> > > +		ret = (pd->get_signal)(plchan->cd);
> 
> > Hmm, that's strange. The former is a completely valid piece of
> code...
> 
> I know, hence...
> 
> > > to get it to build which makes me suspect the compiler a bit as
> well...
> 
> ...my comment about suspecting the compiler.

Can you just make that minimal change, and diff the objdump of the two .o's?
It would be worth a bug-report against the toolchain if different code was
being generated. If objdump spews huge numbers of diffs (due to one address
changing and pushing everything else out of kilter), then feel free to
forward both .o's or both objdumps to me, and I can run a script over them,
which knows to ignore unimportant address changes. 

Praying that this mail is readable to you, as it's not readable as I write
it,
Phil

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Thu, Jun 20, 2013 at 12:24:47PM +0300, Phil Carmody wrote:

> Can you just make that minimal change, and diff the objdump of the two .o's?
> It would be worth a bug-report against the toolchain if different code was
> being generated. If objdump spews huge numbers of diffs (due to one address
> changing and pushing everything else out of kilter), then feel free to
> forward both .o's or both objdumps to me, and I can run a script over them,
> which knows to ignore unimportant address changes. 

See Arnd's followup - this looks like a collision with the get_signal
macro in signal.h.

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Thu, Jun 20, 2013 at 12:24:47PM +0300, Phil Carmody wrote:

> Can you just make that minimal change, and diff the objdump of the two .o's?
> It would be worth a bug-report against the toolchain if different code was
> being generated. If objdump spews huge numbers of diffs (due to one address
> changing and pushing everything else out of kilter), then feel free to
> forward both .o's or both objdumps to me, and I can run a script over them,
> which knows to ignore unimportant address changes. 

See Arnd's followup - this looks like a collision with the get_signal
macro in signal.h.
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RE: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Phil Carmody]

> -----Original Message-----
> On Thu, Jun 20, 2013 at 12:24:47PM +0300, Phil Carmody wrote:
> > Can you just make that minimal change, and diff the objdump of the
> two .o's?
> > It would be worth a bug-report against the toolchain if different
> code
> > was being generated. If objdump spews huge numbers of diffs (due to
> > one address changing and pushing everything else out of kilter), then
> > feel free to forward both .o's or both objdumps to me, and I can run
> a
> > script over them, which knows to ignore unimportant address changes.
> 
> See Arnd's followup - this looks like a collision with the get_signal
> macro in signal.h.


With my language-lawyer hat on, I'd suggest ``(get_signal)'' to prevent the
macro expansion:

/tmp$ cat crap.c

#define fnlikemacro(foo) foo+

int x(int y) {
  int (fnlikemacro) = y;
  return fnlikemacro(y)(fnlikemacro);
}

/tmp$ gcc -E crap.c

int x(int y) {
  int (fnlikemacro) = y;
  return y+(fnlikemacro);
}

(and yes, that compiles.)

However, it's more tempting (i.e. sensible) to just rename the 
one with the weaker claim to the name.

Phil

[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Phil Carmody]

> -----Original Message-----
> On Thu, Jun 20, 2013 at 12:24:47PM +0300, Phil Carmody wrote:
> > Can you just make that minimal change, and diff the objdump of the
> two .o's?
> > It would be worth a bug-report against the toolchain if different
> code
> > was being generated. If objdump spews huge numbers of diffs (due to
> > one address changing and pushing everything else out of kilter), then
> > feel free to forward both .o's or both objdumps to me, and I can run
> a
> > script over them, which knows to ignore unimportant address changes.
> 
> See Arnd's followup - this looks like a collision with the get_signal
> macro in signal.h.


With my language-lawyer hat on, I'd suggest ``(get_signal)'' to prevent the
macro expansion:

/tmp$ cat crap.c

#define fnlikemacro(foo) foo+

int x(int y) {
  int (fnlikemacro) = y;
  return fnlikemacro(y)(fnlikemacro);
}

/tmp$ gcc -E crap.c

int x(int y) {
  int (fnlikemacro) = y;
  return y+(fnlikemacro);
}

(and yes, that compiles.)

However, it's more tempting (i.e. sensible) to just rename the 
one with the weaker claim to the name.

Phil

Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Thu, Jun 20, 2013 at 02:14:53PM +0300, Phil Carmody wrote:

> With my language-lawyer hat on, I'd suggest ``(get_signal)'' to prevent the
> macro expansion:

Right, which the patch I posted in the mail was doing IIRC.

> However, it's more tempting (i.e. sensible) to just rename the 
> one with the weaker claim to the name.

I sent a patch for that which Vinod has applied.

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Re: [RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

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On Thu, Jun 20, 2013 at 02:14:53PM +0300, Phil Carmody wrote:

> With my language-lawyer hat on, I'd suggest ``(get_signal)'' to prevent the
> macro expansion:

Right, which the patch I posted in the mail was doing IIRC.

> However, it's more tempting (i.e. sensible) to just rename the 
> one with the weaker claim to the name.

I sent a patch for that which Vinod has applied.

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[RFC PATCH 00/11] ARM: s3c64xx: Let amba-pl08x driver handle DMA

[Mark Brown]

On Thu, Jun 20, 2013 at 02:14:53PM +0300, Phil Carmody wrote:

> With my language-lawyer hat on, I'd suggest ``(get_signal)'' to prevent the
> macro expansion:

Right, which the patch I posted in the mail was doing IIRC.

> However, it's more tempting (i.e. sensible) to just rename the 
> one with the weaker claim to the name.

I sent a patch for that which Vinod has applied.
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