[PATCH 1/4] ACPI / PMIC: Add partial support for Cherry Trail Crystal Cove PMIC

[PATCH 1/4] ACPI / PMIC: Add partial support for Cherry Trail Crystal Cove PMIC

[Hans de Goede]

Hi All,

Our current Crystal Cove OpRegion driver is only valid for the
Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
Cherry Trail (CHT) based boards use another variant.

At least the regulator registers are different on CHT and these registers
are one of the things controlled by the custom PMIC OpRegion.

This series renames the existing Crystal Cove driver to make clear that it
is for the BYT variant only and then adds a new (very minimal) Cherry
Trail Crystal Cove driver.

Lee, the changes to the mfd code here are very minimal / trivial, I believe
that it is best if this series is merged in its entirety through Rafael's
tree, can we have your Acked-by for this?

Regards,

Hans

[PATCH 1/4] ACPI / PMIC: Do not register handlers for unhandled OpRegions

[Hans de Goede]

For some model PMIC's used on Intel boards we do not know how to
handle the power or thermal opregions because we have no documentation.

For example in the intel_pmic_chtwc.c driver thermal_table_count is 0,
which means that our PMIC_THERMAL_OPREGION_ID handler will always fail
with AE_BAD_PARAMETER, in this case it is better to simply not register
the handler at all.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/acpi/pmic/intel_pmic.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/acpi/pmic/intel_pmic.c b/drivers/acpi/pmic/intel_pmic.c
index 452041398b34..a371f273f99d 100644
--- a/drivers/acpi/pmic/intel_pmic.c
+++ b/drivers/acpi/pmic/intel_pmic.c
@@ -252,7 +252,7 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
 					struct regmap *regmap,
 					struct intel_pmic_opregion_data *d)
 {
-	acpi_status status;
+	acpi_status status = AE_OK;
 	struct intel_pmic_opregion *opregion;
 	int ret;
 
@@ -270,7 +270,8 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
 	opregion->regmap = regmap;
 	opregion->lpat_table = acpi_lpat_get_conversion_table(handle);
 
-	status = acpi_install_address_space_handler(handle,
+	if (d->power_table_count)
+		status = acpi_install_address_space_handler(handle,
 						    PMIC_POWER_OPREGION_ID,
 						    intel_pmic_power_handler,
 						    NULL, opregion);
@@ -279,7 +280,8 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
 		goto out_error;
 	}
 
-	status = acpi_install_address_space_handler(handle,
+	if (d->thermal_table_count)
+		status = acpi_install_address_space_handler(handle,
 						    PMIC_THERMAL_OPREGION_ID,
 						    intel_pmic_thermal_handler,
 						    NULL, opregion);
@@ -301,12 +303,16 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
 	return 0;
 
 out_remove_thermal_handler:
-	acpi_remove_address_space_handler(handle, PMIC_THERMAL_OPREGION_ID,
-					  intel_pmic_thermal_handler);
+	if (d->thermal_table_count)
+		acpi_remove_address_space_handler(handle,
+						  PMIC_THERMAL_OPREGION_ID,
+						  intel_pmic_thermal_handler);
 
 out_remove_power_handler:
-	acpi_remove_address_space_handler(handle, PMIC_POWER_OPREGION_ID,
-					  intel_pmic_power_handler);
+	if (d->power_table_count)
+		acpi_remove_address_space_handler(handle,
+						  PMIC_POWER_OPREGION_ID,
+						  intel_pmic_power_handler);
 
 out_error:
 	acpi_lpat_free_conversion_table(opregion->lpat_table);
-- 
2.23.0

[PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Hans de Goede]

Our current Crystal Cove OpRegion driver is only valid for the
Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
Cherry Trail (CHT) based boards use another variant.

At least the regulator registers are different on CHT and these registers
are one of the things controlled by the custom PMIC OpRegion.

Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell
configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.

This commit renames the intel_pmic_crc.c driver and the cell to be
prefixed with "byt" to indicate that this code is for BYT devices only.

This is a preparation patch for adding a separate PMIC OpRegion
driver for the CHT variant of the Crystal Cove PMIC (sometimes called
Crystal Cove Plus in Android kernel sources).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/acpi/Kconfig                                       | 7 ++++---
 drivers/acpi/Makefile                                      | 2 +-
 .../acpi/pmic/{intel_pmic_crc.c => intel_pmic_bytcrc.c}    | 4 ++--
 drivers/mfd/intel_soc_pmic_crc.c                           | 2 +-
 4 files changed, 8 insertions(+), 7 deletions(-)
 rename drivers/acpi/pmic/{intel_pmic_crc.c => intel_pmic_bytcrc.c} (98%)

diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index ebe1e9e5fd81..089f7f8e1be7 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -513,11 +513,12 @@ menuconfig PMIC_OPREGION
 	  PMIC chip.
 
 if PMIC_OPREGION
-config CRC_PMIC_OPREGION
-	bool "ACPI operation region support for CrystalCove PMIC"
+config BYTCRC_PMIC_OPREGION
+	bool "ACPI operation region support for Bay Trail Crystal Cove PMIC"
 	depends on INTEL_SOC_PMIC
 	help
-	  This config adds ACPI operation region support for CrystalCove PMIC.
+	  This config adds ACPI operation region support for the Bay Trail
+	  version of the Crystal Cove PMIC.
 
 config XPOWER_PMIC_OPREGION
 	bool "ACPI operation region support for XPower AXP288 PMIC"
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index 5d361e4e3405..ee59b1db69a1 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -109,7 +109,7 @@ obj-$(CONFIG_ACPI_APEI)		+= apei/
 obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o
 
 obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o
-obj-$(CONFIG_CRC_PMIC_OPREGION) += pmic/intel_pmic_crc.o
+obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o
 obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
 obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
 obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
diff --git a/drivers/acpi/pmic/intel_pmic_crc.c b/drivers/acpi/pmic/intel_pmic_bytcrc.c
similarity index 98%
rename from drivers/acpi/pmic/intel_pmic_crc.c
rename to drivers/acpi/pmic/intel_pmic_bytcrc.c
index a0f411a6e5ac..2a692cc4b7ae 100644
--- a/drivers/acpi/pmic/intel_pmic_crc.c
+++ b/drivers/acpi/pmic/intel_pmic_bytcrc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Intel CrystalCove PMIC operation region driver
+ * Intel Bay Trail Crystal Cove PMIC operation region driver
  *
  * Copyright (C) 2014 Intel Corporation. All rights reserved.
  */
@@ -295,7 +295,7 @@ static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
 static struct platform_driver intel_crc_pmic_opregion_driver = {
 	.probe = intel_crc_pmic_opregion_probe,
 	.driver = {
-		.name = "crystal_cove_pmic",
+		.name = "byt_crystal_cove_pmic",
 	},
 };
 builtin_platform_driver(intel_crc_pmic_opregion_driver);
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index b6ab72fa0569..ab09b8225b76 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
 		.resources = gpio_resources,
 	},
 	{
-		.name = "crystal_cove_pmic",
+		.name = "byt_crystal_cove_pmic",
 	},
 	{
 		.name = "crystal_cove_pwm",
-- 
2.23.0

[PATCH 3/4] ACPI / PMIC: Add Cherry Trail Crystal Cove PMIC OpRegion driver

[Hans de Goede]

We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
could be used to get register info for the regulators if we need to
implement regulator support in the future.

For now the sole purpose of this driver is to make
intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
CHT Crystal Cove PMIC.

Specifically this fixes the following MIPI PMIC sequence related errors
on e.g. an Asus T100HA:

[  178.211801] intel_soc_pmic_exec_mipi_pmic_seq_element: No PMIC registered
[  178.211897] [drm:intel_dsi_dcs_init_backlight_funcs [i915]] *ERROR* mipi_exec_pmic failed, error: -6

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/acpi/Kconfig                  |  7 +++++
 drivers/acpi/Makefile                 |  1 +
 drivers/acpi/pmic/intel_pmic_chtcrc.c | 44 +++++++++++++++++++++++++++
 3 files changed, 52 insertions(+)
 create mode 100644 drivers/acpi/pmic/intel_pmic_chtcrc.c

diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 089f7f8e1be7..0f23d8b22c42 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -520,6 +520,13 @@ config BYTCRC_PMIC_OPREGION
 	  This config adds ACPI operation region support for the Bay Trail
 	  version of the Crystal Cove PMIC.
 
+config CHTCRC_PMIC_OPREGION
+	bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
+	depends on INTEL_SOC_PMIC
+	help
+	  This config adds ACPI operation region support for the Cherry Trail
+	  version of the Crystal Cove PMIC.
+
 config XPOWER_PMIC_OPREGION
 	bool "ACPI operation region support for XPower AXP288 PMIC"
 	depends on MFD_AXP20X_I2C && IOSF_MBI=y
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index ee59b1db69a1..68853f23e901 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o
 
 obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o
 obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o
+obj-$(CONFIG_CHTCRC_PMIC_OPREGION) += pmic/intel_pmic_chtcrc.o
 obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
 obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
 obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
diff --git a/drivers/acpi/pmic/intel_pmic_chtcrc.c b/drivers/acpi/pmic/intel_pmic_chtcrc.c
new file mode 100644
index 000000000000..ebf8d3187df1
--- /dev/null
+++ b/drivers/acpi/pmic/intel_pmic_chtcrc.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Cherry Trail Crystal Cove PMIC operation region driver
+ *
+ * Copyright (C) 2019 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#include <linux/acpi.h>
+#include <linux/init.h>
+#include <linux/mfd/intel_soc_pmic.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include "intel_pmic.h"
+
+/*
+ * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
+ * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
+ * Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
+ * could be used to get register info for the regulators if we need to
+ * implement regulator support in the future.
+ *
+ * For now the sole purpose of this driver is to make
+ * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
+ * CHT Crystal Cove PMIC.
+ */
+static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
+	.pmic_i2c_address = 0x6e,
+};
+
+static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev)
+{
+	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
+	return intel_pmic_install_opregion_handler(&pdev->dev,
+			ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
+			&intel_chtcrc_pmic_opregion_data);
+}
+
+static struct platform_driver intel_chtcrc_pmic_opregion_driver = {
+	.probe = intel_chtcrc_pmic_opregion_probe,
+	.driver = {
+		.name = "cht_crystal_cove_pmic",
+	},
+};
+builtin_platform_driver(intel_chtcrc_pmic_opregion_driver);
-- 
2.23.0

[PATCH 4/4] mfd: intel_soc_pmic_crc: Add "cht_crystal_cove_pmic" cell to CHT cells

[Hans de Goede]

Add a "cht_crystal_cove_pmic" cell to the cells for the Cherry Trail
variant of the Crystal Cove PMIC. Adding this cell enables / hooks-up
the new Cherry Trail Crystal Cove PMIC OpRegion driver.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/mfd/intel_soc_pmic_crc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index ab09b8225b76..429efa1f8e55 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -88,6 +88,9 @@ static struct mfd_cell crystal_cove_cht_dev[] = {
 		.num_resources = ARRAY_SIZE(gpio_resources),
 		.resources = gpio_resources,
 	},
+	{
+		.name = "cht_crystal_cove_pmic",
+	},
 	{
 		.name = "crystal_cove_pwm",
 	},
-- 
2.23.0

Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Andy Shevchenko]

On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote:
> Our current Crystal Cove OpRegion driver is only valid for the
> Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
> Cherry Trail (CHT) based boards use another variant.
> 
> At least the regulator registers are different on CHT and these registers
> are one of the things controlled by the custom PMIC OpRegion.
> 
> Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell
> configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
> devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.
> 
> This commit renames the intel_pmic_crc.c driver and the cell to be
> prefixed with "byt" to indicate that this code is for BYT devices only.
> 
> This is a preparation patch for adding a separate PMIC OpRegion
> driver for the CHT variant of the Crystal Cove PMIC (sometimes called
> Crystal Cove Plus in Android kernel sources).

>  .../acpi/pmic/{intel_pmic_crc.c => intel_pmic_bytcrc.c}    | 4 ++--
>  drivers/mfd/intel_soc_pmic_crc.c                           | 2 +-

I would go with previously established pattern, i.e. intel_pmic_bytcc.c.

> +++ b/drivers/mfd/intel_soc_pmic_crc.c
> @@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
>  		.resources = gpio_resources,
>  	},
>  	{
> -		.name = "crystal_cove_pmic",
> +		.name = "byt_crystal_cove_pmic",
>  	},
>  	{
>  		.name = "crystal_cove_pwm",

I'm wondering shouldn't we rename the PWM and GPIO for the sake of consistency?
Yes, if a driver is used on both CHT and BYT, let it provide two names.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 1/4] ACPI / PMIC: Do not register handlers for unhandled OpRegions

[Andy Shevchenko]

On Thu, Oct 24, 2019 at 11:38:24PM +0200, Hans de Goede wrote:
> For some model PMIC's used on Intel boards we do not know how to
> handle the power or thermal opregions because we have no documentation.
> 
> For example in the intel_pmic_chtwc.c driver thermal_table_count is 0,
> which means that our PMIC_THERMAL_OPREGION_ID handler will always fail
> with AE_BAD_PARAMETER, in this case it is better to simply not register
> the handler at all.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/acpi/pmic/intel_pmic.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/acpi/pmic/intel_pmic.c b/drivers/acpi/pmic/intel_pmic.c
> index 452041398b34..a371f273f99d 100644
> --- a/drivers/acpi/pmic/intel_pmic.c
> +++ b/drivers/acpi/pmic/intel_pmic.c
> @@ -252,7 +252,7 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
>  					struct regmap *regmap,
>  					struct intel_pmic_opregion_data *d)
>  {
> -	acpi_status status;
> +	acpi_status status = AE_OK;
>  	struct intel_pmic_opregion *opregion;
>  	int ret;
>  
> @@ -270,7 +270,8 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
>  	opregion->regmap = regmap;
>  	opregion->lpat_table = acpi_lpat_get_conversion_table(handle);
>  
> -	status = acpi_install_address_space_handler(handle,
> +	if (d->power_table_count)
> +		status = acpi_install_address_space_handler(handle,
>  						    PMIC_POWER_OPREGION_ID,
>  						    intel_pmic_power_handler,
>  						    NULL, opregion);
> @@ -279,7 +280,8 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
>  		goto out_error;
>  	}
>  
> -	status = acpi_install_address_space_handler(handle,
> +	if (d->thermal_table_count)
> +		status = acpi_install_address_space_handler(handle,
>  						    PMIC_THERMAL_OPREGION_ID,
>  						    intel_pmic_thermal_handler,
>  						    NULL, opregion);
> @@ -301,12 +303,16 @@ int intel_pmic_install_opregion_handler(struct device *dev, acpi_handle handle,
>  	return 0;
>  
>  out_remove_thermal_handler:
> -	acpi_remove_address_space_handler(handle, PMIC_THERMAL_OPREGION_ID,
> -					  intel_pmic_thermal_handler);
> +	if (d->thermal_table_count)
> +		acpi_remove_address_space_handler(handle,
> +						  PMIC_THERMAL_OPREGION_ID,
> +						  intel_pmic_thermal_handler);
>  
>  out_remove_power_handler:
> -	acpi_remove_address_space_handler(handle, PMIC_POWER_OPREGION_ID,
> -					  intel_pmic_power_handler);
> +	if (d->power_table_count)
> +		acpi_remove_address_space_handler(handle,
> +						  PMIC_POWER_OPREGION_ID,
> +						  intel_pmic_power_handler);
>  
>  out_error:
>  	acpi_lpat_free_conversion_table(opregion->lpat_table);
> -- 
> 2.23.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 3/4] ACPI / PMIC: Add Cherry Trail Crystal Cove PMIC OpRegion driver

[Andy Shevchenko]

On Thu, Oct 24, 2019 at 11:38:26PM +0200, Hans de Goede wrote:
> We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
> code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
> Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
> could be used to get register info for the regulators if we need to
> implement regulator support in the future.
> 
> For now the sole purpose of this driver is to make
> intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
> CHT Crystal Cove PMIC.
> 
> Specifically this fixes the following MIPI PMIC sequence related errors
> on e.g. an Asus T100HA:
> 
> [  178.211801] intel_soc_pmic_exec_mipi_pmic_seq_element: No PMIC registered
> [  178.211897] [drm:intel_dsi_dcs_init_backlight_funcs [i915]] *ERROR* mipi_exec_pmic failed, error: -6
> 

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

as long as name pattern uses "chtcc".


> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/acpi/Kconfig                  |  7 +++++
>  drivers/acpi/Makefile                 |  1 +
>  drivers/acpi/pmic/intel_pmic_chtcrc.c | 44 +++++++++++++++++++++++++++
>  3 files changed, 52 insertions(+)
>  create mode 100644 drivers/acpi/pmic/intel_pmic_chtcrc.c
> 
> diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
> index 089f7f8e1be7..0f23d8b22c42 100644
> --- a/drivers/acpi/Kconfig
> +++ b/drivers/acpi/Kconfig
> @@ -520,6 +520,13 @@ config BYTCRC_PMIC_OPREGION
>  	  This config adds ACPI operation region support for the Bay Trail
>  	  version of the Crystal Cove PMIC.
>  
> +config CHTCRC_PMIC_OPREGION
> +	bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
> +	depends on INTEL_SOC_PMIC
> +	help
> +	  This config adds ACPI operation region support for the Cherry Trail
> +	  version of the Crystal Cove PMIC.
> +
>  config XPOWER_PMIC_OPREGION
>  	bool "ACPI operation region support for XPower AXP288 PMIC"
>  	depends on MFD_AXP20X_I2C && IOSF_MBI=y
> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
> index ee59b1db69a1..68853f23e901 100644
> --- a/drivers/acpi/Makefile
> +++ b/drivers/acpi/Makefile
> @@ -110,6 +110,7 @@ obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o
>  
>  obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o
>  obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o
> +obj-$(CONFIG_CHTCRC_PMIC_OPREGION) += pmic/intel_pmic_chtcrc.o
>  obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
>  obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
>  obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
> diff --git a/drivers/acpi/pmic/intel_pmic_chtcrc.c b/drivers/acpi/pmic/intel_pmic_chtcrc.c
> new file mode 100644
> index 000000000000..ebf8d3187df1
> --- /dev/null
> +++ b/drivers/acpi/pmic/intel_pmic_chtcrc.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Intel Cherry Trail Crystal Cove PMIC operation region driver
> + *
> + * Copyright (C) 2019 Hans de Goede <hdegoede@redhat.com>
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/init.h>
> +#include <linux/mfd/intel_soc_pmic.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include "intel_pmic.h"
> +
> +/*
> + * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
> + * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
> + * Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
> + * could be used to get register info for the regulators if we need to
> + * implement regulator support in the future.
> + *
> + * For now the sole purpose of this driver is to make
> + * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
> + * CHT Crystal Cove PMIC.
> + */
> +static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
> +	.pmic_i2c_address = 0x6e,
> +};
> +
> +static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev)
> +{
> +	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
> +	return intel_pmic_install_opregion_handler(&pdev->dev,
> +			ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
> +			&intel_chtcrc_pmic_opregion_data);
> +}
> +
> +static struct platform_driver intel_chtcrc_pmic_opregion_driver = {
> +	.probe = intel_chtcrc_pmic_opregion_probe,
> +	.driver = {
> +		.name = "cht_crystal_cove_pmic",
> +	},
> +};
> +builtin_platform_driver(intel_chtcrc_pmic_opregion_driver);
> -- 
> 2.23.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 4/4] mfd: intel_soc_pmic_crc: Add "cht_crystal_cove_pmic" cell to CHT cells

[Andy Shevchenko]

On Thu, Oct 24, 2019 at 11:38:27PM +0200, Hans de Goede wrote:
> Add a "cht_crystal_cove_pmic" cell to the cells for the Cherry Trail
> variant of the Crystal Cove PMIC. Adding this cell enables / hooks-up
> the new Cherry Trail Crystal Cove PMIC OpRegion driver.
> 

The code below is fine, although same wondering about naming scheme for PWM /
GPIO.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/intel_soc_pmic_crc.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
> index ab09b8225b76..429efa1f8e55 100644
> --- a/drivers/mfd/intel_soc_pmic_crc.c
> +++ b/drivers/mfd/intel_soc_pmic_crc.c
> @@ -88,6 +88,9 @@ static struct mfd_cell crystal_cove_cht_dev[] = {
>  		.num_resources = ARRAY_SIZE(gpio_resources),
>  		.resources = gpio_resources,
>  	},
> +	{
> +		.name = "cht_crystal_cove_pmic",
> +	},
>  	{
>  		.name = "crystal_cove_pwm",
>  	},
> -- 
> 2.23.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Andy Shevchenko]

On Fri, Oct 25, 2019 at 10:41:54AM +0300, Andy Shevchenko wrote:
> On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote:
> > Our current Crystal Cove OpRegion driver is only valid for the
> > Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
> > Cherry Trail (CHT) based boards use another variant.
> > 
> > At least the regulator registers are different on CHT and these registers
> > are one of the things controlled by the custom PMIC OpRegion.
> > 
> > Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell
> > configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
> > devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.
> > 
> > This commit renames the intel_pmic_crc.c driver and the cell to be
> > prefixed with "byt" to indicate that this code is for BYT devices only.
> > 
> > This is a preparation patch for adding a separate PMIC OpRegion
> > driver for the CHT variant of the Crystal Cove PMIC (sometimes called
> > Crystal Cove Plus in Android kernel sources).
> 
> >  .../acpi/pmic/{intel_pmic_crc.c => intel_pmic_bytcrc.c}    | 4 ++--
> >  drivers/mfd/intel_soc_pmic_crc.c                           | 2 +-
> 
> I would go with previously established pattern, i.e. intel_pmic_bytcc.c.

That said you may use mine
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> 
> > +++ b/drivers/mfd/intel_soc_pmic_crc.c
> > @@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
> >  		.resources = gpio_resources,
> >  	},
> >  	{
> > -		.name = "crystal_cove_pmic",
> > +		.name = "byt_crystal_cove_pmic",
> >  	},
> >  	{
> >  		.name = "crystal_cove_pwm",
> 
> I'm wondering shouldn't we rename the PWM and GPIO for the sake of consistency?
> Yes, if a driver is used on both CHT and BYT, let it provide two names.
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Hans de Goede]

Hi,

On 25-10-2019 09:41, Andy Shevchenko wrote:
> On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote:
>> Our current Crystal Cove OpRegion driver is only valid for the
>> Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
>> Cherry Trail (CHT) based boards use another variant.
>>
>> At least the regulator registers are different on CHT and these registers
>> are one of the things controlled by the custom PMIC OpRegion.
>>
>> Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell
>> configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
>> devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.
>>
>> This commit renames the intel_pmic_crc.c driver and the cell to be
>> prefixed with "byt" to indicate that this code is for BYT devices only.
>>
>> This is a preparation patch for adding a separate PMIC OpRegion
>> driver for the CHT variant of the Crystal Cove PMIC (sometimes called
>> Crystal Cove Plus in Android kernel sources).
> 
>>   .../acpi/pmic/{intel_pmic_crc.c => intel_pmic_bytcrc.c}    | 4 ++--
>>   drivers/mfd/intel_soc_pmic_crc.c                           | 2 +-
> 
> I would go with previously established pattern, i.e. intel_pmic_bytcc.c.

Well that would be consistent with the chtwc for the Whiskey Cove, but
Crystal Cove related files are shortened to crc in many places already:

Filenames before this patch:
drivers/acpi/pmic/intel_pmic_crc.c
drivers/pwm/pwm-crc.c
drivers/mfd/intel_soc_pmic_crc.c

And to me "cc" stands for the Type-C cc lines, or for Cc: from email,
so IMHO it is best to stick with crc here.

>> +++ b/drivers/mfd/intel_soc_pmic_crc.c
>> @@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
>>   		.resources = gpio_resources,
>>   	},
>>   	{
>> -		.name = "crystal_cove_pmic",
>> +		.name = "byt_crystal_cove_pmic",
>>   	},
>>   	{
>>   		.name = "crystal_cove_pwm",
> 
> I'm wondering shouldn't we rename the PWM and GPIO for the sake of consistency?
> Yes, if a driver is used on both CHT and BYT, let it provide two names.

I believe it is fine to keep the blocks which are identical between
the 2 versions as just "crystal_cove_foo", but renaming them is fine with me
too, but that follows outside the scope of this series and should be
done in a follow-up series IMHO.

Regards,

Hans

Re: [PATCH 3/4] ACPI / PMIC: Add Cherry Trail Crystal Cove PMIC OpRegion driver

[Hans de Goede]

Hi,

On 25-10-2019 09:45, Andy Shevchenko wrote:
> On Thu, Oct 24, 2019 at 11:38:26PM +0200, Hans de Goede wrote:
>> We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
>> code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
>> Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
>> could be used to get register info for the regulators if we need to
>> implement regulator support in the future.
>>
>> For now the sole purpose of this driver is to make
>> intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
>> CHT Crystal Cove PMIC.
>>
>> Specifically this fixes the following MIPI PMIC sequence related errors
>> on e.g. an Asus T100HA:
>>
>> [  178.211801] intel_soc_pmic_exec_mipi_pmic_seq_element: No PMIC registered
>> [  178.211897] [drm:intel_dsi_dcs_init_backlight_funcs [i915]] *ERROR* mipi_exec_pmic failed, error: -6
>>
> 
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> as long as name pattern uses "chtcc".

As I already replied to your other similar remark, I would really like to
stick with crc, crc to me means either crystal-cove or well a crc, cc triggers
different associations in my mind. Also other crystal-cove files also use crc
in their filename. Or alternatively we could just write out crystalcove like the
gpio driver does: drivers/gpio/gpio-crystalcove.c

Regards,

Hans



> 
> 
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>>   drivers/acpi/Kconfig                  |  7 +++++
>>   drivers/acpi/Makefile                 |  1 +
>>   drivers/acpi/pmic/intel_pmic_chtcrc.c | 44 +++++++++++++++++++++++++++
>>   3 files changed, 52 insertions(+)
>>   create mode 100644 drivers/acpi/pmic/intel_pmic_chtcrc.c
>>
>> diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
>> index 089f7f8e1be7..0f23d8b22c42 100644
>> --- a/drivers/acpi/Kconfig
>> +++ b/drivers/acpi/Kconfig
>> @@ -520,6 +520,13 @@ config BYTCRC_PMIC_OPREGION
>>   	  This config adds ACPI operation region support for the Bay Trail
>>   	  version of the Crystal Cove PMIC.
>>   
>> +config CHTCRC_PMIC_OPREGION
>> +	bool "ACPI operation region support for Cherry Trail Crystal Cove PMIC"
>> +	depends on INTEL_SOC_PMIC
>> +	help
>> +	  This config adds ACPI operation region support for the Cherry Trail
>> +	  version of the Crystal Cove PMIC.
>> +
>>   config XPOWER_PMIC_OPREGION
>>   	bool "ACPI operation region support for XPower AXP288 PMIC"
>>   	depends on MFD_AXP20X_I2C && IOSF_MBI=y
>> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
>> index ee59b1db69a1..68853f23e901 100644
>> --- a/drivers/acpi/Makefile
>> +++ b/drivers/acpi/Makefile
>> @@ -110,6 +110,7 @@ obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o
>>   
>>   obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o
>>   obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o
>> +obj-$(CONFIG_CHTCRC_PMIC_OPREGION) += pmic/intel_pmic_chtcrc.o
>>   obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o
>>   obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o
>>   obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o
>> diff --git a/drivers/acpi/pmic/intel_pmic_chtcrc.c b/drivers/acpi/pmic/intel_pmic_chtcrc.c
>> new file mode 100644
>> index 000000000000..ebf8d3187df1
>> --- /dev/null
>> +++ b/drivers/acpi/pmic/intel_pmic_chtcrc.c
>> @@ -0,0 +1,44 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Intel Cherry Trail Crystal Cove PMIC operation region driver
>> + *
>> + * Copyright (C) 2019 Hans de Goede <hdegoede@redhat.com>
>> + */
>> +
>> +#include <linux/acpi.h>
>> +#include <linux/init.h>
>> +#include <linux/mfd/intel_soc_pmic.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include "intel_pmic.h"
>> +
>> +/*
>> + * We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
>> + * code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
>> + * Cove Plus" PMIC and talks about Cherry Trail, so presuambly that one
>> + * could be used to get register info for the regulators if we need to
>> + * implement regulator support in the future.
>> + *
>> + * For now the sole purpose of this driver is to make
>> + * intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
>> + * CHT Crystal Cove PMIC.
>> + */
>> +static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
>> +	.pmic_i2c_address = 0x6e,
>> +};
>> +
>> +static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev)
>> +{
>> +	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
>> +	return intel_pmic_install_opregion_handler(&pdev->dev,
>> +			ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
>> +			&intel_chtcrc_pmic_opregion_data);
>> +}
>> +
>> +static struct platform_driver intel_chtcrc_pmic_opregion_driver = {
>> +	.probe = intel_chtcrc_pmic_opregion_probe,
>> +	.driver = {
>> +		.name = "cht_crystal_cove_pmic",
>> +	},
>> +};
>> +builtin_platform_driver(intel_chtcrc_pmic_opregion_driver);
>> -- 
>> 2.23.0
>>
> 

Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Andy Shevchenko]

On Fri, Oct 25, 2019 at 10:59:06AM +0200, Hans de Goede wrote:
> On 25-10-2019 09:41, Andy Shevchenko wrote:
> > On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote:

> > I would go with previously established pattern, i.e. intel_pmic_bytcc.c.

> Well that would be consistent with the chtwc for the Whiskey Cove, but
> Crystal Cove related files are shortened to crc in many places already:
> 
> Filenames before this patch:
> drivers/acpi/pmic/intel_pmic_crc.c
> drivers/pwm/pwm-crc.c
> drivers/mfd/intel_soc_pmic_crc.c
> 
> And to me "cc" stands for the Type-C cc lines, or for Cc: from email,
> so IMHO it is best to stick with crc here.

Okay, let's do an exception here due to the fact the code and name already
exists and spreads enough thru sources.

It means you may use mine tags.

> > I'm wondering shouldn't we rename the PWM and GPIO for the sake of consistency?
> > Yes, if a driver is used on both CHT and BYT, let it provide two names.
> 
> I believe it is fine to keep the blocks which are identical between
> the 2 versions as just "crystal_cove_foo", but renaming them is fine with me
> too, but that follows outside the scope of this series and should be
> done in a follow-up series IMHO.

True.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 3/4] ACPI / PMIC: Add Cherry Trail Crystal Cove PMIC OpRegion driver

[Andy Shevchenko]

On Fri, Oct 25, 2019 at 11:06:40AM +0200, Hans de Goede wrote:
> On 25-10-2019 09:45, Andy Shevchenko wrote:
> > On Thu, Oct 24, 2019 at 11:38:26PM +0200, Hans de Goede wrote:

> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > 
> > as long as name pattern uses "chtcc".
> 
> As I already replied to your other similar remark, I would really like to
> stick with crc, crc to me means either crystal-cove or well a crc, cc triggers
> different associations in my mind. Also other crystal-cove files also use crc
> in their filename.

Okay, let's stick with crc for this one.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/4] ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver

[Rafael J. Wysocki]

On Fri, Oct 25, 2019 at 11:33 AM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> On Fri, Oct 25, 2019 at 10:59:06AM +0200, Hans de Goede wrote:
> > On 25-10-2019 09:41, Andy Shevchenko wrote:
> > > On Thu, Oct 24, 2019 at 11:38:25PM +0200, Hans de Goede wrote:
>
> > > I would go with previously established pattern, i.e. intel_pmic_bytcc.c.
>
> > Well that would be consistent with the chtwc for the Whiskey Cove, but
> > Crystal Cove related files are shortened to crc in many places already:
> >
> > Filenames before this patch:
> > drivers/acpi/pmic/intel_pmic_crc.c
> > drivers/pwm/pwm-crc.c
> > drivers/mfd/intel_soc_pmic_crc.c
> >
> > And to me "cc" stands for the Type-C cc lines, or for Cc: from email,
> > so IMHO it is best to stick with crc here.
>
> Okay, let's do an exception here due to the fact the code and name already
> exists and spreads enough thru sources.
>
> It means you may use mine tags.

OK, applying the series as 5.5 material, thanks!

Re: [PATCH 4/4] mfd: intel_soc_pmic_crc: Add "cht_crystal_cove_pmic" cell to CHT cells

[Lee Jones]

On Thu, 24 Oct 2019, Hans de Goede wrote:

> Add a "cht_crystal_cove_pmic" cell to the cells for the Cherry Trail
> variant of the Crystal Cove PMIC. Adding this cell enables / hooks-up
> the new Cherry Trail Crystal Cove PMIC OpRegion driver.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/intel_soc_pmic_crc.c | 3 +++
>  1 file changed, 3 insertions(+)

Applied, thanks.

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 4/4] mfd: intel_soc_pmic_crc: Add "cht_crystal_cove_pmic" cell to CHT cells

[Rafael J. Wysocki]

On Friday, November 1, 2019 10:01:11 AM CET Lee Jones wrote:
> On Thu, 24 Oct 2019, Hans de Goede wrote:
> 
> > Add a "cht_crystal_cove_pmic" cell to the cells for the Cherry Trail
> > variant of the Crystal Cove PMIC. Adding this cell enables / hooks-up
> > the new Cherry Trail Crystal Cove PMIC OpRegion driver.
> > 
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > ---
> >  drivers/mfd/intel_soc_pmic_crc.c | 3 +++
> >  1 file changed, 3 insertions(+)
> 
> Applied, thanks.

OK, I need to drop it then, thanks!