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From: Michal Simek <michal.simek@xilinx.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full region
Date: Mon, 10 Jul 2017 09:33:49 +0200	[thread overview]
Message-ID: <2356ae68-a91b-e4cb-19c4-4363ef795f5a@xilinx.com> (raw)
In-Reply-To: <CAAtXAHfXHLUVr==RkE+7BWvHwMjFjqZ2xZgjAL9ifkZTRLU_7g@mail.gmail.com>

On 29.6.2017 19:38, Moritz Fischer wrote:
> Hi Michal,
> 
> can you / did you send this to the kernel ML, too?

We need to send fpga manager driver first but yes we will do it.

> 
> On Thu, Jun 29, 2017 at 3:14 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This will simplify dt overlay structure for the whole PL.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>

Thanks,
Michal

      reply	other threads:[~2017-07-10  7:33 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29 10:14 [U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full region Michal Simek
2017-06-29 17:38 ` Moritz Fischer
2017-07-10  7:33   ` Michal Simek [this message]

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