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From: duckycool <duckycool@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Please help for Data TLB Error in MPC8544
Date: Thu, 21 May 2009 06:45:02 -0700 (PDT)	[thread overview]
Message-ID: <23653353.post@talk.nabble.com> (raw)


Hi all,
My board can't boot normally, and I found it just hang in data tlb error
through the system.map.
Could any one help for this?
Some regisers are as below:
============================================
DEAR: 0xf400fff0 (L1 init ram base address is 0xf4010000)
IVPR : 0xfff80000 , IVPR3: 0x000004000
EELADR: 0xf4010000 , CSn_BNDS: all 0x00000000 (I think SPD of DDR is not
found yet)
L2MMU_TLB0 : 84000000 51000000 ff7000000 ff7000000 (CCSR is not relocated to
0xe0000000 yet)
============================================

The TLB1 registers from CodeWarrior is as below:
=================================================
L2MMU_CAM0 600007CA 1C080000 FFC00000 FFC000001 (boot flash, 4M)
L2MMU_CAM1 A0007FCA 1C080000 80000000 800000001 (PCIE, 1G)
L2MMU_CAM2 90003FCA 1C080000 C0000000 C00000001 (PCI, 256M)
L2MMU_CAM3 90003FCA 1C080000 D0000000 D00000001 (PCI, 256M)
L2MMU_CAM4 80001FCA 1C080000 E0000000 E00000001 (CCSR, 64M)
L2MMU_CAM5 80001FCA 1C080000 F0000000 F00000001 (?? , 64M)
L2MMU_CAM6 300000CA 18080000 FF040000 FF0400001 (NAND, 64K)
L2MMU_CAM7 20000042 18080000 FF010000 FF0100001 (NAND, 16K)
L2MMU_CAM8 20000042 18080000 FF050000 FF0500001 (NAND, 16K)
L2MMU_CAM9 C87FD651 EB40000D 27DE6000 2397E000
L2MMU_CAM10 D0E2E2DF EB680009 B494F000 8F634000
L2MMU_CAM11 00FC8DCA 5A11000D BCB9B000 77EF6000
L2MMU_CAM12 300000CA 18080000 FF000000 FF000001 (NAND, 64K)
L2MMU_CAM13 D891AFD8 18180002 50A70000 F7AB6000
L2MMU_CAM14 E0F6AE97 DA390009 F5DF6000 4F425000
L2MMU_CAM15 D8EFEF88 C750000F AEBA7000 3229F000
===================================================

And this is my init.s below:
==================================================================
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>

#define LAWAR_TRGT_PCI1		0x00000000
#define LAWAR_TRGT_PCIE1	             0x00200000
#define LAWAR_TRGT_PCIE2	             0x00100000
#define LAWAR_TRGT_PCIE3	             0x00300000
#define LAWAR_TRGT_LBC		0x00400000
#define LAWAR_TRGT_DDR		0x00f00000

#define	entry_start \
	mflr	r1	;	\
	bl	0f	;

#define	entry_end \
0:	mflr	r0	;	\
	mtlr	r1	;	\
	blr		;


	.section	.bootpg, "ax"
	.globl	tlb1_entry
tlb1_entry:
	entry_start

	/*
	 * Number of TLB0 and TLB1 entries in the following table
	 */
	.long (2f-1f)/16
1:
	/*
	 * TLB0		4K	Non-cacheable, guarded
	 * 0xff700000	4K	Initial CCSRBAR mapping
	 *
	 * This ends up at a TLB0 Index==0 entry, and must not collide
	 * with other TLB0 Entries.
	 */
	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB0		16K	Cacheable, guarded
	 * Temporary Global data for initialization
	 *
	 * Use four 4K TLB0 entries.  These entries must be cacheable
	 * as they provide the bootstrap memory before the memory
	 * controler and real memory have been configured.
	 *
	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
	 * and must not collide with other TLB0 entries.
	 */
	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 *
1024),0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 *
1024),0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 *
1024),0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 *
1024),0,0,0,0,0,1,0,1,0,1)


	/*
	 * TLB 0:	4M	Non-cacheable, guarded
	 * 0xffc00000	4M	Covers FLASH at 0xFFC00000
	 * Out of reset this entry is only 4K.
	 */
	.long TLB1_MAS0(1, 0, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 1:	1G	Non-cacheable, guarded
	 * 0x80000000	1G	PCIE  8,9,a,b
	 */
	.long TLB1_MAS0(1, 1, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),0,0,0,0,0,1,0,1,0,1)
	

	/*
	 * TLB 2:	256M	Non-cacheable, guarded
	 */
	.long TLB1_MAS0(1, 2, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS),0,0,0,0,0,1,0,1,0,1)
	 

	/*
	 * TLB 3:	256M	Non-cacheable, guarded
	 */
	.long TLB1_MAS0(1, 3, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS +
0x10000000),0,0,0,0,0,1,0,1,0,1)
	

	/*
	 * TLB 4:	64M	Non-cacheable, guarded
	 * 0xe000_0000	1M	CCSRBAR
	 * 0xe100_0000	255M	PCI IO range
	 */
	.long TLB1_MAS0(1, 4, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
	

	/*
	 * TLB 5:	64M	Non-cacheable, non-guarded , reserve from MPC8544DS (don't
know what is                                     it for)
	 */
	.long TLB1_MAS0(1, 5, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(0xf0000000), 0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(0xf0000000), 0,0,0,0,0,1,0,1,0,1)
	 

	/*
	 * TLB 6:	64K	Non-cacheable, guarded
	 * 0xff040000	64K	1G NAND flash 2 area 1 0xff040000
	 */
	.long TLB1_MAS0(1, 6, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
	.long TLB1_MAS2(E500_TLB_EPN(0xff040000), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(0xff040000), 0,0,0,0,0,0,0,1,0,1)
	

	/*
	 * TLB 7:	16K	Non-cacheable, guarded
	 * 0xff010000	16K	1G NAND flash 1 area 2 0xff010000
	 */
	.long TLB1_MAS0(1, 7, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
	.long TLB1_MAS2(E500_TLB_EPN(0xff010000), 0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(0xff010000), 0,0,0,0,0,0,0,1,0,1)
	

	/*
	 * TLB 8:	16K	Non-cacheable, guarded
	 * 0xff050000	16K	1G NAND flash 2 area 2 0xff050000
	 */
	.long TLB1_MAS0(1, 8, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
	.long TLB1_MAS2(E500_TLB_EPN(0xff050000), 0,0,0,0,0,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(0xff050000), 0,0,0,0,0,0,0,1,0,1)
	 

	/*
	 * TLB 12:	64K	Non-cacheable, guarded
	 * 0xff000000	64K	1G NAND flash 1 area 1 0xff000000
	 */
	.long TLB1_MAS0(1, 12, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
	.long TLB1_MAS2(E500_TLB_EPN(0xff000000), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(0xff000000), 0,0,0,0,0,0,0,1,0,1)
	 
2:
	entry_end

/*
 * LAW(Local Access Window) configuration:
 */

	.section .bootpg, "ax"
	.globl	law_entry
law_entry:
	entry_start

	.long (4f-3f)/8
3:
	.long	0
	.long	LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)

	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)

	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)

	.long	(0xf0000000>>12) & 0xfffff
	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)

	.long	0
	.long	0

	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_32G)
4:
	entry_end
==============================================================================

What I think the problem might be
1. I didn't access the SPD to initial DDR , so failed ?
2. The TLB1_5 should take away ? 
3. I shall add one more TLB for DDR ? 
4. The real problem is not related with any above, and I shall post the
other regisers for check ?? 

Thanks.

-- 
View this message in context: http://www.nabble.com/Please-help-for-Data-TLB-Error-in-MPC8544-tp23653353p23653353.html
Sent from the Uboot - Users mailing list archive at Nabble.com.

             reply	other threads:[~2009-05-21 13:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-21 13:45 duckycool [this message]
2009-05-22  1:24 ` [U-Boot] Please help for Data TLB Error in MPC8544 Liu Dave-R63238
2009-05-22 15:20   ` duckycool
2009-05-25  5:38     ` Liu Dave-R63238
2009-05-26 16:21       ` duckycool

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