From: Liu Dave-R63238 <DaveLiu@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Please help for Data TLB Error in MPC8544
Date: Mon, 25 May 2009 13:38:40 +0800 [thread overview]
Message-ID: <D7CCA83BB0796C49BC0BB53B6AB12089348F1C@zch01exm21.fsl.freescale.net> (raw)
In-Reply-To: <23672726.post@talk.nabble.com>
> >EELADR - 0XF4010000, it is INIT_RAM address, why the
> transaction with
> >address(0xF4010000) go to system bus?
> >It should keep in the cache due to cache lock, never out to
> system bus.
>
> I don't know why... and it just happened.... shall I allocate
> a entry of tlb for it?? or cover it in some space ?
Not need.
> A quick question is, there is a FPGA(actel pixis) in
> mpc8544ds board, and it seems related with system clock ???
> There is no such FPGA in my board, is it the problem??
It is possible to be problem.
> Shall I remove the pixis related code from board.h and
> board.c and try to configure system clock by myself ?? Still
> confusing.....
Yes, remove the pixis related code. Configure the sys clk directly.
Thanks, Dave
next prev parent reply other threads:[~2009-05-25 5:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-21 13:45 [U-Boot] Please help for Data TLB Error in MPC8544 duckycool
2009-05-22 1:24 ` Liu Dave-R63238
2009-05-22 15:20 ` duckycool
2009-05-25 5:38 ` Liu Dave-R63238 [this message]
2009-05-26 16:21 ` duckycool
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