From: Jan Beulich <jbeulich@suse.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 5/6] x86/vpic: issue dpci EOI for cleared pins at ICW1
Date: Tue, 20 Apr 2021 11:32:54 +0200 [thread overview]
Message-ID: <23ceee47-a69d-5aaa-d5ad-e12fae1f62cf@suse.com> (raw)
In-Reply-To: <f20953be-ee22-c336-bca5-8da84af49261@suse.com>
On 26.01.2021 17:57, Jan Beulich wrote:
> On 26.01.2021 14:45, Roger Pau Monne wrote:
>> When pins are cleared from either ISR or IRR as part of the
>> initialization sequence forward the clearing of those pins to the dpci
>> EOI handler, as it is equivalent to an EOI. Not doing so can bring the
>> interrupt controller state out of sync with the dpci handling logic,
>> that expects a notification when a pin has been EOI'ed.
>>
>> Fixes: 7b3cb5e5416 ('IRQ injection changes for HVM PCI passthru.')
>> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
>
> As said before, under the assumption that the clearing of IRR
> and ISR that we do is correct, I agree with the change. I'd
> like to give it some time though before giving my R-b here, for
> the inquiry to hopefully get answered. After all there's still
> the possibility of us needing to instead squash that clearing
> (which then would seem to result in getting things in sync the
> other way around).
Still haven't heard anything, so
Reviewed-by: Jan Beulich <jbeulich@suse.com>
In the worst case we'd need to consider reverting later on.
Jan
next prev parent reply other threads:[~2021-04-20 9:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-26 13:45 [PATCH v3 0/6] x86/intr: HVM guest interrupt handling fixes/cleanup Roger Pau Monne
2021-01-26 13:45 ` [PATCH v3 1/6] x86/vioapic: top word redir entry writes don't trigger interrupts Roger Pau Monne
2021-01-26 15:24 ` Jan Beulich
2021-01-26 13:45 ` [PATCH v3 2/6] x86/vioapic: issue EOI to dpci when switching pin to edge trigger mode Roger Pau Monne
2021-01-26 15:25 ` Jan Beulich
2021-01-26 13:45 ` [PATCH v3 3/6] x86/vpic: force int output to low when in init mode Roger Pau Monne
2021-01-26 16:50 ` Jan Beulich
2021-01-26 13:45 ` [PATCH v3 4/6] x86/vpic: don't trigger unmask event until end of init Roger Pau Monne
2021-01-26 16:53 ` Jan Beulich
2021-01-26 13:45 ` [PATCH v3 5/6] x86/vpic: issue dpci EOI for cleared pins at ICW1 Roger Pau Monne
2021-01-26 16:57 ` Jan Beulich
2021-01-27 9:15 ` Roger Pau Monné
2021-01-27 9:30 ` Jan Beulich
2021-04-20 9:32 ` Jan Beulich [this message]
2021-01-26 13:45 ` [PATCH v3 6/6] x86/dpci: remove the dpci EOI timer Roger Pau Monne
2021-01-26 17:07 ` [PATCH v3 0/6] x86/intr: HVM guest interrupt handling fixes/cleanup Jan Beulich
2021-01-27 9:21 ` Roger Pau Monné
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