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From: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Alexey Firago
	<alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>,
	Geert Uytterhoeven
	<geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	linux-clk <linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH v2 1/3] clk: vc5: Add structure to describe particular chip features
Date: Wed, 5 Apr 2017 16:20:07 +0200	[thread overview]
Message-ID: <23dd9324-ee97-633d-129e-6063af757f47@gmail.com> (raw)
In-Reply-To: <de978809-5bec-d675-1ea3-cc61804e2c61-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>

On 04/05/2017 02:36 PM, Alexey Firago wrote:
> Hi Geert,
> 
> On 05.04.2017 15:15, Geert Uytterhoeven wrote:
>> Hi Alexey,
>>
>> On Wed, Apr 5, 2017 at 1:46 PM, Alexey Firago
>> <alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> wrote:
>>> Introduce vc5_chip_info structure to describe features of a particular
>>> VC5 chip (id, number of FODs, number of outputs, flags).
>>> For now flags are only used to indicate if chip has internal XTAL.
>>> vc5_chip_info is set on probe from the matched of_device_id->data.
>>>
>>> Also add defines to specify maximum number of FODs and clock outputs
>>> supported by the driver.
>>>
>>> With these changes it should be easier to extend driver to support
>>> more VC5 models.
>>>
>>> Signed-off-by: Alexey Firago <alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
>>
>> Thanks for your patch!
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>>
>>> --- a/drivers/clk/clk-versaclock5.c
>>> +++ b/drivers/clk/clk-versaclock5.c
>>> @@ -113,12 +113,30 @@
>>>  #define VC5_MUX_IN_XIN         BIT(0)
>>>  #define VC5_MUX_IN_CLKIN       BIT(1)
>>>
>>> +/* Maximum number of clk_out supported by this driver */
>>> +#define VC5_MAX_CLK_OUT_NUM    3
>>> +
>>> +/* Maximum number of FODs supported by this driver */
>>> +#define VC5_MAX_FOD_NUM        2
>>> +
>>> +/* flags to describe chip features */
>>> +/* chip has built-in oscilator */
>>> +#define VC5_HAS_INTERNAL_XTAL  BIT(0)
>>
>> VC5_HAS_INTERNAL_OSC?
> 
> I'm fine with renaming it, but shouldn't it be consistent with the rest
> of the driver (see "internal-xtal", VC5_XTAL*, etc) and IDT datasheet?
> 

Do you have one with internal ring oscillator or with internal xtal ?
The one I had has internal xtal according to the datasheet.

-- 
Best regards,
Marek Vasut
--
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WARNING: multiple messages have this Message-ID (diff)
From: Marek Vasut <marek.vasut@gmail.com>
To: Alexey Firago <alexey_firago@mentor.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Rob Herring <robh+dt@kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 1/3] clk: vc5: Add structure to describe particular chip features
Date: Wed, 5 Apr 2017 16:20:07 +0200	[thread overview]
Message-ID: <23dd9324-ee97-633d-129e-6063af757f47@gmail.com> (raw)
In-Reply-To: <de978809-5bec-d675-1ea3-cc61804e2c61@mentor.com>

On 04/05/2017 02:36 PM, Alexey Firago wrote:
> Hi Geert,
> 
> On 05.04.2017 15:15, Geert Uytterhoeven wrote:
>> Hi Alexey,
>>
>> On Wed, Apr 5, 2017 at 1:46 PM, Alexey Firago
>> <alexey_firago@mentor.com> wrote:
>>> Introduce vc5_chip_info structure to describe features of a particular
>>> VC5 chip (id, number of FODs, number of outputs, flags).
>>> For now flags are only used to indicate if chip has internal XTAL.
>>> vc5_chip_info is set on probe from the matched of_device_id->data.
>>>
>>> Also add defines to specify maximum number of FODs and clock outputs
>>> supported by the driver.
>>>
>>> With these changes it should be easier to extend driver to support
>>> more VC5 models.
>>>
>>> Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
>>
>> Thanks for your patch!
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>>> --- a/drivers/clk/clk-versaclock5.c
>>> +++ b/drivers/clk/clk-versaclock5.c
>>> @@ -113,12 +113,30 @@
>>>  #define VC5_MUX_IN_XIN         BIT(0)
>>>  #define VC5_MUX_IN_CLKIN       BIT(1)
>>>
>>> +/* Maximum number of clk_out supported by this driver */
>>> +#define VC5_MAX_CLK_OUT_NUM    3
>>> +
>>> +/* Maximum number of FODs supported by this driver */
>>> +#define VC5_MAX_FOD_NUM        2
>>> +
>>> +/* flags to describe chip features */
>>> +/* chip has built-in oscilator */
>>> +#define VC5_HAS_INTERNAL_XTAL  BIT(0)
>>
>> VC5_HAS_INTERNAL_OSC?
> 
> I'm fine with renaming it, but shouldn't it be consistent with the rest
> of the driver (see "internal-xtal", VC5_XTAL*, etc) and IDT datasheet?
> 

Do you have one with internal ring oscillator or with internal xtal ?
The one I had has internal xtal according to the datasheet.

-- 
Best regards,
Marek Vasut

  parent reply	other threads:[~2017-04-05 14:20 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-05 11:46 [PATCH v2 0/3] clk: Add support for IDT 5P49V5935 Alexey Firago
2017-04-05 11:46 ` Alexey Firago
2017-04-05 11:46 ` [PATCH v2 1/3] clk: vc5: Add structure to describe particular chip features Alexey Firago
2017-04-05 11:46   ` Alexey Firago
     [not found]   ` <1491392819-698-2-git-send-email-alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
2017-04-05 12:15     ` Geert Uytterhoeven
2017-04-05 12:15       ` Geert Uytterhoeven
     [not found]       ` <CAMuHMdXEa=1__WMtsRphKbN6h+jVkP7szudENsM3hvGSzDfbwg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05 12:36         ` Alexey Firago
2017-04-05 12:36           ` Alexey Firago
     [not found]           ` <de978809-5bec-d675-1ea3-cc61804e2c61-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
2017-04-05 14:20             ` Marek Vasut [this message]
2017-04-05 14:20               ` Marek Vasut
     [not found]               ` <23dd9324-ee97-633d-129e-6063af757f47-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-04-05 15:09                 ` Alexey Firago
2017-04-05 15:09                   ` Alexey Firago
2017-04-05 11:46 ` [PATCH v2 2/3] clk: vc5: Add bindings for IDT VersaClock 5P49V5935 Alexey Firago
2017-04-05 11:46   ` Alexey Firago
     [not found] ` <1491392819-698-1-git-send-email-alexey_firago-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
2017-04-05 11:46   ` [PATCH v2 3/3] clk: vc5: Add support " Alexey Firago
2017-04-05 11:46     ` Alexey Firago
2017-04-05 12:20     ` Geert Uytterhoeven

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