[PATCH] x86: limit issuing of IBPB during context switch

[PATCH] x86: limit issuing of IBPB during context switch

[Jan Beulich]

When the outgoing vCPU had IBPB issued upon entering Xen there's no
need for a 2nd barrier during context switch.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -2098,7 +2098,8 @@ void context_switch(struct vcpu *prev, s
 
         ctxt_switch_levelling(next);
 
-        if ( opt_ibpb_ctxt_switch && !is_idle_domain(nextd) )
+        if ( opt_ibpb_ctxt_switch && !is_idle_domain(nextd) &&
+             !(prevd->arch.spec_ctrl_flags & SCF_entry_ibpb) )
         {
             static DEFINE_PER_CPU(unsigned int, last);
             unsigned int *last_id = &this_cpu(last);

Re: [PATCH] x86: limit issuing of IBPB during context switch

[Andrew Cooper]

On 25/07/2022 13:09, Jan Beulich wrote:
> When the outgoing vCPU had IBPB issued upon entering Xen there's no
> need for a 2nd barrier during context switch.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

That's already accounted for by opt_ibpb_ctxt_switch conditionally being
not set.

~Andrew

Re: [PATCH] x86: limit issuing of IBPB during context switch

[Jan Beulich]

On 25.07.2022 14:15, Andrew Cooper wrote:
> On 25/07/2022 13:09, Jan Beulich wrote:
>> When the outgoing vCPU had IBPB issued upon entering Xen there's no
>> need for a 2nd barrier during context switch.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> That's already accounted for by opt_ibpb_ctxt_switch conditionally being
> not set.

That option defaults to false only if both PV and HVM have the entry
barrier turned on. In fact, if it wasn't for Dom0 I was first thinking
the global could go away and only the per-domain setting could be
inspected here.

Jan