[PATCH v2 00/23] sunxi: Add and use a pinctrl driver

[PATCH v2 00/23] sunxi: Add and use a pinctrl driver

[Samuel Holland]

This series resolves some longstanding TODOs by implementing a pinctrl
driver for sunxi platforms and converting DM drivers to use it.

Changes in v2:
 - Merge all SoC drivers into one file and one U_BOOT_DRIVER.
 - Add a consumer for the APB bus clock
 - Add support for the F1C100s SoC

Samuel Holland (23):
  sunxi: pinctrl: Create the driver skeleton
  sunxi: pinctrl: Implement pin muxing functions
  sunxi: pinctrl: Implement get_pin_muxing function
  sunxi: pinctrl: Implement pin configuration
  pinctrl: sunxi: Add UART pinmuxes
  sunxi: Skip non-DM UART pin setup when PINCTRL=y
  pinctrl: sunxi: Add sun4i EMAC pinmuxes
  net: sunxi_emac: Remove non-DM pin setup
  pinctrl: sunxi: Add sunxi GMAC pinmuxes
  sunxi: Remove non-DM GMAC pin setup
  pinctrl: sunxi: Add sun8i EMAC pinmuxes
  net: sun8i_emac: Remove non-DM pin setup
  pinctrl: sunxi: Add I2C pinmuxes
  sunxi: Remove options and setup code for I2C2-I2C4
  sunxi: Remove non-DM I2C clock/pin setup from U-Boot
  i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
  i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
  pinctrl: sunxi: Add MMC pinmuxes
  sunxi: Remove non-DM MMC pin setup
  pinctrl: sunxi: Add the A64 PWM pinmux
  pwm: sunxi: Remove non-DM pin setup
  pinctrl: sunxi: Add SPI0 pinmuxes
  spi: sun4i_spi: Remove non-DM pin setup

 MAINTAINERS                            |   1 +
 arch/arm/Kconfig                       |   1 +
 arch/arm/include/asm/arch-sunxi/gpio.h |  17 +-
 arch/arm/include/asm/arch-sunxi/i2c.h  |  11 +-
 arch/arm/mach-sunxi/Kconfig            |  22 -
 arch/arm/mach-sunxi/board.c            |   2 +
 board/sunxi/board.c                    |  67 --
 board/sunxi/gmac.c                     |  55 --
 drivers/gpio/sunxi_gpio.c              | 130 +---
 drivers/i2c/sun6i_p2wi.c               |  12 +-
 drivers/i2c/sun8i_rsb.c                |  46 +-
 drivers/net/sun8i_emac.c               |  90 ---
 drivers/net/sunxi_emac.c               |   7 +-
 drivers/pinctrl/Kconfig                |   1 +
 drivers/pinctrl/Makefile               |   2 +-
 drivers/pinctrl/sunxi/Kconfig          | 127 ++++
 drivers/pinctrl/sunxi/Makefile         |   3 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c  | 887 +++++++++++++++++++++++++
 drivers/pwm/sunxi_pwm.c                |  11 -
 drivers/spi/spi-sunxi.c                |  84 ---
 20 files changed, 1057 insertions(+), 519 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/Kconfig
 create mode 100644 drivers/pinctrl/sunxi/Makefile
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c

-- 
2.33.1

[PATCH v2 01/23] sunxi: pinctrl: Create the driver skeleton

[Samuel Holland]

Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v2:
 - Merge all SoC drivers into one file and one U_BOOT_DRIVER.
 - Add a consumer for the APB bus clock
 - Add support for the F1C100s SoC

 MAINTAINERS                            |   1 +
 arch/arm/Kconfig                       |   1 +
 arch/arm/include/asm/arch-sunxi/gpio.h |   5 +
 drivers/gpio/sunxi_gpio.c              | 130 +--------
 drivers/pinctrl/Kconfig                |   1 +
 drivers/pinctrl/Makefile               |   2 +-
 drivers/pinctrl/sunxi/Kconfig          | 125 +++++++++
 drivers/pinctrl/sunxi/Makefile         |   3 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c  | 362 +++++++++++++++++++++++++
 9 files changed, 501 insertions(+), 129 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/Kconfig
 create mode 100644 drivers/pinctrl/sunxi/Makefile
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 8defd09a64..efee30d134 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -516,6 +516,7 @@ F:	arch/arm/mach-sunxi/
 F:	board/sunxi/
 F:	drivers/clk/sunxi/
 F:	drivers/phy/allwinner/
+F:	drivers/pinctrl/sunxi/
 F:	drivers/video/sunxi/
 
 ARM TEGRA
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4567c183fb..ea3d7ece91 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1072,6 +1072,7 @@ config ARCH_SUNXI
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
+	select PINCTRL
 	select SPECIFY_CONSOLE_INDEX
 	select SPL_SEPARATE_BSS if SPL
 	select SPL_STACK_R if SPL
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index edd0fbf49f..773711b6a3 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -224,6 +224,11 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
 #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
 
+struct sunxi_gpio_plat {
+	struct sunxi_gpio	*regs;
+	char			bank_name[3];
+};
+
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 6c3c10862c..1e85db179a 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -16,15 +16,8 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
-#include <dm/device-internal.h>
 #include <dt-bindings/gpio/gpio.h>
 
-struct sunxi_gpio_plat {
-	struct sunxi_gpio *regs;
-	const char *bank_name;	/* Name of bank, e.g. "B" */
-	int gpio_count;
-};
-
 #if !CONFIG_IS_ENABLED(DM_GPIO)
 static int sunxi_gpio_output(u32 pin, u32 val)
 {
@@ -211,28 +204,6 @@ static const struct dm_gpio_ops gpio_sunxi_ops = {
 	.set_flags		= sunxi_gpio_set_flags,
 };
 
-/**
- * Returns the name of a GPIO bank
- *
- * GPIO banks are named A, B, C, ...
- *
- * @bank:	Bank number (0, 1..n-1)
- * Return: allocated string containing the name
- */
-static char *gpio_bank_name(int bank)
-{
-	char *name;
-
-	name = malloc(3);
-	if (name) {
-		name[0] = 'P';
-		name[1] = 'A' + bank;
-		name[2] = '\0';
-	}
-
-	return name;
-}
-
 static int gpio_sunxi_probe(struct udevice *dev)
 {
 	struct sunxi_gpio_plat *plat = dev_get_plat(dev);
@@ -240,114 +211,17 @@ static int gpio_sunxi_probe(struct udevice *dev)
 
 	/* Tell the uclass how many GPIOs we have */
 	if (plat) {
-		uc_priv->gpio_count = plat->gpio_count;
+		uc_priv->gpio_count = SUNXI_GPIOS_PER_BANK;
 		uc_priv->bank_name = plat->bank_name;
 	}
 
 	return 0;
 }
 
-struct sunxi_gpio_soc_data {
-	int start;
-	int no_banks;
-};
-
-/**
- * We have a top-level GPIO device with no actual GPIOs. It has a child
- * device for each Sunxi bank.
- */
-static int gpio_sunxi_bind(struct udevice *parent)
-{
-	struct sunxi_gpio_soc_data *soc_data =
-		(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
-	struct sunxi_gpio_plat *plat = dev_get_plat(parent);
-	struct sunxi_gpio_reg *ctlr;
-	int bank, ret;
-
-	/* If this is a child device, there is nothing to do here */
-	if (plat)
-		return 0;
-
-	ctlr = dev_read_addr_ptr(parent);
-	for (bank = 0; bank < soc_data->no_banks; bank++) {
-		struct sunxi_gpio_plat *plat;
-		struct udevice *dev;
-
-		plat = calloc(1, sizeof(*plat));
-		if (!plat)
-			return -ENOMEM;
-		plat->regs = &ctlr->gpio_bank[bank];
-		plat->bank_name = gpio_bank_name(soc_data->start + bank);
-		plat->gpio_count = SUNXI_GPIOS_PER_BANK;
-
-		ret = device_bind(parent, parent->driver, plat->bank_name, plat,
-				  dev_ofnode(parent), &dev);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static const struct sunxi_gpio_soc_data soc_data_a_all = {
-	.start = 0,
-	.no_banks = SUNXI_GPIO_BANKS,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_1 = {
-	.start = 'L' - 'A',
-	.no_banks = 1,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_2 = {
-	.start = 'L' - 'A',
-	.no_banks = 2,
-};
-
-static const struct sunxi_gpio_soc_data soc_data_l_3 = {
-	.start = 'L' - 'A',
-	.no_banks = 3,
-};
-
-#define ID(_compat_, _soc_data_) \
-	{ .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
-
-static const struct udevice_id sunxi_gpio_ids[] = {
-	ID("allwinner,sun4i-a10-pinctrl",	a_all),
-	ID("allwinner,sun5i-a10s-pinctrl",	a_all),
-	ID("allwinner,sun5i-a13-pinctrl",	a_all),
-	ID("allwinner,sun50i-h5-pinctrl",	a_all),
-	ID("allwinner,sun6i-a31-pinctrl",	a_all),
-	ID("allwinner,sun6i-a31s-pinctrl",	a_all),
-	ID("allwinner,sun7i-a20-pinctrl",	a_all),
-	ID("allwinner,sun8i-a23-pinctrl",	a_all),
-	ID("allwinner,sun8i-a33-pinctrl",	a_all),
-	ID("allwinner,sun8i-a83t-pinctrl",	a_all),
-	ID("allwinner,sun8i-h3-pinctrl",	a_all),
-	ID("allwinner,sun8i-r40-pinctrl",	a_all),
-	ID("allwinner,sun8i-v3-pinctrl",	a_all),
-	ID("allwinner,sun8i-v3s-pinctrl",	a_all),
-	ID("allwinner,sun9i-a80-pinctrl",	a_all),
-	ID("allwinner,sun50i-a64-pinctrl",	a_all),
-	ID("allwinner,sun50i-h6-pinctrl",	a_all),
-	ID("allwinner,sun50i-h616-pinctrl",	a_all),
-	ID("allwinner,sun6i-a31-r-pinctrl",	l_2),
-	ID("allwinner,sun8i-a23-r-pinctrl",	l_1),
-	ID("allwinner,sun8i-a83t-r-pinctrl",	l_1),
-	ID("allwinner,sun8i-h3-r-pinctrl",	l_1),
-	ID("allwinner,sun9i-a80-r-pinctrl",	l_3),
-	ID("allwinner,sun50i-a64-r-pinctrl",	l_1),
-	ID("allwinner,sun50i-h6-r-pinctrl",	l_2),
-	ID("allwinner,sun50i-h616-r-pinctrl",	l_1),
-	{ }
-};
-
 U_BOOT_DRIVER(gpio_sunxi) = {
 	.name	= "gpio_sunxi",
 	.id	= UCLASS_GPIO,
-	.ops	= &gpio_sunxi_ops,
-	.of_match = sunxi_gpio_ids,
-	.bind	= gpio_sunxi_bind,
 	.probe	= gpio_sunxi_probe,
+	.ops	= &gpio_sunxi_ops,
 };
 #endif /* DM_GPIO */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03946245c7..6a640ba3a2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -332,6 +332,7 @@ source "drivers/pinctrl/nexell/Kconfig"
 source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
+source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index df37c32033..32283ddd88 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
 obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_RMOBILE) += renesas/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
-
+obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
 obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl_pic32.o
 obj-$(CONFIG_PINCTRL_EXYNOS)	+= exynos/
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
new file mode 100644
index 0000000000..96c2f35f3a
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_SUNXI
+
+config PINCTRL_SUNXI
+	select PINCTRL_FULL
+	select PINCTRL_GENERIC
+	bool
+
+config PINCTRL_SUNIV_F1C100S
+	bool "Support for the Allwinner F1C100s PIO"
+	default MACH_SUNIV
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN4I_A10
+	bool "Support for the Allwinner A10 PIO"
+	default MACH_SUN4I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN5I_A13
+	bool "Support for the Allwinner A10s/A13 PIO"
+	default MACH_SUN5I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31
+	bool "Support for the Allwinner A31 PIO"
+	default MACH_SUN6I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31_R
+	bool "Support for the Allwinner A31 R-PIO"
+	default MACH_SUN6I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN7I_A20
+	bool "Support for the Allwinner A20/R40 PIO"
+	default MACH_SUN7I || MACH_SUN8I_R40
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23
+	bool "Support for the Allwinner A23 PIO"
+	default MACH_SUN8I_A23
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23_R
+	bool "Support for the Allwinner A23/A33 R-PIO"
+	default MACH_SUN8I_A23 || MACH_SUN8I_A33
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A33
+	bool "Support for the Allwinner A33 PIO"
+	default MACH_SUN8I_A33
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T
+	bool "Support for the Allwinner A83T PIO"
+	default MACH_SUN8I_A83T
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T_R
+	bool "Support for the Allwinner A83T R-PIO"
+	default MACH_SUN8I_A83T
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3
+	bool "Support for the Allwinner H3 PIO"
+	default MACH_SUN8I_H3
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3_R
+	bool "Support for the Allwinner H3/H5 R-PIO"
+	default MACH_SUN8I_H3 || MACH_SUN50I_H5
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_V3S
+	bool "Support for the Allwinner V3s PIO"
+	default MACH_SUN8I_V3S
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80
+	bool "Support for the Allwinner A80 PIO"
+	default MACH_SUN9I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80_R
+	bool "Support for the Allwinner A80 R-PIO"
+	default MACH_SUN9I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64
+	bool "Support for the Allwinner A64 PIO"
+	default MACH_SUN50I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64_R
+	bool "Support for the Allwinner A64 R-PIO"
+	default MACH_SUN50I
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H5
+	bool "Support for the Allwinner H5 PIO"
+	default MACH_SUN50I_H5
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6
+	bool "Support for the Allwinner H6 PIO"
+	default MACH_SUN50I_H6
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6_R
+	bool "Support for the Allwinner H6 R-PIO"
+	default MACH_SUN50I_H6
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616
+	bool "Support for the Allwinner H616 PIO"
+	default MACH_SUN50I_H616
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616_R
+	bool "Support for the Allwinner H616 R-PIO"
+	default MACH_SUN50I_H616
+	select PINCTRL_SUNXI
+
+endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
new file mode 100644
index 0000000000..6a8c01f372
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y					+= pinctrl-sunxi.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
new file mode 100644
index 0000000000..43bb1ec650
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <malloc.h>
+
+#include <asm/gpio.h>
+
+extern U_BOOT_DRIVER(gpio_sunxi);
+
+struct sunxi_pinctrl_desc {
+	u8					first_bank;
+	u8					num_banks;
+};
+
+struct sunxi_pinctrl_plat {
+	struct sunxi_gpio __iomem *base;
+};
+
+static const struct pinctrl_ops sunxi_pinctrl_ops = {
+	.set_state		= pinctrl_generic_set_state,
+};
+
+static int sunxi_pinctrl_bind(struct udevice *dev)
+{
+	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+	struct sunxi_pinctrl_desc *desc;
+	struct sunxi_gpio_plat *gpio_plat;
+	struct udevice *gpio_dev;
+	int i, ret;
+
+	desc = (void *)dev_get_driver_data(dev);
+	if (!desc)
+		return -EINVAL;
+	dev_set_priv(dev, desc);
+
+	plat->base = dev_read_addr_ptr(dev);
+
+	ret = device_bind_driver_to_node(dev, "gpio_sunxi", dev->name,
+					 dev_ofnode(dev), &gpio_dev);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < desc->num_banks; ++i) {
+		gpio_plat = malloc(sizeof(*gpio_plat));
+		if (!gpio_plat)
+			return -ENOMEM;
+
+		gpio_plat->regs = plat->base + i;
+		gpio_plat->bank_name[0] = 'P';
+		gpio_plat->bank_name[1] = 'A' + desc->first_bank + i;
+		gpio_plat->bank_name[2] = '\0';
+
+		ret = device_bind(gpio_dev, DM_DRIVER_REF(gpio_sunxi),
+				  gpio_plat->bank_name, gpio_plat,
+				  ofnode_null(), NULL);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int sunxi_pinctrl_probe(struct udevice *dev)
+{
+	struct clk *apb_clk;
+
+	apb_clk = devm_clk_get(dev, "apb");
+	if (!IS_ERR(apb_clk))
+		clk_enable(apb_clk);
+
+	return 0;
+}
+
+static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 6,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 9,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 7,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 2,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 9,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 7,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 7,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 3,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 7,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 2,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 9,
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
+static const struct udevice_id sunxi_pinctrl_ids[] = {
+#ifdef CONFIG_PINCTRL_SUNIV_F1C100S
+	{
+		.compatible = "allwinner,suniv-f1c100s-pinctrl",
+		.data = (ulong)&suniv_f1c100s_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN4I_A10
+	{
+		.compatible = "allwinner,sun4i-a10-pinctrl",
+		.data = (ulong)&sun4i_a10_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN5I_A13
+	{
+		.compatible = "allwinner,sun5i-a10s-pinctrl",
+		.data = (ulong)&sun5i_a13_pinctrl_desc,
+	},
+	{
+		.compatible = "allwinner,sun5i-a13-pinctrl",
+		.data = (ulong)&sun5i_a13_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN6I_A31
+	{
+		.compatible = "allwinner,sun6i-a31-pinctrl",
+		.data = (ulong)&sun6i_a31_pinctrl_desc,
+	},
+	{
+		.compatible = "allwinner,sun6i-a31s-pinctrl",
+		.data = (ulong)&sun6i_a31_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN6I_A31_R
+	{
+		.compatible = "allwinner,sun6i-a31-r-pinctrl",
+		.data = (ulong)&sun6i_a31_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN7I_A20
+	{
+		.compatible = "allwinner,sun7i-a20-pinctrl",
+		.data = (ulong)&sun7i_a20_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A23
+	{
+		.compatible = "allwinner,sun8i-a23-pinctrl",
+		.data = (ulong)&sun8i_a23_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A23_R
+	{
+		.compatible = "allwinner,sun8i-a23-r-pinctrl",
+		.data = (ulong)&sun8i_a23_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A33
+	{
+		.compatible = "allwinner,sun8i-a33-pinctrl",
+		.data = (ulong)&sun8i_a33_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A83T
+	{
+		.compatible = "allwinner,sun8i-a83t-pinctrl",
+		.data = (ulong)&sun8i_a83t_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_A83T_R
+	{
+		.compatible = "allwinner,sun8i-a83t-r-pinctrl",
+		.data = (ulong)&sun8i_a83t_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_H3
+	{
+		.compatible = "allwinner,sun8i-h3-pinctrl",
+		.data = (ulong)&sun8i_h3_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_H3_R
+	{
+		.compatible = "allwinner,sun8i-h3-r-pinctrl",
+		.data = (ulong)&sun8i_h3_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN7I_A20
+	{
+		.compatible = "allwinner,sun8i-r40-pinctrl",
+		.data = (ulong)&sun7i_a20_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN8I_V3S
+	{
+		.compatible = "allwinner,sun8i-v3-pinctrl",
+		.data = (ulong)&sun8i_v3s_pinctrl_desc,
+	},
+	{
+		.compatible = "allwinner,sun8i-v3s-pinctrl",
+		.data = (ulong)&sun8i_v3s_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN9I_A80
+	{
+		.compatible = "allwinner,sun9i-a80-pinctrl",
+		.data = (ulong)&sun9i_a80_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN9I_A80_R
+	{
+		.compatible = "allwinner,sun9i-a80-r-pinctrl",
+		.data = (ulong)&sun9i_a80_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A64
+	{
+		.compatible = "allwinner,sun50i-a64-pinctrl",
+		.data = (ulong)&sun50i_a64_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A64_R
+	{
+		.compatible = "allwinner,sun50i-a64-r-pinctrl",
+		.data = (ulong)&sun50i_a64_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H5
+	{
+		.compatible = "allwinner,sun50i-h5-pinctrl",
+		.data = (ulong)&sun50i_h5_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H6
+	{
+		.compatible = "allwinner,sun50i-h6-pinctrl",
+		.data = (ulong)&sun50i_h6_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H6_R
+	{
+		.compatible = "allwinner,sun50i-h6-r-pinctrl",
+		.data = (ulong)&sun50i_h6_r_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H616
+	{
+		.compatible = "allwinner,sun50i-h616-pinctrl",
+		.data = (ulong)&sun50i_h616_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_H616_R
+	{
+		.compatible = "allwinner,sun50i-h616-r-pinctrl",
+		.data = (ulong)&sun50i_h616_r_pinctrl_desc,
+	},
+#endif
+	{}
+};
+
+U_BOOT_DRIVER(sunxi_pinctrl) = {
+	.name		= "sunxi-pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= sunxi_pinctrl_ids,
+	.bind		= sunxi_pinctrl_bind,
+	.probe		= sunxi_pinctrl_probe,
+	.plat_auto	= sizeof(struct sunxi_pinctrl_plat),
+	.ops		= &sunxi_pinctrl_ops,
+};
-- 
2.33.1

[PATCH v2 02/23] sunxi: pinctrl: Implement pin muxing functions

[Samuel Holland]

Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.

We assume all pins associated with a function use the same mux value for
that function. This is generally true within a group of pins on a single
port, but generally false when some peripheral can be muxed to multiple
ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
But all of the port D pins use the same mux value, and so do all of the
port H pins. This applies even when the pins for some function are not
contiguous, and when the lower-numbered mux values are unused. A good
example of both of these cases is SPI0 on most SoCs.

This strategy saves a lot of space (which is especially important for
SPL), but where the mux value for a certain function differs across
ports, it forces us to choose a single port for that function at build
time. Since almost all boards use the default (i.e. reference design)
pin muxes[1], this is unlikely to be a problem.

[1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/Kconfig         |   1 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 227 ++++++++++++++++++++++++++
 2 files changed, 228 insertions(+)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 96c2f35f3a..f4949f89e0 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -5,6 +5,7 @@ if ARCH_SUNXI
 config PINCTRL_SUNXI
 	select PINCTRL_FULL
 	select PINCTRL_GENERIC
+	select PINMUX
 	bool
 
 config PINCTRL_SUNIV_F1C100S
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 43bb1ec650..6ea8245c8e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -12,7 +12,14 @@
 
 extern U_BOOT_DRIVER(gpio_sunxi);
 
+struct sunxi_pinctrl_function {
+	const char	name[sizeof("gpio_out")];
+	u8		mux;
+};
+
 struct sunxi_pinctrl_desc {
+	const struct sunxi_pinctrl_function	*functions;
+	u8					num_functions;
 	u8					first_bank;
 	u8					num_banks;
 };
@@ -21,7 +28,66 @@ struct sunxi_pinctrl_plat {
 	struct sunxi_gpio __iomem *base;
 };
 
+static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
+{
+	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+	return desc->num_banks * SUNXI_GPIOS_PER_BANK;
+}
+
+static const char *sunxi_pinctrl_get_pin_name(struct udevice *dev,
+					      uint pin_selector)
+{
+	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+	static char pin_name[sizeof("PN31")];
+
+	snprintf(pin_name, sizeof(pin_name), "P%c%d",
+		 pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
+		 pin_selector % SUNXI_GPIOS_PER_BANK);
+
+	return pin_name;
+}
+
+static int sunxi_pinctrl_get_functions_count(struct udevice *dev)
+{
+	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+	return desc->num_functions;
+}
+
+static const char *sunxi_pinctrl_get_function_name(struct udevice *dev,
+						   uint func_selector)
+{
+	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+
+	return desc->functions[func_selector].name;
+}
+
+static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
+				    uint func_selector)
+{
+	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
+	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+	int pin	 = pin_selector % SUNXI_GPIOS_PER_BANK;
+
+	debug("set mux: %-4s => %s (%d)\n",
+	      sunxi_pinctrl_get_pin_name(dev, pin_selector),
+	      sunxi_pinctrl_get_function_name(dev, func_selector),
+	      desc->functions[func_selector].mux);
+
+	sunxi_gpio_set_cfgbank(plat->base + bank, pin,
+			       desc->functions[func_selector].mux);
+
+	return 0;
+}
+
 static const struct pinctrl_ops sunxi_pinctrl_ops = {
+	.get_pins_count		= sunxi_pinctrl_get_pins_count,
+	.get_pin_name		= sunxi_pinctrl_get_pin_name,
+	.get_functions_count	= sunxi_pinctrl_get_functions_count,
+	.get_function_name	= sunxi_pinctrl_get_function_name,
+	.pinmux_set		= sunxi_pinctrl_pinmux_set,
 	.set_state		= pinctrl_generic_set_state,
 };
 
@@ -76,117 +142,278 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
 	return 0;
 }
 
+static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
+	.functions	= suniv_f1c100s_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(suniv_f1c100s_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 6,
 };
 
+static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
+	.functions	= sun4i_a10_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun4i_a10_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 9,
 };
 
+static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
+	.functions	= sun5i_a13_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun5i_a13_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 7,
 };
 
+static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
+	.functions	= sun6i_a31_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun6i_a31_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
+	.functions	= sun6i_a31_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun6i_a31_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 2,
 };
 
+static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
+	.functions	= sun7i_a20_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun7i_a20_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 9,
 };
 
+static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
+	.functions	= sun8i_a23_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_a23_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
+	.functions	= sun8i_a23_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_a23_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
+	.functions	= sun8i_a33_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_a33_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
+	.functions	= sun8i_a83t_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_a83t_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
+	.functions	= sun8i_a83t_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_a83t_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
+	.functions	= sun8i_h3_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_h3_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 7,
 };
 
+static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
+	.functions	= sun8i_h3_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_h3_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
+	.functions	= sun8i_v3s_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun8i_v3s_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 7,
 };
 
+static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
+	.functions	= sun9i_a80_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun9i_a80_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
+	.functions	= sun9i_a80_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun9i_a80_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 3,
 };
 
+static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
+	.functions	= sun50i_a64_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a64_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
+	.functions	= sun50i_a64_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a64_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
+	.functions	= sun50i_h5_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_h5_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 7,
 };
 
+static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
+	.functions	= sun50i_h6_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_h6_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 8,
 };
 
+static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
+	.functions	= sun50i_h6_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_h6_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 2,
 };
 
+static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
+	.functions	= sun50i_h616_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_h616_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_A,
 	.num_banks	= 9,
 };
 
+static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+};
+
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
+	.functions	= sun50i_h616_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_h616_r_pinctrl_functions),
 	.first_bank	= SUNXI_GPIO_L,
 	.num_banks	= 1,
 };
-- 
2.33.1

[PATCH v2 03/23] sunxi: pinctrl: Implement get_pin_muxing function

[Samuel Holland]

The pinmux command uses this function to display pinmux status.

Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 6ea8245c8e..4e453cec54 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -82,6 +82,32 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
 	return 0;
 }
 
+static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
+					char *buf, int size)
+{
+	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+	int pin	 = pin_selector % SUNXI_GPIOS_PER_BANK;
+	int mux  = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
+
+	switch (mux) {
+	case SUNXI_GPIO_INPUT:
+		strlcpy(buf, "gpio input", size);
+		break;
+	case SUNXI_GPIO_OUTPUT:
+		strlcpy(buf, "gpio output", size);
+		break;
+	case SUNXI_GPIO_DISABLE:
+		strlcpy(buf, "disabled", size);
+		break;
+	default:
+		snprintf(buf, size, "function %d", mux);
+		break;
+	}
+
+	return 0;
+}
+
 static const struct pinctrl_ops sunxi_pinctrl_ops = {
 	.get_pins_count		= sunxi_pinctrl_get_pins_count,
 	.get_pin_name		= sunxi_pinctrl_get_pin_name,
@@ -89,6 +115,7 @@ static const struct pinctrl_ops sunxi_pinctrl_ops = {
 	.get_function_name	= sunxi_pinctrl_get_function_name,
 	.pinmux_set		= sunxi_pinctrl_pinmux_set,
 	.set_state		= pinctrl_generic_set_state,
+	.get_pin_muxing		= sunxi_pinctrl_get_pin_muxing,
 };
 
 static int sunxi_pinctrl_bind(struct udevice *dev)
-- 
2.33.1

[PATCH v2 04/23] sunxi: pinctrl: Implement pin configuration

[Samuel Holland]

The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/Kconfig         |  1 +
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 53 +++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f4949f89e0..77da90836b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -5,6 +5,7 @@ if ARCH_SUNXI
 config PINCTRL_SUNXI
 	select PINCTRL_FULL
 	select PINCTRL_GENERIC
+	select PINCONF
 	select PINMUX
 	bool
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 4e453cec54..24b9647054 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -82,6 +82,56 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
 	return 0;
 }
 
+static const struct pinconf_param sunxi_pinctrl_pinconf_params[] = {
+	{ "bias-disable",	PIN_CONFIG_BIAS_DISABLE,	 0 },
+	{ "bias-pull-down",	PIN_CONFIG_BIAS_PULL_DOWN,	 2 },
+	{ "bias-pull-up",	PIN_CONFIG_BIAS_PULL_UP,	 1 },
+	{ "drive-strength",	PIN_CONFIG_DRIVE_STRENGTH,	10 },
+};
+
+static int sunxi_pinctrl_pinconf_set_pull(struct sunxi_pinctrl_plat *plat,
+					  uint bank, uint pin, uint bias)
+{
+	struct sunxi_gpio *regs = &plat->base[bank];
+
+	sunxi_gpio_set_pull_bank(regs, pin, bias);
+
+	return 0;
+}
+
+static int sunxi_pinctrl_pinconf_set_drive(struct sunxi_pinctrl_plat *plat,
+					   uint bank, uint pin, uint drive)
+{
+	struct sunxi_gpio *regs = &plat->base[bank];
+
+	if (drive < 10 || drive > 40)
+		return -EINVAL;
+
+	/* Convert mA to the register value, rounding down. */
+	sunxi_gpio_set_drv_bank(regs, pin, drive / 10 - 1);
+
+	return 0;
+}
+
+static int sunxi_pinctrl_pinconf_set(struct udevice *dev, uint pin_selector,
+				     uint param, uint val)
+{
+	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
+	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
+	int pin  = pin_selector % SUNXI_GPIOS_PER_BANK;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+	case PIN_CONFIG_BIAS_PULL_UP:
+		return sunxi_pinctrl_pinconf_set_pull(plat, bank, pin, val);
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		return sunxi_pinctrl_pinconf_set_drive(plat, bank, pin, val);
+	}
+
+	return -EINVAL;
+}
+
 static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
 					char *buf, int size)
 {
@@ -114,6 +164,9 @@ static const struct pinctrl_ops sunxi_pinctrl_ops = {
 	.get_functions_count	= sunxi_pinctrl_get_functions_count,
 	.get_function_name	= sunxi_pinctrl_get_function_name,
 	.pinmux_set		= sunxi_pinctrl_pinmux_set,
+	.pinconf_num_params	= ARRAY_SIZE(sunxi_pinctrl_pinconf_params),
+	.pinconf_params		= sunxi_pinctrl_pinconf_params,
+	.pinconf_set		= sunxi_pinctrl_pinconf_set,
 	.set_state		= pinctrl_generic_set_state,
 	.get_pin_muxing		= sunxi_pinctrl_get_pin_muxing,
 };
-- 
2.33.1

[PATCH v2 05/23] pinctrl: sunxi: Add UART pinmuxes

[Samuel Holland]

This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 98 +++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 24b9647054..751b47d687 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -225,6 +225,11 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
 static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	5 },	/* PE0-PE1 */
+#endif
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
@@ -237,6 +242,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc
 static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	4 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB22-PB23 */
+#endif
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
@@ -249,6 +259,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	4 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB19-PB20 */
+#endif
+	{ "uart1",	4 },	/* PG3-PG4 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
@@ -261,6 +277,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PH20-PH21 */
+#endif
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
@@ -273,6 +294,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
@@ -285,6 +307,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	4 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB22-PB23 */
+#endif
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
@@ -297,6 +324,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PB0-PB1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
@@ -309,6 +341,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
@@ -321,6 +354,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	3 },	/* PB0-PB1 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PB0-PB1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
@@ -333,6 +373,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB9-PB10 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PB0-PB1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
@@ -345,6 +392,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
@@ -357,6 +405,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc
 static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PA4-PA5 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PA0-PA1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
@@ -369,6 +424,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
@@ -381,6 +437,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	3 },	/* PB8-PB9 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PB0-PB1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
@@ -393,6 +456,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	4 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PH12-PH13 */
+#endif
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
@@ -405,6 +473,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	3 },	/* PL0-PL1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
@@ -417,6 +486,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	4 },	/* PB8-PB9 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PB0-PB1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
@@ -429,6 +505,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
@@ -441,6 +518,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc
 static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PA4-PA5 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
+	{ "uart2",	2 },	/* PA0-PA1 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
@@ -453,6 +537,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PH0-PH1 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
@@ -465,6 +555,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
@@ -477,6 +568,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PH0-PH1 */
+#endif
+	{ "uart1",	2 },	/* PG6-PG7 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
@@ -489,6 +586,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
 static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
-- 
2.33.1

[PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when PINCTRL=y

[Samuel Holland]

When a pinctrl driver is available, it will take care of setting up
these pins. However, for now this code is still needed in SPL.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 arch/arm/mach-sunxi/board.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 0071de19ff..32e2477ae7 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -79,6 +79,7 @@ ulong board_get_usable_ram_top(ulong total_size)
 static int gpio_init(void)
 {
 	__maybe_unused uint val;
+#if !CONFIG_IS_ENABLED(PINCTRL)
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
 #if defined(CONFIG_MACH_SUN4I) || \
     defined(CONFIG_MACH_SUN7I) || \
@@ -166,6 +167,7 @@ static int gpio_init(void)
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
+#endif
 
 #ifdef CONFIG_SUN50I_GEN_H6
 	/* Update PIO power bias configuration by copy hardware detected value */
-- 
2.33.1

[PATCH v2 07/23] pinctrl: sunxi: Add sun4i EMAC pinmuxes

[Samuel Holland]

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 751b47d687..2525a91e35 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -240,6 +240,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc
 };
 
 static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
+	{ "emac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -257,6 +258,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
 };
 
 static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
+	{ "emac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -305,6 +307,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
 };
 
 static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
+	{ "emac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
-- 
2.33.1

[PATCH v2 08/23] net: sunxi_emac: Remove non-DM pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
 drivers/net/sunxi_emac.c               | 7 +------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 773711b6a3..e93c9e84c9 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -135,7 +135,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_OUTPUT	1
 #define SUNXI_GPIO_DISABLE	7
 
-#define SUNXI_GPA_EMAC		2
 #define SUN6I_GPA_GMAC		2
 #define SUN7I_GPA_GMAC		5
 #define SUN8I_H3_GPA_UART0	2
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 17ad88e732..d15b0add7c 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -17,7 +17,6 @@
 #include <net.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
 
 /* EMAC register  */
 struct emac_regs {
@@ -511,15 +510,11 @@ static int sunxi_emac_board_setup(struct udevice *dev,
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
 	struct emac_regs *regs = priv->regs;
-	int pin, ret;
+	int ret;
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);
 
-	/* Configure pin mux settings for MII Ethernet */
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
-
 	/* Set up clock gating */
 	ret = clk_enable(&priv->clk);
 	if (ret) {
-- 
2.33.1

[PATCH v2 09/23] pinctrl: sunxi: Add sunxi GMAC pinmuxes

[Samuel Holland]

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 2525a91e35..7540e7668a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -277,6 +277,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
 };
 
 static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
+	{ "gmac",	2 },	/* PA0-PA27 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -308,6 +309,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
 
 static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
 	{ "emac",	2 },	/* PA0-PA17 */
+	{ "gmac",	5 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -457,6 +459,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
 };
 
 static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
+	{ "gmac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
-- 
2.33.1

[PATCH v2 10/23] sunxi: Remove non-DM GMAC pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 arch/arm/include/asm/arch-sunxi/gpio.h |  2 -
 board/sunxi/gmac.c                     | 55 --------------------------
 2 files changed, 57 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index e93c9e84c9..2aa6bbb178 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -135,8 +135,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_OUTPUT	1
 #define SUNXI_GPIO_DISABLE	7
 
-#define SUN6I_GPA_GMAC		2
-#define SUN7I_GPA_GMAC		5
 #define SUN8I_H3_GPA_UART0	2
 
 #define SUN4I_GPB_PWM		2
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 1fa54ed72d..2a885305eb 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -1,13 +1,11 @@
 #include <common.h>
 #include <netdev.h>
 #include <miiphy.h>
-#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 
 void eth_init_board(void)
 {
-	int pin;
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
@@ -21,57 +19,4 @@ void eth_init_board(void)
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
 		CCM_GMAC_CTRL_GPIT_MII);
 #endif
-
-#ifndef CONFIG_MACH_SUN6I
-	/* Configure pin mux settings for GMAC */
-#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
-#else
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
-#endif
-#ifdef CONFIG_RGMII
-		/* skip unused pins in RGMII mode */
-		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
-			continue;
-#endif
-		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 3);
-	}
-#elif defined CONFIG_RGMII
-	/* Configure sun6i RGMII mode pin mux settings */
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 3);
-	}
-	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 3);
-	}
-	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 3);
-	}
-	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 3);
-	}
-#elif defined CONFIG_GMII
-	/* Configure sun6i GMII mode pin mux settings */
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-		sunxi_gpio_set_drv(pin, 2);
-	}
-#else
-	/* Configure sun6i MII mode pin mux settings */
-	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
-		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
-#endif
 }
-- 
2.33.1

[PATCH v2 11/23] pinctrl: sunxi: Add sun8i EMAC pinmuxes

[Samuel Holland]

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 7540e7668a..2de793689a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -376,6 +376,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
 };
 
 static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
+	{ "gmac",	4 },	/* PD2-PD23 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -408,6 +409,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc
 };
 
 static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
+	{ "emac",	2 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -440,6 +442,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc =
 };
 
 static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
+	{ "emac",	4 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -490,6 +493,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
 };
 
 static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
+	{ "emac",	4 },	/* PD8-PD23 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -522,6 +526,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc
 };
 
 static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
+	{ "emac",	2 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -541,6 +546,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
 };
 
 static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
+	{ "emac",	5 },	/* PD0-PD20 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
@@ -572,6 +578,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
 };
 
 static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
+	{ "emac0",	2 },	/* PI0-PI16 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
-- 
2.33.1

[PATCH v2 12/23] net: sun8i_emac: Remove non-DM pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/net/sun8i_emac.c | 90 ----------------------------------------
 1 file changed, 90 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 2e24d12214..b23faa228e 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -29,7 +29,6 @@
 #include <miiphy.h>
 #include <net.h>
 #include <reset.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
 #include <wait_bit.h>
 
 #define MDIO_CMD_MII_BUSY		BIT(0)
@@ -81,13 +80,6 @@
 
 #define AHB_GATE_OFFSET_EPHY	0
 
-/* IO mux settings */
-#define SUN8I_IOMUX_H3		2
-#define SUN8I_IOMUX_R40		5
-#define SUN8I_IOMUX_H6		5
-#define SUN8I_IOMUX_H616	2
-#define SUN8I_IOMUX		4
-
 /* H3/A64 EMAC Register's offset */
 #define EMAC_CTL0		0x00
 #define EMAC_CTL0_FULL_DUPLEX		BIT(0)
@@ -519,85 +511,6 @@ static int sun8i_emac_eth_start(struct udevice *dev)
 	return 0;
 }
 
-static int parse_phy_pins(struct udevice *dev)
-{
-	int offset;
-	const char *pin_name;
-	int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
-	u32 iomux;
-
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-				       "pinctrl-0");
-	if (offset < 0) {
-		printf("WARNING: emac: cannot find pinctrl-0 node\n");
-		return offset;
-	}
-
-	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
-					     "drive-strength", ~0);
-	if (drive != ~0) {
-		if (drive <= 10)
-			drive = SUN4I_PINCTRL_10_MA;
-		else if (drive <= 20)
-			drive = SUN4I_PINCTRL_20_MA;
-		else if (drive <= 30)
-			drive = SUN4I_PINCTRL_30_MA;
-		else
-			drive = SUN4I_PINCTRL_40_MA;
-	}
-
-	if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
-		pull = SUN4I_PINCTRL_PULL_UP;
-	else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
-		pull = SUN4I_PINCTRL_PULL_DOWN;
-
-	/*
-	 * The GPIO pinmux value is an integration choice, so depends on the
-	 * SoC, not the EMAC variant.
-	 */
-	if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
-		iomux = SUN8I_IOMUX_H3;
-	else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
-		iomux = SUN8I_IOMUX_R40;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
-		iomux = SUN8I_IOMUX_H6;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
-		iomux = SUN8I_IOMUX_H616;
-	else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
-		iomux = SUN8I_IOMUX;
-	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
-		iomux = SUN8I_IOMUX;
-	else
-		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
-
-	for (i = 0; ; i++) {
-		int pin;
-
-		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
-					      "pins", i, NULL);
-		if (!pin_name)
-			break;
-
-		pin = sunxi_name_to_gpio(pin_name);
-		if (pin < 0)
-			continue;
-
-		sunxi_gpio_set_cfgpin(pin, iomux);
-
-		if (drive != ~0)
-			sunxi_gpio_set_drv(pin, drive);
-		if (pull != ~0)
-			sunxi_gpio_set_pull(pin, pull);
-	}
-
-	if (!i) {
-		printf("WARNING: emac: cannot find pins property\n");
-		return -2;
-	}
-
-	return 0;
-}
-
 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct emac_eth_dev *priv = dev_get_priv(dev);
@@ -965,9 +878,6 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 
 	priv->interface = pdata->phy_interface;
 
-	if (!priv->use_internal_phy)
-		parse_phy_pins(dev);
-
 	sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
 						  "allwinner,tx-delay-ps", 0);
 	if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
-- 
2.33.1

[PATCH v2 13/23] pinctrl: sunxi: Add I2C pinmuxes

[Samuel Holland]

Where multiple options were available, the one matching board.c and the
device trees was chosen.

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 2de793689a..3a2fbee324 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -225,6 +225,8 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
 static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	3 },	/* PE11-PE12 */
+	{ "i2c1",	3 },	/* PD5-PD6 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -243,6 +245,8 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
 	{ "emac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PB0-PB1 */
+	{ "i2c1",	2 },	/* PB18-PB19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -261,6 +265,8 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
 	{ "emac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PB0-PB1 */
+	{ "i2c1",	2 },	/* PB15-PB16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -280,6 +286,8 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
 	{ "gmac",	2 },	/* PA0-PA27 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH14-PH15 */
+	{ "i2c1",	2 },	/* PH16-PH17 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -297,6 +305,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	2 },	/* PL0-PL1 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -312,6 +321,8 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
 	{ "gmac",	5 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PB0-PB1 */
+	{ "i2c1",	2 },	/* PB18-PB19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -329,6 +340,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH2-PH3 */
+	{ "i2c1",	2 },	/* PH4-PH5 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #endif
@@ -346,6 +359,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	3 },	/* PL0-PL1 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -359,6 +373,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH2-PH3 */
+	{ "i2c1",	2 },	/* PH4-PH5 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -379,6 +395,8 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
 	{ "gmac",	4 },	/* PD2-PD23 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH0-PH1 */
+	{ "i2c1",	2 },	/* PH2-PH3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -398,6 +416,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	2 },	/* PL8-PL9 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -412,6 +431,8 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
 	{ "emac",	2 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PA11-PA12 */
+	{ "i2c1",	3 },	/* PA18-PA19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -431,6 +452,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	2 },	/* PL0-PL1 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -445,6 +467,8 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
 	{ "emac",	4 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PB6-PB7 */
+	{ "i2c1",	2 },	/* PB8-PB9 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -465,6 +489,8 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
 	{ "gmac",	2 },	/* PA0-PA17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH0-PH1 */
+	{ "i2c1",	2 },	/* PH2-PH3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -482,6 +508,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c0",	2 },	/* PN0-PN1 */
+	{ "s_i2c1",	3 },	/* PM8-PM9 */
 	{ "s_uart",	3 },	/* PL0-PL1 */
 };
 
@@ -496,6 +524,8 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
 	{ "emac",	4 },	/* PD8-PD23 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PH0-PH1 */
+	{ "i2c1",	2 },	/* PH2-PH3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -515,6 +545,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	2 },	/* PL8-PL9 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -529,6 +560,8 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
 	{ "emac",	2 },	/* PD0-PD17 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PA11-PA12 */
+	{ "i2c1",	2 },	/* PA18-PA19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -549,6 +582,8 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
 	{ "emac",	5 },	/* PD0-PD20 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "i2c0",	2 },	/* PD25-PD26 */
+	{ "i2c1",	4 },	/* PH5-PH6 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -567,6 +602,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
 static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	3 },	/* PL0-PL1 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
@@ -599,6 +635,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc =
 static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "s_i2c",	3 },	/* PL0-PL1 */
 	{ "s_uart",	2 },	/* PL2-PL3 */
 };
 
-- 
2.33.1

[PATCH v2 14/23] sunxi: Remove options and setup code for I2C2-I2C4

[Samuel Holland]

These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 arch/arm/include/asm/arch-sunxi/gpio.h |  8 -----
 arch/arm/include/asm/arch-sunxi/i2c.h  | 11 +-----
 arch/arm/mach-sunxi/Kconfig            | 22 ------------
 board/sunxi/board.c                    | 48 --------------------------
 4 files changed, 1 insertion(+), 88 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2aa6bbb178..cf5afdac6a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -141,8 +141,6 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_TWI0		2
 #define SUN4I_GPB_TWI1		2
 #define SUN5I_GPB_TWI1		2
-#define SUN4I_GPB_TWI2		2
-#define SUN5I_GPB_TWI2		2
 #define SUN8I_V3S_GPB_TWI0	2
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
@@ -164,8 +162,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPD_PWM		2
 
 #define SUNIV_GPE_UART0		5
-#define SUN8I_GPE_TWI2		3
-#define SUN50I_GPE_TWI2		3
 
 #define SUNXI_GPF_SDC0		2
 #define SUNXI_GPF_UART0		4
@@ -176,7 +172,6 @@ enum sunxi_gpio_number {
 #define SUN6I_GPG_SDC1		2
 #define SUN8I_GPG_SDC1		2
 #define SUN8I_GPG_UART1		2
-#define SUN6I_GPG_TWI3		2
 #define SUN5I_GPG_UART1		4
 
 #define SUN6I_GPH_PWM		2
@@ -188,15 +183,12 @@ enum sunxi_gpio_number {
 #define SUN6I_GPH_TWI1		2
 #define SUN8I_GPH_TWI1		2
 #define SUN50I_GPH_TWI1		2
-#define SUN6I_GPH_TWI2		2
 #define SUN6I_GPH_UART0		2
 #define SUN9I_GPH_UART0		2
 #define SUN50I_H6_GPH_UART0	2
 #define SUN50I_H616_GPH_UART0	2
 
 #define SUNXI_GPI_SDC3		2
-#define SUN7I_GPI_TWI3		3
-#define SUN7I_GPI_TWI4		3
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 1cb2ba6b0a..3525f22e7d 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -13,17 +13,8 @@
 #ifdef CONFIG_I2C1_ENABLE
 #define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
 #endif
-#ifdef CONFIG_I2C2_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2	SUNXI_TWI2_BASE
-#endif
-#ifdef CONFIG_I2C3_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE3	SUNXI_TWI3_BASE
-#endif
-#ifdef CONFIG_I2C4_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
-#endif
 #ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
 #endif
 
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 73da6b8f61..e5ed1d97e8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -755,20 +755,6 @@ config I2C1_ENABLE
 	---help---
 	See I2C0_ENABLE help text.
 
-config I2C2_ENABLE
-	bool "Enable I2C/TWI controller 2"
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-
-if MACH_SUN6I || MACH_SUN7I
-config I2C3_ENABLE
-	bool "Enable I2C/TWI controller 3"
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-endif
-
 if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
 config R_I2C_ENABLE
 	bool "Enable the PRCM I2C/TWI controller"
@@ -779,14 +765,6 @@ config R_I2C_ENABLE
 	Set this to y to enable the I2C controller which is part of the PRCM.
 endif
 
-if MACH_SUN7I
-config I2C4_ENABLE
-	bool "Enable I2C/TWI controller 4"
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-endif
-
 config AXP_GPIO
 	bool "Enable support for gpio-s on axp PMICs"
 	depends on AXP_PMIC_BUS
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index a096159047..05249d47eb 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -106,54 +106,6 @@ void i2c_init_board(void)
 #endif
 #endif
 
-#ifdef CONFIG_I2C2_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || \
-    defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN50I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
-	clock_twi_onoff(2, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C3_ENABLE
-#if defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
-	clock_twi_onoff(3, 1);
-#elif defined(CONFIG_MACH_SUN7I) || \
-      defined(CONFIG_MACH_SUN8I_R40)
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
-	clock_twi_onoff(3, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C4_ENABLE
-#if defined(CONFIG_MACH_SUN7I) || \
-    defined(CONFIG_MACH_SUN8I_R40)
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
-	clock_twi_onoff(4, 1);
-#endif
-#endif
-
 #ifdef CONFIG_R_I2C_ENABLE
 #ifdef CONFIG_MACH_SUN50I
 	clock_twi_onoff(5, 1);
-- 
2.33.1

[PATCH v2 15/23] sunxi: Remove non-DM I2C clock/pin setup from U-Boot

[Samuel Holland]

This is now handled automatically by the clock and pinctrl drivers.

SPL still calls this function because it needes the non-DM code.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 board/sunxi/board.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 05249d47eb..77ceefdb46 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -241,14 +241,6 @@ int board_init(void)
 		}
 	}
 
-#if CONFIG_IS_ENABLED(DM_I2C)
-	/*
-	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
-	 * clk, reset and pinctrl drivers land.
-	 */
-	i2c_init_board();
-#endif
-
 #ifdef CONFIG_DM_MMC
 	/*
 	 * Temporary workaround for enabling MMC clocks until a sunxi DM
-- 
2.33.1

[PATCH v2 16/23] i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C

[Samuel Holland]

When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/i2c/sun6i_p2wi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
index c9e1b3fcd5..73b808b09b 100644
--- a/drivers/i2c/sun6i_p2wi.c
+++ b/drivers/i2c/sun6i_p2wi.c
@@ -102,12 +102,6 @@ static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
 
 static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
 {
-	/* Enable p2wi and PIO clk, and de-assert their resets */
-	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
-
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
-
 	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
 	writel(P2WI_CTRL_RESET, &base->ctrl);
 	sdelay(0x100);
@@ -142,6 +136,12 @@ void p2wi_init(void)
 {
 	struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 
+	/* Enable p2wi and PIO clk, and de-assert their resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
+
 	sun6i_p2wi_init(base);
 }
 #endif
-- 
2.33.1

[PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

[Samuel Holland]

When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.

Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------
 1 file changed, 19 insertions(+), 27 deletions(-)

diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
index 716b245a00..0dea8f7a92 100644
--- a/drivers/i2c/sun8i_rsb.c
+++ b/drivers/i2c/sun8i_rsb.c
@@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
 	return sun8i_rsb_do_trans(base);
 }
 
-static void sun8i_rsb_cfg_io(void)
-{
-#ifdef CONFIG_MACH_SUN8I
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
-	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
-	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
-	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
-	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
-#elif defined CONFIG_MACH_SUN9I
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
-	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
-	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
-	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
-	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
-#else
-#error unsupported MACH_SUNXI
-#endif
-}
-
 static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
 {
 	u32 div = 0;
@@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
 
 static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
 {
-	/* Enable RSB and PIO clk, and de-assert their resets */
-	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
-
-	/* Setup external pins */
-	sun8i_rsb_cfg_io();
-
 	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
 	sun8i_rsb_set_clk(base);
 
@@ -185,6 +158,25 @@ int rsb_init(void)
 {
 	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
+	/* Enable RSB and PIO clk, and de-assert their resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
+
+	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
+		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
+		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+	} else {
+		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
+		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
+		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
+		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
+		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+	}
+
 	return sun8i_rsb_init(base);
 }
 #endif
-- 
2.33.1

[PATCH v2 18/23] pinctrl: sunxi: Add MMC pinmuxes

[Samuel Holland]

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 54 +++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 3a2fbee324..14d40a016b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -227,6 +227,8 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	3 },	/* PE11-PE12 */
 	{ "i2c1",	3 },	/* PD5-PD6 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	3 },	/* PC0-PC2 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -247,6 +249,14 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PB0-PB1 */
 	{ "i2c1",	2 },	/* PB18-PB19 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
+	{ "mmc1",	5 },	/* PH22-PH27 */
+#else
+	{ "mmc1",	4 },	/* PG0-PG5 */
+#endif
+	{ "mmc2",	3 },	/* PC6-PC15 */
+	{ "mmc3",	2 },	/* PI4-PI9 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -267,6 +277,9 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PB0-PB1 */
 	{ "i2c1",	2 },	/* PB15-PB16 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG3-PG8 */
+	{ "mmc2",	3 },	/* PC6-PC15 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -288,6 +301,10 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH14-PH15 */
 	{ "i2c1",	2 },	/* PH16-PH17 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
+	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -323,6 +340,13 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PB0-PB1 */
 	{ "i2c1",	2 },	/* PB18-PB19 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
+	{ "mmc1",	5 },	/* PH22-PH27 */
+#else
+	{ "mmc1",	4 },	/* PG0-PG5 */
+#endif
+	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -342,6 +366,9 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH2-PH3 */
 	{ "i2c1",	2 },	/* PH4-PH5 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC5-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #endif
@@ -375,6 +402,9 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH2-PH3 */
 	{ "i2c1",	2 },	/* PH4-PH5 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC5-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -397,6 +427,9 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH0-PH1 */
 	{ "i2c1",	2 },	/* PH2-PH3 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC5-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -433,6 +466,9 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PA11-PA12 */
 	{ "i2c1",	3 },	/* PA18-PA19 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC5-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -469,6 +505,9 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PB6-PB7 */
 	{ "i2c1",	2 },	/* PB8-PB9 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	2 },	/* PC0-PC10 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -491,6 +530,9 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH0-PH1 */
 	{ "i2c1",	2 },	/* PH2-PH3 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC6-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -526,6 +568,9 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PH0-PH1 */
 	{ "i2c1",	2 },	/* PH2-PH3 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC1-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -562,6 +607,9 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PA11-PA12 */
 	{ "i2c1",	2 },	/* PA18-PA19 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC1-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -584,6 +632,9 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
 	{ "gpio_out",	1 },
 	{ "i2c0",	2 },	/* PD25-PD26 */
 	{ "i2c1",	4 },	/* PH5-PH6 */
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC1-PC14 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -617,6 +668,9 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
 	{ "emac0",	2 },	/* PI0-PI16 */
 	{ "gpio_in",	0 },
 	{ "gpio_out",	1 },
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC0-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
-- 
2.33.1

[PATCH v2 19/23] sunxi: Remove non-DM MMC pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 board/sunxi/board.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 77ceefdb46..9a18399294 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -241,17 +241,6 @@ int board_init(void)
 		}
 	}
 
-#ifdef CONFIG_DM_MMC
-	/*
-	 * Temporary workaround for enabling MMC clocks until a sunxi DM
-	 * pinctrl driver lands.
-	 */
-	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
-#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
-	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
-#endif
-#endif	/* CONFIG_DM_MMC */
-
 	return 0;
 }
 
-- 
2.33.1

[PATCH v2 20/23] pinctrl: sunxi: Add the A64 PWM pinmux

[Samuel Holland]

This is the only possible mux setting for the A64's PWM peripheral.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 14d40a016b..dc52de0cf1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -571,6 +571,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC16 */
+	{ "pwm",	2 },	/* PD22 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
-- 
2.33.1

[PATCH v2 21/23] pwm: sunxi: Remove non-DM pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 arch/arm/include/asm/arch-sunxi/gpio.h |  1 -
 drivers/pwm/sunxi_pwm.c                | 11 -----------
 2 files changed, 12 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index cf5afdac6a..9f07d907e5 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -159,7 +159,6 @@ enum sunxi_gpio_number {
 
 #define SUNXI_GPD_LCD0		2
 #define SUNXI_GPD_LVDS0		3
-#define SUNXI_GPD_PWM		2
 
 #define SUNIV_GPE_UART0		5
 
diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
index e3d5ee456b..bb1bec05ec 100644
--- a/drivers/pwm/sunxi_pwm.c
+++ b/drivers/pwm/sunxi_pwm.c
@@ -13,7 +13,6 @@
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
-#include <asm/arch/gpio.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,14 +44,6 @@ static const u32 prescaler_table[] = {
 	1,	/* 1111 */
 };
 
-static int sunxi_pwm_config_pinmux(void)
-{
-#ifdef CONFIG_MACH_SUN50I
-	sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
-#endif
-	return 0;
-}
-
 static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
 				bool polarity)
 {
@@ -137,8 +128,6 @@ static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
 		return 0;
 	}
 
-	sunxi_pwm_config_pinmux();
-
 	if (priv->invert)
 		v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
 	else
-- 
2.33.1

[PATCH v2 22/23] pinctrl: sunxi: Add SPI0 pinmuxes

[Samuel Holland]

Pin lists and mux values were taken from the Linux drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index dc52de0cf1..932aa6e2d8 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -229,6 +229,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
 	{ "i2c1",	3 },	/* PD5-PD6 */
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	3 },	/* PC0-PC2 */
+	{ "spi0",	2 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -257,6 +258,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
 #endif
 	{ "mmc2",	3 },	/* PC6-PC15 */
 	{ "mmc3",	2 },	/* PI4-PI9 */
+	{ "spi0",	3 },	/* PC0-PC2, PC23 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -280,6 +282,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG3-PG8 */
 	{ "mmc2",	3 },	/* PC6-PC15 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -305,6 +308,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
 	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
+	{ "spi0",	3 },	/* PC0-PC2, PC27 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -347,6 +351,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
 	{ "mmc1",	4 },	/* PG0-PG5 */
 #endif
 	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
+	{ "spi0",	3 },	/* PC0-PC2, PC23 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -369,6 +374,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #endif
@@ -405,6 +411,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -430,6 +437,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -469,6 +477,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC5-PC16 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -508,6 +517,7 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	2 },	/* PC0-PC10 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -533,6 +543,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC6-PC16 */
+	{ "spi0",	3 },	/* PC0-PC2, PC19 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	4 },	/* PF2-PF4 */
 #else
@@ -572,6 +583,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC16 */
 	{ "pwm",	2 },	/* PD22 */
+	{ "spi0",	4 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -611,6 +623,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC16 */
+	{ "spi0",	3 },	/* PC0-PC3 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -636,6 +649,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC1-PC14 */
+	{ "spi0",	4 },	/* PC0-PC7 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
@@ -672,6 +686,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
 	{ "mmc0",	2 },	/* PF0-PF5 */
 	{ "mmc1",	2 },	/* PG0-PG5 */
 	{ "mmc2",	3 },	/* PC0-PC16 */
+	{ "spi0",	4 },	/* PC0-PC7, PC15-PC16 */
 #if IS_ENABLED(CONFIG_UART0_PORT_F)
 	{ "uart0",	3 },	/* PF2-PF4 */
 #else
-- 
2.33.1

[PATCH v2 23/23] spi: sun4i_spi: Remove non-DM pin setup

[Samuel Holland]

This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

(no changes since v1)

 drivers/spi/spi-sunxi.c | 84 -----------------------------------------
 1 file changed, 84 deletions(-)

diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index d62355ec6f..b6cd7ddafa 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -32,7 +32,6 @@
 #include <linux/bitops.h>
 
 #include <asm/bitops.h>
-#include <asm/gpio.h>
 #include <asm/io.h>
 
 #include <linux/iopoll.h>
@@ -180,87 +179,6 @@ static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
 	writel(reg, SPI_REG(priv, SPI_TCR));
 }
 
-static int sun4i_spi_parse_pins(struct udevice *dev)
-{
-	const void *fdt = gd->fdt_blob;
-	const char *pin_name;
-	const fdt32_t *list;
-	u32 phandle;
-	int drive, pull = 0, pin, i;
-	int offset;
-	int size;
-
-	list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
-	if (!list) {
-		printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
-		return -EINVAL;
-	}
-
-	while (size) {
-		phandle = fdt32_to_cpu(*list++);
-		size -= sizeof(*list);
-
-		offset = fdt_node_offset_by_phandle(fdt, phandle);
-		if (offset < 0)
-			return offset;
-
-		drive = fdt_getprop_u32_default_node(fdt, offset, 0,
-						     "drive-strength", 0);
-		if (drive) {
-			if (drive <= 10)
-				drive = 0;
-			else if (drive <= 20)
-				drive = 1;
-			else if (drive <= 30)
-				drive = 2;
-			else
-				drive = 3;
-		} else {
-			drive = fdt_getprop_u32_default_node(fdt, offset, 0,
-							     "allwinner,drive",
-							      0);
-			drive = min(drive, 3);
-		}
-
-		if (fdt_get_property(fdt, offset, "bias-disable", NULL))
-			pull = 0;
-		else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
-			pull = 1;
-		else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
-			pull = 2;
-		else
-			pull = fdt_getprop_u32_default_node(fdt, offset, 0,
-							    "allwinner,pull",
-							     0);
-		pull = min(pull, 2);
-
-		for (i = 0; ; i++) {
-			pin_name = fdt_stringlist_get(fdt, offset,
-						      "pins", i, NULL);
-			if (!pin_name) {
-				pin_name = fdt_stringlist_get(fdt, offset,
-							      "allwinner,pins",
-							       i, NULL);
-				if (!pin_name)
-					break;
-			}
-
-			pin = sunxi_name_to_gpio(pin_name);
-			if (pin < 0)
-				break;
-
-			if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
-			    IS_ENABLED(CONFIG_SUN50I_GEN_H6))
-				sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
-			else
-				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
-			sunxi_gpio_set_drv(pin, drive);
-			sunxi_gpio_set_pull(pin, pull);
-		}
-	}
-	return 0;
-}
-
 static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
 {
 	struct sun4i_spi_priv *priv = dev_get_priv(dev);
@@ -507,8 +425,6 @@ static int sun4i_spi_probe(struct udevice *bus)
 		return ret;
 	}
 
-	sun4i_spi_parse_pins(bus);
-
 	priv->variant = plat->variant;
 	priv->base = plat->base;
 	priv->freq = plat->max_hz;
-- 
2.33.1

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

[Heinrich Schuchardt]

On 3/18/22 04:54, Samuel Holland wrote:
> When the DM_I2C driver is loaded, the pin setup is done automatically
> from the device tree by the pinctrl driver.
> 
> Clean up the code in the process: remove #ifdefs and recognize that the
> pin configuration is the same for all sun8i/sun50i SoCs, not just those
> which select CONFIG_MACH_SUN8I.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
> (no changes since v1)
> 
>   drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------
>   1 file changed, 19 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
> index 716b245a00..0dea8f7a92 100644
> --- a/drivers/i2c/sun8i_rsb.c
> +++ b/drivers/i2c/sun8i_rsb.c
> @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
>   	return sun8i_rsb_do_trans(base);
>   }
>   
> -static void sun8i_rsb_cfg_io(void)
> -{
> -#ifdef CONFIG_MACH_SUN8I
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
> -	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
> -	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
> -	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
> -	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
> -#elif defined CONFIG_MACH_SUN9I
> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
> -	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
> -	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
> -	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
> -	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
> -#else
> -#error unsupported MACH_SUNXI
> -#endif
> -}
> -
>   static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
>   {
>   	u32 div = 0;
> @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
>   
>   static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
>   {
> -	/* Enable RSB and PIO clk, and de-assert their resets */
> -	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
> -
> -	/* Setup external pins */
> -	sun8i_rsb_cfg_io();
> -
>   	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
>   	sun8i_rsb_set_clk(base);
>   
> @@ -185,6 +158,25 @@ int rsb_init(void)
>   {
>   	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
>   
> +	/* Enable RSB and PIO clk, and de-assert their resets */
> +	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
> +
> +	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
> +		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
> +		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
> +		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
> +		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
> +	} else {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
> +		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
> +		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
> +		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
> +		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);

Don't repeat yourself. Please, pull these 4 lines out of the if-else 
construct.

Best regards

Heinrich

> +	}
> +
>   	return sun8i_rsb_init(base);
>   }
>   #endif

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

[Heinrich Schuchardt]

On 3/20/22 08:17, Heinrich Schuchardt wrote:
> 
> 
> On 3/18/22 04:54, Samuel Holland wrote:
>> When the DM_I2C driver is loaded, the pin setup is done automatically
>> from the device tree by the pinctrl driver.
>>
>> Clean up the code in the process: remove #ifdefs and recognize that the
>> pin configuration is the same for all sun8i/sun50i SoCs, not just those
>> which select CONFIG_MACH_SUN8I.
>>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>> (no changes since v1)
>>
>>   drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------
>>   1 file changed, 19 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
>> index 716b245a00..0dea8f7a92 100644
>> --- a/drivers/i2c/sun8i_rsb.c
>> +++ b/drivers/i2c/sun8i_rsb.c
>> @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct 
>> sunxi_rsb_reg *base,
>>       return sun8i_rsb_do_trans(base);
>>   }
>> -static void sun8i_rsb_cfg_io(void)
>> -{
>> -#ifdef CONFIG_MACH_SUN8I
>> -    sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
>> -    sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
>> -    sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
>> -    sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
>> -    sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
>> -    sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
>> -#elif defined CONFIG_MACH_SUN9I
>> -    sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
>> -    sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
>> -    sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
>> -    sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
>> -    sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
>> -    sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
>> -#else
>> -#error unsupported MACH_SUNXI
>> -#endif
>> -}
>> -
>>   static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
>>   {
>>       u32 div = 0;
>> @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct 
>> sunxi_rsb_reg *base)
>>   static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
>>   {
>> -    /* Enable RSB and PIO clk, and de-assert their resets */
>> -    prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
>> -
>> -    /* Setup external pins */
>> -    sun8i_rsb_cfg_io();
>> -
>>       writel(RSB_CTRL_SOFT_RST, &base->ctrl);
>>       sun8i_rsb_set_clk(base);
>> @@ -185,6 +158,25 @@ int rsb_init(void)
>>   {
>>       struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg 
>> *)SUNXI_RSB_BASE;
>> +    /* Enable RSB and PIO clk, and de-assert their resets */
>> +    prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
>> +
>> +    if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
>> +        sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
>> +        sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
>> +        sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
>> +        sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
>> +        sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
>> +        sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
>> +    } else {
>> +        sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
>> +        sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
>> +        sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
>> +        sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
>> +        sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
>> +        sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
> 
> Don't repeat yourself. Please, pull these 4 lines out of the if-else 
> construct.

Sorry missied N vs L.

> 
> Best regards
> 
> Heinrich
> 
>> +    }
>> +
>>       return sun8i_rsb_init(base);
>>   }
>>   #endif

Re: [PATCH v2 13/23] pinctrl: sunxi: Add I2C pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:10 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi,

> Where multiple options were available, the one matching board.c and the
> device trees was chosen.
> 
> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 2de793689a..3a2fbee324 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -225,6 +225,8 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
>  static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	3 },	/* PE11-PE12 */
> +	{ "i2c1",	3 },	/* PD5-PD6 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -243,6 +245,8 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
>  	{ "emac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PB0-PB1 */
> +	{ "i2c1",	2 },	/* PB18-PB19 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -261,6 +265,8 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
>  	{ "emac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PB0-PB1 */
> +	{ "i2c1",	2 },	/* PB15-PB16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -280,6 +286,8 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
>  	{ "gmac",	2 },	/* PA0-PA27 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH14-PH15 */
> +	{ "i2c1",	2 },	/* PH16-PH17 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -297,6 +305,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	2 },	/* PL0-PL1 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -312,6 +321,8 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "gmac",	5 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PB0-PB1 */
> +	{ "i2c1",	2 },	/* PB18-PB19 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -329,6 +340,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH2-PH3 */
> +	{ "i2c1",	2 },	/* PH4-PH5 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #endif
> @@ -346,6 +359,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	3 },	/* PL0-PL1 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -359,6 +373,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH2-PH3 */
> +	{ "i2c1",	2 },	/* PH4-PH5 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -379,6 +395,8 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
>  	{ "gmac",	4 },	/* PD2-PD23 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH0-PH1 */
> +	{ "i2c1",	2 },	/* PH2-PH3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -398,6 +416,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	2 },	/* PL8-PL9 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -412,6 +431,8 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
>  	{ "emac",	2 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PA11-PA12 */
> +	{ "i2c1",	3 },	/* PA18-PA19 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -431,6 +452,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	2 },	/* PL0-PL1 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -445,6 +467,8 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
>  	{ "emac",	4 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PB6-PB7 */
> +	{ "i2c1",	2 },	/* PB8-PB9 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -465,6 +489,8 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
>  	{ "gmac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH0-PH1 */
> +	{ "i2c1",	2 },	/* PH2-PH3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -482,6 +508,8 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c0",	2 },	/* PN0-PN1 */
> +	{ "s_i2c1",	3 },	/* PM8-PM9 */
>  	{ "s_uart",	3 },	/* PL0-PL1 */
>  };
>  
> @@ -496,6 +524,8 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "emac",	4 },	/* PD8-PD23 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PH0-PH1 */
> +	{ "i2c1",	2 },	/* PH2-PH3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -515,6 +545,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	2 },	/* PL8-PL9 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -529,6 +560,8 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
>  	{ "emac",	2 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PA11-PA12 */
> +	{ "i2c1",	2 },	/* PA18-PA19 */

According to both the user manual and the Linux driver this should be a
mux value of 3 (I guess mix up with I2S vs. I2C)

Cheers,
Andre

>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -549,6 +582,8 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
>  	{ "emac",	5 },	/* PD0-PD20 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "i2c0",	2 },	/* PD25-PD26 */
> +	{ "i2c1",	4 },	/* PH5-PH6 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -567,6 +602,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	3 },	/* PL0-PL1 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
> @@ -599,6 +635,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_i2c",	3 },	/* PL0-PL1 */
>  	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  

Re: [PATCH v2 05/23] pinctrl: sunxi: Add UART pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:02 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This includes UART0 and R_UART (s_uart) on all supported platforms, plus
> the additional UART configurations from arch/arm/mach-sunxi/board.c.
> 
> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compare against the individual manuals.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 98 +++++++++++++++++++++++++++
>  1 file changed, 98 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 24b9647054..751b47d687 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -225,6 +225,11 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
>  static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	5 },	/* PE0-PE1 */
> +#endif
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
> @@ -237,6 +242,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc
>  static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	4 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PB22-PB23 */
> +#endif
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
> @@ -249,6 +259,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	4 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PB19-PB20 */
> +#endif
> +	{ "uart1",	4 },	/* PG3-PG4 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
> @@ -261,6 +277,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PH20-PH21 */
> +#endif
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
> @@ -273,6 +294,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
> @@ -285,6 +307,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	4 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PB22-PB23 */
> +#endif
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
> @@ -297,6 +324,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PB0-PB1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
> @@ -309,6 +341,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
> @@ -321,6 +354,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	3 },	/* PB0-PB1 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PB0-PB1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
> @@ -333,6 +373,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PB9-PB10 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PB0-PB1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
> @@ -345,6 +392,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
> @@ -357,6 +405,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc
>  static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PA4-PA5 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PA0-PA1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
> @@ -369,6 +424,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
> @@ -381,6 +437,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	3 },	/* PB8-PB9 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PB0-PB1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
> @@ -393,6 +456,11 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	4 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PH12-PH13 */
> +#endif
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
> @@ -405,6 +473,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	3 },	/* PL0-PL1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
> @@ -417,6 +486,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	4 },	/* PB8-PB9 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PB0-PB1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
> @@ -429,6 +505,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
> @@ -441,6 +518,13 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc
>  static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PA4-PA5 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
> +	{ "uart2",	2 },	/* PA0-PA1 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
> @@ -453,6 +537,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PH0-PH1 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
> @@ -465,6 +555,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
>  static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
> @@ -477,6 +568,12 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +#if IS_ENABLED(CONFIG_UART0_PORT_F)
> +	{ "uart0",	3 },	/* PF2-PF4 */
> +#else
> +	{ "uart0",	2 },	/* PH0-PH1 */
> +#endif
> +	{ "uart1",	2 },	/* PG6-PG7 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
> @@ -489,6 +586,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc =
>  static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "s_uart",	2 },	/* PL2-PL3 */
>  };
>  
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {

Re: [PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when PINCTRL=y

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:03 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi Samuel,

> When a pinctrl driver is available, it will take care of setting up
> these pins. However, for now this code is still needed in SPL.
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
> (no changes since v1)
> 
>  arch/arm/mach-sunxi/board.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 0071de19ff..32e2477ae7 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -79,6 +79,7 @@ ulong board_get_usable_ram_top(ulong total_size)
>  static int gpio_init(void)
>  {
>  	__maybe_unused uint val;
> +#if !CONFIG_IS_ENABLED(PINCTRL)

So first this looks somewhat redundant, since the whole function (and
its caller) is already wrapped in #ifdef CONFIG_SPL_BUILD. Unless you
plan to have DM_PINCTRL for the RISC-V SPL?

But more importantly this function is already a nested #ifdef
nightmare. I experimented with:
	if (CONFIG_IS_ENABLED(PINCTRL))
		return 0;
and the toolchain garbage collection did the rest. This naive
version breaks H6, AFAICS, but with a bit of refactoring this could be
solved. But this is probably something for an independent cleanup patch.

So: if you agree to the SPL == !PINCTRL redundancy, please drop this
patch. If you want to keep the extra check, please at least add a
comment after the #endif, and I will look at cleaning this up
separately.

Cheers,
Andre


>  #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
>  #if defined(CONFIG_MACH_SUN4I) || \
>      defined(CONFIG_MACH_SUN7I) || \
> @@ -166,6 +167,7 @@ static int gpio_init(void)
>  #else
>  #error Unsupported console port number. Please fix pin mux settings in board.c
>  #endif
> +#endif
>  
>  #ifdef CONFIG_SUN50I_GEN_H6
>  	/* Update PIO power bias configuration by copy hardware detected value */

Re: [PATCH v2 07/23] pinctrl: sunxi: Add sun4i EMAC pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:04 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective manuals.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 751b47d687..2525a91e35 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -240,6 +240,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc
>  };
>  
>  static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
> +	{ "emac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -257,6 +258,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
>  };
>  
>  static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
> +	{ "emac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -305,6 +307,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
>  };
>  
>  static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
> +	{ "emac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)

Re: [PATCH v2 08/23] net: sunxi_emac: Remove non-DM pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:05 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
>  drivers/net/sunxi_emac.c               | 7 +------
>  2 files changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 773711b6a3..e93c9e84c9 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -135,7 +135,6 @@ enum sunxi_gpio_number {
>  #define SUNXI_GPIO_OUTPUT	1
>  #define SUNXI_GPIO_DISABLE	7
>  
> -#define SUNXI_GPA_EMAC		2
>  #define SUN6I_GPA_GMAC		2
>  #define SUN7I_GPA_GMAC		5
>  #define SUN8I_H3_GPA_UART0	2
> diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
> index 17ad88e732..d15b0add7c 100644
> --- a/drivers/net/sunxi_emac.c
> +++ b/drivers/net/sunxi_emac.c
> @@ -17,7 +17,6 @@
>  #include <net.h>
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
> -#include <asm/arch/gpio.h>
>  
>  /* EMAC register  */
>  struct emac_regs {
> @@ -511,15 +510,11 @@ static int sunxi_emac_board_setup(struct udevice *dev,
>  	struct sunxi_sramc_regs *sram =
>  		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
>  	struct emac_regs *regs = priv->regs;
> -	int pin, ret;
> +	int ret;
>  
>  	/* Map SRAM to EMAC */
>  	setbits_le32(&sram->ctrl1, 0x5 << 2);
>  
> -	/* Configure pin mux settings for MII Ethernet */
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
> -
>  	/* Set up clock gating */
>  	ret = clk_enable(&priv->clk);
>  	if (ret) {

Re: [PATCH v2 09/23] pinctrl: sunxi: Add sunxi GMAC pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:06 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective manuals.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 2525a91e35..7540e7668a 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -277,6 +277,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
>  };
>  
>  static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
> +	{ "gmac",	2 },	/* PA0-PA27 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -308,6 +309,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc =
>  
>  static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "emac",	2 },	/* PA0-PA17 */
> +	{ "gmac",	5 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -457,6 +459,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
>  };
>  
>  static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
> +	{ "gmac",	2 },	/* PA0-PA17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)

Re: [PATCH v2 10/23] sunxi: Remove non-DM GMAC pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:07 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Yeah!

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  arch/arm/include/asm/arch-sunxi/gpio.h |  2 -
>  board/sunxi/gmac.c                     | 55 --------------------------
>  2 files changed, 57 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index e93c9e84c9..2aa6bbb178 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -135,8 +135,6 @@ enum sunxi_gpio_number {
>  #define SUNXI_GPIO_OUTPUT	1
>  #define SUNXI_GPIO_DISABLE	7
>  
> -#define SUN6I_GPA_GMAC		2
> -#define SUN7I_GPA_GMAC		5
>  #define SUN8I_H3_GPA_UART0	2
>  
>  #define SUN4I_GPB_PWM		2
> diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
> index 1fa54ed72d..2a885305eb 100644
> --- a/board/sunxi/gmac.c
> +++ b/board/sunxi/gmac.c
> @@ -1,13 +1,11 @@
>  #include <common.h>
>  #include <netdev.h>
>  #include <miiphy.h>
> -#include <asm/gpio.h>
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
>  
>  void eth_init_board(void)
>  {
> -	int pin;
>  	struct sunxi_ccm_reg *const ccm =
>  		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>  
> @@ -21,57 +19,4 @@ void eth_init_board(void)
>  	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
>  		CCM_GMAC_CTRL_GPIT_MII);
>  #endif
> -
> -#ifndef CONFIG_MACH_SUN6I
> -	/* Configure pin mux settings for GMAC */
> -#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
> -#else
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
> -#endif
> -#ifdef CONFIG_RGMII
> -		/* skip unused pins in RGMII mode */
> -		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
> -			continue;
> -#endif
> -		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 3);
> -	}
> -#elif defined CONFIG_RGMII
> -	/* Configure sun6i RGMII mode pin mux settings */
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 3);
> -	}
> -	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 3);
> -	}
> -	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 3);
> -	}
> -	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 3);
> -	}
> -#elif defined CONFIG_GMII
> -	/* Configure sun6i GMII mode pin mux settings */
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -		sunxi_gpio_set_drv(pin, 2);
> -	}
> -#else
> -	/* Configure sun6i MII mode pin mux settings */
> -	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
> -		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
> -#endif
>  }

Re: [PATCH v2 11/23] pinctrl: sunxi: Add sun8i EMAC pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:08 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective manuals.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 7540e7668a..2de793689a 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -376,6 +376,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
>  };
>  
>  static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
> +	{ "gmac",	4 },	/* PD2-PD23 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -408,6 +409,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc
>  };
>  
>  static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
> +	{ "emac",	2 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -440,6 +442,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc =
>  };
>  
>  static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
> +	{ "emac",	4 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -490,6 +493,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc =
>  };
>  
>  static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
> +	{ "emac",	4 },	/* PD8-PD23 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -522,6 +526,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc
>  };
>  
>  static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
> +	{ "emac",	2 },	/* PD0-PD17 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -541,6 +546,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
>  };
>  
>  static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
> +	{ "emac",	5 },	/* PD0-PD20 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
> @@ -572,6 +578,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc =
>  };
>  
>  static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
> +	{ "emac0",	2 },	/* PI0-PI16 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)

Re: [PATCH v2 12/23] net: sun8i_emac: Remove non-DM pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:09 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Love that diffstat!

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/net/sun8i_emac.c | 90 ----------------------------------------
>  1 file changed, 90 deletions(-)
> 
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 2e24d12214..b23faa228e 100644
> --- a/drivers/net/sun8i_emac.c
> +++ b/drivers/net/sun8i_emac.c
> @@ -29,7 +29,6 @@
>  #include <miiphy.h>
>  #include <net.h>
>  #include <reset.h>
> -#include <dt-bindings/pinctrl/sun4i-a10.h>
>  #include <wait_bit.h>
>  
>  #define MDIO_CMD_MII_BUSY		BIT(0)
> @@ -81,13 +80,6 @@
>  
>  #define AHB_GATE_OFFSET_EPHY	0
>  
> -/* IO mux settings */
> -#define SUN8I_IOMUX_H3		2
> -#define SUN8I_IOMUX_R40		5
> -#define SUN8I_IOMUX_H6		5
> -#define SUN8I_IOMUX_H616	2
> -#define SUN8I_IOMUX		4
> -
>  /* H3/A64 EMAC Register's offset */
>  #define EMAC_CTL0		0x00
>  #define EMAC_CTL0_FULL_DUPLEX		BIT(0)
> @@ -519,85 +511,6 @@ static int sun8i_emac_eth_start(struct udevice *dev)
>  	return 0;
>  }
>  
> -static int parse_phy_pins(struct udevice *dev)
> -{
> -	int offset;
> -	const char *pin_name;
> -	int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
> -	u32 iomux;
> -
> -	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
> -				       "pinctrl-0");
> -	if (offset < 0) {
> -		printf("WARNING: emac: cannot find pinctrl-0 node\n");
> -		return offset;
> -	}
> -
> -	drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
> -					     "drive-strength", ~0);
> -	if (drive != ~0) {
> -		if (drive <= 10)
> -			drive = SUN4I_PINCTRL_10_MA;
> -		else if (drive <= 20)
> -			drive = SUN4I_PINCTRL_20_MA;
> -		else if (drive <= 30)
> -			drive = SUN4I_PINCTRL_30_MA;
> -		else
> -			drive = SUN4I_PINCTRL_40_MA;
> -	}
> -
> -	if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
> -		pull = SUN4I_PINCTRL_PULL_UP;
> -	else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
> -		pull = SUN4I_PINCTRL_PULL_DOWN;
> -
> -	/*
> -	 * The GPIO pinmux value is an integration choice, so depends on the
> -	 * SoC, not the EMAC variant.
> -	 */
> -	if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
> -		iomux = SUN8I_IOMUX_H3;
> -	else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
> -		iomux = SUN8I_IOMUX_R40;
> -	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
> -		iomux = SUN8I_IOMUX_H6;
> -	else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
> -		iomux = SUN8I_IOMUX_H616;
> -	else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
> -		iomux = SUN8I_IOMUX;
> -	else if (IS_ENABLED(CONFIG_MACH_SUN50I))
> -		iomux = SUN8I_IOMUX;
> -	else
> -		BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
> -
> -	for (i = 0; ; i++) {
> -		int pin;
> -
> -		pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
> -					      "pins", i, NULL);
> -		if (!pin_name)
> -			break;
> -
> -		pin = sunxi_name_to_gpio(pin_name);
> -		if (pin < 0)
> -			continue;
> -
> -		sunxi_gpio_set_cfgpin(pin, iomux);
> -
> -		if (drive != ~0)
> -			sunxi_gpio_set_drv(pin, drive);
> -		if (pull != ~0)
> -			sunxi_gpio_set_pull(pin, pull);
> -	}
> -
> -	if (!i) {
> -		printf("WARNING: emac: cannot find pins property\n");
> -		return -2;
> -	}
> -
> -	return 0;
> -}
> -
>  static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
>  {
>  	struct emac_eth_dev *priv = dev_get_priv(dev);
> @@ -965,9 +878,6 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
>  
>  	priv->interface = pdata->phy_interface;
>  
> -	if (!priv->use_internal_phy)
> -		parse_phy_pins(dev);
> -
>  	sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
>  						  "allwinner,tx-delay-ps", 0);
>  	if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)

Re: [PATCH v2 15/23] sunxi: Remove non-DM I2C clock/pin setup from U-Boot

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:12 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the clock and pinctrl drivers.
> 
> SPL still calls this function because it needes the non-DM code.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Looks good, but needs some testing to see if really cover all the
clocks already.

Anyway:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  board/sunxi/board.c | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 05249d47eb..77ceefdb46 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -241,14 +241,6 @@ int board_init(void)
>  		}
>  	}
>  
> -#if CONFIG_IS_ENABLED(DM_I2C)
> -	/*
> -	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
> -	 * clk, reset and pinctrl drivers land.
> -	 */
> -	i2c_init_board();
> -#endif
> -
>  #ifdef CONFIG_DM_MMC
>  	/*
>  	 * Temporary workaround for enabling MMC clocks until a sunxi DM

Re: [PATCH v2 16/23] i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:13 -0500
Samuel Holland <samuel@sholland.org> wrote:

> When the DM_I2C driver is loaded, the pin setup is done automatically
> from the device tree by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/i2c/sun6i_p2wi.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c
> index c9e1b3fcd5..73b808b09b 100644
> --- a/drivers/i2c/sun6i_p2wi.c
> +++ b/drivers/i2c/sun6i_p2wi.c
> @@ -102,12 +102,6 @@ static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base,
>  
>  static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base)
>  {
> -	/* Enable p2wi and PIO clk, and de-assert their resets */
> -	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
> -
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
> -
>  	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
>  	writel(P2WI_CTRL_RESET, &base->ctrl);
>  	sdelay(0x100);
> @@ -142,6 +136,12 @@ void p2wi_init(void)
>  {
>  	struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
>  
> +	/* Enable p2wi and PIO clk, and de-assert their resets */
> +	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
> +
> +	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
> +	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
> +
>  	sun6i_p2wi_init(base);
>  }
>  #endif

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:14 -0500
Samuel Holland <samuel@sholland.org> wrote:

> When the DM_I2C driver is loaded, the pin setup is done automatically
> from the device tree by the pinctrl driver.
> 
> Clean up the code in the process: remove #ifdefs and recognize that the
> pin configuration is the same for all sun8i/sun50i SoCs, not just those
> which select CONFIG_MACH_SUN8I.

Indeed, even though the F1C100s uses mux 4, but we don't use the RSB
there, and can fix that when we need it.

So this means we could enable RSB for the H616 SPL?

Regardless this looks alright:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
> (no changes since v1)
> 
>  drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------
>  1 file changed, 19 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
> index 716b245a00..0dea8f7a92 100644
> --- a/drivers/i2c/sun8i_rsb.c
> +++ b/drivers/i2c/sun8i_rsb.c
> @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
>  	return sun8i_rsb_do_trans(base);
>  }
>  
> -static void sun8i_rsb_cfg_io(void)
> -{
> -#ifdef CONFIG_MACH_SUN8I
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
> -	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
> -	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
> -	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
> -	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
> -#elif defined CONFIG_MACH_SUN9I
> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
> -	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
> -	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
> -	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
> -	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
> -#else
> -#error unsupported MACH_SUNXI
> -#endif
> -}
> -
>  static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
>  {
>  	u32 div = 0;
> @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
>  
>  static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
>  {
> -	/* Enable RSB and PIO clk, and de-assert their resets */
> -	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
> -
> -	/* Setup external pins */
> -	sun8i_rsb_cfg_io();
> -
>  	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
>  	sun8i_rsb_set_clk(base);
>  
> @@ -185,6 +158,25 @@ int rsb_init(void)
>  {
>  	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
>  
> +	/* Enable RSB and PIO clk, and de-assert their resets */
> +	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
> +
> +	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
> +		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
> +		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
> +		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
> +		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
> +	} else {
> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
> +		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
> +		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
> +		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
> +		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
> +	}
> +
>  	return sun8i_rsb_init(base);
>  }
>  #endif

Re: [PATCH v2 18/23] pinctrl: sunxi: Add MMC pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:15 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective manuals:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 54 +++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 3a2fbee324..14d40a016b 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -227,6 +227,8 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	3 },	/* PE11-PE12 */
>  	{ "i2c1",	3 },	/* PD5-PD6 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	3 },	/* PC0-PC2 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -247,6 +249,14 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PB0-PB1 */
>  	{ "i2c1",	2 },	/* PB18-PB19 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
> +	{ "mmc1",	5 },	/* PH22-PH27 */
> +#else
> +	{ "mmc1",	4 },	/* PG0-PG5 */
> +#endif
> +	{ "mmc2",	3 },	/* PC6-PC15 */
> +	{ "mmc3",	2 },	/* PI4-PI9 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -267,6 +277,9 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PB0-PB1 */
>  	{ "i2c1",	2 },	/* PB15-PB16 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG3-PG8 */
> +	{ "mmc2",	3 },	/* PC6-PC15 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -288,6 +301,10 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH14-PH15 */
>  	{ "i2c1",	2 },	/* PH16-PH17 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
> +	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -323,6 +340,13 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PB0-PB1 */
>  	{ "i2c1",	2 },	/* PB18-PB19 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +#if IS_ENABLED(CONFIG_MMC1_PINS_PH)
> +	{ "mmc1",	5 },	/* PH22-PH27 */
> +#else
> +	{ "mmc1",	4 },	/* PG0-PG5 */
> +#endif
> +	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -342,6 +366,9 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH2-PH3 */
>  	{ "i2c1",	2 },	/* PH4-PH5 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC5-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #endif
> @@ -375,6 +402,9 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH2-PH3 */
>  	{ "i2c1",	2 },	/* PH4-PH5 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC5-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -397,6 +427,9 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH0-PH1 */
>  	{ "i2c1",	2 },	/* PH2-PH3 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC5-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -433,6 +466,9 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PA11-PA12 */
>  	{ "i2c1",	3 },	/* PA18-PA19 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC5-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -469,6 +505,9 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PB6-PB7 */
>  	{ "i2c1",	2 },	/* PB8-PB9 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	2 },	/* PC0-PC10 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -491,6 +530,9 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH0-PH1 */
>  	{ "i2c1",	2 },	/* PH2-PH3 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC6-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -526,6 +568,9 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PH0-PH1 */
>  	{ "i2c1",	2 },	/* PH2-PH3 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC1-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -562,6 +607,9 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PA11-PA12 */
>  	{ "i2c1",	2 },	/* PA18-PA19 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC1-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -584,6 +632,9 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
>  	{ "gpio_out",	1 },
>  	{ "i2c0",	2 },	/* PD25-PD26 */
>  	{ "i2c1",	4 },	/* PH5-PH6 */
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC1-PC14 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -617,6 +668,9 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
>  	{ "emac0",	2 },	/* PI0-PI16 */
>  	{ "gpio_in",	0 },
>  	{ "gpio_out",	1 },
> +	{ "mmc0",	2 },	/* PF0-PF5 */
> +	{ "mmc1",	2 },	/* PG0-PG5 */
> +	{ "mmc2",	3 },	/* PC0-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else

Re: [PATCH v2 19/23] sunxi: Remove non-DM MMC pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:16 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

The comment was slightly wrong, this function really only does pinmux
setup, and doesn't touch any clocks. So this is fine now:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  board/sunxi/board.c | 11 -----------
>  1 file changed, 11 deletions(-)
> 
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 77ceefdb46..9a18399294 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -241,17 +241,6 @@ int board_init(void)
>  		}
>  	}
>  
> -#ifdef CONFIG_DM_MMC
> -	/*
> -	 * Temporary workaround for enabling MMC clocks until a sunxi DM
> -	 * pinctrl driver lands.
> -	 */
> -	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
> -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
> -	mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> -#endif
> -#endif	/* CONFIG_DM_MMC */
> -
>  	return 0;
>  }
>  

Re: [PATCH v2 20/23] pinctrl: sunxi: Add the A64 PWM pinmux

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:17 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is the only possible mux setting for the A64's PWM peripheral.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the manual:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre


> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 14d40a016b..dc52de0cf1 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -571,6 +571,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC16 */
> +	{ "pwm",	2 },	/* PD22 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else

Re: [PATCH v2 21/23] pwm: sunxi: Remove non-DM pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:18 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  arch/arm/include/asm/arch-sunxi/gpio.h |  1 -
>  drivers/pwm/sunxi_pwm.c                | 11 -----------
>  2 files changed, 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
> index cf5afdac6a..9f07d907e5 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -159,7 +159,6 @@ enum sunxi_gpio_number {
>  
>  #define SUNXI_GPD_LCD0		2
>  #define SUNXI_GPD_LVDS0		3
> -#define SUNXI_GPD_PWM		2
>  
>  #define SUNIV_GPE_UART0		5
>  
> diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c
> index e3d5ee456b..bb1bec05ec 100644
> --- a/drivers/pwm/sunxi_pwm.c
> +++ b/drivers/pwm/sunxi_pwm.c
> @@ -13,7 +13,6 @@
>  #include <asm/global_data.h>
>  #include <asm/io.h>
>  #include <asm/arch/pwm.h>
> -#include <asm/arch/gpio.h>
>  #include <power/regulator.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -45,14 +44,6 @@ static const u32 prescaler_table[] = {
>  	1,	/* 1111 */
>  };
>  
> -static int sunxi_pwm_config_pinmux(void)
> -{
> -#ifdef CONFIG_MACH_SUN50I
> -	sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
> -#endif
> -	return 0;
> -}
> -
>  static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
>  				bool polarity)
>  {
> @@ -137,8 +128,6 @@ static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
>  		return 0;
>  	}
>  
> -	sunxi_pwm_config_pinmux();
> -
>  	if (priv->invert)
>  		v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
>  	else

Re: [PATCH v2 22/23] pinctrl: sunxi: Add SPI0 pinmuxes

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:19 -0500
Samuel Holland <samuel@sholland.org> wrote:

> Pin lists and mux values were taken from the Linux drivers.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Compared against the respective manuals:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index dc52de0cf1..932aa6e2d8 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -229,6 +229,7 @@ static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
>  	{ "i2c1",	3 },	/* PD5-PD6 */
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	3 },	/* PC0-PC2 */
> +	{ "spi0",	2 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -257,6 +258,7 @@ static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
>  #endif
>  	{ "mmc2",	3 },	/* PC6-PC15 */
>  	{ "mmc3",	2 },	/* PI4-PI9 */
> +	{ "spi0",	3 },	/* PC0-PC2, PC23 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -280,6 +282,7 @@ static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG3-PG8 */
>  	{ "mmc2",	3 },	/* PC6-PC15 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -305,6 +308,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC6-PC15, PC24 */
>  	{ "mmc3",	4 },	/* PC6-PC15, PC24 */
> +	{ "spi0",	3 },	/* PC0-PC2, PC27 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -347,6 +351,7 @@ static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
>  	{ "mmc1",	4 },	/* PG0-PG5 */
>  #endif
>  	{ "mmc2",	3 },	/* PC5-PC15, PC24 */
> +	{ "spi0",	3 },	/* PC0-PC2, PC23 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -369,6 +374,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #endif
> @@ -405,6 +411,7 @@ static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -430,6 +437,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -469,6 +477,7 @@ static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC5-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -508,6 +517,7 @@ static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	2 },	/* PC0-PC10 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -533,6 +543,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC6-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC2, PC19 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	4 },	/* PF2-PF4 */
>  #else
> @@ -572,6 +583,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC16 */
>  	{ "pwm",	2 },	/* PD22 */
> +	{ "spi0",	4 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -611,6 +623,7 @@ static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC16 */
> +	{ "spi0",	3 },	/* PC0-PC3 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -636,6 +649,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC1-PC14 */
> +	{ "spi0",	4 },	/* PC0-PC7 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else
> @@ -672,6 +686,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
>  	{ "mmc0",	2 },	/* PF0-PF5 */
>  	{ "mmc1",	2 },	/* PG0-PG5 */
>  	{ "mmc2",	3 },	/* PC0-PC16 */
> +	{ "spi0",	4 },	/* PC0-PC7, PC15-PC16 */
>  #if IS_ENABLED(CONFIG_UART0_PORT_F)
>  	{ "uart0",	3 },	/* PF2-PF4 */
>  #else

Re: [PATCH v2 23/23] spi: sun4i_spi: Remove non-DM pin setup

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:20 -0500
Samuel Holland <samuel@sholland.org> wrote:

> This is now handled automatically by the pinctrl driver.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Again a nice cleanup!

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/spi/spi-sunxi.c | 84 -----------------------------------------
>  1 file changed, 84 deletions(-)
> 
> diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
> index d62355ec6f..b6cd7ddafa 100644
> --- a/drivers/spi/spi-sunxi.c
> +++ b/drivers/spi/spi-sunxi.c
> @@ -32,7 +32,6 @@
>  #include <linux/bitops.h>
>  
>  #include <asm/bitops.h>
> -#include <asm/gpio.h>
>  #include <asm/io.h>
>  
>  #include <linux/iopoll.h>
> @@ -180,87 +179,6 @@ static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
>  	writel(reg, SPI_REG(priv, SPI_TCR));
>  }
>  
> -static int sun4i_spi_parse_pins(struct udevice *dev)
> -{
> -	const void *fdt = gd->fdt_blob;
> -	const char *pin_name;
> -	const fdt32_t *list;
> -	u32 phandle;
> -	int drive, pull = 0, pin, i;
> -	int offset;
> -	int size;
> -
> -	list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
> -	if (!list) {
> -		printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
> -		return -EINVAL;
> -	}
> -
> -	while (size) {
> -		phandle = fdt32_to_cpu(*list++);
> -		size -= sizeof(*list);
> -
> -		offset = fdt_node_offset_by_phandle(fdt, phandle);
> -		if (offset < 0)
> -			return offset;
> -
> -		drive = fdt_getprop_u32_default_node(fdt, offset, 0,
> -						     "drive-strength", 0);
> -		if (drive) {
> -			if (drive <= 10)
> -				drive = 0;
> -			else if (drive <= 20)
> -				drive = 1;
> -			else if (drive <= 30)
> -				drive = 2;
> -			else
> -				drive = 3;
> -		} else {
> -			drive = fdt_getprop_u32_default_node(fdt, offset, 0,
> -							     "allwinner,drive",
> -							      0);
> -			drive = min(drive, 3);
> -		}
> -
> -		if (fdt_get_property(fdt, offset, "bias-disable", NULL))
> -			pull = 0;
> -		else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
> -			pull = 1;
> -		else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
> -			pull = 2;
> -		else
> -			pull = fdt_getprop_u32_default_node(fdt, offset, 0,
> -							    "allwinner,pull",
> -							     0);
> -		pull = min(pull, 2);
> -
> -		for (i = 0; ; i++) {
> -			pin_name = fdt_stringlist_get(fdt, offset,
> -						      "pins", i, NULL);
> -			if (!pin_name) {
> -				pin_name = fdt_stringlist_get(fdt, offset,
> -							      "allwinner,pins",
> -							       i, NULL);
> -				if (!pin_name)
> -					break;
> -			}
> -
> -			pin = sunxi_name_to_gpio(pin_name);
> -			if (pin < 0)
> -				break;
> -
> -			if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
> -			    IS_ENABLED(CONFIG_SUN50I_GEN_H6))
> -				sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
> -			else
> -				sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
> -			sunxi_gpio_set_drv(pin, drive);
> -			sunxi_gpio_set_pull(pin, pull);
> -		}
> -	}
> -	return 0;
> -}
> -
>  static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
>  {
>  	struct sun4i_spi_priv *priv = dev_get_priv(dev);
> @@ -507,8 +425,6 @@ static int sun4i_spi_probe(struct udevice *bus)
>  		return ret;
>  	}
>  
> -	sun4i_spi_parse_pins(bus);
> -
>  	priv->variant = plat->variant;
>  	priv->base = plat->base;
>  	priv->freq = plat->max_hz;

Re: [PATCH v2 02/23] sunxi: pinctrl: Implement pin muxing functions

[Andre Przywara]

On Thu, 17 Mar 2022 22:53:59 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi Samuel,

> Implement the operations to get pin and function names, and to set the
> mux for a pin. The pin count and pin names are calculated as if each
> bank has the maximum number of pins. Function names are simply the index
> into a list of { function name, mux value } pairs.

Thank you very much for this neat and lean solution, I like that.

> We assume all pins associated with a function use the same mux value for
> that function. This is generally true within a group of pins on a single
> port, but generally false when some peripheral can be muxed to multiple
> ports. For example, A64 UART3 uses mux 3 on port D, and mux 2 on port H.
> But all of the port D pins use the same mux value, and so do all of the
> port H pins. This applies even when the pins for some function are not
> contiguous, and when the lower-numbered mux values are unused. A good
> example of both of these cases is SPI0 on most SoCs.

This is only *almost* universally true, however, but the exceptions are
not relevant for U-Boot, as it affects some multimedia functions only.
One example I could quickly find is CSI on the H6, for instance.

> This strategy saves a lot of space (which is especially important for
> SPL), but where the mux value for a certain function differs across
> ports, it forces us to choose a single port for that function at build
> time. Since almost all boards use the default (i.e. reference design)
> pin muxes[1], this is unlikely to be a problem.

Yes, I can live with that restriction. Should we come to a point where
we need non-consistent muxes across different ports, we can always add
a "port" member to struct sunxi_pinctrl_function, and encode 0 as
"don't care", so we would just need to explicitly add that to the groups
that actually differ.

Can you add at least a short summary of your commit message
(that it is a simplified mapping, and just noting the restrictions) to
the code as a comment, just before the struct sunxi_pinctrl_function
declaration? I am not sure this nice explanation will be found
easily otherwise. Or you copy the whole explanation in, I don't mind.

Cheers,
Andre


> 
> [1]: See commit dda9fa734f81 ("sunxi: Simplify MMC pinmux selection")
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/Kconfig         |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 227 ++++++++++++++++++++++++++
>  2 files changed, 228 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 96c2f35f3a..f4949f89e0 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -5,6 +5,7 @@ if ARCH_SUNXI
>  config PINCTRL_SUNXI
>  	select PINCTRL_FULL
>  	select PINCTRL_GENERIC
> +	select PINMUX
>  	bool
>  
>  config PINCTRL_SUNIV_F1C100S
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 43bb1ec650..6ea8245c8e 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -12,7 +12,14 @@
>  
>  extern U_BOOT_DRIVER(gpio_sunxi);
>  
> +struct sunxi_pinctrl_function {
> +	const char	name[sizeof("gpio_out")];
> +	u8		mux;
> +};
> +
>  struct sunxi_pinctrl_desc {
> +	const struct sunxi_pinctrl_function	*functions;
> +	u8					num_functions;
>  	u8					first_bank;
>  	u8					num_banks;
>  };
> @@ -21,7 +28,66 @@ struct sunxi_pinctrl_plat {
>  	struct sunxi_gpio __iomem *base;
>  };
>  
> +static int sunxi_pinctrl_get_pins_count(struct udevice *dev)
> +{
> +	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
> +
> +	return desc->num_banks * SUNXI_GPIOS_PER_BANK;
> +}
> +
> +static const char *sunxi_pinctrl_get_pin_name(struct udevice *dev,
> +					      uint pin_selector)
> +{
> +	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
> +	static char pin_name[sizeof("PN31")];
> +
> +	snprintf(pin_name, sizeof(pin_name), "P%c%d",
> +		 pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
> +		 pin_selector % SUNXI_GPIOS_PER_BANK);
> +
> +	return pin_name;
> +}
> +
> +static int sunxi_pinctrl_get_functions_count(struct udevice *dev)
> +{
> +	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
> +
> +	return desc->num_functions;
> +}
> +
> +static const char *sunxi_pinctrl_get_function_name(struct udevice *dev,
> +						   uint func_selector)
> +{
> +	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
> +
> +	return desc->functions[func_selector].name;
> +}
> +
> +static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
> +				    uint func_selector)
> +{
> +	const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
> +	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
> +	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
> +	int pin	 = pin_selector % SUNXI_GPIOS_PER_BANK;
> +
> +	debug("set mux: %-4s => %s (%d)\n",
> +	      sunxi_pinctrl_get_pin_name(dev, pin_selector),
> +	      sunxi_pinctrl_get_function_name(dev, func_selector),
> +	      desc->functions[func_selector].mux);
> +
> +	sunxi_gpio_set_cfgbank(plat->base + bank, pin,
> +			       desc->functions[func_selector].mux);
> +
> +	return 0;
> +}
> +
>  static const struct pinctrl_ops sunxi_pinctrl_ops = {
> +	.get_pins_count		= sunxi_pinctrl_get_pins_count,
> +	.get_pin_name		= sunxi_pinctrl_get_pin_name,
> +	.get_functions_count	= sunxi_pinctrl_get_functions_count,
> +	.get_function_name	= sunxi_pinctrl_get_function_name,
> +	.pinmux_set		= sunxi_pinctrl_pinmux_set,
>  	.set_state		= pinctrl_generic_set_state,
>  };
>  
> @@ -76,117 +142,278 @@ static int sunxi_pinctrl_probe(struct udevice *dev)
>  	return 0;
>  }
>  
> +static const struct sunxi_pinctrl_function suniv_f1c100s_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused suniv_f1c100s_pinctrl_desc = {
> +	.functions	= suniv_f1c100s_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(suniv_f1c100s_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 6,
>  };
>  
> +static const struct sunxi_pinctrl_function sun4i_a10_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun4i_a10_pinctrl_desc = {
> +	.functions	= sun4i_a10_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun4i_a10_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 9,
>  };
>  
> +static const struct sunxi_pinctrl_function sun5i_a13_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun5i_a13_pinctrl_desc = {
> +	.functions	= sun5i_a13_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun5i_a13_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 7,
>  };
>  
> +static const struct sunxi_pinctrl_function sun6i_a31_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_pinctrl_desc = {
> +	.functions	= sun6i_a31_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun6i_a31_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun6i_a31_r_pinctrl_desc = {
> +	.functions	= sun6i_a31_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun6i_a31_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 2,
>  };
>  
> +static const struct sunxi_pinctrl_function sun7i_a20_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun7i_a20_pinctrl_desc = {
> +	.functions	= sun7i_a20_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun7i_a20_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 9,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_a23_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_pinctrl_desc = {
> +	.functions	= sun8i_a23_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_a23_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a23_r_pinctrl_desc = {
> +	.functions	= sun8i_a23_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_a23_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 1,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_a33_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a33_pinctrl_desc = {
> +	.functions	= sun8i_a33_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_a33_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_a83t_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_pinctrl_desc = {
> +	.functions	= sun8i_a83t_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_a83t_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_a83t_r_pinctrl_desc = {
> +	.functions	= sun8i_a83t_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_a83t_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 1,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_h3_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_pinctrl_desc = {
> +	.functions	= sun8i_h3_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_h3_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 7,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_h3_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_h3_r_pinctrl_desc = {
> +	.functions	= sun8i_h3_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_h3_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 1,
>  };
>  
> +static const struct sunxi_pinctrl_function sun8i_v3s_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun8i_v3s_pinctrl_desc = {
> +	.functions	= sun8i_v3s_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun8i_v3s_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 7,
>  };
>  
> +static const struct sunxi_pinctrl_function sun9i_a80_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_pinctrl_desc = {
> +	.functions	= sun9i_a80_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun9i_a80_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = {
> +	.functions	= sun9i_a80_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun9i_a80_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 3,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_pinctrl_desc = {
> +	.functions	= sun50i_a64_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_a64_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a64_r_pinctrl_desc = {
> +	.functions	= sun50i_a64_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_a64_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 1,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_h5_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h5_pinctrl_desc = {
> +	.functions	= sun50i_h5_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_h5_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 7,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_h6_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_pinctrl_desc = {
> +	.functions	= sun50i_h6_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_h6_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 8,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h6_r_pinctrl_desc = {
> +	.functions	= sun50i_h6_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_h6_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 2,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_h616_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = {
> +	.functions	= sun50i_h616_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_h616_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_A,
>  	.num_banks	= 9,
>  };
>  
> +static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
> +	{ "gpio_in",	0 },
> +	{ "gpio_out",	1 },
> +};
> +
>  static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc = {
> +	.functions	= sun50i_h616_r_pinctrl_functions,
> +	.num_functions	= ARRAY_SIZE(sun50i_h616_r_pinctrl_functions),
>  	.first_bank	= SUNXI_GPIO_L,
>  	.num_banks	= 1,
>  };

Re: [PATCH v2 03/23] sunxi: pinctrl: Implement get_pin_muxing function

[Andre Przywara]

On Thu, 17 Mar 2022 22:54:00 -0500
Samuel Holland <samuel@sholland.org> wrote:

> The pinmux command uses this function to display pinmux status.
> 
> Since the driver cannot map pin numbers to a list of supported
> functions, only functions which are common across all pins can be
> reported by name.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

I can surely live with that drawback:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 6ea8245c8e..4e453cec54 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -82,6 +82,32 @@ static int sunxi_pinctrl_pinmux_set(struct udevice *dev, uint pin_selector,
>  	return 0;
>  }
>  
> +static int sunxi_pinctrl_get_pin_muxing(struct udevice *dev, uint pin_selector,
> +					char *buf, int size)
> +{
> +	struct sunxi_pinctrl_plat *plat = dev_get_plat(dev);
> +	int bank = pin_selector / SUNXI_GPIOS_PER_BANK;
> +	int pin	 = pin_selector % SUNXI_GPIOS_PER_BANK;
> +	int mux  = sunxi_gpio_get_cfgbank(plat->base + bank, pin);
> +
> +	switch (mux) {
> +	case SUNXI_GPIO_INPUT:
> +		strlcpy(buf, "gpio input", size);
> +		break;
> +	case SUNXI_GPIO_OUTPUT:
> +		strlcpy(buf, "gpio output", size);
> +		break;
> +	case SUNXI_GPIO_DISABLE:
> +		strlcpy(buf, "disabled", size);
> +		break;
> +	default:
> +		snprintf(buf, size, "function %d", mux);
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
>  static const struct pinctrl_ops sunxi_pinctrl_ops = {
>  	.get_pins_count		= sunxi_pinctrl_get_pins_count,
>  	.get_pin_name		= sunxi_pinctrl_get_pin_name,
> @@ -89,6 +115,7 @@ static const struct pinctrl_ops sunxi_pinctrl_ops = {
>  	.get_function_name	= sunxi_pinctrl_get_function_name,
>  	.pinmux_set		= sunxi_pinctrl_pinmux_set,
>  	.set_state		= pinctrl_generic_set_state,
> +	.get_pin_muxing		= sunxi_pinctrl_get_pin_muxing,
>  };
>  
>  static int sunxi_pinctrl_bind(struct udevice *dev)

Re: [PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when PINCTRL=y

[Samuel Holland]

On 3/31/22 6:19 PM, Andre Przywara wrote:
> On Thu, 17 Mar 2022 22:54:03 -0500
> Samuel Holland <samuel@sholland.org> wrote:
> 
> Hi Samuel,
> 
>> When a pinctrl driver is available, it will take care of setting up
>> these pins. However, for now this code is still needed in SPL.
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>> (no changes since v1)
>>
>>  arch/arm/mach-sunxi/board.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
>> index 0071de19ff..32e2477ae7 100644
>> --- a/arch/arm/mach-sunxi/board.c
>> +++ b/arch/arm/mach-sunxi/board.c
>> @@ -79,6 +79,7 @@ ulong board_get_usable_ram_top(ulong total_size)
>>  static int gpio_init(void)
>>  {
>>  	__maybe_unused uint val;
>> +#if !CONFIG_IS_ENABLED(PINCTRL)
> 
> So first this looks somewhat redundant, since the whole function (and
> its caller) is already wrapped in #ifdef CONFIG_SPL_BUILD. Unless you
> plan to have DM_PINCTRL for the RISC-V SPL?

Yes, I do. But that is not too relevant anyway, because this code is in
arch/arm. So I am okay with dropping the patch.

Regards,
Samuel

> But more importantly this function is already a nested #ifdef
> nightmare. I experimented with:
> 	if (CONFIG_IS_ENABLED(PINCTRL))
> 		return 0;
> and the toolchain garbage collection did the rest. This naive
> version breaks H6, AFAICS, but with a bit of refactoring this could be
> solved. But this is probably something for an independent cleanup patch.
> 
> So: if you agree to the SPL == !PINCTRL redundancy, please drop this
> patch. If you want to keep the extra check, please at least add a
> comment after the #endif, and I will look at cleaning this up
> separately.
> 
> Cheers,
> Andre
> 
> 
>>  #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
>>  #if defined(CONFIG_MACH_SUN4I) || \
>>      defined(CONFIG_MACH_SUN7I) || \
>> @@ -166,6 +167,7 @@ static int gpio_init(void)
>>  #else
>>  #error Unsupported console port number. Please fix pin mux settings in board.c
>>  #endif
>> +#endif
>>  
>>  #ifdef CONFIG_SUN50I_GEN_H6
>>  	/* Update PIO power bias configuration by copy hardware detected value */
> 

Re: [PATCH v2 15/23] sunxi: Remove non-DM I2C clock/pin setup from U-Boot

[Samuel Holland]

On 3/31/22 6:20 PM, Andre Przywara wrote:
> On Thu, 17 Mar 2022 22:54:12 -0500
> Samuel Holland <samuel@sholland.org> wrote:
> 
>> This is now handled automatically by the clock and pinctrl drivers.
>>
>> SPL still calls this function because it needes the non-DM code.
>>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
> 
> Looks good, but needs some testing to see if really cover all the
> clocks already.

This is a good point. A31 and A23/A33 are still using the legacy PRCM MFD/clocks
binding, so we will need drivers for those before we can merge this (and the
P2WI/RSB patches).

Regards,
Samuel

> Anyway:
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> 
> Cheers,
> Andre
> 
>> ---
>>
>> (no changes since v1)
>>
>>  board/sunxi/board.c | 8 --------
>>  1 file changed, 8 deletions(-)
>>
>> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
>> index 05249d47eb..77ceefdb46 100644
>> --- a/board/sunxi/board.c
>> +++ b/board/sunxi/board.c
>> @@ -241,14 +241,6 @@ int board_init(void)
>>  		}
>>  	}
>>  
>> -#if CONFIG_IS_ENABLED(DM_I2C)
>> -	/*
>> -	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
>> -	 * clk, reset and pinctrl drivers land.
>> -	 */
>> -	i2c_init_board();
>> -#endif
>> -
>>  #ifdef CONFIG_DM_MMC
>>  	/*
>>  	 * Temporary workaround for enabling MMC clocks until a sunxi DM
> 

Re: [PATCH v2 17/23] i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C

[Samuel Holland]

On 3/31/22 6:20 PM, Andre Przywara wrote:
> On Thu, 17 Mar 2022 22:54:14 -0500
> Samuel Holland <samuel@sholland.org> wrote:
> 
>> When the DM_I2C driver is loaded, the pin setup is done automatically
>> from the device tree by the pinctrl driver.
>>
>> Clean up the code in the process: remove #ifdefs and recognize that the
>> pin configuration is the same for all sun8i/sun50i SoCs, not just those
>> which select CONFIG_MACH_SUN8I.
> 
> Indeed, even though the F1C100s uses mux 4, but we don't use the RSB
> there, and can fix that when we need it.
> 
> So this means we could enable RSB for the H616 SPL?

Not in SPL, because the DM clock driver is not yet available there, and
prcm_apb0_enable() does not support the H6 and newer CCU gate/reset bits layout.
It should work for H616 in U-Boot proper.

Regards,
Samuel

> Regardless this looks alright:
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> 
> Cheers,
> Andre
> 
>>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>
>> (no changes since v1)
>>
>>  drivers/i2c/sun8i_rsb.c | 46 +++++++++++++++++------------------------
>>  1 file changed, 19 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c
>> index 716b245a00..0dea8f7a92 100644
>> --- a/drivers/i2c/sun8i_rsb.c
>> +++ b/drivers/i2c/sun8i_rsb.c
>> @@ -95,27 +95,6 @@ static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
>>  	return sun8i_rsb_do_trans(base);
>>  }
>>  
>> -static void sun8i_rsb_cfg_io(void)
>> -{
>> -#ifdef CONFIG_MACH_SUN8I
>> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
>> -	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
>> -	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
>> -	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
>> -	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
>> -	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
>> -#elif defined CONFIG_MACH_SUN9I
>> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
>> -	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
>> -	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
>> -	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
>> -	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
>> -	sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
>> -#else
>> -#error unsupported MACH_SUNXI
>> -#endif
>> -}
>> -
>>  static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
>>  {
>>  	u32 div = 0;
>> @@ -147,12 +126,6 @@ static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
>>  
>>  static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
>>  {
>> -	/* Enable RSB and PIO clk, and de-assert their resets */
>> -	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
>> -
>> -	/* Setup external pins */
>> -	sun8i_rsb_cfg_io();
>> -
>>  	writel(RSB_CTRL_SOFT_RST, &base->ctrl);
>>  	sun8i_rsb_set_clk(base);
>>  
>> @@ -185,6 +158,25 @@ int rsb_init(void)
>>  {
>>  	struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
>>  
>> +	/* Enable RSB and PIO clk, and de-assert their resets */
>> +	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
>> +
>> +	if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
>> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
>> +		sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
>> +		sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
>> +		sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
>> +		sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
>> +		sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
>> +	} else {
>> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
>> +		sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
>> +		sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
>> +		sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
>> +		sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
>> +		sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
>> +	}
>> +
>>  	return sun8i_rsb_init(base);
>>  }
>>  #endif
> 

Re: [PATCH v2 00/23] sunxi: Add and use a pinctrl driver

[Andre Przywara]

On Thu, 17 Mar 2022 22:53:57 -0500
Samuel Holland <samuel@sholland.org> wrote:

Hi Samuel,

> This series resolves some longstanding TODOs by implementing a pinctrl
> driver for sunxi platforms and converting DM drivers to use it.

So as mentioned before, this is a huge step forward, and helps to
remove some dodgy and heavy-maintenance code parts. Many thanks for
that!

So I plan on taking this into the first PR for the 2022.07 merge
window, with the following changes (apart from adding my tags):
- Dropping "[PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when
  PINCTRL=y", as agreed in the review.
- Dropping "[PATCH v2 15/23] sunxi: Remove non-DM I2C clock/pin setup
  from U-Boot", as this probably breaks older boards. IIUC, this should
  still work with the new functionality, the old I2C setup code would
  just be redundant, for now.
- Fixing H5 pinmux value in "[PATCH v2 13/23] pinctrl: sunxi: Add I2C
  pinmuxes".
- Copying a summary of the commit message from "[PATCH v2 02/23] sunxi:
  pinctrl: Implement pin muxing functions" into the code, as a comment.

Samuel, does that make sense? If you agree, there would be no need to
re-send this series. I am happy to take fixups later, for instance for
some currently unknown gate clocks. I will be on holidays from
Wednesday until Easter, so don't want to wait until then with that
series.

Thanks,
Andre


> 
> Changes in v2:
>  - Merge all SoC drivers into one file and one U_BOOT_DRIVER.
>  - Add a consumer for the APB bus clock
>  - Add support for the F1C100s SoC
> 
> Samuel Holland (23):
>   sunxi: pinctrl: Create the driver skeleton
>   sunxi: pinctrl: Implement pin muxing functions
>   sunxi: pinctrl: Implement get_pin_muxing function
>   sunxi: pinctrl: Implement pin configuration
>   pinctrl: sunxi: Add UART pinmuxes
>   sunxi: Skip non-DM UART pin setup when PINCTRL=y
>   pinctrl: sunxi: Add sun4i EMAC pinmuxes
>   net: sunxi_emac: Remove non-DM pin setup
>   pinctrl: sunxi: Add sunxi GMAC pinmuxes
>   sunxi: Remove non-DM GMAC pin setup
>   pinctrl: sunxi: Add sun8i EMAC pinmuxes
>   net: sun8i_emac: Remove non-DM pin setup
>   pinctrl: sunxi: Add I2C pinmuxes
>   sunxi: Remove options and setup code for I2C2-I2C4
>   sunxi: Remove non-DM I2C clock/pin setup from U-Boot
>   i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
>   i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
>   pinctrl: sunxi: Add MMC pinmuxes
>   sunxi: Remove non-DM MMC pin setup
>   pinctrl: sunxi: Add the A64 PWM pinmux
>   pwm: sunxi: Remove non-DM pin setup
>   pinctrl: sunxi: Add SPI0 pinmuxes
>   spi: sun4i_spi: Remove non-DM pin setup
> 
>  MAINTAINERS                            |   1 +
>  arch/arm/Kconfig                       |   1 +
>  arch/arm/include/asm/arch-sunxi/gpio.h |  17 +-
>  arch/arm/include/asm/arch-sunxi/i2c.h  |  11 +-
>  arch/arm/mach-sunxi/Kconfig            |  22 -
>  arch/arm/mach-sunxi/board.c            |   2 +
>  board/sunxi/board.c                    |  67 --
>  board/sunxi/gmac.c                     |  55 --
>  drivers/gpio/sunxi_gpio.c              | 130 +---
>  drivers/i2c/sun6i_p2wi.c               |  12 +-
>  drivers/i2c/sun8i_rsb.c                |  46 +-
>  drivers/net/sun8i_emac.c               |  90 ---
>  drivers/net/sunxi_emac.c               |   7 +-
>  drivers/pinctrl/Kconfig                |   1 +
>  drivers/pinctrl/Makefile               |   2 +-
>  drivers/pinctrl/sunxi/Kconfig          | 127 ++++
>  drivers/pinctrl/sunxi/Makefile         |   3 +
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c  | 887 +++++++++++++++++++++++++
>  drivers/pwm/sunxi_pwm.c                |  11 -
>  drivers/spi/spi-sunxi.c                |  84 ---
>  20 files changed, 1057 insertions(+), 519 deletions(-)
>  create mode 100644 drivers/pinctrl/sunxi/Kconfig
>  create mode 100644 drivers/pinctrl/sunxi/Makefile
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
> 

Re: [PATCH v2 00/23] sunxi: Add and use a pinctrl driver

[Samuel Holland]

Hi Andre,

On 4/3/22 7:54 PM, Andre Przywara wrote:
> On Thu, 17 Mar 2022 22:53:57 -0500
> Samuel Holland <samuel@sholland.org> wrote:
> 
> Hi Samuel,
> 
>> This series resolves some longstanding TODOs by implementing a pinctrl
>> driver for sunxi platforms and converting DM drivers to use it.
> 
> So as mentioned before, this is a huge step forward, and helps to
> remove some dodgy and heavy-maintenance code parts. Many thanks for
> that!
> 
> So I plan on taking this into the first PR for the 2022.07 merge
> window, with the following changes (apart from adding my tags):
> - Dropping "[PATCH v2 06/23] sunxi: Skip non-DM UART pin setup when
>   PINCTRL=y", as agreed in the review.
> - Dropping "[PATCH v2 15/23] sunxi: Remove non-DM I2C clock/pin setup
>   from U-Boot", as this probably breaks older boards. IIUC, this should
>   still work with the new functionality, the old I2C setup code would
>   just be redundant, for now.
> - Fixing H5 pinmux value in "[PATCH v2 13/23] pinctrl: sunxi: Add I2C
>   pinmuxes".
> - Copying a summary of the commit message from "[PATCH v2 02/23] sunxi:
>   pinctrl: Implement pin muxing functions" into the code, as a comment.
> 
> Samuel, does that make sense? If you agree, there would be no need to
> re-send this series. I am happy to take fixups later, for instance for
> some currently unknown gate clocks. I will be on holidays from
> Wednesday until Easter, so don't want to wait until then with that
> series.

Yes, this plan works for me.

Regards,
Samuel

> Thanks,
> Andre
> 
> 
>>
>> Changes in v2:
>>  - Merge all SoC drivers into one file and one U_BOOT_DRIVER.
>>  - Add a consumer for the APB bus clock
>>  - Add support for the F1C100s SoC
>>
>> Samuel Holland (23):
>>   sunxi: pinctrl: Create the driver skeleton
>>   sunxi: pinctrl: Implement pin muxing functions
>>   sunxi: pinctrl: Implement get_pin_muxing function
>>   sunxi: pinctrl: Implement pin configuration
>>   pinctrl: sunxi: Add UART pinmuxes
>>   sunxi: Skip non-DM UART pin setup when PINCTRL=y
>>   pinctrl: sunxi: Add sun4i EMAC pinmuxes
>>   net: sunxi_emac: Remove non-DM pin setup
>>   pinctrl: sunxi: Add sunxi GMAC pinmuxes
>>   sunxi: Remove non-DM GMAC pin setup
>>   pinctrl: sunxi: Add sun8i EMAC pinmuxes
>>   net: sun8i_emac: Remove non-DM pin setup
>>   pinctrl: sunxi: Add I2C pinmuxes
>>   sunxi: Remove options and setup code for I2C2-I2C4
>>   sunxi: Remove non-DM I2C clock/pin setup from U-Boot
>>   i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
>>   i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
>>   pinctrl: sunxi: Add MMC pinmuxes
>>   sunxi: Remove non-DM MMC pin setup
>>   pinctrl: sunxi: Add the A64 PWM pinmux
>>   pwm: sunxi: Remove non-DM pin setup
>>   pinctrl: sunxi: Add SPI0 pinmuxes
>>   spi: sun4i_spi: Remove non-DM pin setup
>>
>>  MAINTAINERS                            |   1 +
>>  arch/arm/Kconfig                       |   1 +
>>  arch/arm/include/asm/arch-sunxi/gpio.h |  17 +-
>>  arch/arm/include/asm/arch-sunxi/i2c.h  |  11 +-
>>  arch/arm/mach-sunxi/Kconfig            |  22 -
>>  arch/arm/mach-sunxi/board.c            |   2 +
>>  board/sunxi/board.c                    |  67 --
>>  board/sunxi/gmac.c                     |  55 --
>>  drivers/gpio/sunxi_gpio.c              | 130 +---
>>  drivers/i2c/sun6i_p2wi.c               |  12 +-
>>  drivers/i2c/sun8i_rsb.c                |  46 +-
>>  drivers/net/sun8i_emac.c               |  90 ---
>>  drivers/net/sunxi_emac.c               |   7 +-
>>  drivers/pinctrl/Kconfig                |   1 +
>>  drivers/pinctrl/Makefile               |   2 +-
>>  drivers/pinctrl/sunxi/Kconfig          | 127 ++++
>>  drivers/pinctrl/sunxi/Makefile         |   3 +
>>  drivers/pinctrl/sunxi/pinctrl-sunxi.c  | 887 +++++++++++++++++++++++++
>>  drivers/pwm/sunxi_pwm.c                |  11 -
>>  drivers/spi/spi-sunxi.c                |  84 ---
>>  20 files changed, 1057 insertions(+), 519 deletions(-)
>>  create mode 100644 drivers/pinctrl/sunxi/Kconfig
>>  create mode 100644 drivers/pinctrl/sunxi/Makefile
>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>
>