Re: [PATCH V10 2/4] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya <quic_devipriy@quicinc.com>]

On 3/27/2023 10:18 PM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-03-27 06:27:16)
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>> new file mode 100644
>> index 000000000000..b2a2d618a5ec
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -0,0 +1,4248 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
> 
> What is this include for?
This include actually don't seem necessary. But, I see that of.h & 
platform_device.h are being included via of_device.h
Would you suggest to drop of_device.h or the other two
headers instead?
> 
>> +#include <linux/regmap.h>
> 
> Need to include clk-provider.h
> 
>> +
>> +#include <linux/reset-controller.h>
> 
> Put a newline here.
Okay
> 
>> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +
>> +#include "clk-rcg.h"
>> +#include "clk-branch.h"
>> +#include "clk-alpha-pll.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "clk-regmap-phy-mux.h"
>> +#include "reset.h"
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> +       DT_XO,
>> +       DT_SLEEP_CLK,
>> +       DT_BIAS_PLL_UBI_NC_CLK,
>> +       DT_PCIE30_PHY0_PIPE_CLK,
>> +       DT_PCIE30_PHY1_PIPE_CLK,
>> +       DT_PCIE30_PHY2_PIPE_CLK,
>> +       DT_PCIE30_PHY3_PIPE_CLK,
>> +       DT_USB3PHY_0_CC_PIPE_CLK,
>> +};
>> +
>> +enum {
>> +       P_XO,
>> +       P_PCIE30_PHY0_PIPE,
>> +       P_PCIE30_PHY1_PIPE,
>> +       P_PCIE30_PHY2_PIPE,
>> +       P_PCIE30_PHY3_PIPE,
>> +       P_USB3PHY_0_PIPE,
>> +       P_GPLL0,
>> +       P_GPLL0_DIV2,
>> +       P_GPLL0_OUT_AUX,
>> +       P_GPLL2,
>> +       P_GPLL4,
>> +       P_PI_SLEEP,
>> +       P_BIAS_PLL_UBI_NC_CLK,
>> +};
>> +
>> +static const struct parent_map gcc_xo_map[] = {
>> +       { P_XO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_data[] = {
>> +       { .index = DT_XO },
>> +};
>> +
>> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
>> +       { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> +       .offset = 0x20000,
>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +       .clkr = {
>> +               .enable_reg = 0x0b000,
>> +               .enable_mask = BIT(0),
>> +               .hw.init = &(struct clk_init_data) {
> 
> All these clk_init_data structs should be const.
Okay
> 
>> +                       .name = "gpll0_main",
>> +                       .parent_data = gcc_xo_data,
>> +                       .num_parents = ARRAY_SIZE(gcc_xo_data),
>> +                       .ops = &clk_alpha_pll_ops,
>> +               },
>> +       },
>> +};
Thanks,
Devi Priya