* [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers
@ 2020-07-01 13:42 Jonathan Marek
2020-07-01 13:42 ` [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings Jonathan Marek
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Georgi Djakov, open list, open list:INTERCONNECT API,
Rob Herring
Most of this is generated from downstream dts using a script.
There are a couple things I'm not sure about:
* When to set keepalive in DEFINE_QBCM macro (set to all false)
* Address/size for the reg fields - the "display" nodes have the same
address as the non-"display" nodes. For the size I just used 0x1000.
reg field is unused by the upstream driver so isn't a problem functionally.
Jonathan Marek (6):
dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings
dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings
interconnect: qcom: Add SM8150 interconnect provider driver
interconnect: qcom: Add SM8250 interconnect provider driver
arm64: dts: qcom: sm8150: add interconnect nodes
arm64: dts: qcom: sm8250: add interconnect nodes
.../bindings/interconnect/qcom,sm8150.yaml | 86 ++
.../bindings/interconnect/qcom,sm8250.yaml | 86 ++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 118 +++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 118 +++
drivers/interconnect/qcom/Kconfig | 20 +
drivers/interconnect/qcom/Makefile | 4 +
drivers/interconnect/qcom/sm8150.c | 719 +++++++++++++++++
drivers/interconnect/qcom/sm8150.h | 163 ++++
drivers/interconnect/qcom/sm8250.c | 733 ++++++++++++++++++
drivers/interconnect/qcom/sm8250.h | 173 +++++
.../dt-bindings/interconnect/qcom,sm8150.h | 176 +++++
.../dt-bindings/interconnect/qcom,sm8250.h | 186 +++++
12 files changed, 2582 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
create mode 100644 drivers/interconnect/qcom/sm8150.c
create mode 100644 drivers/interconnect/qcom/sm8150.h
create mode 100644 drivers/interconnect/qcom/sm8250.c
create mode 100644 drivers/interconnect/qcom/sm8250.h
create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h
create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h
--
2.26.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
2020-07-02 20:48 ` Rob Herring
2020-07-01 13:42 ` [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 " Jonathan Marek
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Georgi Djakov, Rob Herring,
open list:INTERCONNECT API,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
The Qualcomm SM8150 platform has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../bindings/interconnect/qcom,sm8150.yaml | 86 +++++++++
.../dt-bindings/interconnect/qcom,sm8150.h | 176 ++++++++++++++++++
2 files changed, 262 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
new file mode 100644
index 000000000000..99fb881bc797
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm8150.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 Network-On-Chip Interconnect
+
+maintainers:
+ -
+
+description: |
+ SM8150 interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+properties:
+ reg:
+ maxItems: 1
+
+ compatible:
+ enum:
+ - qcom,sm8150-aggre1-noc
+ - qcom,sm8150-aggre2-noc
+ - qcom,sm8150-camnoc-noc
+ - qcom,sm8150-compute-noc
+ - qcom,sm8150-config-noc
+ - qcom,sm8150-dc-noc
+ - qcom,sm8150-gem-noc
+ - qcom,sm8150-ipa-virt
+ - qcom,sm8150-mc-virt
+ - qcom,sm8150-mmss-noc
+ - qcom,sm8150-system-noc
+ - qcom,sm8150-gem-noc-display
+ - qcom,sm8150-mc-virt-display
+ - qcom,sm8150-mmss-noc-display
+
+ '#interconnect-cells':
+ const: 1
+
+ qcom,bcm-voters:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandles to qcom,bcm-voter nodes that are required by
+ this interconnect to send RPMh commands.
+
+ qcom,bcm-voter-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: |
+ Names for each of the qcom,bcm-voters specified.
+
+required:
+ - compatible
+ - reg
+ - '#interconnect-cells'
+ - qcom,bcm-voters
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interconnect/qcom,sm8150.h>
+
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm8150-config-noc";
+ reg = <0x01500000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1629000 {
+ compatible = "qcom,sm8150-system-noc";
+ reg = <0x01629000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1749000 {
+ compatible = "qcom,sm8150-mmss-noc";
+ reg = <0x01749000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h
new file mode 100644
index 000000000000..0550d7313817
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8150.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm SM8150 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H
+
+#define MASTER_A1NOC_CFG 0
+#define MASTER_QUP_0 1
+#define MASTER_EMAC 2
+#define MASTER_UFS_MEM 3
+#define MASTER_USB3 4
+#define MASTER_USB3_1 5
+#define A1NOC_SNOC_SLV 6
+#define SLAVE_SERVICE_A1NOC 7
+
+#define MASTER_A2NOC_CFG 0
+#define MASTER_QDSS_BAM 1
+#define MASTER_QSPI 2
+#define MASTER_QUP_1 3
+#define MASTER_QUP_2 4
+#define MASTER_SENSORS_AHB 5
+#define MASTER_TSIF 6
+#define MASTER_CNOC_A2NOC 7
+#define MASTER_CRYPTO_CORE_0 8
+#define MASTER_IPA 9
+#define MASTER_PCIE 10
+#define MASTER_PCIE_1 11
+#define MASTER_QDSS_ETR 12
+#define MASTER_SDCC_2 13
+#define MASTER_SDCC_4 14
+#define A2NOC_SNOC_SLV 15
+#define SLAVE_ANOC_PCIE_GEM_NOC 16
+#define SLAVE_SERVICE_A2NOC 17
+
+#define MASTER_CAMNOC_HF0_UNCOMP 0
+#define MASTER_CAMNOC_HF1_UNCOMP 1
+#define MASTER_CAMNOC_SF_UNCOMP 2
+#define SLAVE_CAMNOC_UNCOMP 3
+
+#define MASTER_NPU 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_SPDM 0
+#define SNOC_CNOC_MAS 1
+#define MASTER_QDSS_DAP 2
+#define SLAVE_A1NOC_CFG 3
+#define SLAVE_A2NOC_CFG 4
+#define SLAVE_AHB2PHY_SOUTH 5
+#define SLAVE_AOP 6
+#define SLAVE_AOSS 7
+#define SLAVE_CAMERA_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_CDSP_CFG 10
+#define SLAVE_RBCPR_CX_CFG 11
+#define SLAVE_RBCPR_MMCX_CFG 12
+#define SLAVE_RBCPR_MX_CFG 13
+#define SLAVE_CRYPTO_0_CFG 14
+#define SLAVE_CNOC_DDRSS 15
+#define SLAVE_DISPLAY_CFG 16
+#define SLAVE_EMAC_CFG 17
+#define SLAVE_GLM 18
+#define SLAVE_GRAPHICS_3D_CFG 19
+#define SLAVE_IMEM_CFG 20
+#define SLAVE_IPA_CFG 21
+#define SLAVE_CNOC_MNOC_CFG 22
+#define SLAVE_NPU_CFG 23
+#define SLAVE_PCIE_0_CFG 24
+#define SLAVE_PCIE_1_CFG 25
+#define SLAVE_NORTH_PHY_CFG 26
+#define SLAVE_PIMEM_CFG 27
+#define SLAVE_PRNG 28
+#define SLAVE_QDSS_CFG 29
+#define SLAVE_QSPI 30
+#define SLAVE_QUP_2 31
+#define SLAVE_QUP_1 32
+#define SLAVE_QUP_0 33
+#define SLAVE_SDCC_2 34
+#define SLAVE_SDCC_4 35
+#define SLAVE_SNOC_CFG 36
+#define SLAVE_SPDM_WRAPPER 37
+#define SLAVE_SPSS_CFG 38
+#define SLAVE_SSC_CFG 39
+#define SLAVE_TCSR 40
+#define SLAVE_TLMM_EAST 41
+#define SLAVE_TLMM_NORTH 42
+#define SLAVE_TLMM_SOUTH 43
+#define SLAVE_TLMM_WEST 44
+#define SLAVE_TSIF 45
+#define SLAVE_UFS_CARD_CFG 46
+#define SLAVE_UFS_MEM_CFG 47
+#define SLAVE_USB3 48
+#define SLAVE_USB3_1 49
+#define SLAVE_VENUS_CFG 50
+#define SLAVE_VSENSE_CTRL_CFG 51
+#define SLAVE_CNOC_A2NOC 52
+#define SLAVE_SERVICE_CNOC 53
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_LLCC_CFG 1
+#define SLAVE_GEM_NOC_CFG 2
+
+#define MASTER_AMPSS_M0 0
+#define MASTER_GPU_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_GEM_NOC_CFG 3
+#define MASTER_COMPUTE_NOC 4
+#define MASTER_GRAPHICS_3D 5
+#define MASTER_MNOC_HF_MEM_NOC 6
+#define MASTER_MNOC_SF_MEM_NOC 7
+#define MASTER_GEM_NOC_PCIE_SNOC 8
+#define MASTER_SNOC_GC_MEM_NOC 9
+#define MASTER_SNOC_SF_MEM_NOC 10
+#define MASTER_ECC 11
+#define SLAVE_MSS_PROC_MS_MPU_CFG 12
+#define SLAVE_ECC 13
+#define SLAVE_GEM_NOC_SNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_SERVICE_GEM_NOC 16
+
+#define MASTER_IPA_CORE 0
+#define SLAVE_IPA_CORE 1
+
+#define MASTER_LLCC 0
+#define MASTER_ALC 1
+#define SLAVE_EBI_CH0 2
+
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_CAMNOC_HF0 1
+#define MASTER_CAMNOC_HF1 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_MDP_PORT0 4
+#define MASTER_MDP_PORT1 5
+#define MASTER_ROTATOR 6
+#define MASTER_VIDEO_P0 7
+#define MASTER_VIDEO_P1 8
+#define MASTER_VIDEO_PROC 9
+#define SLAVE_MNOC_SF_MEM_NOC 10
+#define SLAVE_MNOC_HF_MEM_NOC 11
+#define SLAVE_SERVICE_MNOC 12
+
+#define MASTER_SNOC_CFG 0
+#define A1NOC_SNOC_MAS 1
+#define A2NOC_SNOC_MAS 2
+#define MASTER_GEM_NOC_SNOC 3
+#define MASTER_PIMEM 4
+#define MASTER_GIC 5
+#define SLAVE_APPSS 6
+#define SNOC_CNOC_SLV 7
+#define SLAVE_SNOC_GEM_NOC_GC 8
+#define SLAVE_SNOC_GEM_NOC_SF 9
+#define SLAVE_OCIMEM 10
+#define SLAVE_PIMEM 11
+#define SLAVE_SERVICE_SNOC 12
+#define SLAVE_PCIE_0 13
+#define SLAVE_PCIE_1 14
+#define SLAVE_QDSS_STM 15
+#define SLAVE_TCU 16
+
+#define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0
+#define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1
+#define SLAVE_LLCC_DISPLAY 2
+
+#define MASTER_LLCC_DISPLAY 0
+#define SLAVE_EBI_CH0_DISPLAY 1
+
+#define MASTER_MDP_PORT0_DISPLAY 0
+#define MASTER_MDP_PORT1_DISPLAY 1
+#define MASTER_ROTATOR_DISPLAY 2
+#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3
+#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
2020-07-01 13:42 ` [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
2020-07-02 20:49 ` Rob Herring
2020-07-02 20:49 ` Rob Herring
2020-07-01 13:42 ` [PATCH 3/6] interconnect: qcom: Add SM8150 interconnect provider driver Jonathan Marek
` (3 subsequent siblings)
5 siblings, 2 replies; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Georgi Djakov, Rob Herring,
open list:INTERCONNECT API,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
The Qualcomm SM8250 platform has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../bindings/interconnect/qcom,sm8250.yaml | 86 ++++++++
.../dt-bindings/interconnect/qcom,sm8250.h | 186 ++++++++++++++++++
2 files changed, 272 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
new file mode 100644
index 000000000000..bc4e2358ad78
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8250 Network-On-Chip Interconnect
+
+maintainers:
+ -
+
+description: |
+ SM8250 interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+properties:
+ reg:
+ maxItems: 1
+
+ compatible:
+ enum:
+ - qcom,sm8250-aggre1-noc
+ - qcom,sm8250-aggre2-noc
+ - qcom,sm8250-compute-noc
+ - qcom,sm8250-config-noc
+ - qcom,sm8250-dc-noc
+ - qcom,sm8250-gem-noc
+ - qcom,sm8250-ipa-virt
+ - qcom,sm8250-mc-virt
+ - qcom,sm8250-mmss-noc
+ - qcom,sm8250-npu-noc
+ - qcom,sm8250-system-noc
+ - qcom,sm8250-gem-noc-display
+ - qcom,sm8250-mc-virt-display
+ - qcom,sm8250-mmss-noc-display
+
+ '#interconnect-cells':
+ const: 1
+
+ qcom,bcm-voters:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandles to qcom,bcm-voter nodes that are required by
+ this interconnect to send RPMh commands.
+
+ qcom,bcm-voter-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: |
+ Names for each of the qcom,bcm-voters specified.
+
+required:
+ - compatible
+ - reg
+ - '#interconnect-cells'
+ - qcom,bcm-voters
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interconnect/qcom,sm8250.h>
+
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm8250-config-noc";
+ reg = <0x01500000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1632000 {
+ compatible = "qcom,sm8250-system-noc";
+ reg = <0x01632000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@174a000 {
+ compatible = "qcom,sm8250-mmss-noc";
+ reg = <0x0174a000 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h
new file mode 100644
index 000000000000..265571ff957a
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8250.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm SM8250 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8250_H
+
+#define MASTER_A1NOC_CFG 0
+#define MASTER_QSPI_0 1
+#define MASTER_QUP_1 2
+#define MASTER_QUP_2 3
+#define MASTER_TSIF 4
+#define MASTER_PCIE_2 5
+#define MASTER_SDCC_4 6
+#define MASTER_UFS_MEM 7
+#define MASTER_USB3 8
+#define MASTER_USB3_1 9
+#define A1NOC_SNOC_SLV 10
+#define SLAVE_ANOC_PCIE_GEM_NOC_1 11
+#define SLAVE_SERVICE_A1NOC 12
+
+#define MASTER_A2NOC_CFG 0
+#define MASTER_QDSS_BAM 1
+#define MASTER_QUP_0 2
+#define MASTER_CNOC_A2NOC 3
+#define MASTER_CRYPTO_CORE_0 4
+#define MASTER_IPA 5
+#define MASTER_PCIE 6
+#define MASTER_PCIE_1 7
+#define MASTER_QDSS_ETR 8
+#define MASTER_SDCC_2 9
+#define MASTER_UFS_CARD 10
+#define A2NOC_SNOC_SLV 11
+#define SLAVE_ANOC_PCIE_GEM_NOC 12
+#define SLAVE_SERVICE_A2NOC 13
+
+#define MASTER_NPU 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define SNOC_CNOC_MAS 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_A1NOC_CFG 2
+#define SLAVE_A2NOC_CFG 3
+#define SLAVE_AHB2PHY_SOUTH 4
+#define SLAVE_AHB2PHY_NORTH 5
+#define SLAVE_AOSS 6
+#define SLAVE_CAMERA_CFG 7
+#define SLAVE_CLK_CTL 8
+#define SLAVE_CDSP_CFG 9
+#define SLAVE_RBCPR_CX_CFG 10
+#define SLAVE_RBCPR_MMCX_CFG 11
+#define SLAVE_RBCPR_MX_CFG 12
+#define SLAVE_CRYPTO_0_CFG 13
+#define SLAVE_CX_RDPM 14
+#define SLAVE_DCC_CFG 15
+#define SLAVE_CNOC_DDRSS 16
+#define SLAVE_DISPLAY_CFG 17
+#define SLAVE_GRAPHICS_3D_CFG 18
+#define SLAVE_IMEM_CFG 19
+#define SLAVE_IPA_CFG 20
+#define SLAVE_IPC_ROUTER_CFG 21
+#define SLAVE_LPASS 22
+#define SLAVE_CNOC_MNOC_CFG 23
+#define SLAVE_NPU_CFG 24
+#define SLAVE_PCIE_0_CFG 25
+#define SLAVE_PCIE_1_CFG 26
+#define SLAVE_PCIE_2_CFG 27
+#define SLAVE_PDM 28
+#define SLAVE_PIMEM_CFG 29
+#define SLAVE_PRNG 30
+#define SLAVE_QDSS_CFG 31
+#define SLAVE_QSPI_0 32
+#define SLAVE_QUP_0 33
+#define SLAVE_QUP_1 34
+#define SLAVE_QUP_2 35
+#define SLAVE_SDCC_2 36
+#define SLAVE_SDCC_4 37
+#define SLAVE_SNOC_CFG 38
+#define SLAVE_TCSR 39
+#define SLAVE_TLMM_NORTH 40
+#define SLAVE_TLMM_SOUTH 41
+#define SLAVE_TLMM_WEST 42
+#define SLAVE_TSIF 43
+#define SLAVE_UFS_CARD_CFG 44
+#define SLAVE_UFS_MEM_CFG 45
+#define SLAVE_USB3 46
+#define SLAVE_USB3_1 47
+#define SLAVE_VENUS_CFG 48
+#define SLAVE_VSENSE_CTRL_CFG 49
+#define SLAVE_CNOC_A2NOC 50
+#define SLAVE_SERVICE_CNOC 51
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_LLCC_CFG 1
+#define SLAVE_GEM_NOC_CFG 2
+
+#define MASTER_GPU_TCU 0
+#define MASTER_SYS_TCU 1
+#define MASTER_AMPSS_M0 2
+#define MASTER_GEM_NOC_CFG 3
+#define MASTER_COMPUTE_NOC 4
+#define MASTER_GRAPHICS_3D 5
+#define MASTER_MNOC_HF_MEM_NOC 6
+#define MASTER_MNOC_SF_MEM_NOC 7
+#define MASTER_ANOC_PCIE_GEM_NOC 8
+#define MASTER_SNOC_GC_MEM_NOC 9
+#define MASTER_SNOC_SF_MEM_NOC 10
+#define SLAVE_GEM_NOC_SNOC 11
+#define SLAVE_LLCC 12
+#define SLAVE_MEM_NOC_PCIE_SNOC 13
+#define SLAVE_SERVICE_GEM_NOC_1 14
+#define SLAVE_SERVICE_GEM_NOC_2 15
+#define SLAVE_SERVICE_GEM_NOC 16
+
+#define MASTER_IPA_CORE 0
+#define SLAVE_IPA_CORE 1
+
+#define MASTER_LLCC 0
+#define MASTER_ALC 1
+#define SLAVE_EBI_CH0 2
+
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_CAMNOC_HF 1
+#define MASTER_CAMNOC_ICP 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_VIDEO_P0 4
+#define MASTER_VIDEO_P1 5
+#define MASTER_VIDEO_PROC 6
+#define MASTER_MDP_PORT0 7
+#define MASTER_MDP_PORT1 8
+#define MASTER_ROTATOR 9
+#define SLAVE_MNOC_HF_MEM_NOC 10
+#define SLAVE_MNOC_SF_MEM_NOC 11
+#define SLAVE_SERVICE_MNOC 12
+
+#define MASTER_NPU_SYS 0
+#define MASTER_NPU_CDP 1
+#define MASTER_NPU_NOC_CFG 2
+#define SLAVE_NPU_CAL_DP0 3
+#define SLAVE_NPU_CAL_DP1 4
+#define SLAVE_NPU_CP 5
+#define SLAVE_NPU_INT_DMA_BWMON_CFG 6
+#define SLAVE_NPU_DPM 7
+#define SLAVE_ISENSE_CFG 8
+#define SLAVE_NPU_LLM_CFG 9
+#define SLAVE_NPU_TCM 10
+#define SLAVE_NPU_COMPUTE_NOC 11
+#define SLAVE_SERVICE_NPU_NOC 12
+
+#define MASTER_SNOC_CFG 0
+#define A1NOC_SNOC_MAS 1
+#define A2NOC_SNOC_MAS 2
+#define MASTER_GEM_NOC_SNOC 3
+#define MASTER_GEM_NOC_PCIE_SNOC 4
+#define MASTER_PIMEM 5
+#define MASTER_GIC 6
+#define SLAVE_APPSS 7
+#define SNOC_CNOC_SLV 8
+#define SLAVE_SNOC_GEM_NOC_GC 9
+#define SLAVE_SNOC_GEM_NOC_SF 10
+#define SLAVE_OCIMEM 11
+#define SLAVE_PIMEM 12
+#define SLAVE_SERVICE_SNOC 13
+#define SLAVE_PCIE_0 14
+#define SLAVE_PCIE_1 15
+#define SLAVE_PCIE_2 16
+#define SLAVE_QDSS_STM 17
+#define SLAVE_TCU 18
+
+#define MASTER_MNOC_HF_MEM_NOC_DISPLAY 0
+#define MASTER_MNOC_SF_MEM_NOC_DISPLAY 1
+#define SLAVE_LLCC_DISPLAY 2
+
+#define MASTER_LLCC_DISPLAY 0
+#define SLAVE_EBI_CH0_DISPLAY 1
+
+#define MASTER_MDP_PORT0_DISPLAY 0
+#define MASTER_MDP_PORT1_DISPLAY 1
+#define MASTER_ROTATOR_DISPLAY 2
+#define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 3
+#define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 4
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/6] interconnect: qcom: Add SM8150 interconnect provider driver
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
2020-07-01 13:42 ` [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings Jonathan Marek
2020-07-01 13:42 ` [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 " Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
2020-07-01 13:42 ` [PATCH 4/6] interconnect: qcom: Add SM8250 " Jonathan Marek
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Georgi Djakov, open list,
open list:INTERCONNECT API
Add driver for the Qualcomm interconnect buses found in SM8150 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.
Based on SC7180 driver and generated from downstream dts.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/sm8150.c | 719 +++++++++++++++++++++++++++++
drivers/interconnect/qcom/sm8150.h | 163 +++++++
4 files changed, 894 insertions(+)
create mode 100644 drivers/interconnect/qcom/sm8150.c
create mode 100644 drivers/interconnect/qcom/sm8150.h
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index a88f2f07bc27..25486de5a38d 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -65,5 +65,15 @@ config INTERCONNECT_QCOM_SDM845
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms.
+config INTERCONNECT_QCOM_SM8150
+ tristate "Qualcomm SM8150 interconnect driver"
+ depends on INTERCONNECT_QCOM
+ depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on sm8150-based
+ platforms.
+
config INTERCONNECT_QCOM_SMD_RPM
tristate
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 3a047fe6e45a..1702ece67dc5 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -8,6 +8,7 @@ qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
qnoc-sdm845-objs := sdm845.o
+qnoc-sm8150-objs := sm8150.o
icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@@ -18,4 +19,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c
new file mode 100644
index 000000000000..095ddcfea382
--- /dev/null
+++ b/drivers/interconnect/qcom/sm8150.c
@@ -0,0 +1,719 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,sm8150.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+#include "sm8150.h"
+
+DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
+DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
+DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
+DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
+DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
+DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
+DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
+DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
+DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
+DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
+DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
+DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
+DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
+DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
+DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
+DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
+DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
+DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
+DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
+DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
+DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
+DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
+DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
+DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
+DEFINE_QNODE(alc, SM8150_MASTER_ALC, 1, 1);
+DEFINE_QNODE(qnm_mnoc_hf_display, SM8150_MASTER_MNOC_HF_MEM_NOC_DISPLAY, 2, 32, SM8150_SLAVE_LLCC_DISPLAY);
+DEFINE_QNODE(qnm_mnoc_sf_display, SM8150_MASTER_MNOC_SF_MEM_NOC_DISPLAY, 1, 32, SM8150_SLAVE_LLCC_DISPLAY);
+DEFINE_QNODE(llcc_mc_display, SM8150_MASTER_LLCC_DISPLAY, 4, 4, SM8150_SLAVE_EBI_CH0_DISPLAY);
+DEFINE_QNODE(qxm_mdp0_display, SM8150_MASTER_MDP_PORT0_DISPLAY, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qxm_mdp1_display, SM8150_MASTER_MDP_PORT1_DISPLAY, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qxm_rot_display, SM8150_MASTER_ROTATOR_DISPLAY, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
+DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
+DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
+DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
+DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
+DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
+DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
+DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
+DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
+DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
+DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
+DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
+DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
+DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
+DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
+DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
+DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
+DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
+DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
+DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
+DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
+DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
+DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
+DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
+DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
+DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
+DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
+DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
+DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
+DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
+DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
+DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
+DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
+DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
+DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
+DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
+DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
+DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
+DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
+DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
+DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
+DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
+DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
+DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
+DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
+DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
+DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
+DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
+DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
+DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
+DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
+DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
+DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
+DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
+DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
+DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
+DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
+DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
+DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
+DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
+DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
+DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
+DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
+DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
+DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
+DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
+DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
+DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
+DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
+DEFINE_QNODE(qns_llcc_display, SM8150_SLAVE_LLCC_DISPLAY, 4, 16, SM8150_MASTER_LLCC_DISPLAY);
+DEFINE_QNODE(ebi_display, SM8150_SLAVE_EBI_CH0_DISPLAY, 4, 4);
+DEFINE_QNODE(qns2_mem_noc_display, SM8150_SLAVE_MNOC_SF_MEM_NOC_DISPLAY, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qns_mem_noc_hf_display, SM8150_SLAVE_MNOC_HF_MEM_NOC_DISPLAY, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC_DISPLAY);
+
+DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
+DEFINE_QBCM(bcm_alc, "ALC", false, &alc);
+DEFINE_QBCM(bcm_mc0, "MC0", false, &ebi);
+DEFINE_QBCM(bcm_sh0, "SH0", false, &qns_llcc);
+DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
+DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
+DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
+DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
+DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
+DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
+DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
+DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
+DEFINE_QBCM(bcm_sn0, "SN0", false, &qns_gemnoc_sf);
+DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
+DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
+DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
+DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
+DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
+DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
+DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
+DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
+DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
+DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
+DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
+DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
+DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
+DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
+DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
+DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
+DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
+DEFINE_QBCM(bcm_acv_display, "ACV", false, &ebi_display);
+/* DEFINE_QBCM(bcm_alc_display, "ALC", false); */
+DEFINE_QBCM(bcm_mc0_display, "MC0", false, &ebi_display);
+DEFINE_QBCM(bcm_sh0_display, "SH0", false, &qns_llcc_display);
+DEFINE_QBCM(bcm_mm0_display, "MM0", false, &qns_mem_noc_hf_display);
+DEFINE_QBCM(bcm_mm1_display, "MM1", false, &qxm_mdp0_display, &qxm_mdp1_display);
+DEFINE_QBCM(bcm_mm2_display, "MM2", false, &qns2_mem_noc_display);
+DEFINE_QBCM(bcm_mm3_display, "MM3", false, &qxm_rot_display);
+
+static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
+ &bcm_qup0,
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node *aggre1_noc_nodes[] = {
+ [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
+ [MASTER_QUP_0] = &qhm_qup0,
+ [MASTER_EMAC] = &xm_emac,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3_0,
+ [MASTER_USB3_1] = &xm_usb3_1,
+ [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
+ [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
+};
+
+static struct qcom_icc_desc sm8150_aggre1_noc = {
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+};
+
+static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
+ &bcm_ce0,
+ &bcm_qup0,
+ &bcm_sn14,
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node *aggre2_noc_nodes[] = {
+ [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
+ [MASTER_QDSS_BAM] = &qhm_qdss_bam,
+ [MASTER_QSPI] = &qhm_qspi,
+ [MASTER_QUP_1] = &qhm_qup1,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
+ [MASTER_TSIF] = &qhm_tsif,
+ [MASTER_CNOC_A2NOC] = &qnm_cnoc,
+ [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_PCIE] = &xm_pcie3_0,
+ [MASTER_PCIE_1] = &xm_pcie3_1,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
+ [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
+};
+
+static struct qcom_icc_desc sm8150_aggre2_noc = {
+ .nodes = aggre2_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
+ .bcms = aggre2_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+};
+
+static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node *camnoc_virt_nodes[] = {
+ [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
+ [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
+ [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
+ [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
+};
+
+static struct qcom_icc_desc sm8150_camnoc_virt = {
+ .nodes = camnoc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
+ .bcms = camnoc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *compute_noc_bcms[] = {
+ &bcm_co0,
+ &bcm_co1,
+};
+
+static struct qcom_icc_node *compute_noc_nodes[] = {
+ [MASTER_NPU] = &qnm_npu,
+ [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
+};
+
+static struct qcom_icc_desc sm8150_compute_noc = {
+ .nodes = compute_noc_nodes,
+ .num_nodes = ARRAY_SIZE(compute_noc_nodes),
+ .bcms = compute_noc_bcms,
+ .num_bcms = ARRAY_SIZE(compute_noc_bcms),
+};
+
+static struct qcom_icc_bcm *config_noc_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node *config_noc_nodes[] = {
+ [MASTER_SPDM] = &qhm_spdm,
+ [SNOC_CNOC_MAS] = &qnm_snoc,
+ [MASTER_QDSS_DAP] = &xm_qdss_dap,
+ [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
+ [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
+ [SLAVE_AOP] = &qhs_aop,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
+ [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
+ [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
+ [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
+ [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
+ [SLAVE_GLM] = &qhs_glm,
+ [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
+ [SLAVE_NPU_CFG] = &qhs_npu_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+ [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
+ [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+ [SLAVE_QSPI] = &qhs_qspi,
+ [SLAVE_QUP_2] = &qhs_qupv3_east,
+ [SLAVE_QUP_1] = &qhs_qupv3_north,
+ [SLAVE_QUP_0] = &qhs_qupv3_south,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
+ [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
+ [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
+ [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
+ [SLAVE_TCSR] = &qhs_tcsr,
+ [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
+ [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
+ [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
+ [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
+ [SLAVE_TSIF] = &qhs_tsif,
+ [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3_0,
+ [SLAVE_USB3_1] = &qhs_usb3_1,
+ [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
+ [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
+};
+
+static struct qcom_icc_desc sm8150_config_noc = {
+ .nodes = config_noc_nodes,
+ .num_nodes = ARRAY_SIZE(config_noc_nodes),
+ .bcms = config_noc_bcms,
+ .num_bcms = ARRAY_SIZE(config_noc_bcms),
+};
+
+static struct qcom_icc_bcm *dc_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *dc_noc_nodes[] = {
+ [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
+ [SLAVE_LLCC_CFG] = &qhs_llcc,
+ [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
+};
+
+static struct qcom_icc_desc sm8150_dc_noc = {
+ .nodes = dc_noc_nodes,
+ .num_nodes = ARRAY_SIZE(dc_noc_nodes),
+ .bcms = dc_noc_bcms,
+ .num_bcms = ARRAY_SIZE(dc_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_bcms[] = {
+ &bcm_sh0,
+ &bcm_sh2,
+ &bcm_sh3,
+ &bcm_sh4,
+ &bcm_sh5,
+};
+
+static struct qcom_icc_node *gem_noc_nodes[] = {
+ [MASTER_AMPSS_M0] = &acm_apps,
+ [MASTER_GPU_TCU] = &acm_gpu_tcu,
+ [MASTER_SYS_TCU] = &acm_sys_tcu,
+ [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
+ [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
+ [MASTER_GRAPHICS_3D] = &qnm_gpu,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
+ [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_ECC] = &qxm_ecc,
+ [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
+ [SLAVE_ECC] = &qns_ecc,
+ [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
+};
+
+static struct qcom_icc_desc sm8150_gem_noc = {
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm *ipa_virt_bcms[] = {
+ &bcm_ip0,
+};
+
+static struct qcom_icc_node *ipa_virt_nodes[] = {
+ [MASTER_IPA_CORE] = &ipa_core_master,
+ [SLAVE_IPA_CORE] = &ipa_core_slave,
+};
+
+static struct qcom_icc_desc sm8150_ipa_virt = {
+ .nodes = ipa_virt_nodes,
+ .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
+ .bcms = ipa_virt_bcms,
+ .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_alc,
+ &bcm_mc0,
+};
+
+static struct qcom_icc_node *mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_ALC] = &alc,
+ [SLAVE_EBI_CH0] = &ebi,
+};
+
+static struct qcom_icc_desc sm8150_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+ &bcm_mm2,
+ &bcm_mm3,
+};
+
+static struct qcom_icc_node *mmss_noc_nodes[] = {
+ [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
+ [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
+ [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
+ [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
+ [MASTER_MDP_PORT0] = &qxm_mdp0,
+ [MASTER_MDP_PORT1] = &qxm_mdp1,
+ [MASTER_ROTATOR] = &qxm_rot,
+ [MASTER_VIDEO_P0] = &qxm_venus0,
+ [MASTER_VIDEO_P1] = &qxm_venus1,
+ [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
+};
+
+static struct qcom_icc_desc sm8150_mmss_noc = {
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm *system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn1,
+ &bcm_sn11,
+ &bcm_sn12,
+ &bcm_sn15,
+ &bcm_sn2,
+ &bcm_sn3,
+ &bcm_sn4,
+ &bcm_sn5,
+ &bcm_sn8,
+ &bcm_sn9,
+};
+
+static struct qcom_icc_node *system_noc_nodes[] = {
+ [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
+ [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
+ [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
+ [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
+ [MASTER_PIMEM] = &qxm_pimem,
+ [MASTER_GIC] = &xm_gic,
+ [SLAVE_APPSS] = &qhs_apss,
+ [SNOC_CNOC_SLV] = &qns_cnoc,
+ [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+ [SLAVE_OCIMEM] = &qxs_imem,
+ [SLAVE_PIMEM] = &qxs_pimem,
+ [SLAVE_SERVICE_SNOC] = &srvc_snoc,
+ [SLAVE_PCIE_0] = &xs_pcie_0,
+ [SLAVE_PCIE_1] = &xs_pcie_1,
+ [SLAVE_QDSS_STM] = &xs_qdss_stm,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static struct qcom_icc_desc sm8150_system_noc = {
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_display_bcms[] = {
+ &bcm_sh0_display,
+};
+
+static struct qcom_icc_node *gem_noc_display_nodes[] = {
+ [MASTER_MNOC_HF_MEM_NOC_DISPLAY] = &qnm_mnoc_hf_display,
+ [MASTER_MNOC_SF_MEM_NOC_DISPLAY] = &qnm_mnoc_sf_display,
+ [SLAVE_LLCC_DISPLAY] = &qns_llcc_display,
+};
+
+static struct qcom_icc_desc sm8150_gem_noc_display = {
+ .nodes = gem_noc_display_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_display_nodes),
+ .bcms = gem_noc_display_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_display_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_display_bcms[] = {
+ &bcm_acv_display,
+ &bcm_mc0_display,
+};
+
+static struct qcom_icc_node *mc_virt_display_nodes[] = {
+ [MASTER_LLCC_DISPLAY] = &llcc_mc_display,
+ [SLAVE_EBI_CH0_DISPLAY] = &ebi_display,
+};
+
+static struct qcom_icc_desc sm8150_mc_virt_display = {
+ .nodes = mc_virt_display_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_display_nodes),
+ .bcms = mc_virt_display_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_display_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_display_bcms[] = {
+ &bcm_mm0_display,
+ &bcm_mm1_display,
+ &bcm_mm2_display,
+ &bcm_mm3_display,
+};
+
+static struct qcom_icc_node *mmss_noc_display_nodes[] = {
+ [MASTER_MDP_PORT0_DISPLAY] = &qxm_mdp0_display,
+ [MASTER_MDP_PORT1_DISPLAY] = &qxm_mdp1_display,
+ [MASTER_ROTATOR_DISPLAY] = &qxm_rot_display,
+ [SLAVE_MNOC_SF_MEM_NOC_DISPLAY] = &qns2_mem_noc_display,
+ [SLAVE_MNOC_HF_MEM_NOC_DISPLAY] = &qns_mem_noc_hf_display,
+};
+
+static struct qcom_icc_desc sm8150_mmss_noc_display = {
+ .nodes = mmss_noc_display_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_display_nodes),
+ .bcms = mmss_noc_display_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_display_bcms),
+};
+
+static int qnoc_probe(struct platform_device *pdev)
+{
+ const struct qcom_icc_desc *desc;
+ struct icc_onecell_data *data;
+ struct icc_provider *provider;
+ struct qcom_icc_node **qnodes;
+ struct qcom_icc_provider *qp;
+ struct icc_node *node;
+ size_t num_nodes, i;
+ int ret;
+
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ qnodes = desc->nodes;
+ num_nodes = desc->num_nodes;
+
+ qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
+ if (!qp)
+ return -ENOMEM;
+
+ data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ provider = &qp->provider;
+ provider->dev = &pdev->dev;
+ provider->set = qcom_icc_set;
+ provider->pre_aggregate = qcom_icc_pre_aggregate;
+ provider->aggregate = qcom_icc_aggregate;
+ provider->xlate = of_icc_xlate_onecell;
+ INIT_LIST_HEAD(&provider->nodes);
+ provider->data = data;
+
+ qp->dev = &pdev->dev;
+ qp->bcms = desc->bcms;
+ qp->num_bcms = desc->num_bcms;
+
+ qp->voter = of_bcm_voter_get(qp->dev, NULL);
+ if (IS_ERR(qp->voter))
+ return PTR_ERR(qp->voter);
+
+ ret = icc_provider_add(provider);
+ if (ret) {
+ dev_err(&pdev->dev, "error adding interconnect provider\n");
+ return ret;
+ }
+
+ for (i = 0; i < num_nodes; i++) {
+ size_t j;
+
+ if (!qnodes[i])
+ continue;
+
+ node = icc_node_create(qnodes[i]->id);
+ if (IS_ERR(node)) {
+ ret = PTR_ERR(node);
+ goto err;
+ }
+
+ node->name = qnodes[i]->name;
+ node->data = qnodes[i];
+ icc_node_add(node, provider);
+
+ for (j = 0; j < qnodes[i]->num_links; j++)
+ icc_link_create(node, qnodes[i]->links[j]);
+
+ data->nodes[i] = node;
+ }
+ data->num_nodes = num_nodes;
+
+ for (i = 0; i < qp->num_bcms; i++)
+ qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
+
+ platform_set_drvdata(pdev, qp);
+
+ return 0;
+err:
+ icc_nodes_remove(provider);
+ icc_provider_del(provider);
+ return ret;
+}
+
+static int qnoc_remove(struct platform_device *pdev)
+{
+ struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
+
+ icc_nodes_remove(&qp->provider);
+ return icc_provider_del(&qp->provider);
+}
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,sm8150-aggre1-noc",
+ .data = &sm8150_aggre1_noc},
+ { .compatible = "qcom,sm8150-aggre2-noc",
+ .data = &sm8150_aggre2_noc},
+ { .compatible = "qcom,sm8150-camnoc-virt",
+ .data = &sm8150_camnoc_virt},
+ { .compatible = "qcom,sm8150-compute-noc",
+ .data = &sm8150_compute_noc},
+ { .compatible = "qcom,sm8150-config-noc",
+ .data = &sm8150_config_noc},
+ { .compatible = "qcom,sm8150-dc-noc",
+ .data = &sm8150_dc_noc},
+ { .compatible = "qcom,sm8150-gem-noc",
+ .data = &sm8150_gem_noc},
+ { .compatible = "qcom,sm8150-ipa-virt",
+ .data = &sm8150_ipa_virt},
+ { .compatible = "qcom,sm8150-mc-virt",
+ .data = &sm8150_mc_virt},
+ { .compatible = "qcom,sm8150-mmss-noc",
+ .data = &sm8150_mmss_noc},
+ { .compatible = "qcom,sm8150-system-noc",
+ .data = &sm8150_system_noc},
+ { .compatible = "qcom,sm8150-gem-noc-display",
+ .data = &sm8150_gem_noc_display},
+ { .compatible = "qcom,sm8150-mc-virt-display",
+ .data = &sm8150_mc_virt_display},
+ { .compatible = "qcom,sm8150-mmss-noc-display",
+ .data = &sm8150_mmss_noc_display},
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qnoc_probe,
+ .remove = qnoc_remove,
+ .driver = {
+ .name = "qnoc-sm8150",
+ .of_match_table = qnoc_of_match,
+ },
+};
+module_platform_driver(qnoc_driver);
+
+MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h
new file mode 100644
index 000000000000..f17d27fd3dd3
--- /dev/null
+++ b/drivers/interconnect/qcom/sm8150.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm #define SM8250 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8150_H
+#define __DRIVERS_INTERCONNECT_QCOM_SM8150_H
+
+#define SM8150_A1NOC_SNOC_MAS 0
+#define SM8150_A1NOC_SNOC_SLV 1
+#define SM8150_A2NOC_SNOC_MAS 2
+#define SM8150_A2NOC_SNOC_SLV 3
+#define SM8150_MASTER_A1NOC_CFG 4
+#define SM8150_MASTER_A2NOC_CFG 5
+#define SM8150_MASTER_ALC 6
+#define SM8150_MASTER_AMPSS_M0 7
+#define SM8150_MASTER_CAMNOC_HF0 8
+#define SM8150_MASTER_CAMNOC_HF0_UNCOMP 9
+#define SM8150_MASTER_CAMNOC_HF1 10
+#define SM8150_MASTER_CAMNOC_HF1_UNCOMP 11
+#define SM8150_MASTER_CAMNOC_SF 12
+#define SM8150_MASTER_CAMNOC_SF_UNCOMP 13
+#define SM8150_MASTER_CNOC_A2NOC 14
+#define SM8150_MASTER_CNOC_DC_NOC 15
+#define SM8150_MASTER_CNOC_MNOC_CFG 16
+#define SM8150_MASTER_COMPUTE_NOC 17
+#define SM8150_MASTER_CRYPTO_CORE_0 18
+#define SM8150_MASTER_ECC 19
+#define SM8150_MASTER_EMAC 20
+#define SM8150_MASTER_GEM_NOC_CFG 21
+#define SM8150_MASTER_GEM_NOC_PCIE_SNOC 22
+#define SM8150_MASTER_GEM_NOC_SNOC 23
+#define SM8150_MASTER_GIC 24
+#define SM8150_MASTER_GPU_TCU 25
+#define SM8150_MASTER_GRAPHICS_3D 26
+#define SM8150_MASTER_IPA 27
+#define SM8150_MASTER_IPA_CORE 28
+#define SM8150_MASTER_LLCC 29
+#define SM8150_MASTER_LLCC_DISPLAY 30
+#define SM8150_MASTER_MDP_PORT0 31
+#define SM8150_MASTER_MDP_PORT0_DISPLAY 32
+#define SM8150_MASTER_MDP_PORT1 33
+#define SM8150_MASTER_MDP_PORT1_DISPLAY 34
+#define SM8150_MASTER_MNOC_HF_MEM_NOC 35
+#define SM8150_MASTER_MNOC_HF_MEM_NOC_DISPLAY 36
+#define SM8150_MASTER_MNOC_SF_MEM_NOC 37
+#define SM8150_MASTER_MNOC_SF_MEM_NOC_DISPLAY 38
+#define SM8150_MASTER_NPU 39
+#define SM8150_MASTER_PCIE 40
+#define SM8150_MASTER_PCIE_1 41
+#define SM8150_MASTER_PIMEM 42
+#define SM8150_MASTER_QDSS_BAM 43
+#define SM8150_MASTER_QDSS_DAP 44
+#define SM8150_MASTER_QDSS_ETR 45
+#define SM8150_MASTER_QSPI 46
+#define SM8150_MASTER_QUP_0 47
+#define SM8150_MASTER_QUP_1 48
+#define SM8150_MASTER_QUP_2 49
+#define SM8150_MASTER_ROTATOR 50
+#define SM8150_MASTER_ROTATOR_DISPLAY 51
+#define SM8150_MASTER_SDCC_2 52
+#define SM8150_MASTER_SDCC_4 53
+#define SM8150_MASTER_SENSORS_AHB 54
+#define SM8150_MASTER_SNOC_CFG 55
+#define SM8150_MASTER_SNOC_GC_MEM_NOC 56
+#define SM8150_MASTER_SNOC_SF_MEM_NOC 57
+#define SM8150_MASTER_SPDM 58
+#define SM8150_MASTER_SYS_TCU 59
+#define SM8150_MASTER_TSIF 60
+#define SM8150_MASTER_UFS_MEM 61
+#define SM8150_MASTER_USB3 62
+#define SM8150_MASTER_USB3_1 63
+#define SM8150_MASTER_VIDEO_P0 64
+#define SM8150_MASTER_VIDEO_P1 65
+#define SM8150_MASTER_VIDEO_PROC 66
+#define SM8150_SLAVE_A1NOC_CFG 67
+#define SM8150_SLAVE_A2NOC_CFG 68
+#define SM8150_SLAVE_AHB2PHY_SOUTH 69
+#define SM8150_SLAVE_ANOC_PCIE_GEM_NOC 70
+#define SM8150_SLAVE_AOP 71
+#define SM8150_SLAVE_AOSS 72
+#define SM8150_SLAVE_APPSS 73
+#define SM8150_SLAVE_CAMERA_CFG 74
+#define SM8150_SLAVE_CAMNOC_UNCOMP 75
+#define SM8150_SLAVE_CDSP_CFG 76
+#define SM8150_SLAVE_CDSP_MEM_NOC 77
+#define SM8150_SLAVE_CLK_CTL 78
+#define SM8150_SLAVE_CNOC_A2NOC 79
+#define SM8150_SLAVE_CNOC_DDRSS 80
+#define SM8150_SLAVE_CNOC_MNOC_CFG 81
+#define SM8150_SLAVE_CRYPTO_0_CFG 82
+#define SM8150_SLAVE_DISPLAY_CFG 83
+#define SM8150_SLAVE_EBI_CH0 84
+#define SM8150_SLAVE_EBI_CH0_DISPLAY 85
+#define SM8150_SLAVE_ECC 86
+#define SM8150_SLAVE_EMAC_CFG 87
+#define SM8150_SLAVE_GEM_NOC_CFG 88
+#define SM8150_SLAVE_GEM_NOC_SNOC 89
+#define SM8150_SLAVE_GLM 90
+#define SM8150_SLAVE_GRAPHICS_3D_CFG 91
+#define SM8150_SLAVE_IMEM_CFG 92
+#define SM8150_SLAVE_IPA_CFG 93
+#define SM8150_SLAVE_IPA_CORE 94
+#define SM8150_SLAVE_LLCC 95
+#define SM8150_SLAVE_LLCC_CFG 96
+#define SM8150_SLAVE_LLCC_DISPLAY 97
+#define SM8150_SLAVE_MNOC_HF_MEM_NOC 98
+#define SM8150_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 99
+#define SM8150_SLAVE_MNOC_SF_MEM_NOC 100
+#define SM8150_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 101
+#define SM8150_SLAVE_MSS_PROC_MS_MPU_CFG 102
+#define SM8150_SLAVE_NORTH_PHY_CFG 103
+#define SM8150_SLAVE_NPU_CFG 104
+#define SM8150_SLAVE_OCIMEM 105
+#define SM8150_SLAVE_PCIE_0 106
+#define SM8150_SLAVE_PCIE_0_CFG 107
+#define SM8150_SLAVE_PCIE_1 108
+#define SM8150_SLAVE_PCIE_1_CFG 109
+#define SM8150_SLAVE_PIMEM 110
+#define SM8150_SLAVE_PIMEM_CFG 111
+#define SM8150_SLAVE_PRNG 112
+#define SM8150_SLAVE_QDSS_CFG 113
+#define SM8150_SLAVE_QDSS_STM 114
+#define SM8150_SLAVE_QSPI 115
+#define SM8150_SLAVE_QUP_0 116
+#define SM8150_SLAVE_QUP_1 117
+#define SM8150_SLAVE_QUP_2 118
+#define SM8150_SLAVE_RBCPR_CX_CFG 119
+#define SM8150_SLAVE_RBCPR_MMCX_CFG 120
+#define SM8150_SLAVE_RBCPR_MX_CFG 121
+#define SM8150_SLAVE_SDCC_2 122
+#define SM8150_SLAVE_SDCC_4 123
+#define SM8150_SLAVE_SERVICE_A1NOC 124
+#define SM8150_SLAVE_SERVICE_A2NOC 125
+#define SM8150_SLAVE_SERVICE_CNOC 126
+#define SM8150_SLAVE_SERVICE_GEM_NOC 127
+#define SM8150_SLAVE_SERVICE_MNOC 128
+#define SM8150_SLAVE_SERVICE_SNOC 129
+#define SM8150_SLAVE_SNOC_CFG 130
+#define SM8150_SLAVE_SNOC_GEM_NOC_GC 131
+#define SM8150_SLAVE_SNOC_GEM_NOC_SF 132
+#define SM8150_SLAVE_SPDM_WRAPPER 133
+#define SM8150_SLAVE_SPSS_CFG 134
+#define SM8150_SLAVE_SSC_CFG 135
+#define SM8150_SLAVE_TCSR 136
+#define SM8150_SLAVE_TCU 137
+#define SM8150_SLAVE_TLMM_EAST 138
+#define SM8150_SLAVE_TLMM_NORTH 139
+#define SM8150_SLAVE_TLMM_SOUTH 140
+#define SM8150_SLAVE_TLMM_WEST 141
+#define SM8150_SLAVE_TSIF 142
+#define SM8150_SLAVE_UFS_CARD_CFG 143
+#define SM8150_SLAVE_UFS_MEM_CFG 144
+#define SM8150_SLAVE_USB3 145
+#define SM8150_SLAVE_USB3_1 146
+#define SM8150_SLAVE_VENUS_CFG 147
+#define SM8150_SLAVE_VSENSE_CTRL_CFG 148
+#define SM8150_SNOC_CNOC_MAS 149
+#define SM8150_SNOC_CNOC_SLV 150
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/6] interconnect: qcom: Add SM8250 interconnect provider driver
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
` (2 preceding siblings ...)
2020-07-01 13:42 ` [PATCH 3/6] interconnect: qcom: Add SM8150 interconnect provider driver Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
2020-07-13 13:30 ` Georgi Djakov
2020-07-01 13:42 ` [PATCH 5/6] arm64: dts: qcom: sm8150: add interconnect nodes Jonathan Marek
2020-07-01 13:42 ` [PATCH 6/6] arm64: dts: qcom: sm8250: " Jonathan Marek
5 siblings, 1 reply; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Georgi Djakov, open list,
open list:INTERCONNECT API
Add driver for the Qualcomm interconnect buses found in SM8250 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.
Based on SC7180 driver and generated from downstream dts.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/sm8250.c | 733 +++++++++++++++++++++++++++++
drivers/interconnect/qcom/sm8250.h | 173 +++++++
4 files changed, 918 insertions(+)
create mode 100644 drivers/interconnect/qcom/sm8250.c
create mode 100644 drivers/interconnect/qcom/sm8250.h
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 25486de5a38d..a8f93ba265f8 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -75,5 +75,15 @@ config INTERCONNECT_QCOM_SM8150
This is a driver for the Qualcomm Network-on-Chip on sm8150-based
platforms.
+config INTERCONNECT_QCOM_SM8250
+ tristate "Qualcomm SM8250 interconnect driver"
+ depends on INTERCONNECT_QCOM
+ depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ help
+ This is a driver for the Qualcomm Network-on-Chip on sm8250-based
+ platforms.
+
config INTERCONNECT_QCOM_SMD_RPM
tristate
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 1702ece67dc5..cf628f7990cd 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -9,6 +9,7 @@ icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
qnoc-sdm845-objs := sdm845.o
qnoc-sm8150-objs := sm8150.o
+qnoc-sm8250-objs := sm8250.o
icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@@ -20,4 +21,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c
new file mode 100644
index 000000000000..afc256f09386
--- /dev/null
+++ b/drivers/interconnect/qcom/sm8250.c
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,sm8250.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+#include "sm8250.h"
+
+DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
+DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
+DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
+DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
+DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
+DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
+DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
+DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
+DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
+DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
+DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
+DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
+DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
+DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
+DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
+DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
+DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
+DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
+DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
+DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
+DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
+DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
+DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
+DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
+DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
+DEFINE_QNODE(alc, SM8250_MASTER_ALC, 1, 1);
+DEFINE_QNODE(qnm_mnoc_hf_display, SM8250_MASTER_MNOC_HF_MEM_NOC_DISPLAY, 2, 32, SM8250_SLAVE_LLCC_DISPLAY);
+DEFINE_QNODE(qnm_mnoc_sf_display, SM8250_MASTER_MNOC_SF_MEM_NOC_DISPLAY, 2, 32, SM8250_SLAVE_LLCC_DISPLAY);
+DEFINE_QNODE(llcc_mc_display, SM8250_MASTER_LLCC_DISPLAY, 4, 4, SM8250_SLAVE_EBI_CH0_DISPLAY);
+DEFINE_QNODE(qxm_mdp0_display, SM8250_MASTER_MDP_PORT0_DISPLAY, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qxm_mdp1_display, SM8250_MASTER_MDP_PORT1_DISPLAY, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qxm_rot_display, SM8250_MASTER_ROTATOR_DISPLAY, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
+DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
+DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
+DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
+DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
+DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
+DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
+DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
+DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
+DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
+DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
+DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
+DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
+DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
+DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
+DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
+DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
+DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
+DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
+DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
+DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
+DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
+DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
+DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
+DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
+DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
+DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
+DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
+DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
+DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
+DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
+DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
+DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
+DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
+DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
+DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
+DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
+DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
+DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
+DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
+DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
+DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
+DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
+DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
+DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
+DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
+DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
+DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
+DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
+DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
+DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
+DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
+DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
+DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
+DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
+DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
+DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
+DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
+DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
+DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
+DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
+DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
+DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
+DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
+DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
+DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
+DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
+DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
+DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
+DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
+DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
+DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
+DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
+DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
+DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
+DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
+DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
+DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
+DEFINE_QNODE(qns_llcc_display, SM8250_SLAVE_LLCC_DISPLAY, 4, 16, SM8250_MASTER_LLCC_DISPLAY);
+DEFINE_QNODE(ebi_display, SM8250_SLAVE_EBI_CH0_DISPLAY, 4, 4);
+DEFINE_QNODE(qns_mem_noc_hf_display, SM8250_SLAVE_MNOC_HF_MEM_NOC_DISPLAY, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC_DISPLAY);
+DEFINE_QNODE(qns_mem_noc_sf_display, SM8250_SLAVE_MNOC_SF_MEM_NOC_DISPLAY, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC_DISPLAY);
+
+DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
+DEFINE_QBCM(bcm_alc, "ALC", false, &alc);
+DEFINE_QBCM(bcm_mc0, "MC0", false, &ebi);
+DEFINE_QBCM(bcm_sh0, "SH0", false, &qns_llcc);
+DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
+DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
+DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
+DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
+DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
+DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
+DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
+DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
+DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
+DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
+DEFINE_QBCM(bcm_sn0, "SN0", false, &qns_gemnoc_sf);
+DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
+DEFINE_QBCM(bcm_cn0, "CN0", false, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
+DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
+DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
+DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
+DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
+DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
+DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
+DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
+DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
+DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
+DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
+DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
+DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
+DEFINE_QBCM(bcm_acv_display, "ACV", false, &ebi_display);
+/* DEFINE_QBCM(bcm_alc_display, "ALC", false); */
+DEFINE_QBCM(bcm_mc0_display, "MC0", false, &ebi_display);
+DEFINE_QBCM(bcm_sh0_display, "SH0", false, &qns_llcc_display);
+DEFINE_QBCM(bcm_mm0_display, "MM0", false, &qns_mem_noc_hf_display);
+DEFINE_QBCM(bcm_mm1_display, "MM1", false, &qxm_mdp0_display, &qxm_mdp1_display);
+DEFINE_QBCM(bcm_mm2_display, "MM2", false, &qns_mem_noc_sf_display);
+
+static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
+ &bcm_qup0,
+ &bcm_sn12,
+};
+
+static struct qcom_icc_node *aggre1_noc_nodes[] = {
+ [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
+ [MASTER_QSPI_0] = &qhm_qspi,
+ [MASTER_QUP_1] = &qhm_qup1,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_TSIF] = &qhm_tsif,
+ [MASTER_PCIE_2] = &xm_pcie3_modem,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3_0,
+ [MASTER_USB3_1] = &xm_usb3_1,
+ [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
+ [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
+ [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
+};
+
+static struct qcom_icc_desc sm8250_aggre1_noc = {
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+};
+
+static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
+ &bcm_ce0,
+ &bcm_qup0,
+ &bcm_sn12,
+};
+
+static struct qcom_icc_node *aggre2_noc_nodes[] = {
+ [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
+ [MASTER_QDSS_BAM] = &qhm_qdss_bam,
+ [MASTER_QUP_0] = &qhm_qup0,
+ [MASTER_CNOC_A2NOC] = &qnm_cnoc,
+ [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_PCIE] = &xm_pcie3_0,
+ [MASTER_PCIE_1] = &xm_pcie3_1,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_UFS_CARD] = &xm_ufs_card,
+ [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
+ [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
+};
+
+static struct qcom_icc_desc sm8250_aggre2_noc = {
+ .nodes = aggre2_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
+ .bcms = aggre2_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+};
+
+static struct qcom_icc_bcm *compute_noc_bcms[] = {
+ &bcm_co0,
+ &bcm_co2,
+};
+
+static struct qcom_icc_node *compute_noc_nodes[] = {
+ [MASTER_NPU] = &qnm_npu,
+ [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
+};
+
+static struct qcom_icc_desc sm8250_compute_noc = {
+ .nodes = compute_noc_nodes,
+ .num_nodes = ARRAY_SIZE(compute_noc_nodes),
+ .bcms = compute_noc_bcms,
+ .num_bcms = ARRAY_SIZE(compute_noc_bcms),
+};
+
+static struct qcom_icc_bcm *config_noc_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node *config_noc_nodes[] = {
+ [SNOC_CNOC_MAS] = &qnm_snoc,
+ [MASTER_QDSS_DAP] = &xm_qdss_dap,
+ [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
+ [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
+ [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
+ [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
+ [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
+ [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
+ [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
+ [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
+ [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_LPASS] = &qhs_lpass_cfg,
+ [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
+ [SLAVE_NPU_CFG] = &qhs_npu_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+ [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
+ [SLAVE_PDM] = &qhs_pdm,
+ [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_0] = &qhs_qup0,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
+ [SLAVE_TCSR] = &qhs_tcsr,
+ [SLAVE_TLMM_NORTH] = &qhs_tlmm0,
+ [SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
+ [SLAVE_TLMM_WEST] = &qhs_tlmm2,
+ [SLAVE_TSIF] = &qhs_tsif,
+ [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3_0,
+ [SLAVE_USB3_1] = &qhs_usb3_1,
+ [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
+ [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
+};
+
+static struct qcom_icc_desc sm8250_config_noc = {
+ .nodes = config_noc_nodes,
+ .num_nodes = ARRAY_SIZE(config_noc_nodes),
+ .bcms = config_noc_bcms,
+ .num_bcms = ARRAY_SIZE(config_noc_bcms),
+};
+
+static struct qcom_icc_bcm *dc_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *dc_noc_nodes[] = {
+ [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
+ [SLAVE_LLCC_CFG] = &qhs_llcc,
+ [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
+};
+
+static struct qcom_icc_desc sm8250_dc_noc = {
+ .nodes = dc_noc_nodes,
+ .num_nodes = ARRAY_SIZE(dc_noc_nodes),
+ .bcms = dc_noc_bcms,
+ .num_bcms = ARRAY_SIZE(dc_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_bcms[] = {
+ &bcm_sh0,
+ &bcm_sh2,
+ &bcm_sh3,
+ &bcm_sh4,
+};
+
+static struct qcom_icc_node *gem_noc_nodes[] = {
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_AMPSS_M0] = &chm_apps,
+ [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
+ [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
+ [MASTER_GRAPHICS_3D] = &qnm_gpu,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
+ [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
+ [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
+ [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
+};
+
+static struct qcom_icc_desc sm8250_gem_noc = {
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm *ipa_virt_bcms[] = {
+ &bcm_ip0,
+};
+
+static struct qcom_icc_node *ipa_virt_nodes[] = {
+ [MASTER_IPA_CORE] = &ipa_core_master,
+ [SLAVE_IPA_CORE] = &ipa_core_slave,
+};
+
+static struct qcom_icc_desc sm8250_ipa_virt = {
+ .nodes = ipa_virt_nodes,
+ .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
+ .bcms = ipa_virt_bcms,
+ .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_alc,
+ &bcm_mc0,
+};
+
+static struct qcom_icc_node *mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_ALC] = &alc,
+ [SLAVE_EBI_CH0] = &ebi,
+};
+
+static struct qcom_icc_desc sm8250_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+ &bcm_mm2,
+ &bcm_mm3,
+};
+
+static struct qcom_icc_node *mmss_noc_nodes[] = {
+ [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_VIDEO_P0] = &qnm_video0,
+ [MASTER_VIDEO_P1] = &qnm_video1,
+ [MASTER_VIDEO_PROC] = &qnm_video_cvp,
+ [MASTER_MDP_PORT0] = &qxm_mdp0,
+ [MASTER_MDP_PORT1] = &qxm_mdp1,
+ [MASTER_ROTATOR] = &qxm_rot,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+ [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
+};
+
+static struct qcom_icc_desc sm8250_mmss_noc = {
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm *npu_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *npu_noc_nodes[] = {
+ [MASTER_NPU_SYS] = &amm_npu_sys,
+ [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
+ [MASTER_NPU_NOC_CFG] = &qhm_cfg,
+ [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
+ [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
+ [SLAVE_NPU_CP] = &qhs_cp,
+ [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
+ [SLAVE_NPU_DPM] = &qhs_dpm,
+ [SLAVE_ISENSE_CFG] = &qhs_isense,
+ [SLAVE_NPU_LLM_CFG] = &qhs_llm,
+ [SLAVE_NPU_TCM] = &qhs_tcm,
+ [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
+ [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
+};
+
+static struct qcom_icc_desc sm8250_npu_noc = {
+ .nodes = npu_noc_nodes,
+ .num_nodes = ARRAY_SIZE(npu_noc_nodes),
+ .bcms = npu_noc_bcms,
+ .num_bcms = ARRAY_SIZE(npu_noc_bcms),
+};
+
+static struct qcom_icc_bcm *system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn1,
+ &bcm_sn11,
+ &bcm_sn2,
+ &bcm_sn3,
+ &bcm_sn4,
+ &bcm_sn5,
+ &bcm_sn6,
+ &bcm_sn7,
+ &bcm_sn8,
+ &bcm_sn9,
+};
+
+static struct qcom_icc_node *system_noc_nodes[] = {
+ [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
+ [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
+ [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
+ [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [MASTER_PIMEM] = &qxm_pimem,
+ [MASTER_GIC] = &xm_gic,
+ [SLAVE_APPSS] = &qhs_apss,
+ [SNOC_CNOC_SLV] = &qns_cnoc,
+ [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+ [SLAVE_OCIMEM] = &qxs_imem,
+ [SLAVE_PIMEM] = &qxs_pimem,
+ [SLAVE_SERVICE_SNOC] = &srvc_snoc,
+ [SLAVE_PCIE_0] = &xs_pcie_0,
+ [SLAVE_PCIE_1] = &xs_pcie_1,
+ [SLAVE_PCIE_2] = &xs_pcie_modem,
+ [SLAVE_QDSS_STM] = &xs_qdss_stm,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static struct qcom_icc_desc sm8250_system_noc = {
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_display_bcms[] = {
+ &bcm_sh0_display,
+};
+
+static struct qcom_icc_node *gem_noc_display_nodes[] = {
+ [MASTER_MNOC_HF_MEM_NOC_DISPLAY] = &qnm_mnoc_hf_display,
+ [MASTER_MNOC_SF_MEM_NOC_DISPLAY] = &qnm_mnoc_sf_display,
+ [SLAVE_LLCC_DISPLAY] = &qns_llcc_display,
+};
+
+static struct qcom_icc_desc sm8250_gem_noc_display = {
+ .nodes = gem_noc_display_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_display_nodes),
+ .bcms = gem_noc_display_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_display_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_display_bcms[] = {
+ &bcm_acv_display,
+ &bcm_mc0_display,
+};
+
+static struct qcom_icc_node *mc_virt_display_nodes[] = {
+ [MASTER_LLCC_DISPLAY] = &llcc_mc_display,
+ [SLAVE_EBI_CH0_DISPLAY] = &ebi_display,
+};
+
+static struct qcom_icc_desc sm8250_mc_virt_display = {
+ .nodes = mc_virt_display_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_display_nodes),
+ .bcms = mc_virt_display_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_display_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_display_bcms[] = {
+ &bcm_mm0_display,
+ &bcm_mm1_display,
+ &bcm_mm2_display,
+};
+
+static struct qcom_icc_node *mmss_noc_display_nodes[] = {
+ [MASTER_MDP_PORT0_DISPLAY] = &qxm_mdp0_display,
+ [MASTER_MDP_PORT1_DISPLAY] = &qxm_mdp1_display,
+ [MASTER_ROTATOR_DISPLAY] = &qxm_rot_display,
+ [SLAVE_MNOC_HF_MEM_NOC_DISPLAY] = &qns_mem_noc_hf_display,
+ [SLAVE_MNOC_SF_MEM_NOC_DISPLAY] = &qns_mem_noc_sf_display,
+};
+
+static struct qcom_icc_desc sm8250_mmss_noc_display = {
+ .nodes = mmss_noc_display_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_display_nodes),
+ .bcms = mmss_noc_display_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_display_bcms),
+};
+
+static int qnoc_probe(struct platform_device *pdev)
+{
+ const struct qcom_icc_desc *desc;
+ struct icc_onecell_data *data;
+ struct icc_provider *provider;
+ struct qcom_icc_node **qnodes;
+ struct qcom_icc_provider *qp;
+ struct icc_node *node;
+ size_t num_nodes, i;
+ int ret;
+
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ qnodes = desc->nodes;
+ num_nodes = desc->num_nodes;
+
+ qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
+ if (!qp)
+ return -ENOMEM;
+
+ data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ provider = &qp->provider;
+ provider->dev = &pdev->dev;
+ provider->set = qcom_icc_set;
+ provider->pre_aggregate = qcom_icc_pre_aggregate;
+ provider->aggregate = qcom_icc_aggregate;
+ provider->xlate = of_icc_xlate_onecell;
+ INIT_LIST_HEAD(&provider->nodes);
+ provider->data = data;
+
+ qp->dev = &pdev->dev;
+ qp->bcms = desc->bcms;
+ qp->num_bcms = desc->num_bcms;
+
+ qp->voter = of_bcm_voter_get(qp->dev, NULL);
+ if (IS_ERR(qp->voter))
+ return PTR_ERR(qp->voter);
+
+ ret = icc_provider_add(provider);
+ if (ret) {
+ dev_err(&pdev->dev, "error adding interconnect provider\n");
+ return ret;
+ }
+
+ for (i = 0; i < num_nodes; i++) {
+ size_t j;
+
+ if (!qnodes[i])
+ continue;
+
+ node = icc_node_create(qnodes[i]->id);
+ if (IS_ERR(node)) {
+ ret = PTR_ERR(node);
+ goto err;
+ }
+
+ node->name = qnodes[i]->name;
+ node->data = qnodes[i];
+ icc_node_add(node, provider);
+
+ for (j = 0; j < qnodes[i]->num_links; j++)
+ icc_link_create(node, qnodes[i]->links[j]);
+
+ data->nodes[i] = node;
+ }
+ data->num_nodes = num_nodes;
+
+ for (i = 0; i < qp->num_bcms; i++)
+ qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
+
+ platform_set_drvdata(pdev, qp);
+
+ return 0;
+err:
+ icc_nodes_remove(provider);
+ icc_provider_del(provider);
+ return ret;
+}
+
+static int qnoc_remove(struct platform_device *pdev)
+{
+ struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
+
+ icc_nodes_remove(&qp->provider);
+ return icc_provider_del(&qp->provider);
+}
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,sm8250-aggre1-noc",
+ .data = &sm8250_aggre1_noc},
+ { .compatible = "qcom,sm8250-aggre2-noc",
+ .data = &sm8250_aggre2_noc},
+ { .compatible = "qcom,sm8250-compute-noc",
+ .data = &sm8250_compute_noc},
+ { .compatible = "qcom,sm8250-config-noc",
+ .data = &sm8250_config_noc},
+ { .compatible = "qcom,sm8250-dc-noc",
+ .data = &sm8250_dc_noc},
+ { .compatible = "qcom,sm8250-gem-noc",
+ .data = &sm8250_gem_noc},
+ { .compatible = "qcom,sm8250-ipa-virt",
+ .data = &sm8250_ipa_virt},
+ { .compatible = "qcom,sm8250-mc-virt",
+ .data = &sm8250_mc_virt},
+ { .compatible = "qcom,sm8250-mmss-noc",
+ .data = &sm8250_mmss_noc},
+ { .compatible = "qcom,sm8250-npu-noc",
+ .data = &sm8250_npu_noc},
+ { .compatible = "qcom,sm8250-system-noc",
+ .data = &sm8250_system_noc},
+ { .compatible = "qcom,sm8250-gem-noc-display",
+ .data = &sm8250_gem_noc_display},
+ { .compatible = "qcom,sm8250-mc-virt-display",
+ .data = &sm8250_mc_virt_display},
+ { .compatible = "qcom,sm8250-mmss-noc-display",
+ .data = &sm8250_mmss_noc_display},
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qnoc_probe,
+ .remove = qnoc_remove,
+ .driver = {
+ .name = "qnoc-sm8250",
+ .of_match_table = qnoc_of_match,
+ },
+};
+module_platform_driver(qnoc_driver);
+
+MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h
new file mode 100644
index 000000000000..19888a171b50
--- /dev/null
+++ b/drivers/interconnect/qcom/sm8250.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm #define SM8250 interconnect IDs
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
+#define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
+
+#define SM8250_A1NOC_SNOC_MAS 0
+#define SM8250_A1NOC_SNOC_SLV 1
+#define SM8250_A2NOC_SNOC_MAS 2
+#define SM8250_A2NOC_SNOC_SLV 3
+#define SM8250_MASTER_A1NOC_CFG 4
+#define SM8250_MASTER_A2NOC_CFG 5
+#define SM8250_MASTER_ALC 6
+#define SM8250_MASTER_AMPSS_M0 7
+#define SM8250_MASTER_ANOC_PCIE_GEM_NOC 8
+#define SM8250_MASTER_CAMNOC_HF 9
+#define SM8250_MASTER_CAMNOC_ICP 10
+#define SM8250_MASTER_CAMNOC_SF 11
+#define SM8250_MASTER_CNOC_A2NOC 12
+#define SM8250_MASTER_CNOC_DC_NOC 13
+#define SM8250_MASTER_CNOC_MNOC_CFG 14
+#define SM8250_MASTER_COMPUTE_NOC 15
+#define SM8250_MASTER_CRYPTO_CORE_0 16
+#define SM8250_MASTER_GEM_NOC_CFG 17
+#define SM8250_MASTER_GEM_NOC_PCIE_SNOC 18
+#define SM8250_MASTER_GEM_NOC_SNOC 19
+#define SM8250_MASTER_GIC 20
+#define SM8250_MASTER_GPU_TCU 21
+#define SM8250_MASTER_GRAPHICS_3D 22
+#define SM8250_MASTER_IPA 23
+#define SM8250_MASTER_IPA_CORE 24
+#define SM8250_MASTER_LLCC 25
+#define SM8250_MASTER_LLCC_DISPLAY 26
+#define SM8250_MASTER_MDP_PORT0 27
+#define SM8250_MASTER_MDP_PORT0_DISPLAY 28
+#define SM8250_MASTER_MDP_PORT1 29
+#define SM8250_MASTER_MDP_PORT1_DISPLAY 30
+#define SM8250_MASTER_MNOC_HF_MEM_NOC 31
+#define SM8250_MASTER_MNOC_HF_MEM_NOC_DISPLAY 32
+#define SM8250_MASTER_MNOC_SF_MEM_NOC 33
+#define SM8250_MASTER_MNOC_SF_MEM_NOC_DISPLAY 34
+#define SM8250_MASTER_NPU 35
+#define SM8250_MASTER_NPU_CDP 36
+#define SM8250_MASTER_NPU_NOC_CFG 37
+#define SM8250_MASTER_NPU_SYS 38
+#define SM8250_MASTER_PCIE 39
+#define SM8250_MASTER_PCIE_1 40
+#define SM8250_MASTER_PCIE_2 41
+#define SM8250_MASTER_PIMEM 42
+#define SM8250_MASTER_QDSS_BAM 43
+#define SM8250_MASTER_QDSS_DAP 44
+#define SM8250_MASTER_QDSS_ETR 45
+#define SM8250_MASTER_QSPI_0 46
+#define SM8250_MASTER_QUP_0 47
+#define SM8250_MASTER_QUP_1 48
+#define SM8250_MASTER_QUP_2 49
+#define SM8250_MASTER_ROTATOR 50
+#define SM8250_MASTER_ROTATOR_DISPLAY 51
+#define SM8250_MASTER_SDCC_2 52
+#define SM8250_MASTER_SDCC_4 53
+#define SM8250_MASTER_SNOC_CFG 54
+#define SM8250_MASTER_SNOC_GC_MEM_NOC 55
+#define SM8250_MASTER_SNOC_SF_MEM_NOC 56
+#define SM8250_MASTER_SYS_TCU 57
+#define SM8250_MASTER_TSIF 58
+#define SM8250_MASTER_UFS_CARD 59
+#define SM8250_MASTER_UFS_MEM 60
+#define SM8250_MASTER_USB3 61
+#define SM8250_MASTER_USB3_1 62
+#define SM8250_MASTER_VIDEO_P0 63
+#define SM8250_MASTER_VIDEO_P1 64
+#define SM8250_MASTER_VIDEO_PROC 65
+#define SM8250_SLAVE_A1NOC_CFG 66
+#define SM8250_SLAVE_A2NOC_CFG 67
+#define SM8250_SLAVE_AHB2PHY_NORTH 68
+#define SM8250_SLAVE_AHB2PHY_SOUTH 69
+#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 70
+#define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 71
+#define SM8250_SLAVE_AOSS 72
+#define SM8250_SLAVE_APPSS 73
+#define SM8250_SLAVE_CAMERA_CFG 74
+#define SM8250_SLAVE_CDSP_CFG 75
+#define SM8250_SLAVE_CDSP_MEM_NOC 76
+#define SM8250_SLAVE_CLK_CTL 77
+#define SM8250_SLAVE_CNOC_A2NOC 78
+#define SM8250_SLAVE_CNOC_DDRSS 79
+#define SM8250_SLAVE_CNOC_MNOC_CFG 80
+#define SM8250_SLAVE_CRYPTO_0_CFG 81
+#define SM8250_SLAVE_CX_RDPM 82
+#define SM8250_SLAVE_DCC_CFG 83
+#define SM8250_SLAVE_DISPLAY_CFG 84
+#define SM8250_SLAVE_EBI_CH0 85
+#define SM8250_SLAVE_EBI_CH0_DISPLAY 86
+#define SM8250_SLAVE_GEM_NOC_CFG 87
+#define SM8250_SLAVE_GEM_NOC_SNOC 88
+#define SM8250_SLAVE_GRAPHICS_3D_CFG 89
+#define SM8250_SLAVE_IMEM_CFG 90
+#define SM8250_SLAVE_IPA_CFG 91
+#define SM8250_SLAVE_IPA_CORE 92
+#define SM8250_SLAVE_IPC_ROUTER_CFG 93
+#define SM8250_SLAVE_ISENSE_CFG 94
+#define SM8250_SLAVE_LLCC 95
+#define SM8250_SLAVE_LLCC_CFG 96
+#define SM8250_SLAVE_LLCC_DISPLAY 97
+#define SM8250_SLAVE_LPASS 98
+#define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 99
+#define SM8250_SLAVE_MNOC_HF_MEM_NOC 100
+#define SM8250_SLAVE_MNOC_HF_MEM_NOC_DISPLAY 101
+#define SM8250_SLAVE_MNOC_SF_MEM_NOC 102
+#define SM8250_SLAVE_MNOC_SF_MEM_NOC_DISPLAY 103
+#define SM8250_SLAVE_NPU_CAL_DP0 104
+#define SM8250_SLAVE_NPU_CAL_DP1 105
+#define SM8250_SLAVE_NPU_CFG 106
+#define SM8250_SLAVE_NPU_COMPUTE_NOC 107
+#define SM8250_SLAVE_NPU_CP 108
+#define SM8250_SLAVE_NPU_DPM 109
+#define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 110
+#define SM8250_SLAVE_NPU_LLM_CFG 111
+#define SM8250_SLAVE_NPU_TCM 112
+#define SM8250_SLAVE_OCIMEM 113
+#define SM8250_SLAVE_PCIE_0 114
+#define SM8250_SLAVE_PCIE_0_CFG 115
+#define SM8250_SLAVE_PCIE_1 116
+#define SM8250_SLAVE_PCIE_1_CFG 117
+#define SM8250_SLAVE_PCIE_2 118
+#define SM8250_SLAVE_PCIE_2_CFG 119
+#define SM8250_SLAVE_PDM 120
+#define SM8250_SLAVE_PIMEM 121
+#define SM8250_SLAVE_PIMEM_CFG 122
+#define SM8250_SLAVE_PRNG 123
+#define SM8250_SLAVE_QDSS_CFG 124
+#define SM8250_SLAVE_QDSS_STM 125
+#define SM8250_SLAVE_QSPI_0 126
+#define SM8250_SLAVE_QUP_0 127
+#define SM8250_SLAVE_QUP_1 128
+#define SM8250_SLAVE_QUP_2 129
+#define SM8250_SLAVE_RBCPR_CX_CFG 130
+#define SM8250_SLAVE_RBCPR_MMCX_CFG 131
+#define SM8250_SLAVE_RBCPR_MX_CFG 132
+#define SM8250_SLAVE_SDCC_2 133
+#define SM8250_SLAVE_SDCC_4 134
+#define SM8250_SLAVE_SERVICE_A1NOC 135
+#define SM8250_SLAVE_SERVICE_A2NOC 136
+#define SM8250_SLAVE_SERVICE_CNOC 137
+#define SM8250_SLAVE_SERVICE_GEM_NOC 138
+#define SM8250_SLAVE_SERVICE_GEM_NOC_1 139
+#define SM8250_SLAVE_SERVICE_GEM_NOC_2 140
+#define SM8250_SLAVE_SERVICE_MNOC 141
+#define SM8250_SLAVE_SERVICE_NPU_NOC 142
+#define SM8250_SLAVE_SERVICE_SNOC 143
+#define SM8250_SLAVE_SNOC_CFG 144
+#define SM8250_SLAVE_SNOC_GEM_NOC_GC 145
+#define SM8250_SLAVE_SNOC_GEM_NOC_SF 146
+#define SM8250_SLAVE_TCSR 147
+#define SM8250_SLAVE_TCU 148
+#define SM8250_SLAVE_TLMM_NORTH 149
+#define SM8250_SLAVE_TLMM_SOUTH 150
+#define SM8250_SLAVE_TLMM_WEST 151
+#define SM8250_SLAVE_TSIF 152
+#define SM8250_SLAVE_UFS_CARD_CFG 153
+#define SM8250_SLAVE_UFS_MEM_CFG 154
+#define SM8250_SLAVE_USB3 155
+#define SM8250_SLAVE_USB3_1 156
+#define SM8250_SLAVE_VENUS_CFG 157
+#define SM8250_SLAVE_VSENSE_CTRL_CFG 158
+#define SM8250_SNOC_CNOC_MAS 159
+#define SM8250_SNOC_CNOC_SLV 160
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/6] arm64: dts: qcom: sm8150: add interconnect nodes
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
` (3 preceding siblings ...)
2020-07-01 13:42 ` [PATCH 4/6] interconnect: qcom: Add SM8250 " Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
2020-07-01 13:42 ` [PATCH 6/6] arm64: dts: qcom: sm8250: " Jonathan Marek
5 siblings, 0 replies; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add the interconnect dts nodes for sm8150.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 118 +++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 5272e27eca70..747521666700 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+#include <dt-bindings/interconnect/qcom,sm8150.h>
/ {
interrupt-parent = <&intc>;
@@ -431,6 +432,75 @@ uart2: serial@a90000 {
};
};
+ dc_noc: interconnect@14e0000 {
+ compatible = "qcom,sm8150-dc-noc";
+ reg = <0 0x014e0000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm8150-config-noc";
+ reg = <0 0x01500000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ camnoc_virt: interconnect@1620000 {
+ compatible = "qcom,sm8150-camnoc-virt";
+ reg = <0 0x01620000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ ipa_virt: interconnect-ipa@1620000 {
+ compatible = "qcom,sm8150-ipa-virt";
+ reg = <0 0x01620000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1629000 {
+ compatible = "qcom,sm8150-system-noc";
+ reg = <0 0x01629000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e4000 {
+ compatible = "qcom,sm8150-aggre1-noc";
+ reg = <0 0x016e4000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1706000 {
+ compatible = "qcom,sm8150-aggre2-noc";
+ reg = <0 0x01706000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ compute_noc: interconnect@1720000 {
+ compatible = "qcom,sm8150-compute-noc";
+ reg = <0 0x01720000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1749000 {
+ compatible = "qcom,sm8150-mmss-noc";
+ reg = <0 0x01749000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc_display: interconnect-display@1749000 {
+ compatible = "qcom,sm8150-mmss-noc-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -851,6 +921,32 @@ usb_2_ssphy: lane@88eb200 {
};
};
+ mc_virt: interconnect@9680000 {
+ compatible = "qcom,sm8150-mc-virt";
+ reg = <0 0x09680000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt_display: interconnect-display@9680000 {
+ compatible = "qcom,sm8150-mc-virt-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
+ gem_noc: interconnect@96ab000 {
+ compatible = "qcom,sm8150-gem-noc";
+ reg = <0 0x096ab000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc_display: interconnect-display@96ab000 {
+ compatible = "qcom,sm8150-gem-noc-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@@ -941,6 +1037,24 @@ usb_2_dwc3: dwc3@a800000 {
};
};
+ disp_rsc: rsc@af20000 {
+ label = "display_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0xaf20000 0x0 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <ACTIVE_TCS 2>,
+ <CONTROL_TCS 0>;
+
+ disp_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x100000>;
@@ -1249,6 +1363,10 @@ rpmhpd_opp_turbo_l1: opp11 {
};
};
};
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
};
cpufreq_hw: cpufreq@18323000 {
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/6] arm64: dts: qcom: sm8250: add interconnect nodes
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
` (4 preceding siblings ...)
2020-07-01 13:42 ` [PATCH 5/6] arm64: dts: qcom: sm8150: add interconnect nodes Jonathan Marek
@ 2020-07-01 13:42 ` Jonathan Marek
5 siblings, 0 replies; 13+ messages in thread
From: Jonathan Marek @ 2020-07-01 13:42 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add the interconnect dts nodes for sm8250.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 118 +++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index c9b38dd88f43..b417523f1f1b 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/interconnect/qcom,sm8250.h>
/ {
interrupt-parent = <&intc>;
@@ -310,6 +311,61 @@ uart2: serial@a90000 {
};
};
+ config_noc: interconnect@1500000 {
+ compatible = "qcom,sm8250-config-noc";
+ reg = <0 0x01500000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ ipa_virt: interconnect@1620000 {
+ compatible = "qcom,sm8250-ipa-virt";
+ reg = <0 0x01620000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1632000 {
+ compatible = "qcom,sm8250-system-noc";
+ reg = <0 0x01632000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e2000 {
+ compatible = "qcom,sm8250-aggre1-noc";
+ reg = <0 0x016e2000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1703000 {
+ compatible = "qcom,sm8250-aggre2-noc";
+ reg = <0 0x01703000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ compute_noc: interconnect@1733000 {
+ compatible = "qcom,sm8250-compute-noc";
+ reg = <0 0x01733000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@174a000 {
+ compatible = "qcom,sm8250-mmss-noc";
+ reg = <0 0x0174a000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc_display: interconnect-display@174a000 {
+ compatible = "qcom,sm8250-mmss-noc-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -620,6 +676,46 @@ usb_2_ssphy: lane@88eb200 {
};
};
+ dc_noc: interconnect@90c0000 {
+ compatible = "qcom,sm8250-dc-noc";
+ reg = <0 0x090c0000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@9100000 {
+ compatible = "qcom,sm8250-mc-virt";
+ reg = <0 0x09100000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt_display: interconnect-display@9100000 {
+ compatible = "qcom,sm8250-mc-virt-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9121000 {
+ compatible = "qcom,sm8250-gem-noc";
+ reg = <0 0x09121000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc_display: interconnect-display@9121000 {
+ compatible = "qcom,sm8250-gem-noc-display";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&disp_bcm_voter>;
+ };
+
+ npu_noc: interconnect@9990000 {
+ compatible = "qcom,sm8250-npu-noc";
+ reg = <0 0x09990000 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@@ -710,6 +806,24 @@ usb_2_dwc3: dwc3@a800000 {
};
};
+ disp_rsc: rsc@af20000 {
+ label = "disp_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0xaf20000 0x0 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <ACTIVE_TCS 0>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+
+ disp_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8250-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@@ -997,6 +1111,10 @@ rpmhpd_opp_turbo_l1: opp10 {
};
};
};
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
};
cpufreq_hw: cpufreq@18591000 {
--
2.26.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings
2020-07-01 13:42 ` [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings Jonathan Marek
@ 2020-07-02 20:48 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-07-02 20:48 UTC (permalink / raw)
To: Jonathan Marek
Cc: Rob Herring, devicetree, linux-kernel, linux-arm-msm, linux-pm,
Bjorn Andersson, Georgi Djakov, Andy Gross
On Wed, 01 Jul 2020 09:42:50 -0400, Jonathan Marek wrote:
> The Qualcomm SM8150 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../bindings/interconnect/qcom,sm8150.yaml | 86 +++++++++
> .../dt-bindings/interconnect/qcom,sm8150.h | 176 ++++++++++++++++++
> 2 files changed, 262 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml: maintainers:0: None is not of type 'string'
Documentation/devicetree/bindings/Makefile:20: recipe for target 'Documentation/devicetree/bindings/interconnect/qcom,sm8150.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/interconnect/qcom,sm8150.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/interconnect/qcom,sm8150.yaml
Makefile:1347: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1320475
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings
2020-07-01 13:42 ` [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 " Jonathan Marek
@ 2020-07-02 20:49 ` Rob Herring
2020-07-02 20:49 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-07-02 20:49 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Bjorn Andersson, Georgi Djakov,
open list:INTERCONNECT API,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
On Wed, Jul 01, 2020 at 09:42:51AM -0400, Jonathan Marek wrote:
> The Qualcomm SM8250 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
Again, looks like these 2 could be combined.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../bindings/interconnect/qcom,sm8250.yaml | 86 ++++++++
> .../dt-bindings/interconnect/qcom,sm8250.h | 186 ++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 DT bindings
2020-07-01 13:42 ` [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 " Jonathan Marek
2020-07-02 20:49 ` Rob Herring
@ 2020-07-02 20:49 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-07-02 20:49 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-kernel, linux-arm-msm, Andy Gross, Bjorn Andersson,
Georgi Djakov, devicetree, linux-pm, Rob Herring
On Wed, 01 Jul 2020 09:42:51 -0400, Jonathan Marek wrote:
> The Qualcomm SM8250 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../bindings/interconnect/qcom,sm8250.yaml | 86 ++++++++
> .../dt-bindings/interconnect/qcom,sm8250.h | 186 ++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,sm8250.h
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml: maintainers:0: None is not of type 'string'
Documentation/devicetree/bindings/Makefile:20: recipe for target 'Documentation/devicetree/bindings/interconnect/qcom,sm8250.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/interconnect/qcom,sm8250.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml: ignoring, error in schema: maintainers: 0
warning: no schema found in file: ./Documentation/devicetree/bindings/interconnect/qcom,sm8250.yaml
Makefile:1347: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1320476
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/6] interconnect: qcom: Add SM8250 interconnect provider driver
2020-07-01 13:42 ` [PATCH 4/6] interconnect: qcom: Add SM8250 " Jonathan Marek
@ 2020-07-13 13:30 ` Georgi Djakov
2020-07-13 13:47 ` Jonathan Marek
0 siblings, 1 reply; 13+ messages in thread
From: Georgi Djakov @ 2020-07-13 13:30 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, linux-kernel, linux-pm
Hi Jonathan,
Thanks for posting these patches!
On 7/1/20 16:42, Jonathan Marek wrote:
> Add driver for the Qualcomm interconnect buses found in SM8250 based
> platforms. The topology consists of several NoCs that are controlled by
> a remote processor that collects the aggregated bandwidth for each
> master-slave pairs.
>
> Based on SC7180 driver and generated from downstream dts.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
[..]
> +
> +static const struct of_device_id qnoc_of_match[] = {
> + { .compatible = "qcom,sm8250-aggre1-noc",
> + .data = &sm8250_aggre1_noc},
> + { .compatible = "qcom,sm8250-aggre2-noc",
> + .data = &sm8250_aggre2_noc},
> + { .compatible = "qcom,sm8250-compute-noc",
> + .data = &sm8250_compute_noc},
> + { .compatible = "qcom,sm8250-config-noc",
> + .data = &sm8250_config_noc},
> + { .compatible = "qcom,sm8250-dc-noc",
> + .data = &sm8250_dc_noc},
> + { .compatible = "qcom,sm8250-gem-noc",
> + .data = &sm8250_gem_noc},
> + { .compatible = "qcom,sm8250-ipa-virt",
> + .data = &sm8250_ipa_virt},
> + { .compatible = "qcom,sm8250-mc-virt",
> + .data = &sm8250_mc_virt},
> + { .compatible = "qcom,sm8250-mmss-noc",
> + .data = &sm8250_mmss_noc},
> + { .compatible = "qcom,sm8250-npu-noc",
> + .data = &sm8250_npu_noc},
> + { .compatible = "qcom,sm8250-system-noc",
> + .data = &sm8250_system_noc},
> + { .compatible = "qcom,sm8250-gem-noc-display",
> + .data = &sm8250_gem_noc_display},
> + { .compatible = "qcom,sm8250-mc-virt-display",
> + .data = &sm8250_mc_virt_display},
> + { .compatible = "qcom,sm8250-mmss-noc-display",
> + .data = &sm8250_mmss_noc_display},
> + { }
My main concern here are the display RSC nodes. We should not add the nodes
for voting on the display RSC, but use the "qcom,bcm-voters" property in DT
to list both "hlos" and "disp" as bcm voters for gem-noc, mc-virt and
mmss-noc.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/6] interconnect: qcom: Add SM8250 interconnect provider driver
2020-07-13 13:30 ` Georgi Djakov
@ 2020-07-13 13:47 ` Jonathan Marek
2020-07-13 14:19 ` Georgi Djakov
0 siblings, 1 reply; 13+ messages in thread
From: Jonathan Marek @ 2020-07-13 13:47 UTC (permalink / raw)
To: Georgi Djakov, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, linux-kernel, linux-pm
On 7/13/20 9:30 AM, Georgi Djakov wrote:
> Hi Jonathan,
>
> Thanks for posting these patches!
>
> On 7/1/20 16:42, Jonathan Marek wrote:
>> Add driver for the Qualcomm interconnect buses found in SM8250 based
>> platforms. The topology consists of several NoCs that are controlled by
>> a remote processor that collects the aggregated bandwidth for each
>> master-slave pairs.
>>
>> Based on SC7180 driver and generated from downstream dts.
>>
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
> [..]
>> +
>> +static const struct of_device_id qnoc_of_match[] = {
>> + { .compatible = "qcom,sm8250-aggre1-noc",
>> + .data = &sm8250_aggre1_noc},
>> + { .compatible = "qcom,sm8250-aggre2-noc",
>> + .data = &sm8250_aggre2_noc},
>> + { .compatible = "qcom,sm8250-compute-noc",
>> + .data = &sm8250_compute_noc},
>> + { .compatible = "qcom,sm8250-config-noc",
>> + .data = &sm8250_config_noc},
>> + { .compatible = "qcom,sm8250-dc-noc",
>> + .data = &sm8250_dc_noc},
>> + { .compatible = "qcom,sm8250-gem-noc",
>> + .data = &sm8250_gem_noc},
>> + { .compatible = "qcom,sm8250-ipa-virt",
>> + .data = &sm8250_ipa_virt},
>> + { .compatible = "qcom,sm8250-mc-virt",
>> + .data = &sm8250_mc_virt},
>> + { .compatible = "qcom,sm8250-mmss-noc",
>> + .data = &sm8250_mmss_noc},
>> + { .compatible = "qcom,sm8250-npu-noc",
>> + .data = &sm8250_npu_noc},
>> + { .compatible = "qcom,sm8250-system-noc",
>> + .data = &sm8250_system_noc},
>> + { .compatible = "qcom,sm8250-gem-noc-display",
>> + .data = &sm8250_gem_noc_display},
>> + { .compatible = "qcom,sm8250-mc-virt-display",
>> + .data = &sm8250_mc_virt_display},
>> + { .compatible = "qcom,sm8250-mmss-noc-display",
>> + .data = &sm8250_mmss_noc_display},
>> + { }
>
> My main concern here are the display RSC nodes. We should not add the nodes
> for voting on the display RSC, but use the "qcom,bcm-voters" property in DT
> to list both "hlos" and "disp" as bcm voters for gem-noc, mc-virt and
> mmss-noc.
>
Would it be OK to just drop the display RSC parts from this series then?
Not sure if anything needs it to work, but I'm not using it currently.
Though if you can provide details for a solution, I could implement it
(qcom_icc_provider needs to have a list of voters, but I'm not sure how
to deal with everything else).
> Thanks,
> Georgi
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/6] interconnect: qcom: Add SM8250 interconnect provider driver
2020-07-13 13:47 ` Jonathan Marek
@ 2020-07-13 14:19 ` Georgi Djakov
0 siblings, 0 replies; 13+ messages in thread
From: Georgi Djakov @ 2020-07-13 14:19 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, linux-kernel, linux-pm
On 7/13/20 16:47, Jonathan Marek wrote:
> On 7/13/20 9:30 AM, Georgi Djakov wrote:
>> Hi Jonathan,
>>
>> Thanks for posting these patches!
>>
>> On 7/1/20 16:42, Jonathan Marek wrote:
>>> Add driver for the Qualcomm interconnect buses found in SM8250 based
>>> platforms. The topology consists of several NoCs that are controlled by
>>> a remote processor that collects the aggregated bandwidth for each
>>> master-slave pairs.
>>>
>>> Based on SC7180 driver and generated from downstream dts.
>>>
>>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>>> ---
>> [..]
>>> +
>>> +static const struct of_device_id qnoc_of_match[] = {
>>> + { .compatible = "qcom,sm8250-aggre1-noc",
>>> + .data = &sm8250_aggre1_noc},
>>> + { .compatible = "qcom,sm8250-aggre2-noc",
>>> + .data = &sm8250_aggre2_noc},
>>> + { .compatible = "qcom,sm8250-compute-noc",
>>> + .data = &sm8250_compute_noc},
>>> + { .compatible = "qcom,sm8250-config-noc",
>>> + .data = &sm8250_config_noc},
>>> + { .compatible = "qcom,sm8250-dc-noc",
>>> + .data = &sm8250_dc_noc},
>>> + { .compatible = "qcom,sm8250-gem-noc",
>>> + .data = &sm8250_gem_noc},
>>> + { .compatible = "qcom,sm8250-ipa-virt",
>>> + .data = &sm8250_ipa_virt},
>>> + { .compatible = "qcom,sm8250-mc-virt",
>>> + .data = &sm8250_mc_virt},
>>> + { .compatible = "qcom,sm8250-mmss-noc",
>>> + .data = &sm8250_mmss_noc},
>>> + { .compatible = "qcom,sm8250-npu-noc",
>>> + .data = &sm8250_npu_noc},
>>> + { .compatible = "qcom,sm8250-system-noc",
>>> + .data = &sm8250_system_noc},
>>> + { .compatible = "qcom,sm8250-gem-noc-display",
>>> + .data = &sm8250_gem_noc_display},
>>> + { .compatible = "qcom,sm8250-mc-virt-display",
>>> + .data = &sm8250_mc_virt_display},
>>> + { .compatible = "qcom,sm8250-mmss-noc-display",
>>> + .data = &sm8250_mmss_noc_display},
>>> + { }
>>
>> My main concern here are the display RSC nodes. We should not add the nodes
>> for voting on the display RSC, but use the "qcom,bcm-voters" property in DT
>> to list both "hlos" and "disp" as bcm voters for gem-noc, mc-virt and
>> mmss-noc.
>>
>
> Would it be OK to just drop the display RSC parts from this series then? Not
> sure if anything needs it to work, but I'm not using it currently.
This would be perfect! Let's start without the display bits. Reviewing and
testing the display part would be also a bit tricky for me.
> Though if you can provide details for a solution, I could implement it
> (qcom_icc_provider needs to have a list of voters, but I'm not sure how to deal
> with everything else).
Yes, exactly. The idea is to add voters to each qcom_icc_desc and then "get"
the voters and commit for each of them. But i think there is a patch for this
already, let me check about whether its going upstream anytime soon.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-07-13 14:19 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-01 13:42 [PATCH 0/6] Add SM8150 and SM8250 interconnect drivers Jonathan Marek
2020-07-01 13:42 ` [PATCH 1/6] dt-bindings: interconnect: Add Qualcomm SM8150 DT bindings Jonathan Marek
2020-07-02 20:48 ` Rob Herring
2020-07-01 13:42 ` [PATCH 2/6] dt-bindings: interconnect: Add Qualcomm SM8250 " Jonathan Marek
2020-07-02 20:49 ` Rob Herring
2020-07-02 20:49 ` Rob Herring
2020-07-01 13:42 ` [PATCH 3/6] interconnect: qcom: Add SM8150 interconnect provider driver Jonathan Marek
2020-07-01 13:42 ` [PATCH 4/6] interconnect: qcom: Add SM8250 " Jonathan Marek
2020-07-13 13:30 ` Georgi Djakov
2020-07-13 13:47 ` Jonathan Marek
2020-07-13 14:19 ` Georgi Djakov
2020-07-01 13:42 ` [PATCH 5/6] arm64: dts: qcom: sm8150: add interconnect nodes Jonathan Marek
2020-07-01 13:42 ` [PATCH 6/6] arm64: dts: qcom: sm8250: " Jonathan Marek
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