From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> To: Rob Herring <robh@kernel.org> Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Subject: [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Thu, 29 Jul 2021 13:56:28 +0200 [thread overview] Message-ID: <261a7accef272a1f5fc774e1e3c6e179dd16a85a.1627559126.git.mchehab+huawei@kernel.org> (raw) In-Reply-To: <cover.1627559126.git.mchehab+huawei@kernel.org> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 +++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 20698cfd0637..2cf19c8960f3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -659,6 +665,99 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff + 0xffffffff>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >; + + pcie@4,0 { // Lane 4: M.2 + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 1 0>; + clkreq-gpios = <&gpio27 3 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@5,0 { // Lane 5: Mini PCIe + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 2 0>; + clkreq-gpios = <&gpio17 0 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@7,0 { // Lane 7: Ethernet + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 3 0>; + clkreq-gpios = <&gpio20 0 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> To: Rob Herring <robh@kernel.org> Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Rob Herring <robh+dt@kernel.org>, Wei Xu <xuwei5@hisilicon.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Subject: [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Thu, 29 Jul 2021 13:56:28 +0200 [thread overview] Message-ID: <261a7accef272a1f5fc774e1e3c6e179dd16a85a.1627559126.git.mchehab+huawei@kernel.org> (raw) In-Reply-To: <cover.1627559126.git.mchehab+huawei@kernel.org> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 +++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 20698cfd0637..2cf19c8960f3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -659,6 +665,99 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xffffffff 0xffffffff + 0xffffffff 0xffffffff + 0xffffffff>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >; + + pcie@4,0 { // Lane 4: M.2 + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 1 0>; + clkreq-gpios = <&gpio27 3 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@5,0 { // Lane 5: Mini PCIe + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 2 0>; + clkreq-gpios = <&gpio17 0 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pcie@7,0 { // Lane 7: Ethernet + reg = <0 0 0 0 0>; + compatible = "pciclass,0604"; + device_type = "pci"; + reset-gpios = <&gpio7 3 0>; + clkreq-gpios = <&gpio20 0 0 >; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-29 11:56 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-29 11:56 [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Mauro Carvalho Chehab 2021-07-29 11:56 ` Mauro Carvalho Chehab 2021-07-29 11:56 ` Mauro Carvalho Chehab 2021-07-29 11:56 ` [PATCH 1/5] dt-bindings: PCI: kirin: Fix compatible string Mauro Carvalho Chehab 2021-07-29 11:56 ` [PATCH 2/5] dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml Mauro Carvalho Chehab 2021-07-29 11:56 ` [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970 Mauro Carvalho Chehab 2021-07-29 14:50 ` Rob Herring 2021-07-29 15:20 ` Rob Herring 2021-07-29 19:03 ` Mauro Carvalho Chehab 2021-08-02 22:50 ` Rob Herring 2021-08-03 4:33 ` Mauro Carvalho Chehab 2021-07-29 11:56 ` [PATCH 4/5] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Mauro Carvalho Chehab 2021-07-29 11:56 ` Mauro Carvalho Chehab 2021-07-29 11:56 ` Mauro Carvalho Chehab [this message] 2021-07-29 11:56 ` [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab 2021-07-29 17:20 ` [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Rob Herring 2021-07-29 17:20 ` Rob Herring 2021-07-29 17:20 ` Rob Herring
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