From: Viresh Kumar <viresh.kumar@linaro.org> To: arm@kernel.org, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: Viresh Kumar <viresh.kumar@linaro.org>, Vincent Guittot <vincent.guittot@linaro.org>, ionela.voinescu@arm.com, Daniel Lezcano <daniel.lezcano@linaro.org>, chris.redpath@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/15] arm: dts: imx: Add missing OPP properties for CPUs Date: Fri, 25 May 2018 16:02:01 +0530 [thread overview] Message-ID: <264124e14b966a1bbc07c364fbd89fc55aa765e6.1527244201.git.viresh.kumar@linaro.org> (raw) In-Reply-To: <cover.1527244200.git.viresh.kumar@linaro.org> In-Reply-To: <cover.1527244200.git.viresh.kumar@linaro.org> The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> --- arch/arm/boot/dts/imx6dl.dtsi | 23 ++++++++++ arch/arm/boot/dts/imx6q-cm-fx6.dts | 66 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 87 ++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx7d.dtsi | 5 +++ 4 files changed, 178 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..cc8ffc42d128 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -50,6 +50,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 70483ce72ba6..78b89bb1bfed 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -50,25 +50,106 @@ soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 4c9877ec29f2..5434a8aa5602 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -21,6 +21,11 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; clock-frequency = <996000000>; }; }; -- 2.15.0.194.g9af6a3dea062
WARNING: multiple messages have this Message-ID (diff)
From: viresh.kumar@linaro.org (Viresh Kumar) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 15/15] arm: dts: imx: Add missing OPP properties for CPUs Date: Fri, 25 May 2018 16:02:01 +0530 [thread overview] Message-ID: <264124e14b966a1bbc07c364fbd89fc55aa765e6.1527244201.git.viresh.kumar@linaro.org> (raw) In-Reply-To: <cover.1527244200.git.viresh.kumar@linaro.org> The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> --- arch/arm/boot/dts/imx6dl.dtsi | 23 ++++++++++ arch/arm/boot/dts/imx6q-cm-fx6.dts | 66 +++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 87 ++++++++++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx7d.dtsi | 5 +++ 4 files changed, 178 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..cc8ffc42d128 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -50,6 +50,29 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 70483ce72ba6..78b89bb1bfed 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -50,25 +50,106 @@ soc-supply = <®_soc>; }; - cpu at 1 { + cpu1: cpu at 1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu at 2 { + cpu2: cpu at 2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu at 3 { + cpu3: cpu at 3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 4c9877ec29f2..5434a8aa5602 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -21,6 +21,11 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; clock-frequency = <996000000>; }; }; -- 2.15.0.194.g9af6a3dea062
next prev parent reply other threads:[~2018-05-25 10:33 UTC|newest] Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-25 10:31 [PATCH 00/15] arm: dts: Fix OPP and cooling device properties Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-25 10:31 ` [PATCH 01/15] arm: dts: armada: Fix "#cooling-cells" property's name Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-28 14:53 ` Gregory CLEMENT 2018-05-28 14:53 ` Gregory CLEMENT 2018-05-28 14:53 ` Gregory CLEMENT 2018-05-25 10:31 ` [PATCH 02/15] arm: dts: ls1021a: Add missing cooling device properties for CPUs Viresh Kumar 2018-07-03 1:35 ` Shawn Guo 2018-05-25 10:31 ` [PATCH 03/15] arm: dts: mediatek: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-06-25 14:58 ` Matthias Brugger 2018-06-25 14:58 ` Matthias Brugger 2018-05-25 10:31 ` [PATCH 04/15] arm: dts: rk322x: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-06-17 14:47 ` Heiko Stuebner 2018-06-17 14:47 ` Heiko Stuebner 2018-05-25 10:31 ` [PATCH 05/15] arm: dts: uniphier: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-06-01 3:25 ` Masahiro Yamada 2018-06-01 3:25 ` Masahiro Yamada 2018-05-25 10:31 ` [PATCH 06/15] arm: dts: sun: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-28 8:44 ` Maxime Ripard 2018-05-28 8:44 ` Maxime Ripard 2018-05-28 10:57 ` Viresh Kumar 2018-05-28 10:57 ` Viresh Kumar 2018-05-28 10:57 ` Viresh Kumar 2018-06-01 15:17 ` Maxime Ripard 2018-06-01 15:17 ` Maxime Ripard 2018-06-05 4:47 ` [PATCH V2 1/2] arm: dts: sun8i-h3: " Viresh Kumar 2018-06-05 4:47 ` Viresh Kumar 2018-06-05 4:47 ` [PATCH V2 2/2] arm: dts: sunxi: " Viresh Kumar 2018-06-05 4:47 ` Viresh Kumar 2018-06-05 7:11 ` Maxime Ripard 2018-06-05 7:11 ` Maxime Ripard 2018-06-05 16:02 ` Chen-Yu Tsai 2018-06-05 16:02 ` Chen-Yu Tsai 2018-06-06 6:58 ` Maxime Ripard 2018-06-06 6:58 ` Maxime Ripard 2018-05-25 10:31 ` [PATCH 07/15] arm: dts: exynos: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-29 13:18 ` Krzysztof Kozlowski 2018-05-29 13:18 ` Krzysztof Kozlowski 2018-05-30 4:38 ` Viresh Kumar 2018-05-30 4:38 ` Viresh Kumar 2018-05-30 12:32 ` Krzysztof Kozlowski 2018-05-30 12:32 ` Krzysztof Kozlowski 2018-05-31 5:22 ` Viresh Kumar 2018-05-31 5:22 ` Viresh Kumar 2018-06-20 18:44 ` Krzysztof Kozlowski 2018-06-20 18:44 ` Krzysztof Kozlowski 2018-05-25 10:31 ` [PATCH 08/15] arm: dts: dra74x: " Viresh Kumar 2018-07-03 6:43 ` Tony Lindgren 2018-05-25 10:31 ` [PATCH 09/15] arm: dts: omap: " Viresh Kumar 2018-07-03 6:44 ` Tony Lindgren 2018-05-25 10:31 ` [PATCH 10/15] arm: dts: rk3288: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-06-17 14:47 ` Heiko Stuebner 2018-06-17 14:47 ` Heiko Stuebner 2018-05-25 10:31 ` [PATCH 11/15] arm: dts: berlin: Add missing OPP " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-05-25 10:31 ` [PATCH 12/15] arm: dts: highbank: " Viresh Kumar 2018-05-25 10:31 ` Viresh Kumar 2018-07-02 20:25 ` Rob Herring 2018-07-02 20:25 ` Rob Herring 2018-07-02 20:25 ` Rob Herring 2018-07-02 23:27 ` Olof Johansson 2018-07-02 23:27 ` Olof Johansson 2018-07-02 23:27 ` Olof Johansson 2018-07-03 4:13 ` Viresh Kumar 2018-07-03 4:13 ` Viresh Kumar 2018-07-03 4:13 ` Viresh Kumar 2018-07-03 14:46 ` Olof Johansson 2018-07-03 14:46 ` Olof Johansson 2018-07-03 14:46 ` Olof Johansson 2018-05-25 10:31 ` [PATCH 13/15] arm: dts: r8a7743: " Viresh Kumar 2018-05-28 9:23 ` Simon Horman 2018-05-28 10:58 ` Viresh Kumar 2018-05-28 11:58 ` Simon Horman 2018-05-29 13:33 ` Biju Das 2018-05-30 4:47 ` Viresh Kumar 2018-05-30 4:46 ` [PATCH V2 13/15] arm: dts: r8a77xx: " Viresh Kumar 2018-05-31 14:24 ` Simon Horman 2018-06-04 9:57 ` Simon Horman 2018-06-11 9:26 ` Geert Uytterhoeven 2018-05-25 10:32 ` [PATCH 14/15] arm: dts: qcom: " Viresh Kumar 2018-07-18 6:08 ` Viresh Kumar 2018-07-18 10:22 ` Amit Kucheria 2018-07-18 10:22 ` Amit Kucheria 2018-07-21 18:56 ` Andy Gross 2018-07-21 18:56 ` Andy Gross 2018-05-25 10:32 ` Viresh Kumar [this message] 2018-05-25 10:32 ` [PATCH 15/15] arm: dts: imx: " Viresh Kumar 2018-05-25 11:46 ` Lucas Stach 2018-05-25 11:46 ` Lucas Stach 2018-05-28 11:07 ` Viresh Kumar 2018-05-28 11:07 ` Viresh Kumar 2018-07-03 7:12 ` Shawn Guo 2018-07-03 7:12 ` Shawn Guo 2018-07-03 8:56 ` Lucas Stach 2018-07-03 8:56 ` Lucas Stach 2018-07-03 12:34 ` Shawn Guo 2018-07-03 12:34 ` Shawn Guo
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