* [PATCH] [RFC] amdgpu: Enable full DCN support on POWER
@ 2019-12-05 21:39 Timothy Pearson
2019-12-05 21:45 ` Timothy Pearson
2019-12-05 21:58 ` [PATCH] [RFC v2] " Timothy Pearson
0 siblings, 2 replies; 8+ messages in thread
From: Timothy Pearson @ 2019-12-05 21:39 UTC (permalink / raw)
To: amd-gfx
DCN requires floating point support to operate. Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
---
drivers/gpu/drm/amd/display/Kconfig | 8 +-
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 +
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
drivers/gpu/drm/amd/display/dc/dml/Makefile | 5 +
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 +
drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
11 files changed, 243 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
- select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
+ select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..0d46c37d6c95 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,9 @@
# It calculates Bandwidth and Watermarks values for HW programming
#
+ifdef CONFIG_X86_64
calcs_ccflags := -mhard-float -msse
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +34,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
else
calcs_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..5c913b585ac4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
{
bool updated = false;
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
&& dc->debug.sr_exit_time_ns) {
updated = true;
@@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
dc->dcn_soc->dram_clock_change_latency =
dc->debug.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
return updated;
}
@@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
dcn_bw_sync_calcs_and_dml(dc);
memset(v, 0, sizeof(*v));
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
@@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
@@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (res)
res = verify_clock_values(&fclks);
@@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (res)
res = verify_clock_values(&dcfclks);
@@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
@@ -1496,11 +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
if (!pp || !pp->set_wm_ranges)
return;
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
socclk_khz = dc->dcn_soc->socclk * 1000;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
/* Now notify PPLib/SMU about which Watermarks sets they should select
* depending on DPM state they are in. And update BW MGR GFX Engine and
@@ -1551,7 +1682,20 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
void dcn_bw_sync_calcs_and_dml(struct dc *dc)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
"sr_enter_plus_exit_time: %f ns\n"
"urgent_latency: %f ns\n"
@@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index 63f3bddba7da..a0e4781d0424 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -10,7 +10,9 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DCN20 += dcn20_dsc.o
endif
+ifdef CONFIG_X86_64
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -18,6 +20,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -26,6 +29,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-stack-boundary=4
else
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2
endif
+endif
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index bbd1c98564be..a6f30cdfc905 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1,5 +1,6 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
&& dc->bb_overrides.sr_exit_time_ns) {
bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
@@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
bb->dram_clock_change_latency_us =
dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
index 14113ccf498d..ce589effc338 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -3,7 +3,9 @@
DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+ifdef CONFIG_X86_64
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -11,6 +13,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -19,6 +22,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-stack-boundary=4
else
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
endif
+endif
AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 459bd9a5caed..fb8323c437b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1,5 +1,6 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (dc->bb_overrides.sr_exit_time_ns) {
bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
}
@@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
bb->dram_clock_change_latency_us =
dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
void dcn21_calculate_wm(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 8df251626e22..186934e7e031 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -1,5 +1,6 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -24,7 +25,9 @@
# It provides the general basic services required by other DAL
# subcomponents.
+ifdef CONFIG_X86_64
dml_ccflags := -mhard-float -msse
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +35,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +44,7 @@ dml_ccflags += -mpreferred-stack-boundary=4
else
dml_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 970737217e53..af7b88f9ad4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the 'dsc' sub-component of DAL.
+ifdef CONFIG_X86_64
dsc_ccflags := -mhard-float -msse
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -9,6 +11,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -17,6 +20,7 @@ dsc_ccflags += -mpreferred-stack-boundary=4
else
dsc_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 30ec80ac6fc8..834e69b409d1 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -1,5 +1,6 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -49,7 +50,12 @@
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#if defined(CONFIG_X86_64)
#include <asm/fpu/api.h>
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+#include <asm/switch_to.h>
+#include <asm/cputable.h>
+#endif
#endif
/*
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER
2019-12-05 21:39 [PATCH] [RFC] amdgpu: Enable full DCN support on POWER Timothy Pearson
@ 2019-12-05 21:45 ` Timothy Pearson
2019-12-05 21:58 ` [PATCH] [RFC v2] " Timothy Pearson
1 sibling, 0 replies; 8+ messages in thread
From: Timothy Pearson @ 2019-12-05 21:45 UTC (permalink / raw)
To: amd-gfx
Sent this a bit too early, still running through checks. Watch for a V2 shortly.
----- Original Message -----
> From: "Timothy Pearson" <tpearson@raptorengineering.com>
> To: "amd-gfx" <amd-gfx@lists.freedesktop.org>
> Sent: Thursday, December 5, 2019 3:39:24 PM
> Subject: [PATCH] [RFC] amdgpu: Enable full DCN support on POWER
> DCN requires floating point support to operate. Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>
> Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
> ---
> drivers/gpu/drm/amd/display/Kconfig | 8 +-
> drivers/gpu/drm/amd/display/dc/Makefile | 1 +
> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
> drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
> drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 +
> .../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
> drivers/gpu/drm/amd/display/dc/dml/Makefile | 5 +
> drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 +
> drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
> 11 files changed, 243 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
> bool "AMD DC - Enable new display engine"
> default y
> select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL &&
> KCOV_ENABLE_COMPARISONS)
> help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and
> @@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
> config DRM_AMD_DC_DCN2_0
> bool "DCN 2.0 family"
> default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN1_0
> help
> Choose this option if you want to have
> @@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
>
> config DRM_AMD_DC_DCN2_1
> bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN2_0
> help
> Choose this option if you want to have
> @@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
> config DRM_AMD_DC_DSC_SUPPORT
> bool "DSC support"
> default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN1_0
> depends on DRM_AMD_DC_DCN2_0
> help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
> #
> # Permission is hereby granted, free of charge, to any person obtaining a
> # copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..0d46c37d6c95 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,9 @@
> # It calculates Bandwidth and Watermarks values for HW programming
> #
>
> +ifdef CONFIG_X86_64
> calcs_ccflags := -mhard-float -msse
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -32,6 +34,7 @@ IS_OLD_GCC = 1
> endif
> endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
> @@ -40,6 +43,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
> else
> calcs_ccflags += -msse2
> endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..5c913b585ac4 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
> {
> bool updated = false;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
> && dc->debug.sr_exit_time_ns) {
> updated = true;
> @@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
> dc->dcn_soc->dram_clock_change_latency =
> dc->debug.dram_clock_change_latency_ns / 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> return updated;
> }
> @@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
> dcn_bw_sync_calcs_and_dml(dc);
>
> memset(v, 0, sizeof(*v));
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> v->sr_exit_time = dc->dcn_soc->sr_exit_time;
> v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
> @@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
> bw_limit = dc->dcn_soc->percent_disp_bw_limit *
> v->fabric_and_dram_bandwidth_vmax0p9;
> bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> PERFORMANCE_TRACE_END();
> BW_VAL_TRACE_FINISH();
> @@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> if (res)
> res = verify_clock_values(&fclks);
> @@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> if (res)
> res = verify_clock_values(&dcfclks);
> @@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
> @@ -1496,11 +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
> if (!pp || !pp->set_wm_ranges)
> return;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
> min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
> socclk_khz = dc->dcn_soc->socclk * 1000;
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> /* Now notify PPLib/SMU about which Watermarks sets they should select
> * depending on DPM state they are in. And update BW MGR GFX Engine and
> @@ -1551,7 +1682,20 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>
> void dcn_bw_sync_calcs_and_dml(struct dc *dc)
> {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
> "sr_enter_plus_exit_time: %f ns\n"
> "urgent_latency: %f ns\n"
> @@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
> dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
> dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed ==
> dcn_bw_yes;
> dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> index 63f3bddba7da..a0e4781d0424 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> @@ -10,7 +10,9 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> DCN20 += dcn20_dsc.o
> endif
>
> +ifdef CONFIG_X86_64
> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -18,6 +20,7 @@ IS_OLD_GCC = 1
> endif
> endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
> @@ -26,6 +29,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o +=
> -mpreferred-stack-boundary=4
> else
> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2
> endif
> +endif
>
> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index bbd1c98564be..a6f30cdfc905 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2016 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_s
>
> void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
> *bb)
> {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
> && dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
> @@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_st
> bb->dram_clock_change_latency_us =
> dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> index 14113ccf498d..ce589effc338 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> @@ -3,7 +3,9 @@
>
> DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
> dcn21_link_encoder.o
>
> +ifdef CONFIG_X86_64
> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -11,6 +13,7 @@ IS_OLD_GCC = 1
> endif
> endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
> @@ -19,6 +22,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o +=
> -mpreferred-stack-boundary=4
> else
> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
> endif
> +endif
>
> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index 459bd9a5caed..fb8323c437b7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2018 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
>
> static void patch_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_st *bb)
> {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if (dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
> }
> @@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_s
> bb->dram_clock_change_latency_us =
> dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> void dcn21_calculate_wm(
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index 8df251626e22..186934e7e031 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
> #
> # Permission is hereby granted, free of charge, to any person obtaining a
> # copy of this software and associated documentation files (the "Software"),
> @@ -24,7 +25,9 @@
> # It provides the general basic services required by other DAL
> # subcomponents.
>
> +ifdef CONFIG_X86_64
> dml_ccflags := -mhard-float -msse
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -32,6 +35,7 @@ IS_OLD_GCC = 1
> endif
> endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
> @@ -40,6 +44,7 @@ dml_ccflags += -mpreferred-stack-boundary=4
> else
> dml_ccflags += -msse2
> endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> index 970737217e53..af7b88f9ad4d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> @@ -1,7 +1,9 @@
> #
> # Makefile for the 'dsc' sub-component of DAL.
>
> +ifdef CONFIG_X86_64
> dsc_ccflags := -mhard-float -msse
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y)
> @@ -9,6 +11,7 @@ IS_OLD_GCC = 1
> endif
> endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
> @@ -17,6 +20,7 @@ dsc_ccflags += -mpreferred-stack-boundary=4
> else
> dsc_ccflags += -msse2
> endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
> diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h
> b/drivers/gpu/drm/amd/display/dc/os_types.h
> index 30ec80ac6fc8..834e69b409d1 100644
> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2012-16 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -49,7 +50,12 @@
> #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
>
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> +#if defined(CONFIG_X86_64)
> #include <asm/fpu/api.h>
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
> +#include <asm/switch_to.h>
> +#include <asm/cputable.h>
> +#endif
> #endif
>
> /*
> --
> 2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
2019-12-05 21:39 [PATCH] [RFC] amdgpu: Enable full DCN support on POWER Timothy Pearson
2019-12-05 21:45 ` Timothy Pearson
@ 2019-12-05 21:58 ` Timothy Pearson
2019-12-05 23:02 ` Liu, Zhan
1 sibling, 1 reply; 8+ messages in thread
From: Timothy Pearson @ 2019-12-05 21:58 UTC (permalink / raw)
To: amd-gfx
DCN requires floating point support to operate. Add the appropriate
x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
---
drivers/gpu/drm/amd/display/Kconfig | 8 +-
drivers/gpu/drm/amd/display/dc/Makefile | 1 +
drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
.../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 8 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 8 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
drivers/gpu/drm/amd/display/dc/dml/Makefile | 9 +
drivers/gpu/drm/amd/display/dc/dsc/Makefile | 8 +
drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
11 files changed, 263 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 313183b80032..c73a63f3e245 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -6,7 +6,7 @@ config DRM_AMD_DC
bool "AMD DC - Enable new display engine"
default y
select SND_HDA_COMPONENT if SND_HDA_CORE
- select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
+ select DRM_AMD_DC_DCN1_0 if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
@@ -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0
config DRM_AMD_DC_DCN2_0
bool "DCN 2.0 family"
default y
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
help
Choose this option if you want to have
@@ -28,7 +28,7 @@ config DRM_AMD_DC_DCN2_0
config DRM_AMD_DC_DCN2_1
bool "DCN 2.1 family"
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN2_0
help
Choose this option if you want to have
@@ -37,7 +37,7 @@ config DRM_AMD_DC_DCN2_1
config DRM_AMD_DC_DSC_SUPPORT
bool "DSC support"
default y
- depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC && (X86 || PPC64)
depends on DRM_AMD_DC_DCN1_0
depends on DRM_AMD_DC_DCN2_0
help
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index a160512a2f04..3e026a969386 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -1,5 +1,6 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 26c6d735cdc7..20c88aff930a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -24,7 +24,13 @@
# It calculates Bandwidth and Watermarks values for HW programming
#
+ifdef CONFIG_X86_64
calcs_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+calcs_ccflags := -mhard-float -maltivec
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +38,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-boundary=4
else
calcs_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 9b2cb57bf2ba..236e852ea60b 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1,5 +1,6 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
{
bool updated = false;
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
&& dc->debug.sr_exit_time_ns) {
updated = true;
@@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
dc->dcn_soc->dram_clock_change_latency =
dc->debug.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
return updated;
}
@@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
dcn_bw_sync_calcs_and_dml(dc);
memset(v, 0, sizeof(*v));
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
@@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH();
@@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (res)
res = verify_clock_values(&fclks);
@@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
res = dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (res)
res = verify_clock_values(&dcfclks);
@@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
} else
BREAK_TO_DEBUGGER();
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
@@ -1496,11 +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
if (!pp || !pp->set_wm_ranges)
return;
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
socclk_khz = dc->dcn_soc->socclk * 1000;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
/* Now notify PPLib/SMU about which Watermarks sets they should select
* depending on DPM state they are in. And update BW MGR GFX Engine and
@@ -1551,7 +1682,20 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
void dcn_bw_sync_calcs_and_dml(struct dc *dc)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
"sr_enter_plus_exit_time: %f ns\n"
"urgent_latency: %f ns\n"
@@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index 63f3bddba7da..6a872b7a58bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DCN20 += dcn20_dsc.o
endif
+ifdef CONFIG_X86_64
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -18,6 +24,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -26,6 +33,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-stack-boundary=4
else
CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2
endif
+endif
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index bbd1c98564be..7e1da6b3ca36 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1,5 +1,6 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
&& dc->bb_overrides.sr_exit_time_ns) {
bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
@@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
bb->dram_clock_change_latency_us =
dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
index 14113ccf498d..79bb926a6890 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -3,7 +3,13 @@
DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
+ifdef CONFIG_X86_64
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -11,6 +17,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -19,6 +26,7 @@ CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-stack-boundary=4
else
CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
endif
+endif
AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 459bd9a5caed..8dcd871deceb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1,5 +1,6 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
{
+#if defined(CONFIG_X86_64)
kernel_fpu_begin();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ preempt_disable();
+ enable_kernel_vsx();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ preempt_disable();
+ enable_kernel_altivec();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ preempt_disable();
+ enable_kernel_fp();
+ }
+#endif
if (dc->bb_overrides.sr_exit_time_ns) {
bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
}
@@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
bb->dram_clock_change_latency_us =
dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
}
+#if defined(CONFIG_X86_64)
kernel_fpu_end();
+#elif defined(CONFIG_PPC64)
+ if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
+ disable_kernel_vsx();
+ preempt_enable();
+ } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
+ disable_kernel_altivec();
+ preempt_enable();
+ } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
+ disable_kernel_fp();
+ preempt_enable();
+ }
+#endif
}
void dcn21_calculate_wm(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 8df251626e22..ae49d23386e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -1,5 +1,6 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
+# Copyright 2019 Raptor Engineering, LLC
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -24,7 +25,13 @@
# It provides the general basic services required by other DAL
# subcomponents.
+ifdef CONFIG_X86_64
dml_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+dml_ccflags := -mhard-float -maltivec
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -32,6 +39,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -40,6 +48,7 @@ dml_ccflags += -mpreferred-stack-boundary=4
else
dml_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 970737217e53..f73304af4b85 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -1,7 +1,13 @@
#
# Makefile for the 'dsc' sub-component of DAL.
+ifdef CONFIG_X86_64
dsc_ccflags := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+dsc_ccflags := -mhard-float -maltivec
+endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
@@ -9,6 +15,7 @@ IS_OLD_GCC = 1
endif
endif
+ifdef CONFIG_X86_64
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -17,6 +24,7 @@ dsc_ccflags += -mpreferred-stack-boundary=4
else
dsc_ccflags += -msse2
endif
+endif
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 30ec80ac6fc8..834e69b409d1 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -1,5 +1,6 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -49,7 +50,12 @@
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#if defined(CONFIG_X86_64)
#include <asm/fpu/api.h>
+#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+#include <asm/switch_to.h>
+#include <asm/cputable.h>
+#endif
#endif
/*
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: amdgpu: Enable full DCN support on POWER
2019-12-05 21:58 ` [PATCH] [RFC v2] " Timothy Pearson
@ 2019-12-05 23:02 ` Liu, Zhan
2019-12-05 23:19 ` Harry Wentland
0 siblings, 1 reply; 8+ messages in thread
From: Liu, Zhan @ 2019-12-05 23:02 UTC (permalink / raw)
To: Timothy Pearson, amd-gfx
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Timothy Pearson
> Sent: 2019/December/05, Thursday 4:58 PM
> To: amd-gfx <amd-gfx@lists.freedesktop.org>
> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>
> DCN requires floating point support to operate. Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>
> Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
> ---
> drivers/gpu/drm/amd/display/Kconfig | 8 +-
> drivers/gpu/drm/amd/display/dc/Makefile | 1 +
> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
> drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 8 +
> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
> drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 8 +
> .../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
> drivers/gpu/drm/amd/display/dc/dml/Makefile | 9 +
> drivers/gpu/drm/amd/display/dc/dsc/Makefile | 8 +
> drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
> 11 files changed, 263 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
> bool "AMD DC - Enable new display engine"
> default y
> select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
> && KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
> && !(KCOV_INSTRUMENT_ALL &&
> +KCOV_ENABLE_COMPARISONS)
> help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and @@
> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0 config
> DRM_AMD_DC_DCN2_0
> bool "DCN 2.0 family"
> default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN1_0
> help
> Choose this option if you want to have @@ -28,7 +28,7 @@ config
> DRM_AMD_DC_DCN2_0
>
> config DRM_AMD_DC_DCN2_1
> bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN2_0
> help
> Choose this option if you want to have @@ -37,7 +37,7 @@ config
> DRM_AMD_DC_DCN2_1 config DRM_AMD_DC_DSC_SUPPORT
> bool "DSC support"
> default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
> depends on DRM_AMD_DC_DCN1_0
> depends on DRM_AMD_DC_DCN2_0
> help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
NAK.
IANAL, but I don't think you can add your company's name by modifying part of the code. The copyright notice shows the authors of the original work.
When modifying the code, you are required to agree with that copyright notice. That's the purpose of that copyright notice piece.
> #
> # Permission is hereby granted, free of charge, to any person obtaining a #
> copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..20c88aff930a 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,13 @@
> # It calculates Bandwidth and Watermarks values for HW programming #
>
> +ifdef CONFIG_X86_64
> calcs_ccflags := -mhard-float -msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +calcs_ccflags := -mhard-float -maltivec endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
> 1 endif endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
> boundary=4 else calcs_ccflags += -msse2 endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..236e852ea60b 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct
> dc *dc) {
> bool updated = false;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc-
> >debug.sr_exit_time_ns
> && dc->debug.sr_exit_time_ns) {
> updated = true;
> @@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct
> dc *dc)
> dc->dcn_soc->dram_clock_change_latency =
> dc->debug.dram_clock_change_latency_ns /
> 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> return updated;
> }
> @@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
> dcn_bw_sync_calcs_and_dml(dc);
>
> memset(v, 0, sizeof(*v));
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> v->sr_exit_time = dc->dcn_soc->sr_exit_time;
> v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
> @@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
> bw_limit = dc->dcn_soc->percent_disp_bw_limit * v-
> >fabric_and_dram_bandwidth_vmax0p9;
> bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> PERFORMANCE_TRACE_END();
> BW_VAL_TRACE_FINISH();
> @@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> if (res)
> res = verify_clock_values(&fclks);
> @@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> res = dm_pp_get_clock_levels_by_type_with_voltage(
> ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
>
> if (res)
> res = verify_clock_values(&dcfclks);
> @@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> } else
> BREAK_TO_DEBUGGER();
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) @@ -1496,11
> +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
> if (!pp || !pp->set_wm_ranges)
> return;
>
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> min_fclk_khz = dc->dcn_soc-
> >fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
> min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
> socclk_khz = dc->dcn_soc->socclk * 1000;
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
>
> /* Now notify PPLib/SMU about which Watermarks sets they should
> select
> * depending on DPM state they are in. And update BW MGR GFX
> Engine and @@ -1551,7 +1682,20 @@ void
> dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>
> void dcn_bw_sync_calcs_and_dml(struct dc *dc) {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
> "sr_enter_plus_exit_time: %f ns\n"
> "urgent_latency: %f ns\n"
> @@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
> dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
> dc->dcn_ip-
> >bug_forcing_luma_and_chroma_request_to_same_size_fixed ==
> dcn_bw_yes;
> dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip-
> >dcfclk_cstate_latency;
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> index 63f3bddba7da..6a872b7a58bd 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> @@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> DCN20 += dcn20_dsc.o
> endif
>
> +ifdef CONFIG_X86_64
> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -
> msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float
> +-maltivec endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -18,6 +24,7 @@ IS_OLD_GCC =
> 1 endif endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -26,6 +33,7 @@
> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-
> stack-boundary=4 else
> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2 endif
> +endif
>
> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index bbd1c98564be..7e1da6b3ca36 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2016 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc,
> struct _vcs_dpi_soc_bounding_box_s
>
> void dcn20_patch_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_st *bb) {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if ((int)(bb->sr_exit_time_us * 1000) != dc-
> >bb_overrides.sr_exit_time_ns
> && dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
> 1000.0; @@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct
> dc *dc, struct _vcs_dpi_soc_bounding_box_st
> bb->dram_clock_change_latency_us =
> dc-
> >bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( diff --git
> a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> index 14113ccf498d..79bb926a6890 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
> @@ -3,7 +3,13 @@
>
> DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
> dcn21_link_encoder.o
>
> +ifdef CONFIG_X86_64
> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -
> msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float
> +-maltivec endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -11,6 +17,7 @@ IS_OLD_GCC =
> 1 endif endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -19,6 +26,7 @@
> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-
> stack-boundary=4 else
> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2 endif
> +endif
>
> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index 459bd9a5caed..8dcd871deceb 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2018 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
>
> static void patch_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_st *bb) {
> +#if defined(CONFIG_X86_64)
> kernel_fpu_begin();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + preempt_disable();
> + enable_kernel_vsx();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + preempt_disable();
> + enable_kernel_altivec();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + preempt_disable();
> + enable_kernel_fp();
> + }
> +#endif
> if (dc->bb_overrides.sr_exit_time_ns) {
> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
> 1000.0;
> }
> @@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc,
> struct _vcs_dpi_soc_bounding_box_s
> bb->dram_clock_change_latency_us =
> dc-
> >bb_overrides.dram_clock_change_latency_ns / 1000.0;
> }
> +#if defined(CONFIG_X86_64)
> kernel_fpu_end();
> +#elif defined(CONFIG_PPC64)
> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
> + disable_kernel_vsx();
> + preempt_enable();
> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
> + disable_kernel_altivec();
> + preempt_enable();
> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
> + disable_kernel_fp();
> + preempt_enable();
> + }
> +#endif
> }
>
> void dcn21_calculate_wm(
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index 8df251626e22..ae49d23386e1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -1,5 +1,6 @@
> #
> # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC
> #
> # Permission is hereby granted, free of charge, to any person obtaining a #
> copy of this software and associated documentation files (the "Software"),
> @@ -24,7 +25,13 @@ # It provides the general basic services required by
> other DAL # subcomponents.
>
> +ifdef CONFIG_X86_64
> dml_ccflags := -mhard-float -msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +dml_ccflags := -mhard-float -maltivec
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +39,7 @@ IS_OLD_GCC =
> 1 endif endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -40,6 +48,7 @@ dml_ccflags += -mpreferred-stack-
> boundary=4 else dml_ccflags += -msse2 endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> index 970737217e53..f73304af4b85 100644
> --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> @@ -1,7 +1,13 @@
> #
> # Makefile for the 'dsc' sub-component of DAL.
>
> +ifdef CONFIG_X86_64
> dsc_ccflags := -mhard-float -msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +dsc_ccflags := -mhard-float -maltivec
> +endif
>
> ifdef CONFIG_CC_IS_GCC
> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -9,6 +15,7 @@ IS_OLD_GCC = 1
> endif endif
>
> +ifdef CONFIG_X86_64
> ifdef IS_OLD_GCC
> # Stack alignment mismatch, proceed with caution.
> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -17,6 +24,7 @@ dsc_ccflags += -mpreferred-stack-
> boundary=4 else dsc_ccflags += -msse2 endif
> +endif
>
> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags) diff --git
> a/drivers/gpu/drm/amd/display/dc/os_types.h
> b/drivers/gpu/drm/amd/display/dc/os_types.h
> index 30ec80ac6fc8..834e69b409d1 100644
> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
> @@ -1,5 +1,6 @@
> /*
> * Copyright 2012-16 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
> *
> * Permission is hereby granted, free of charge, to any person obtaining a
> * copy of this software and associated documentation files (the "Software"),
> @@ -49,7 +50,12 @@ #define dm_error(fmt, ...) DRM_ERROR(fmt,
> ##__VA_ARGS__)
>
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> +#if defined(CONFIG_X86_64)
> #include <asm/fpu/api.h>
> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64) #include
> +<asm/switch_to.h> #include <asm/cputable.h> #endif
> #endif
>
> /*
> --
> 2.20.1
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&data=02%7C01%7Czhan.liu%40amd.com%7Ced80e6447d544a463
> 8d808d779ce451e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7
> C637111799221875534&sdata=S4qa%2BDK53ziQ4EWaWCUSC0udcj84q
> jz6qIzeiVg7el0%3D&reserved=0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: amdgpu: Enable full DCN support on POWER
2019-12-05 23:02 ` Liu, Zhan
@ 2019-12-05 23:19 ` Harry Wentland
2019-12-05 23:34 ` Timothy Pearson
0 siblings, 1 reply; 8+ messages in thread
From: Harry Wentland @ 2019-12-05 23:19 UTC (permalink / raw)
To: Liu, Zhan, Timothy Pearson, amd-gfx
On 2019-12-05 6:02 p.m., Liu, Zhan wrote:
>
>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Timothy Pearson
>> Sent: 2019/December/05, Thursday 4:58 PM
>> To: amd-gfx <amd-gfx@lists.freedesktop.org>
>> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>>
>> DCN requires floating point support to operate. Add the appropriate
>> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>>
>> Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
>> ---
>> drivers/gpu/drm/amd/display/Kconfig | 8 +-
>> drivers/gpu/drm/amd/display/dc/Makefile | 1 +
>> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
>> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
>> drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 8 +
>> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
>> drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 8 +
>> .../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
>> drivers/gpu/drm/amd/display/dc/dml/Makefile | 9 +
>> drivers/gpu/drm/amd/display/dc/dsc/Makefile | 8 +
>> drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
>> 11 files changed, 263 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>> b/drivers/gpu/drm/amd/display/Kconfig
>> index 313183b80032..c73a63f3e245 100644
>> --- a/drivers/gpu/drm/amd/display/Kconfig
>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>> bool "AMD DC - Enable new display engine"
>> default y
>> select SND_HDA_COMPONENT if SND_HDA_CORE
>> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
>> && KCOV_ENABLE_COMPARISONS)
>> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
>> && !(KCOV_INSTRUMENT_ALL &&
>> +KCOV_ENABLE_COMPARISONS)
>> help
>> Choose this option if you want to use the new display engine
>> support for AMDGPU. This adds required support for Vega and @@
>> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0 config
>> DRM_AMD_DC_DCN2_0
>> bool "DCN 2.0 family"
>> default y
>> - depends on DRM_AMD_DC && X86
>> + depends on DRM_AMD_DC && (X86 || PPC64)
>> depends on DRM_AMD_DC_DCN1_0
>> help
>> Choose this option if you want to have @@ -28,7 +28,7 @@ config
>> DRM_AMD_DC_DCN2_0
>>
>> config DRM_AMD_DC_DCN2_1
>> bool "DCN 2.1 family"
>> - depends on DRM_AMD_DC && X86
>> + depends on DRM_AMD_DC && (X86 || PPC64)
>> depends on DRM_AMD_DC_DCN2_0
>> help
>> Choose this option if you want to have @@ -37,7 +37,7 @@ config
>> DRM_AMD_DC_DCN2_1 config DRM_AMD_DC_DSC_SUPPORT
>> bool "DSC support"
>> default y
>> - depends on DRM_AMD_DC && X86
>> + depends on DRM_AMD_DC && (X86 || PPC64)
>> depends on DRM_AMD_DC_DCN1_0
>> depends on DRM_AMD_DC_DCN2_0
>> help
>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>> b/drivers/gpu/drm/amd/display/dc/Makefile
>> index a160512a2f04..3e026a969386 100644
>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>> @@ -1,5 +1,6 @@
>> #
>> # Copyright 2017 Advanced Micro Devices, Inc.
>> +# Copyright 2019 Raptor Engineering, LLC
>
> NAK.
>
> IANAL, but I don't think you can add your company's name by modifying part of the code. The copyright notice shows the authors of the original work.
>
> When modifying the code, you are required to agree with that copyright notice. That's the purpose of that copyright notice piece.
>
I always thought these copyright notices are nearly meaningless.
That said, this patch doesn't have any change in this file. I don't
think it warrants an additional copyright notice.
Harry
>> #
>> # Permission is hereby granted, free of charge, to any person obtaining a #
>> copy of this software and associated documentation files (the "Software"),
>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> index 26c6d735cdc7..20c88aff930a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>> @@ -24,7 +24,13 @@
>> # It calculates Bandwidth and Watermarks values for HW programming #
>>
>> +ifdef CONFIG_X86_64
>> calcs_ccflags := -mhard-float -msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +calcs_ccflags := -mhard-float -maltivec endif
>>
>> ifdef CONFIG_CC_IS_GCC
>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
>> 1 endif endif
>>
>> +ifdef CONFIG_X86_64
>> ifdef IS_OLD_GCC
>> # Stack alignment mismatch, proceed with caution.
>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
>> boundary=4 else calcs_ccflags += -msse2 endif
>> +endif
>>
>> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
>> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
>> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>> index 9b2cb57bf2ba..236e852ea60b 100644
>> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>> @@ -1,5 +1,6 @@
>> /*
>> * Copyright 2017 Advanced Micro Devices, Inc.
>> + * Copyright 2019 Raptor Engineering, LLC
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a
>> * copy of this software and associated documentation files (the "Software"),
>> @@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct
>> dc *dc) {
>> bool updated = false;
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>> if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc-
>>> debug.sr_exit_time_ns
>> && dc->debug.sr_exit_time_ns) {
>> updated = true;
>> @@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct
>> dc *dc)
>> dc->dcn_soc->dram_clock_change_latency =
>> dc->debug.dram_clock_change_latency_ns /
>> 1000.0;
>> }
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>>
>> return updated;
>> }
>> @@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
>> dcn_bw_sync_calcs_and_dml(dc);
>>
>> memset(v, 0, sizeof(*v));
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>>
>> v->sr_exit_time = dc->dcn_soc->sr_exit_time;
>> v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
>> @@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
>> bw_limit = dc->dcn_soc->percent_disp_bw_limit * v-
>>> fabric_and_dram_bandwidth_vmax0p9;
>> bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>>
>> PERFORMANCE_TRACE_END();
>> BW_VAL_TRACE_FINISH();
>> @@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>> res = dm_pp_get_clock_levels_by_type_with_voltage(
>> ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>>
>> if (res)
>> res = verify_clock_values(&fclks);
>> @@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>> } else
>> BREAK_TO_DEBUGGER();
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>>
>> res = dm_pp_get_clock_levels_by_type_with_voltage(
>> ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>>
>> if (res)
>> res = verify_clock_values(&dcfclks);
>> @@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>> } else
>> BREAK_TO_DEBUGGER();
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>> }
>>
>> void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) @@ -1496,11
>> +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>> if (!pp || !pp->set_wm_ranges)
>> return;
>>
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>> min_fclk_khz = dc->dcn_soc-
>>> fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
>> min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
>> socclk_khz = dc->dcn_soc->socclk * 1000;
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>>
>> /* Now notify PPLib/SMU about which Watermarks sets they should
>> select
>> * depending on DPM state they are in. And update BW MGR GFX
>> Engine and @@ -1551,7 +1682,20 @@ void
>> dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>>
>> void dcn_bw_sync_calcs_and_dml(struct dc *dc) {
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>> DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
>> "sr_enter_plus_exit_time: %f ns\n"
>> "urgent_latency: %f ns\n"
>> @@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
>> dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
>> dc->dcn_ip-
>>> bug_forcing_luma_and_chroma_request_to_same_size_fixed ==
>> dcn_bw_yes;
>> dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip-
>>> dcfclk_cstate_latency;
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>> }
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>> b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>> index 63f3bddba7da..6a872b7a58bd 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>> @@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>> DCN20 += dcn20_dsc.o
>> endif
>>
>> +ifdef CONFIG_X86_64
>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -
>> msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float
>> +-maltivec endif
>>
>> ifdef CONFIG_CC_IS_GCC
>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -18,6 +24,7 @@ IS_OLD_GCC =
>> 1 endif endif
>>
>> +ifdef CONFIG_X86_64
>> ifdef IS_OLD_GCC
>> # Stack alignment mismatch, proceed with caution.
>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -26,6 +33,7 @@
>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-
>> stack-boundary=4 else
>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2 endif
>> +endif
>>
>> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>> index bbd1c98564be..7e1da6b3ca36 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>> @@ -1,5 +1,6 @@
>> /*
>> * Copyright 2016 Advanced Micro Devices, Inc.
>> + * Copyright 2019 Raptor Engineering, LLC
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a
>> * copy of this software and associated documentation files (the "Software"),
>> @@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc,
>> struct _vcs_dpi_soc_bounding_box_s
>>
>> void dcn20_patch_bounding_box(struct dc *dc, struct
>> _vcs_dpi_soc_bounding_box_st *bb) {
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>> if ((int)(bb->sr_exit_time_us * 1000) != dc-
>>> bb_overrides.sr_exit_time_ns
>> && dc->bb_overrides.sr_exit_time_ns) {
>> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
>> 1000.0; @@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct
>> dc *dc, struct _vcs_dpi_soc_bounding_box_st
>> bb->dram_clock_change_latency_us =
>> dc-
>>> bb_overrides.dram_clock_change_latency_ns / 1000.0;
>> }
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>> }
>>
>> static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( diff --git
>> a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>> b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>> index 14113ccf498d..79bb926a6890 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>> @@ -3,7 +3,13 @@
>>
>> DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
>> dcn21_link_encoder.o
>>
>> +ifdef CONFIG_X86_64
>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -
>> msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float
>> +-maltivec endif
>>
>> ifdef CONFIG_CC_IS_GCC
>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -11,6 +17,7 @@ IS_OLD_GCC =
>> 1 endif endif
>>
>> +ifdef CONFIG_X86_64
>> ifdef IS_OLD_GCC
>> # Stack alignment mismatch, proceed with caution.
>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -19,6 +26,7 @@
>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-
>> stack-boundary=4 else
>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2 endif
>> +endif
>>
>> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>> index 459bd9a5caed..8dcd871deceb 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>> @@ -1,5 +1,6 @@
>> /*
>> * Copyright 2018 Advanced Micro Devices, Inc.
>> + * Copyright 2019 Raptor Engineering, LLC
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a
>> * copy of this software and associated documentation files (the "Software"),
>> @@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
>>
>> static void patch_bounding_box(struct dc *dc, struct
>> _vcs_dpi_soc_bounding_box_st *bb) {
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_begin();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + preempt_disable();
>> + enable_kernel_vsx();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + preempt_disable();
>> + enable_kernel_altivec();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + preempt_disable();
>> + enable_kernel_fp();
>> + }
>> +#endif
>> if (dc->bb_overrides.sr_exit_time_ns) {
>> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
>> 1000.0;
>> }
>> @@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc,
>> struct _vcs_dpi_soc_bounding_box_s
>> bb->dram_clock_change_latency_us =
>> dc-
>>> bb_overrides.dram_clock_change_latency_ns / 1000.0;
>> }
>> +#if defined(CONFIG_X86_64)
>> kernel_fpu_end();
>> +#elif defined(CONFIG_PPC64)
>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>> + disable_kernel_vsx();
>> + preempt_enable();
>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>> + disable_kernel_altivec();
>> + preempt_enable();
>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>> + disable_kernel_fp();
>> + preempt_enable();
>> + }
>> +#endif
>> }
>>
>> void dcn21_calculate_wm(
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>> index 8df251626e22..ae49d23386e1 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>> @@ -1,5 +1,6 @@
>> #
>> # Copyright 2017 Advanced Micro Devices, Inc.
>> +# Copyright 2019 Raptor Engineering, LLC
>> #
>> # Permission is hereby granted, free of charge, to any person obtaining a #
>> copy of this software and associated documentation files (the "Software"),
>> @@ -24,7 +25,13 @@ # It provides the general basic services required by
>> other DAL # subcomponents.
>>
>> +ifdef CONFIG_X86_64
>> dml_ccflags := -mhard-float -msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +dml_ccflags := -mhard-float -maltivec
>> +endif
>>
>> ifdef CONFIG_CC_IS_GCC
>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +39,7 @@ IS_OLD_GCC =
>> 1 endif endif
>>
>> +ifdef CONFIG_X86_64
>> ifdef IS_OLD_GCC
>> # Stack alignment mismatch, proceed with caution.
>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -40,6 +48,7 @@ dml_ccflags += -mpreferred-stack-
>> boundary=4 else dml_ccflags += -msse2 endif
>> +endif
>>
>> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>> b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>> index 970737217e53..f73304af4b85 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>> +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>> @@ -1,7 +1,13 @@
>> #
>> # Makefile for the 'dsc' sub-component of DAL.
>>
>> +ifdef CONFIG_X86_64
>> dsc_ccflags := -mhard-float -msse
>> +endif
>> +
>> +ifdef CONFIG_PPC64
>> +dsc_ccflags := -mhard-float -maltivec
>> +endif
>>
>> ifdef CONFIG_CC_IS_GCC
>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -9,6 +15,7 @@ IS_OLD_GCC = 1
>> endif endif
>>
>> +ifdef CONFIG_X86_64
>> ifdef IS_OLD_GCC
>> # Stack alignment mismatch, proceed with caution.
>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>> boundary=3 @@ -17,6 +24,7 @@ dsc_ccflags += -mpreferred-stack-
>> boundary=4 else dsc_ccflags += -msse2 endif
>> +endif
>>
>> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
>> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags) diff --git
>> a/drivers/gpu/drm/amd/display/dc/os_types.h
>> b/drivers/gpu/drm/amd/display/dc/os_types.h
>> index 30ec80ac6fc8..834e69b409d1 100644
>> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
>> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
>> @@ -1,5 +1,6 @@
>> /*
>> * Copyright 2012-16 Advanced Micro Devices, Inc.
>> + * Copyright 2019 Raptor Engineering, LLC
>> *
>> * Permission is hereby granted, free of charge, to any person obtaining a
>> * copy of this software and associated documentation files (the "Software"),
>> @@ -49,7 +50,12 @@ #define dm_error(fmt, ...) DRM_ERROR(fmt,
>> ##__VA_ARGS__)
>>
>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>> +#if defined(CONFIG_X86_64)
>> #include <asm/fpu/api.h>
>> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64) #include
>> +<asm/switch_to.h> #include <asm/cputable.h> #endif
>> #endif
>>
>> /*
>> --
>> 2.20.1
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
>> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
>> gfx&data=02%7C01%7Czhan.liu%40amd.com%7Ced80e6447d544a463
>> 8d808d779ce451e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7
>> C637111799221875534&sdata=S4qa%2BDK53ziQ4EWaWCUSC0udcj84q
>> jz6qIzeiVg7el0%3D&reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: amdgpu: Enable full DCN support on POWER
2019-12-05 23:19 ` Harry Wentland
@ 2019-12-05 23:34 ` Timothy Pearson
2019-12-06 16:12 ` Michel Dänzer
0 siblings, 1 reply; 8+ messages in thread
From: Timothy Pearson @ 2019-12-05 23:34 UTC (permalink / raw)
To: Harry Wentland; +Cc: Liu, Zhan, amd-gfx
----- Original Message -----
> From: "Harry Wentland" <hwentlan@amd.com>
> To: "Liu, Zhan" <Zhan.Liu@amd.com>, "Timothy Pearson" <tpearson@raptorengineering.com>, "amd-gfx"
> <amd-gfx@lists.freedesktop.org>
> Sent: Thursday, December 5, 2019 5:19:22 PM
> Subject: Re: amdgpu: Enable full DCN support on POWER
> On 2019-12-05 6:02 p.m., Liu, Zhan wrote:
>>
>>
>>> -----Original Message-----
>>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>>> Timothy Pearson
>>> Sent: 2019/December/05, Thursday 4:58 PM
>>> To: amd-gfx <amd-gfx@lists.freedesktop.org>
>>> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
>>>
>>> DCN requires floating point support to operate. Add the appropriate
>>> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
>>>
>>> Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
>>> ---
>>> drivers/gpu/drm/amd/display/Kconfig | 8 +-
>>> drivers/gpu/drm/amd/display/dc/Makefile | 1 +
>>> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
>>> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 157 ++++++++++++++++++
>>> drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 8 +
>>> .../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +++
>>> drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 8 +
>>> .../drm/amd/display/dc/dcn21/dcn21_resource.c | 27 +++
>>> drivers/gpu/drm/amd/display/dc/dml/Makefile | 9 +
>>> drivers/gpu/drm/amd/display/dc/dsc/Makefile | 8 +
>>> drivers/gpu/drm/amd/display/dc/os_types.h | 6 +
>>> 11 files changed, 263 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/Kconfig
>>> b/drivers/gpu/drm/amd/display/Kconfig
>>> index 313183b80032..c73a63f3e245 100644
>>> --- a/drivers/gpu/drm/amd/display/Kconfig
>>> +++ b/drivers/gpu/drm/amd/display/Kconfig
>>> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>>> bool "AMD DC - Enable new display engine"
>>> default y
>>> select SND_HDA_COMPONENT if SND_HDA_CORE
>>> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
>>> && KCOV_ENABLE_COMPARISONS)
>>> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
>>> && !(KCOV_INSTRUMENT_ALL &&
>>> +KCOV_ENABLE_COMPARISONS)
>>> help
>>> Choose this option if you want to use the new display engine
>>> support for AMDGPU. This adds required support for Vega and @@
>>> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0 config
>>> DRM_AMD_DC_DCN2_0
>>> bool "DCN 2.0 family"
>>> default y
>>> - depends on DRM_AMD_DC && X86
>>> + depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> help
>>> Choose this option if you want to have @@ -28,7 +28,7 @@ config
>>> DRM_AMD_DC_DCN2_0
>>>
>>> config DRM_AMD_DC_DCN2_1
>>> bool "DCN 2.1 family"
>>> - depends on DRM_AMD_DC && X86
>>> + depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>> Choose this option if you want to have @@ -37,7 +37,7 @@ config
>>> DRM_AMD_DC_DCN2_1 config DRM_AMD_DC_DSC_SUPPORT
>>> bool "DSC support"
>>> default y
>>> - depends on DRM_AMD_DC && X86
>>> + depends on DRM_AMD_DC && (X86 || PPC64)
>>> depends on DRM_AMD_DC_DCN1_0
>>> depends on DRM_AMD_DC_DCN2_0
>>> help
>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/Makefile
>>> index a160512a2f04..3e026a969386 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
>>> @@ -1,5 +1,6 @@
>>> #
>>> # Copyright 2017 Advanced Micro Devices, Inc.
>>> +# Copyright 2019 Raptor Engineering, LLC
>>
>> NAK.
>>
>> IANAL, but I don't think you can add your company's name by modifying part of
>> the code. The copyright notice shows the authors of the original work.
>>
>> When modifying the code, you are required to agree with that copyright notice.
>> That's the purpose of that copyright notice piece.
>>
>
> I always thought these copyright notices are nearly meaningless.
>
> That said, this patch doesn't have any change in this file. I don't
> think it warrants an additional copyright notice.
>
> Harry
Agreed -- looks like that snuck in with the other changes. I can back this one out, however in general regardless of the notice having any actual legal meaning (the GIT commit history has the actual legal teeth from what I understand as it establishes shared ownership), our general policy per recommendations is to add the copyright line. It helps anyone looking at the file know at a glance that there is more than one corporate author, and therefore e.g. the only terms it can be used on without a complex multi-party license renegotiation is (in this case) the GPL v2.
I'll wait for comments on the actual technical parts of the patch, and will make sure to remove this one spurious line in the final patch series.
Thanks!
>
>>> #
>>> # Permission is hereby granted, free of charge, to any person obtaining a #
>>> copy of this software and associated documentation files (the "Software"),
>>> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> index 26c6d735cdc7..20c88aff930a 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>>> @@ -24,7 +24,13 @@
>>> # It calculates Bandwidth and Watermarks values for HW programming #
>>>
>>> +ifdef CONFIG_X86_64
>>> calcs_ccflags := -mhard-float -msse
>>> +endif
>>> +
>>> +ifdef CONFIG_PPC64
>>> +calcs_ccflags := -mhard-float -maltivec endif
>>>
>>> ifdef CONFIG_CC_IS_GCC
>>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
>>> 1 endif endif
>>>
>>> +ifdef CONFIG_X86_64
>>> ifdef IS_OLD_GCC
>>> # Stack alignment mismatch, proceed with caution.
>>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>>> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
>>> boundary=4 else calcs_ccflags += -msse2 endif
>>> +endif
>>>
>>> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
>>> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
>>> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>> index 9b2cb57bf2ba..236e852ea60b 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>> @@ -1,5 +1,6 @@
>>> /*
>>> * Copyright 2017 Advanced Micro Devices, Inc.
>>> + * Copyright 2019 Raptor Engineering, LLC
>>> *
>>> * Permission is hereby granted, free of charge, to any person obtaining a
>>> * copy of this software and associated documentation files (the "Software"),
>>> @@ -626,7 +627,20 @@ static bool dcn_bw_apply_registry_override(struct
>>> dc *dc) {
>>> bool updated = false;
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>> if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc-
>>>> debug.sr_exit_time_ns
>>> && dc->debug.sr_exit_time_ns) {
>>> updated = true;
>>> @@ -662,7 +676,20 @@ static bool dcn_bw_apply_registry_override(struct
>>> dc *dc)
>>> dc->dcn_soc->dram_clock_change_latency =
>>> dc->debug.dram_clock_change_latency_ns /
>>> 1000.0;
>>> }
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>>
>>> return updated;
>>> }
>>> @@ -742,7 +769,20 @@ bool dcn_validate_bandwidth(
>>> dcn_bw_sync_calcs_and_dml(dc);
>>>
>>> memset(v, 0, sizeof(*v));
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>>
>>> v->sr_exit_time = dc->dcn_soc->sr_exit_time;
>>> v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
>>> @@ -1275,7 +1315,20 @@ bool dcn_validate_bandwidth(
>>> bw_limit = dc->dcn_soc->percent_disp_bw_limit * v-
>>>> fabric_and_dram_bandwidth_vmax0p9;
>>> bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>>
>>> PERFORMANCE_TRACE_END();
>>> BW_VAL_TRACE_FINISH();
>>> @@ -1443,7 +1496,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>>> res = dm_pp_get_clock_levels_by_type_with_voltage(
>>> ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>>
>>> if (res)
>>> res = verify_clock_values(&fclks);
>>> @@ -1463,12 +1529,38 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>>> } else
>>> BREAK_TO_DEBUGGER();
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>>
>>> res = dm_pp_get_clock_levels_by_type_with_voltage(
>>> ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>>
>>> if (res)
>>> res = verify_clock_values(&dcfclks);
>>> @@ -1481,7 +1573,20 @@ void dcn_bw_update_from_pplib(struct dc *dc)
>>> } else
>>> BREAK_TO_DEBUGGER();
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>> }
>>>
>>> void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) @@ -1496,11
>>> +1601,37 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>>> if (!pp || !pp->set_wm_ranges)
>>> return;
>>>
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>> min_fclk_khz = dc->dcn_soc-
>>>> fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
>>> min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
>>> socclk_khz = dc->dcn_soc->socclk * 1000;
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>>
>>> /* Now notify PPLib/SMU about which Watermarks sets they should
>>> select
>>> * depending on DPM state they are in. And update BW MGR GFX
>>> Engine and @@ -1551,7 +1682,20 @@ void
>>> dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
>>>
>>> void dcn_bw_sync_calcs_and_dml(struct dc *dc) {
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>> DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
>>> "sr_enter_plus_exit_time: %f ns\n"
>>> "urgent_latency: %f ns\n"
>>> @@ -1740,5 +1884,18 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
>>> dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
>>> dc->dcn_ip-
>>>> bug_forcing_luma_and_chroma_request_to_same_size_fixed ==
>>> dcn_bw_yes;
>>> dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip-
>>>> dcfclk_cstate_latency;
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>> }
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>>> index 63f3bddba7da..6a872b7a58bd 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>>> @@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>>> DCN20 += dcn20_dsc.o
>>> endif
>>>
>>> +ifdef CONFIG_X86_64
>>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -
>>> msse
>>> +endif
>>> +
>>> +ifdef CONFIG_PPC64
>>> +CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float
>>> +-maltivec endif
>>>
>>> ifdef CONFIG_CC_IS_GCC
>>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -18,6 +24,7 @@ IS_OLD_GCC =
>>> 1 endif endif
>>>
>>> +ifdef CONFIG_X86_64
>>> ifdef IS_OLD_GCC
>>> # Stack alignment mismatch, proceed with caution.
>>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>>> boundary=3 @@ -26,6 +33,7 @@
>>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-
>>> stack-boundary=4 else
>>> CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2 endif
>>> +endif
>>>
>>> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>>> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>>> index bbd1c98564be..7e1da6b3ca36 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>>> @@ -1,5 +1,6 @@
>>> /*
>>> * Copyright 2016 Advanced Micro Devices, Inc.
>>> + * Copyright 2019 Raptor Engineering, LLC
>>> *
>>> * Permission is hereby granted, free of charge, to any person obtaining a
>>> * copy of this software and associated documentation files (the "Software"),
>>> @@ -3173,7 +3174,20 @@ void dcn20_update_bounding_box(struct dc *dc,
>>> struct _vcs_dpi_soc_bounding_box_s
>>>
>>> void dcn20_patch_bounding_box(struct dc *dc, struct
>>> _vcs_dpi_soc_bounding_box_st *bb) {
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>> if ((int)(bb->sr_exit_time_us * 1000) != dc-
>>>> bb_overrides.sr_exit_time_ns
>>> && dc->bb_overrides.sr_exit_time_ns) {
>>> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
>>> 1000.0; @@ -3197,7 +3211,20 @@ void dcn20_patch_bounding_box(struct
>>> dc *dc, struct _vcs_dpi_soc_bounding_box_st
>>> bb->dram_clock_change_latency_us =
>>> dc-
>>>> bb_overrides.dram_clock_change_latency_ns / 1000.0;
>>> }
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>> }
>>>
>>> static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( diff --git
>>> a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>>> index 14113ccf498d..79bb926a6890 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>>> @@ -3,7 +3,13 @@
>>>
>>> DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
>>> dcn21_link_encoder.o
>>>
>>> +ifdef CONFIG_X86_64
>>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -
>>> msse
>>> +endif
>>> +
>>> +ifdef CONFIG_PPC64
>>> +CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float
>>> +-maltivec endif
>>>
>>> ifdef CONFIG_CC_IS_GCC
>>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -11,6 +17,7 @@ IS_OLD_GCC =
>>> 1 endif endif
>>>
>>> +ifdef CONFIG_X86_64
>>> ifdef IS_OLD_GCC
>>> # Stack alignment mismatch, proceed with caution.
>>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>>> boundary=3 @@ -19,6 +26,7 @@
>>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-
>>> stack-boundary=4 else
>>> CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2 endif
>>> +endif
>>>
>>> AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> index 459bd9a5caed..8dcd871deceb 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>>> @@ -1,5 +1,6 @@
>>> /*
>>> * Copyright 2018 Advanced Micro Devices, Inc.
>>> + * Copyright 2019 Raptor Engineering, LLC
>>> *
>>> * Permission is hereby granted, free of charge, to any person obtaining a
>>> * copy of this software and associated documentation files (the "Software"),
>>> @@ -1017,7 +1018,20 @@ static void calculate_wm_set_for_vlevel(
>>>
>>> static void patch_bounding_box(struct dc *dc, struct
>>> _vcs_dpi_soc_bounding_box_st *bb) {
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_begin();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_vsx();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + preempt_disable();
>>> + enable_kernel_altivec();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + preempt_disable();
>>> + enable_kernel_fp();
>>> + }
>>> +#endif
>>> if (dc->bb_overrides.sr_exit_time_ns) {
>>> bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns /
>>> 1000.0;
>>> }
>>> @@ -1035,7 +1049,20 @@ static void patch_bounding_box(struct dc *dc,
>>> struct _vcs_dpi_soc_bounding_box_s
>>> bb->dram_clock_change_latency_us =
>>> dc-
>>>> bb_overrides.dram_clock_change_latency_ns / 1000.0;
>>> }
>>> +#if defined(CONFIG_X86_64)
>>> kernel_fpu_end();
>>> +#elif defined(CONFIG_PPC64)
>>> + if (cpu_has_feature(CPU_FTR_VSX_COMP)) {
>>> + disable_kernel_vsx();
>>> + preempt_enable();
>>> + } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) {
>>> + disable_kernel_altivec();
>>> + preempt_enable();
>>> + } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) {
>>> + disable_kernel_fp();
>>> + preempt_enable();
>>> + }
>>> +#endif
>>> }
>>>
>>> void dcn21_calculate_wm(
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> index 8df251626e22..ae49d23386e1 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> @@ -1,5 +1,6 @@
>>> #
>>> # Copyright 2017 Advanced Micro Devices, Inc.
>>> +# Copyright 2019 Raptor Engineering, LLC
>>> #
>>> # Permission is hereby granted, free of charge, to any person obtaining a #
>>> copy of this software and associated documentation files (the "Software"),
>>> @@ -24,7 +25,13 @@ # It provides the general basic services required by
>>> other DAL # subcomponents.
>>>
>>> +ifdef CONFIG_X86_64
>>> dml_ccflags := -mhard-float -msse
>>> +endif
>>> +
>>> +ifdef CONFIG_PPC64
>>> +dml_ccflags := -mhard-float -maltivec
>>> +endif
>>>
>>> ifdef CONFIG_CC_IS_GCC
>>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +39,7 @@ IS_OLD_GCC =
>>> 1 endif endif
>>>
>>> +ifdef CONFIG_X86_64
>>> ifdef IS_OLD_GCC
>>> # Stack alignment mismatch, proceed with caution.
>>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>>> boundary=3 @@ -40,6 +48,7 @@ dml_ccflags += -mpreferred-stack-
>>> boundary=4 else dml_ccflags += -msse2 endif
>>> +endif
>>>
>>> CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>>> b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>>> index 970737217e53..f73304af4b85 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>>> +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>>> @@ -1,7 +1,13 @@
>>> #
>>> # Makefile for the 'dsc' sub-component of DAL.
>>>
>>> +ifdef CONFIG_X86_64
>>> dsc_ccflags := -mhard-float -msse
>>> +endif
>>> +
>>> +ifdef CONFIG_PPC64
>>> +dsc_ccflags := -mhard-float -maltivec
>>> +endif
>>>
>>> ifdef CONFIG_CC_IS_GCC
>>> ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -9,6 +15,7 @@ IS_OLD_GCC = 1
>>> endif endif
>>>
>>> +ifdef CONFIG_X86_64
>>> ifdef IS_OLD_GCC
>>> # Stack alignment mismatch, proceed with caution.
>>> # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
>>> boundary=3 @@ -17,6 +24,7 @@ dsc_ccflags += -mpreferred-stack-
>>> boundary=4 else dsc_ccflags += -msse2 endif
>>> +endif
>>>
>>> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
>>> CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags) diff --git
>>> a/drivers/gpu/drm/amd/display/dc/os_types.h
>>> b/drivers/gpu/drm/amd/display/dc/os_types.h
>>> index 30ec80ac6fc8..834e69b409d1 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/os_types.h
>>> +++ b/drivers/gpu/drm/amd/display/dc/os_types.h
>>> @@ -1,5 +1,6 @@
>>> /*
>>> * Copyright 2012-16 Advanced Micro Devices, Inc.
>>> + * Copyright 2019 Raptor Engineering, LLC
>>> *
>>> * Permission is hereby granted, free of charge, to any person obtaining a
>>> * copy of this software and associated documentation files (the "Software"),
>>> @@ -49,7 +50,12 @@ #define dm_error(fmt, ...) DRM_ERROR(fmt,
>>> ##__VA_ARGS__)
>>>
>>> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>>> +#if defined(CONFIG_X86_64)
>>> #include <asm/fpu/api.h>
>>> +#elif defined(CONFIG_PPC32) || defined(CONFIG_PPC64) #include
>>> +<asm/switch_to.h> #include <asm/cputable.h> #endif
>>> #endif
>>>
>>> /*
>>> --
>>> 2.20.1
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
>>> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
>>> gfx&data=02%7C01%7Czhan.liu%40amd.com%7Ced80e6447d544a463
>>> 8d808d779ce451e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7
>>> C637111799221875534&sdata=S4qa%2BDK53ziQ4EWaWCUSC0udcj84q
>>> jz6qIzeiVg7el0%3D&reserved=0
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: amdgpu: Enable full DCN support on POWER
2019-12-05 23:34 ` Timothy Pearson
@ 2019-12-06 16:12 ` Michel Dänzer
2019-12-06 20:29 ` Timothy Pearson
0 siblings, 1 reply; 8+ messages in thread
From: Michel Dänzer @ 2019-12-06 16:12 UTC (permalink / raw)
To: Timothy Pearson, Harry Wentland; +Cc: Liu, Zhan, amd-gfx
On 2019-12-06 12:34 a.m., Timothy Pearson wrote:
>> From: "Harry Wentland" <hwentlan@amd.com> On 2019-12-05 6:02 p.m.,
>> Liu, Zhan wrote:
>>>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf
>>>> Of Timothy Pearson
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>>> b/drivers/gpu/drm/amd/display/dc/Makefile index
>>>> a160512a2f04..3e026a969386 100644 ---
>>>> a/drivers/gpu/drm/amd/display/dc/Makefile +++
>>>> b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,5 +1,6 @@ # #
>>>> Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2019
>>>> Raptor Engineering, LLC
>>>
>>> NAK.
>>>
>>> IANAL, but I don't think you can add your company's name by
>>> modifying part of the code. The copyright notice shows the
>>> authors of the original work.
>>>
>>> When modifying the code, you are required to agree with that
>>> copyright notice. That's the purpose of that copyright notice
>>> piece.
Where did you get that from? Adding a copyright line like this to files
containing code to which one holds the copyright is standard practice.
>> I always thought these copyright notices are nearly meaningless.
>>
>> That said, this patch doesn't have any change in this file. I
>> don't think it warrants an additional copyright notice.
>>
>> Harry
>
> Agreed -- looks like that snuck in with the other changes. I can
> back this one out, however in general regardless of the notice having
> any actual legal meaning (the GIT commit history has the actual legal
> teeth from what I understand as it establishes shared ownership), our
> general policy per recommendations is to add the copyright line. It
> helps anyone looking at the file know at a glance that there is more
> than one corporate author, and therefore e.g. the only terms it can
> be used on without a complex multi-party license renegotiation is (in
> this case) the GPL v2.
Did you read the licence under the copyright line you added? :)
Or are you saying that your patch is intended to be available under the
GPL only? I'm afraid that would be a problem.
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast | Mesa and X developer
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: amdgpu: Enable full DCN support on POWER
2019-12-06 16:12 ` Michel Dänzer
@ 2019-12-06 20:29 ` Timothy Pearson
0 siblings, 0 replies; 8+ messages in thread
From: Timothy Pearson @ 2019-12-06 20:29 UTC (permalink / raw)
To: Michel Dänzer; +Cc: Zhan Liu, Harry Wentland, amd-gfx
----- Original Message -----
> From: "Michel Dänzer" <michel@daenzer.net>
> To: "Timothy Pearson" <tpearson@raptorengineering.com>, "Harry Wentland" <hwentlan@amd.com>
> Cc: "Zhan Liu" <Zhan.Liu@amd.com>, "amd-gfx" <amd-gfx@lists.freedesktop.org>
> Sent: Friday, December 6, 2019 10:12:42 AM
> Subject: Re: amdgpu: Enable full DCN support on POWER
> On 2019-12-06 12:34 a.m., Timothy Pearson wrote:
>>> From: "Harry Wentland" <hwentlan@amd.com> On 2019-12-05 6:02 p.m.,
>>> Liu, Zhan wrote:
>>>>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf
>>>>> Of Timothy Pearson
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
>>>>> b/drivers/gpu/drm/amd/display/dc/Makefile index
>>>>> a160512a2f04..3e026a969386 100644 ---
>>>>> a/drivers/gpu/drm/amd/display/dc/Makefile +++
>>>>> b/drivers/gpu/drm/amd/display/dc/Makefile @@ -1,5 +1,6 @@ # #
>>>>> Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2019
>>>>> Raptor Engineering, LLC
>>>>
>>>> NAK.
>>>>
>>>> IANAL, but I don't think you can add your company's name by
>>>> modifying part of the code. The copyright notice shows the
>>>> authors of the original work.
>>>>
>>>> When modifying the code, you are required to agree with that
>>>> copyright notice. That's the purpose of that copyright notice
>>>> piece.
>
> Where did you get that from? Adding a copyright line like this to files
> containing code to which one holds the copyright is standard practice.
>
>
>>> I always thought these copyright notices are nearly meaningless.
>>>
>>> That said, this patch doesn't have any change in this file. I
>>> don't think it warrants an additional copyright notice.
>>>
>>> Harry
>>
>> Agreed -- looks like that snuck in with the other changes. I can
>> back this one out, however in general regardless of the notice having
>> any actual legal meaning (the GIT commit history has the actual legal
>> teeth from what I understand as it establishes shared ownership), our
>> general policy per recommendations is to add the copyright line. It
>> helps anyone looking at the file know at a glance that there is more
>> than one corporate author, and therefore e.g. the only terms it can
>> be used on without a complex multi-party license renegotiation is (in
>> this case) the GPL v2.
>
> Did you read the licence under the copyright line you added? :)
Nope, I didn't, at least not right before sending that reply -- I didn't have a copy of the file up on that device , and was wildly guessing based on the overall kernel distribution license.
> Or are you saying that your patch is intended to be available under the
> GPL only? I'm afraid that would be a problem.
No, there's no problem here with the existing license. Updated version of the patch with a few technical issues fixed should be coming later today / tomorrow (depending on how quickly I can get an ACK/NACK on functionality from the person that has access to the Navi card).
>
> --
> Earthling Michel Dänzer | https://redhat.com
> Libre software enthusiast | Mesa and X developer
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-12-06 20:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-05 21:39 [PATCH] [RFC] amdgpu: Enable full DCN support on POWER Timothy Pearson
2019-12-05 21:45 ` Timothy Pearson
2019-12-05 21:58 ` [PATCH] [RFC v2] " Timothy Pearson
2019-12-05 23:02 ` Liu, Zhan
2019-12-05 23:19 ` Harry Wentland
2019-12-05 23:34 ` Timothy Pearson
2019-12-06 16:12 ` Michel Dänzer
2019-12-06 20:29 ` Timothy Pearson
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