* [Qemu-devel] [PATCH v2 01/21] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:34 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 02/21] blockdev: Introduce IF_AHCI Jason Baron
` (19 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
This field should be initialized by the machine type to the default interface
type which it wants to use (IF_SCSI, IF_AHCI, etc.). If no mach_if is defined,
or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assume IF_IDE.
Please use 'static inline int get_mach_if(int mach_if)', when accesssing the
new mach_if field.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
blockdev.c | 4 ++--
blockdev.h | 19 +++++++++++++++++++
hw/boards.h | 2 +-
hw/device-hotplug.c | 2 +-
hw/highbank.c | 2 +-
hw/leon3.c | 2 +-
hw/mips_jazz.c | 4 ++--
hw/pc_sysfw.c | 2 +-
hw/puv3.c | 2 +-
hw/realview.c | 6 +++---
hw/spapr.c | 2 +-
hw/sun4m.c | 24 ++++++++++++------------
hw/versatilepb.c | 4 ++--
hw/vexpress.c | 4 ++--
hw/xilinx_zynq.c | 2 +-
vl.c | 20 +++++++++++---------
16 files changed, 61 insertions(+), 40 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index e5d450f..93a7bf7 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -274,7 +274,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)
return true;
}
-DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
+DriveInfo *drive_init(QemuOpts *opts, int mach_if)
{
const char *buf;
const char *file = NULL;
@@ -324,7 +324,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
return NULL;
}
} else {
- type = default_to_scsi ? IF_SCSI : IF_IDE;
+ type = get_mach_if(mach_if);
}
max_devs = if_max_devs[type];
diff --git a/blockdev.h b/blockdev.h
index 5f27b64..8b126ad 100644
--- a/blockdev.h
+++ b/blockdev.h
@@ -40,6 +40,22 @@ struct DriveInfo {
int refcount;
};
+/*
+ * Each qemu machine type defines a mach_if field for its default
+ * interface type. If its unspecified, we set it to IF_IDE.
+ */
+static inline int get_mach_if(int mach_if)
+{
+ assert(mach_if < IF_COUNT);
+ assert(mach_if >= IF_DEFAULT);
+
+ if ((mach_if == IF_NONE) || (mach_if == IF_DEFAULT)) {
+ return IF_IDE;
+ }
+
+ return mach_if;
+}
+
DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
int drive_get_max_bus(BlockInterfaceType type);
@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename,
bool has_format, const char *format, Error **errp);
void do_commit(Monitor *mon, const QDict *qdict);
int do_drive_del(Monitor *mon, const QDict *qdict, QObject **ret_data);
+
+
+
#endif
diff --git a/hw/boards.h b/hw/boards.h
index a2e0a54..969fd67 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -20,7 +20,7 @@ typedef struct QEMUMachine {
const char *desc;
QEMUMachineInitFunc *init;
QEMUMachineResetFunc *reset;
- int use_scsi;
+ int mach_if;
int max_cpus;
unsigned int no_serial:1,
no_parallel:1,
diff --git a/hw/device-hotplug.c b/hw/device-hotplug.c
index 2bdc615..1ad233c 100644
--- a/hw/device-hotplug.c
+++ b/hw/device-hotplug.c
@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)
if (!opts)
return NULL;
- dinfo = drive_init(opts, current_machine->use_scsi);
+ dinfo = drive_init(opts, current_machine->mach_if);
if (!dinfo) {
qemu_opts_del(opts);
return NULL;
diff --git a/hw/highbank.c b/hw/highbank.c
index 11aa131..35cef06 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -324,7 +324,7 @@ static QEMUMachine highbank_machine = {
.name = "highbank",
.desc = "Calxeda Highbank (ECX-1000)",
.init = highbank_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/leon3.c b/hw/leon3.c
index 878d3aa..21b7a7b 100644
--- a/hw/leon3.c
+++ b/hw/leon3.c
@@ -214,7 +214,7 @@ QEMUMachine leon3_generic_machine = {
.name = "leon3_generic",
.desc = "Leon-3 generic",
.init = leon3_generic_hw_init,
- .use_scsi = 0,
+ .mach_if = IF_DEFAULT,
};
static void leon3_machine_init(void)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index db927f1..1c7a725 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -325,14 +325,14 @@ static QEMUMachine mips_magnum_machine = {
.name = "magnum",
.desc = "MIPS Magnum",
.init = mips_magnum_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine mips_pica61_machine = {
.name = "pica61",
.desc = "Acer Pica 61",
.init = mips_pica61_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static void mips_jazz_machine_init(void)
diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
index b45f0ac..b8a03a6 100644
--- a/hw/pc_sysfw.c
+++ b/hw/pc_sysfw.c
@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)
return;
}
- drive_init(opts, machine->use_scsi);
+ drive_init(opts, machine->mach_if);
}
static void pc_system_flash_init(MemoryRegion *rom_memory,
diff --git a/hw/puv3.c b/hw/puv3.c
index 43f7216..f68bb61 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -120,7 +120,7 @@ static QEMUMachine puv3_machine = {
.desc = "PKUnity Version-3 based on UniCore32",
.init = puv3_init,
.is_default = 1,
- .use_scsi = 0,
+ .mach_if = IF_DEFAULT,
};
static void puv3_machine_init(void)
diff --git a/hw/realview.c b/hw/realview.c
index 19db4d0..7613f68 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -382,14 +382,14 @@ static QEMUMachine realview_eb_machine = {
.name = "realview-eb",
.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
.init = realview_eb_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine realview_eb_mpcore_machine = {
.name = "realview-eb-mpcore",
.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
.init = realview_eb_mpcore_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
@@ -403,7 +403,7 @@ static QEMUMachine realview_pbx_a9_machine = {
.name = "realview-pbx-a9",
.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
.init = realview_pbx_a9_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/spapr.c b/hw/spapr.c
index c34b767..42977ca 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -849,7 +849,7 @@ static QEMUMachine spapr_machine = {
.init = ppc_spapr_init,
.max_cpus = MAX_CPUS,
.no_parallel = 1,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static void spapr_machine_init(void)
diff --git a/hw/sun4m.c b/hw/sun4m.c
index c98cd5e..de25fea 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -1397,7 +1397,7 @@ static QEMUMachine ss5_machine = {
.name = "SS-5",
.desc = "Sun4m platform, SPARCstation 5",
.init = ss5_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.is_default = 1,
};
@@ -1405,7 +1405,7 @@ static QEMUMachine ss10_machine = {
.name = "SS-10",
.desc = "Sun4m platform, SPARCstation 10",
.init = ss10_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1413,7 +1413,7 @@ static QEMUMachine ss600mp_machine = {
.name = "SS-600MP",
.desc = "Sun4m platform, SPARCserver 600MP",
.init = ss600mp_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1421,7 +1421,7 @@ static QEMUMachine ss20_machine = {
.name = "SS-20",
.desc = "Sun4m platform, SPARCstation 20",
.init = ss20_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
@@ -1429,35 +1429,35 @@ static QEMUMachine voyager_machine = {
.name = "Voyager",
.desc = "Sun4m platform, SPARCstation Voyager",
.init = vger_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine ss_lx_machine = {
.name = "LX",
.desc = "Sun4m platform, SPARCstation LX",
.init = ss_lx_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine ss4_machine = {
.name = "SS-4",
.desc = "Sun4m platform, SPARCstation 4",
.init = ss4_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine scls_machine = {
.name = "SPARCClassic",
.desc = "Sun4m platform, SPARCClassic",
.init = scls_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine sbook_machine = {
.name = "SPARCbook",
.desc = "Sun4m platform, SPARCbook",
.init = sbook_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static const struct sun4d_hwdef sun4d_hwdefs[] = {
@@ -1674,7 +1674,7 @@ static QEMUMachine ss1000_machine = {
.name = "SS-1000",
.desc = "Sun4d platform, SPARCserver 1000",
.init = ss1000_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 8,
};
@@ -1682,7 +1682,7 @@ static QEMUMachine ss2000_machine = {
.name = "SS-2000",
.desc = "Sun4d platform, SPARCcenter 2000",
.init = ss2000_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 20,
};
@@ -1858,7 +1858,7 @@ static QEMUMachine ss2_machine = {
.name = "SS-2",
.desc = "Sun4c platform, SPARCstation 2",
.init = ss2_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static void sun4m_register_types(void)
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 7a92034..17e15c6 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -368,14 +368,14 @@ static QEMUMachine versatilepb_machine = {
.name = "versatilepb",
.desc = "ARM Versatile/PB (ARM926EJ-S)",
.init = vpb_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static QEMUMachine versatileab_machine = {
.name = "versatileab",
.desc = "ARM Versatile/AB (ARM926EJ-S)",
.init = vab_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
};
static void versatile_machine_init(void)
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 3596d1e..3c7c012 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -495,7 +495,7 @@ static QEMUMachine vexpress_a9_machine = {
.name = "vexpress-a9",
.desc = "ARM Versatile Express for Cortex-A9",
.init = vexpress_a9_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
@@ -503,7 +503,7 @@ static QEMUMachine vexpress_a15_machine = {
.name = "vexpress-a15",
.desc = "ARM Versatile Express for Cortex-A15",
.init = vexpress_a15_init,
- .use_scsi = 1,
+ .mach_if = IF_SCSI,
.max_cpus = 4,
};
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 7e6c273..510d93d 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -144,7 +144,7 @@ static QEMUMachine zynq_machine = {
.name = "xilinx-zynq-a9",
.desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
.init = zynq_init,
- .use_scsi = 1,
+ .if_default = IF_SCSI,
.max_cpus = 1,
.no_sdcard = 1
};
diff --git a/vl.c b/vl.c
index 8d305ca..77af809 100644
--- a/vl.c
+++ b/vl.c
@@ -802,9 +802,9 @@ static int parse_sandbox(QemuOpts *opts, void *opaque)
static int drive_init_func(QemuOpts *opts, void *opaque)
{
- int *use_scsi = opaque;
+ int *mach_if = opaque;
- return drive_init(opts, *use_scsi) == NULL;
+ return drive_init(opts, *mach_if) == NULL;
}
static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
@@ -815,14 +815,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
return 0;
}
-static void default_drive(int enable, int snapshot, int use_scsi,
+static void default_drive(int enable, int snapshot, int mach_if,
BlockInterfaceType type, int index,
const char *optstr)
{
QemuOpts *opts;
if (type == IF_DEFAULT) {
- type = use_scsi ? IF_SCSI : IF_IDE;
+ type = get_mach_if(mach_if);
}
if (!enable || drive_get_by_index(type, index)) {
@@ -833,7 +833,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,
if (snapshot) {
drive_enable_snapshot(opts, NULL);
}
- if (!drive_init(opts, use_scsi)) {
+ if (!drive_init(opts, mach_if)) {
exit(1);
}
}
@@ -3537,14 +3537,16 @@ int main(int argc, char **argv, char **envp)
/* open the virtual block devices */
if (snapshot)
qemu_opts_foreach(qemu_find_opts("drive"), drive_enable_snapshot, NULL, 0);
- if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func, &machine->use_scsi, 1) != 0)
+ if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func,
+ &machine->mach_if, 1) != 0) {
exit(1);
+ }
- default_drive(default_cdrom, snapshot, machine->use_scsi,
+ default_drive(default_cdrom, snapshot, machine->mach_if,
IF_DEFAULT, 2, CDROM_OPTS);
- default_drive(default_floppy, snapshot, machine->use_scsi,
+ default_drive(default_floppy, snapshot, machine->mach_if,
IF_FLOPPY, 0, FD_OPTS);
- default_drive(default_sdcard, snapshot, machine->use_scsi,
+ default_drive(default_sdcard, snapshot, machine->mach_if,
IF_SD, 0, SD_OPTS);
register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, NULL);
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 01/21] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 01/21] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if Jason Baron
@ 2012-10-09 7:34 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:34 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> The current QEMUMachine definition has a 'use_scsi' field to indicate if a
> machine type should use scsi by default. However, Q35 wants to use ahci by
> default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
>
> This field should be initialized by the machine type to the default interface
> type which it wants to use (IF_SCSI, IF_AHCI, etc.). If no mach_if is defined,
> or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assume IF_IDE.
>
> Please use 'static inline int get_mach_if(int mach_if)', when accesssing the
> new mach_if field.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> blockdev.c | 4 ++--
> blockdev.h | 19 +++++++++++++++++++
> hw/boards.h | 2 +-
> hw/device-hotplug.c | 2 +-
> hw/highbank.c | 2 +-
> hw/leon3.c | 2 +-
> hw/mips_jazz.c | 4 ++--
> hw/pc_sysfw.c | 2 +-
> hw/puv3.c | 2 +-
> hw/realview.c | 6 +++---
> hw/spapr.c | 2 +-
> hw/sun4m.c | 24 ++++++++++++------------
> hw/versatilepb.c | 4 ++--
> hw/vexpress.c | 4 ++--
> hw/xilinx_zynq.c | 2 +-
> vl.c | 20 +++++++++++---------
> 16 files changed, 61 insertions(+), 40 deletions(-)
>
> diff --git a/blockdev.c b/blockdev.c
> index e5d450f..93a7bf7 100644
> --- a/blockdev.c
> +++ b/blockdev.c
> @@ -274,7 +274,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)
> return true;
> }
>
> -DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
> +DriveInfo *drive_init(QemuOpts *opts, int mach_if)
> {
> const char *buf;
> const char *file = NULL;
> @@ -324,7 +324,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)
> return NULL;
> }
> } else {
> - type = default_to_scsi ? IF_SCSI : IF_IDE;
> + type = get_mach_if(mach_if);
> }
>
> max_devs = if_max_devs[type];
> diff --git a/blockdev.h b/blockdev.h
> index 5f27b64..8b126ad 100644
> --- a/blockdev.h
> +++ b/blockdev.h
> @@ -40,6 +40,22 @@ struct DriveInfo {
> int refcount;
> };
>
> +/*
> + * Each qemu machine type defines a mach_if field for its default
> + * interface type. If its unspecified, we set it to IF_IDE.
> + */
> +static inline int get_mach_if(int mach_if)
> +{
> + assert(mach_if < IF_COUNT);
> + assert(mach_if >= IF_DEFAULT);
> +
> + if ((mach_if == IF_NONE) || (mach_if == IF_DEFAULT)) {
> + return IF_IDE;
> + }
> +
> + return mach_if;
> +}
> +
> DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
> DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
> int drive_get_max_bus(BlockInterfaceType type);
> @@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename,
> bool has_format, const char *format, Error **errp);
> void do_commit(Monitor *mon, const QDict *qdict);
> int do_drive_del(Monitor *mon, const QDict *qdict, QObject **ret_data);
> +
> +
> +
> #endif
> diff --git a/hw/boards.h b/hw/boards.h
> index a2e0a54..969fd67 100644
> --- a/hw/boards.h
> +++ b/hw/boards.h
> @@ -20,7 +20,7 @@ typedef struct QEMUMachine {
> const char *desc;
> QEMUMachineInitFunc *init;
> QEMUMachineResetFunc *reset;
> - int use_scsi;
> + int mach_if;
> int max_cpus;
> unsigned int no_serial:1,
> no_parallel:1,
> diff --git a/hw/device-hotplug.c b/hw/device-hotplug.c
> index 2bdc615..1ad233c 100644
> --- a/hw/device-hotplug.c
> +++ b/hw/device-hotplug.c
> @@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)
> if (!opts)
> return NULL;
>
> - dinfo = drive_init(opts, current_machine->use_scsi);
> + dinfo = drive_init(opts, current_machine->mach_if);
> if (!dinfo) {
> qemu_opts_del(opts);
> return NULL;
> diff --git a/hw/highbank.c b/hw/highbank.c
> index 11aa131..35cef06 100644
> --- a/hw/highbank.c
> +++ b/hw/highbank.c
> @@ -324,7 +324,7 @@ static QEMUMachine highbank_machine = {
> .name = "highbank",
> .desc = "Calxeda Highbank (ECX-1000)",
> .init = highbank_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/leon3.c b/hw/leon3.c
> index 878d3aa..21b7a7b 100644
> --- a/hw/leon3.c
> +++ b/hw/leon3.c
> @@ -214,7 +214,7 @@ QEMUMachine leon3_generic_machine = {
> .name = "leon3_generic",
> .desc = "Leon-3 generic",
> .init = leon3_generic_hw_init,
> - .use_scsi = 0,
> + .mach_if = IF_DEFAULT,
> };
>
> static void leon3_machine_init(void)
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index db927f1..1c7a725 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -325,14 +325,14 @@ static QEMUMachine mips_magnum_machine = {
> .name = "magnum",
> .desc = "MIPS Magnum",
> .init = mips_magnum_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine mips_pica61_machine = {
> .name = "pica61",
> .desc = "Acer Pica 61",
> .init = mips_pica61_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static void mips_jazz_machine_init(void)
> diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
> index b45f0ac..b8a03a6 100644
> --- a/hw/pc_sysfw.c
> +++ b/hw/pc_sysfw.c
> @@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)
> return;
> }
>
> - drive_init(opts, machine->use_scsi);
> + drive_init(opts, machine->mach_if);
> }
>
> static void pc_system_flash_init(MemoryRegion *rom_memory,
> diff --git a/hw/puv3.c b/hw/puv3.c
> index 43f7216..f68bb61 100644
> --- a/hw/puv3.c
> +++ b/hw/puv3.c
> @@ -120,7 +120,7 @@ static QEMUMachine puv3_machine = {
> .desc = "PKUnity Version-3 based on UniCore32",
> .init = puv3_init,
> .is_default = 1,
> - .use_scsi = 0,
> + .mach_if = IF_DEFAULT,
> };
>
> static void puv3_machine_init(void)
> diff --git a/hw/realview.c b/hw/realview.c
> index 19db4d0..7613f68 100644
> --- a/hw/realview.c
> +++ b/hw/realview.c
> @@ -382,14 +382,14 @@ static QEMUMachine realview_eb_machine = {
> .name = "realview-eb",
> .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
> .init = realview_eb_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine realview_eb_mpcore_machine = {
> .name = "realview-eb-mpcore",
> .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
> .init = realview_eb_mpcore_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -403,7 +403,7 @@ static QEMUMachine realview_pbx_a9_machine = {
> .name = "realview-pbx-a9",
> .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
> .init = realview_pbx_a9_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/spapr.c b/hw/spapr.c
> index c34b767..42977ca 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -849,7 +849,7 @@ static QEMUMachine spapr_machine = {
> .init = ppc_spapr_init,
> .max_cpus = MAX_CPUS,
> .no_parallel = 1,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static void spapr_machine_init(void)
> diff --git a/hw/sun4m.c b/hw/sun4m.c
> index c98cd5e..de25fea 100644
> --- a/hw/sun4m.c
> +++ b/hw/sun4m.c
> @@ -1397,7 +1397,7 @@ static QEMUMachine ss5_machine = {
> .name = "SS-5",
> .desc = "Sun4m platform, SPARCstation 5",
> .init = ss5_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .is_default = 1,
> };
>
> @@ -1405,7 +1405,7 @@ static QEMUMachine ss10_machine = {
> .name = "SS-10",
> .desc = "Sun4m platform, SPARCstation 10",
> .init = ss10_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1413,7 +1413,7 @@ static QEMUMachine ss600mp_machine = {
> .name = "SS-600MP",
> .desc = "Sun4m platform, SPARCserver 600MP",
> .init = ss600mp_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1421,7 +1421,7 @@ static QEMUMachine ss20_machine = {
> .name = "SS-20",
> .desc = "Sun4m platform, SPARCstation 20",
> .init = ss20_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -1429,35 +1429,35 @@ static QEMUMachine voyager_machine = {
> .name = "Voyager",
> .desc = "Sun4m platform, SPARCstation Voyager",
> .init = vger_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine ss_lx_machine = {
> .name = "LX",
> .desc = "Sun4m platform, SPARCstation LX",
> .init = ss_lx_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine ss4_machine = {
> .name = "SS-4",
> .desc = "Sun4m platform, SPARCstation 4",
> .init = ss4_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine scls_machine = {
> .name = "SPARCClassic",
> .desc = "Sun4m platform, SPARCClassic",
> .init = scls_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine sbook_machine = {
> .name = "SPARCbook",
> .desc = "Sun4m platform, SPARCbook",
> .init = sbook_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static const struct sun4d_hwdef sun4d_hwdefs[] = {
> @@ -1674,7 +1674,7 @@ static QEMUMachine ss1000_machine = {
> .name = "SS-1000",
> .desc = "Sun4d platform, SPARCserver 1000",
> .init = ss1000_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 8,
> };
>
> @@ -1682,7 +1682,7 @@ static QEMUMachine ss2000_machine = {
> .name = "SS-2000",
> .desc = "Sun4d platform, SPARCcenter 2000",
> .init = ss2000_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 20,
> };
>
> @@ -1858,7 +1858,7 @@ static QEMUMachine ss2_machine = {
> .name = "SS-2",
> .desc = "Sun4c platform, SPARCstation 2",
> .init = ss2_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static void sun4m_register_types(void)
> diff --git a/hw/versatilepb.c b/hw/versatilepb.c
> index 7a92034..17e15c6 100644
> --- a/hw/versatilepb.c
> +++ b/hw/versatilepb.c
> @@ -368,14 +368,14 @@ static QEMUMachine versatilepb_machine = {
> .name = "versatilepb",
> .desc = "ARM Versatile/PB (ARM926EJ-S)",
> .init = vpb_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static QEMUMachine versatileab_machine = {
> .name = "versatileab",
> .desc = "ARM Versatile/AB (ARM926EJ-S)",
> .init = vab_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> };
>
> static void versatile_machine_init(void)
> diff --git a/hw/vexpress.c b/hw/vexpress.c
> index 3596d1e..3c7c012 100644
> --- a/hw/vexpress.c
> +++ b/hw/vexpress.c
> @@ -495,7 +495,7 @@ static QEMUMachine vexpress_a9_machine = {
> .name = "vexpress-a9",
> .desc = "ARM Versatile Express for Cortex-A9",
> .init = vexpress_a9_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> @@ -503,7 +503,7 @@ static QEMUMachine vexpress_a15_machine = {
> .name = "vexpress-a15",
> .desc = "ARM Versatile Express for Cortex-A15",
> .init = vexpress_a15_init,
> - .use_scsi = 1,
> + .mach_if = IF_SCSI,
> .max_cpus = 4,
> };
>
> diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
> index 7e6c273..510d93d 100644
> --- a/hw/xilinx_zynq.c
> +++ b/hw/xilinx_zynq.c
> @@ -144,7 +144,7 @@ static QEMUMachine zynq_machine = {
> .name = "xilinx-zynq-a9",
> .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
> .init = zynq_init,
> - .use_scsi = 1,
> + .if_default = IF_SCSI,
> .max_cpus = 1,
> .no_sdcard = 1
> };
> diff --git a/vl.c b/vl.c
> index 8d305ca..77af809 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -802,9 +802,9 @@ static int parse_sandbox(QemuOpts *opts, void *opaque)
>
> static int drive_init_func(QemuOpts *opts, void *opaque)
> {
> - int *use_scsi = opaque;
> + int *mach_if = opaque;
>
> - return drive_init(opts, *use_scsi) == NULL;
> + return drive_init(opts, *mach_if) == NULL;
> }
>
> static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
> @@ -815,14 +815,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)
> return 0;
> }
>
> -static void default_drive(int enable, int snapshot, int use_scsi,
> +static void default_drive(int enable, int snapshot, int mach_if,
> BlockInterfaceType type, int index,
> const char *optstr)
> {
> QemuOpts *opts;
>
> if (type == IF_DEFAULT) {
> - type = use_scsi ? IF_SCSI : IF_IDE;
> + type = get_mach_if(mach_if);
> }
>
> if (!enable || drive_get_by_index(type, index)) {
> @@ -833,7 +833,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,
> if (snapshot) {
> drive_enable_snapshot(opts, NULL);
> }
> - if (!drive_init(opts, use_scsi)) {
> + if (!drive_init(opts, mach_if)) {
> exit(1);
> }
> }
> @@ -3537,14 +3537,16 @@ int main(int argc, char **argv, char **envp)
> /* open the virtual block devices */
> if (snapshot)
> qemu_opts_foreach(qemu_find_opts("drive"), drive_enable_snapshot, NULL, 0);
> - if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func, &machine->use_scsi, 1) != 0)
> + if (qemu_opts_foreach(qemu_find_opts("drive"), drive_init_func,
> + &machine->mach_if, 1) != 0) {
> exit(1);
> + }
>
> - default_drive(default_cdrom, snapshot, machine->use_scsi,
> + default_drive(default_cdrom, snapshot, machine->mach_if,
> IF_DEFAULT, 2, CDROM_OPTS);
> - default_drive(default_floppy, snapshot, machine->use_scsi,
> + default_drive(default_floppy, snapshot, machine->mach_if,
> IF_FLOPPY, 0, FD_OPTS);
> - default_drive(default_sdcard, snapshot, machine->use_scsi,
> + default_drive(default_sdcard, snapshot, machine->mach_if,
> IF_SD, 0, SD_OPTS);
>
> register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, NULL);
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 02/21] blockdev: Introduce IF_AHCI
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 01/21] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:36 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space Jason Baron
` (18 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is important, since we don't want
to have the meaning of if=ide changing once q35 is introduced. Thus, its
important for this to be applied before we introduce q35.
This patch also adds:
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
Which provides a convient way of attaching ahci drives to an
ahci controller.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
blockdev.c | 13 ++++++++++++-
blockdev.h | 2 ++
hw/ide.h | 6 ++++++
hw/ide/ahci.c | 18 ++++++++++++++++++
hw/ide/core.c | 23 ++++++++++++++++++-----
5 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 93a7bf7..9ccc150 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -32,6 +32,7 @@ static const char *const if_name[IF_COUNT] = {
[IF_SD] = "sd",
[IF_VIRTIO] = "virtio",
[IF_XEN] = "xen",
+ [IF_AHCI] = "ahci",
};
static const int if_max_devs[IF_COUNT] = {
@@ -51,8 +52,17 @@ static const int if_max_devs[IF_COUNT] = {
*/
[IF_IDE] = 2,
[IF_SCSI] = 7,
+ [IF_AHCI] = 6,
};
+int get_if_max_devs(BlockInterfaceType if_type)
+{
+ assert(if_type < IF_COUNT);
+ assert(if_type >= IF_DEFAULT);
+
+ return if_max_devs[if_type];
+}
+
/*
* We automatically delete the drive when a device using it gets
* unplugged. Questionable feature, but we can't just drop it.
@@ -517,7 +527,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)
} else {
/* no id supplied -> create one */
dinfo->id = g_malloc0(32);
- if (type == IF_IDE || type == IF_SCSI)
+ if (type == IF_IDE || type == IF_SCSI || type == IF_AHCI)
mediastr = (media == MEDIA_CDROM) ? "-cd" : "-hd";
if (max_devs)
snprintf(dinfo->id, 32, "%s%i%s%i",
@@ -549,6 +559,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)
switch(type) {
case IF_IDE:
+ case IF_AHCI:
case IF_SCSI:
case IF_XEN:
case IF_NONE:
diff --git a/blockdev.h b/blockdev.h
index 8b126ad..bbd1017 100644
--- a/blockdev.h
+++ b/blockdev.h
@@ -21,6 +21,7 @@ typedef enum {
IF_DEFAULT = -1, /* for use with drive_add() only */
IF_NONE,
IF_IDE, IF_SCSI, IF_FLOPPY, IF_PFLASH, IF_MTD, IF_SD, IF_VIRTIO, IF_XEN,
+ IF_AHCI,
IF_COUNT
} BlockInterfaceType;
@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)
return mach_if;
}
+int get_if_max_devs(BlockInterfaceType if_type);
DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
int drive_get_max_bus(BlockInterfaceType type);
diff --git a/hw/ide.h b/hw/ide.h
index 2db4079..0b7e000 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -4,6 +4,7 @@
#include "isa.h"
#include "pci.h"
#include "memory.h"
+#include "blockdev.h"
#define MAX_IDE_DEVS 2
@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,
int ide_get_bios_chs_trans(BusState *bus, int unit);
/* ide/core.c */
+void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type);
void ide_drive_get(DriveInfo **hd, int max_bus);
+void ahci_drive_get(DriveInfo **hd, int max_bus);
+
+/* ide/ahci.c */
+void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
#endif /* HW_IDE_H */
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 68671bc..824b86f 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -26,6 +26,7 @@
#include <hw/pc.h>
#include <hw/pci.h>
#include <hw/sysbus.h>
+#include <blockdev.h>
#include "monitor.h"
#include "dma.h"
@@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void)
}
type_init(sysbus_ahci_register_types)
+
+void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
+{
+ struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
+ int i;
+ DriveInfo *drive;
+
+ for (i = 0; i < dev->ahci.ports; i++) {
+ if (hd_table[i] == NULL) {
+ continue;
+ }
+ drive = hd_table[i];
+ assert(drive->type == IF_AHCI);
+ ide_create_drive(&dev->ahci.dev[i].port, 0,
+ hd_table[i]);
+ }
+}
diff --git a/hw/ide/core.c b/hw/ide/core.c
index d6fb69c..f2fcc79 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -2351,16 +2351,29 @@ const VMStateDescription vmstate_ide_bus = {
}
};
-void ide_drive_get(DriveInfo **hd, int max_bus)
+void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type)
{
int i;
+ int max_devs;
+
+ assert((type == IF_IDE) || type == IF_AHCI);
- if (drive_get_max_bus(IF_IDE) >= max_bus) {
+ if (drive_get_max_bus(type) >= max_bus) {
fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
exit(1);
}
-
- for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
- hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
+ max_devs = get_if_max_devs(type);
+ for (i = 0; i < max_bus * max_devs; i++) {
+ hd[i] = drive_get(type, i / max_devs, i % max_devs);
}
}
+
+void ide_drive_get(DriveInfo **hd, int max_bus)
+{
+ ata_drive_get(hd, max_bus, IF_IDE);
+}
+
+void ahci_drive_get(DriveInfo **hd, int max_bus)
+{
+ ata_drive_get(hd, max_bus, IF_AHCI);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 02/21] blockdev: Introduce IF_AHCI
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 02/21] blockdev: Introduce IF_AHCI Jason Baron
@ 2012-10-09 7:36 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:36 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
> This allows q35 to specify its default disk type. It also allows q35 to
> differentiate between ahci and ide disks, such that -drive if=ide does not
> result in the creating of an ahci disk. This is important, since we don't want
> to have the meaning of if=ide changing once q35 is introduced. Thus, its
> important for this to be applied before we introduce q35.
>
> This patch also adds:
>
> pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
>
> Which provides a convient way of attaching ahci drives to an
> ahci controller.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> blockdev.c | 13 ++++++++++++-
> blockdev.h | 2 ++
> hw/ide.h | 6 ++++++
> hw/ide/ahci.c | 18 ++++++++++++++++++
> hw/ide/core.c | 23 ++++++++++++++++++-----
> 5 files changed, 56 insertions(+), 6 deletions(-)
>
> diff --git a/blockdev.c b/blockdev.c
> index 93a7bf7..9ccc150 100644
> --- a/blockdev.c
> +++ b/blockdev.c
> @@ -32,6 +32,7 @@ static const char *const if_name[IF_COUNT] = {
> [IF_SD] = "sd",
> [IF_VIRTIO] = "virtio",
> [IF_XEN] = "xen",
> + [IF_AHCI] = "ahci",
> };
>
> static const int if_max_devs[IF_COUNT] = {
> @@ -51,8 +52,17 @@ static const int if_max_devs[IF_COUNT] = {
> */
> [IF_IDE] = 2,
> [IF_SCSI] = 7,
> + [IF_AHCI] = 6,
> };
>
> +int get_if_max_devs(BlockInterfaceType if_type)
> +{
> + assert(if_type < IF_COUNT);
> + assert(if_type >= IF_DEFAULT);
> +
> + return if_max_devs[if_type];
> +}
> +
> /*
> * We automatically delete the drive when a device using it gets
> * unplugged. Questionable feature, but we can't just drop it.
> @@ -517,7 +527,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)
> } else {
> /* no id supplied -> create one */
> dinfo->id = g_malloc0(32);
> - if (type == IF_IDE || type == IF_SCSI)
> + if (type == IF_IDE || type == IF_SCSI || type == IF_AHCI)
> mediastr = (media == MEDIA_CDROM) ? "-cd" : "-hd";
> if (max_devs)
> snprintf(dinfo->id, 32, "%s%i%s%i",
> @@ -549,6 +559,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)
>
> switch(type) {
> case IF_IDE:
> + case IF_AHCI:
> case IF_SCSI:
> case IF_XEN:
> case IF_NONE:
> diff --git a/blockdev.h b/blockdev.h
> index 8b126ad..bbd1017 100644
> --- a/blockdev.h
> +++ b/blockdev.h
> @@ -21,6 +21,7 @@ typedef enum {
> IF_DEFAULT = -1, /* for use with drive_add() only */
> IF_NONE,
> IF_IDE, IF_SCSI, IF_FLOPPY, IF_PFLASH, IF_MTD, IF_SD, IF_VIRTIO, IF_XEN,
> + IF_AHCI,
> IF_COUNT
> } BlockInterfaceType;
>
> @@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)
> return mach_if;
> }
>
> +int get_if_max_devs(BlockInterfaceType if_type);
> DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
> DriveInfo *drive_get_by_index(BlockInterfaceType type, int index);
> int drive_get_max_bus(BlockInterfaceType type);
> diff --git a/hw/ide.h b/hw/ide.h
> index 2db4079..0b7e000 100644
> --- a/hw/ide.h
> +++ b/hw/ide.h
> @@ -4,6 +4,7 @@
> #include "isa.h"
> #include "pci.h"
> #include "memory.h"
> +#include "blockdev.h"
>
> #define MAX_IDE_DEVS 2
>
> @@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,
> int ide_get_bios_chs_trans(BusState *bus, int unit);
>
> /* ide/core.c */
> +void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type);
> void ide_drive_get(DriveInfo **hd, int max_bus);
> +void ahci_drive_get(DriveInfo **hd, int max_bus);
> +
> +/* ide/ahci.c */
> +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
>
> #endif /* HW_IDE_H */
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 68671bc..824b86f 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -26,6 +26,7 @@
> #include <hw/pc.h>
> #include <hw/pci.h>
> #include <hw/sysbus.h>
> +#include <blockdev.h>
>
> #include "monitor.h"
> #include "dma.h"
> @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void)
> }
>
> type_init(sysbus_ahci_register_types)
> +
> +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
> +{
> + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
> + int i;
> + DriveInfo *drive;
> +
> + for (i = 0; i < dev->ahci.ports; i++) {
> + if (hd_table[i] == NULL) {
> + continue;
> + }
> + drive = hd_table[i];
> + assert(drive->type == IF_AHCI);
> + ide_create_drive(&dev->ahci.dev[i].port, 0,
> + hd_table[i]);
> + }
> +}
> diff --git a/hw/ide/core.c b/hw/ide/core.c
> index d6fb69c..f2fcc79 100644
> --- a/hw/ide/core.c
> +++ b/hw/ide/core.c
> @@ -2351,16 +2351,29 @@ const VMStateDescription vmstate_ide_bus = {
> }
> };
>
> -void ide_drive_get(DriveInfo **hd, int max_bus)
> +void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type)
> {
> int i;
> + int max_devs;
> +
> + assert((type == IF_IDE) || type == IF_AHCI);
>
> - if (drive_get_max_bus(IF_IDE) >= max_bus) {
> + if (drive_get_max_bus(type) >= max_bus) {
> fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
> exit(1);
> }
> -
> - for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
> - hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
> + max_devs = get_if_max_devs(type);
> + for (i = 0; i < max_bus * max_devs; i++) {
> + hd[i] = drive_get(type, i / max_devs, i % max_devs);
> }
> }
> +
> +void ide_drive_get(DriveInfo **hd, int max_bus)
> +{
> + ata_drive_get(hd, max_bus, IF_IDE);
> +}
> +
> +void ahci_drive_get(DriveInfo **hd, int max_bus)
> +{
> + ata_drive_get(hd, max_bus, IF_AHCI);
> +}
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 01/21] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if Jason Baron
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 02/21] blockdev: Introduce IF_AHCI Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:36 ` Paolo Bonzini
2012-10-13 8:29 ` Blue Swirl
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 04/21] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
` (17 subsequent siblings)
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index f855cf3..85ebef6 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1626,12 +1626,11 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
return pci_create_simple_multifunction(bus, devfn, false, name);
}
-static int pci_find_space(PCIDevice *pdev, uint8_t size)
+static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
{
- int config_size = pci_config_size(pdev);
int offset = PCI_CONFIG_HEADER_SIZE;
int i;
- for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
+ for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
if (pdev->used[i])
offset = i + 1;
else if (i - offset + 1 == size)
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space Jason Baron
@ 2012-10-09 7:36 ` Paolo Bonzini
2012-10-13 8:29 ` Blue Swirl
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:36 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> pci capability must be in PCI space.
> It can't lay in PCIe extended config space.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pci.c | 5 ++---
> 1 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index f855cf3..85ebef6 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1626,12 +1626,11 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
> return pci_create_simple_multifunction(bus, devfn, false, name);
> }
>
> -static int pci_find_space(PCIDevice *pdev, uint8_t size)
> +static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
> {
> - int config_size = pci_config_size(pdev);
> int offset = PCI_CONFIG_HEADER_SIZE;
> int i;
> - for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
> + for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
> if (pdev->used[i])
> offset = i + 1;
> else if (i - offset + 1 == size)
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space Jason Baron
2012-10-09 7:36 ` Paolo Bonzini
@ 2012-10-13 8:29 ` Blue Swirl
1 sibling, 0 replies; 65+ messages in thread
From: Blue Swirl @ 2012-10-13 8:29 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, armbru, kraxel
On Tue, Oct 9, 2012 at 3:30 AM, Jason Baron <jbaron@redhat.com> wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> pci capability must be in PCI space.
> It can't lay in PCIe extended config space.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pci.c | 5 ++---
> 1 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index f855cf3..85ebef6 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1626,12 +1626,11 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
> return pci_create_simple_multifunction(bus, devfn, false, name);
> }
>
> -static int pci_find_space(PCIDevice *pdev, uint8_t size)
> +static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
> {
> - int config_size = pci_config_size(pdev);
> int offset = PCI_CONFIG_HEADER_SIZE;
> int i;
> - for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
> + for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
Please add braces.
> if (pdev->used[i])
> offset = i + 1;
> else if (i - offset + 1 == size)
> --
> 1.7.1
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 04/21] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (2 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 03/21] pci: pci capability must be in PCI space Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:39 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 06/21] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
` (16 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
[jbaron@redhat.com: drop opaque argument]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 18 ++++++++++++++++++
hw/pci.h | 2 ++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 85ebef6..c457d50 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev,
dev->intx_routing_notifier = notifier;
}
+/*
+ * PCI-to-PCI bridge specification
+ * 9.1: Interrupt routing. Table 9-1
+ *
+ * the PCI Express Base Specification, Revision 2.1
+ * 2.2.8.1: INTx interrutp signaling - Rules
+ * the Implementation Note
+ * Table 2-20
+ */
+/*
+ * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
+ * 0-origin unlike PCI interrupt pin register.
+ */
+int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
+{
+ return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
+}
+
/***********************************************************/
/* monitor info on PCI */
diff --git a/hw/pci.h b/hw/pci.h
index 4b6ab3d..397477e 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, int nirq);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
+/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
+int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque,
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 04/21] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 04/21] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
@ 2012-10-09 7:39 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:39 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
> standardized. PCI bridge swizzle is common logic, by introducing
> this function duplicated swizzle logic will be avoided later.
>
> [jbaron@redhat.com: drop opaque argument]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/pci.c | 18 ++++++++++++++++++
> hw/pci.h | 2 ++
> 2 files changed, 20 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index 85ebef6..c457d50 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev,
> dev->intx_routing_notifier = notifier;
> }
>
> +/*
> + * PCI-to-PCI bridge specification
> + * 9.1: Interrupt routing. Table 9-1
> + *
> + * the PCI Express Base Specification, Revision 2.1
> + * 2.2.8.1: INTx interrutp signaling - Rules
> + * the Implementation Note
> + * Table 2-20
> + */
> +/*
> + * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
> + * 0-origin unlike PCI interrupt pin register.
> + */
> +int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
> +{
> + return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
> +}
> +
> /***********************************************************/
> /* monitor info on PCI */
>
> diff --git a/hw/pci.h b/hw/pci.h
> index 4b6ab3d..397477e 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
> void *irq_opaque, int nirq);
> int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
> void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
> +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
> +int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
> PCIBus *pci_register_bus(DeviceState *parent, const char *name,
> pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
> void *irq_opaque,
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 06/21] pc: Move ioapic_init() from pc_piix.c to pc.c
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (3 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 04/21] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:44 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 05/21] pc, pc_piix: split out pc nic initialization Jason Baron
` (15 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 24 ++++++++++++++++++++++++
hw/pc.h | 2 ++
hw/pc_piix.c | 25 +------------------------
3 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index fef39ba..f5fbd0c 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1148,3 +1148,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
pci_create_simple(pci_bus, -1, "lsi53c895a");
}
}
+
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
+{
+ DeviceState *dev;
+ SysBusDevice *d;
+ unsigned int i;
+
+ if (kvm_irqchip_in_kernel()) {
+ dev = qdev_create(NULL, "kvm-ioapic");
+ } else {
+ dev = qdev_create(NULL, "ioapic");
+ }
+ if (parent_name) {
+ object_property_add_child(object_resolve_path(parent_name, NULL),
+ "ioapic", OBJECT(dev), NULL);
+ }
+ qdev_init_nofail(dev);
+ d = sysbus_from_qdev(dev);
+ sysbus_mmio_map(d, 0, 0xfec00000);
+
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
+ }
+}
diff --git a/hw/pc.h b/hw/pc.h
index d0feb20..c78923c 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -131,6 +131,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
+
/* acpi.c */
extern int acpi_enabled;
extern char *acpi_tables;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 87ca60b..668dccf 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -94,29 +94,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
}
}
-static void ioapic_init(GSIState *gsi_state)
-{
- DeviceState *dev;
- SysBusDevice *d;
- unsigned int i;
-
- if (kvm_irqchip_in_kernel()) {
- dev = qdev_create(NULL, "kvm-ioapic");
- } else {
- dev = qdev_create(NULL, "ioapic");
- }
- /* FIXME: this should be under the piix3. */
- object_property_add_child(object_resolve_path("i440fx", NULL),
- "ioapic", OBJECT(dev), NULL);
- qdev_init_nofail(dev);
- d = sysbus_from_qdev(dev);
- sysbus_mmio_map(d, 0, 0xfec00000);
-
- for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
- }
-}
-
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *system_io,
@@ -220,7 +197,7 @@ static void pc_init1(MemoryRegion *system_memory,
gsi_state->i8259_irq[i] = i8259[i];
}
if (pci_enabled) {
- ioapic_init(gsi_state);
+ ioapic_init_gsi(gsi_state, "i440fx");
}
pc_register_ferr_irq(gsi[13]);
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 06/21] pc: Move ioapic_init() from pc_piix.c to pc.c
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 06/21] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
@ 2012-10-09 7:44 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:44 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
> Rename ioapic_init -> ioapic_init_gsi.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/pc.c | 24 ++++++++++++++++++++++++
> hw/pc.h | 2 ++
> hw/pc_piix.c | 25 +------------------------
> 3 files changed, 27 insertions(+), 24 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index fef39ba..f5fbd0c 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1148,3 +1148,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
> pci_create_simple(pci_bus, -1, "lsi53c895a");
> }
> }
> +
> +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
> +{
> + DeviceState *dev;
> + SysBusDevice *d;
> + unsigned int i;
> +
> + if (kvm_irqchip_in_kernel()) {
> + dev = qdev_create(NULL, "kvm-ioapic");
> + } else {
> + dev = qdev_create(NULL, "ioapic");
> + }
> + if (parent_name) {
> + object_property_add_child(object_resolve_path(parent_name, NULL),
> + "ioapic", OBJECT(dev), NULL);
> + }
> + qdev_init_nofail(dev);
> + d = sysbus_from_qdev(dev);
> + sysbus_mmio_map(d, 0, 0xfec00000);
> +
> + for (i = 0; i < IOAPIC_NUM_PINS; i++) {
> + gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> + }
> +}
> diff --git a/hw/pc.h b/hw/pc.h
> index d0feb20..c78923c 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -131,6 +131,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
> typedef void (*cpu_set_smm_t)(int smm, void *arg);
> void cpu_smm_register(cpu_set_smm_t callback, void *arg);
>
> +void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
> +
> /* acpi.c */
> extern int acpi_enabled;
> extern char *acpi_tables;
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 87ca60b..668dccf 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -94,29 +94,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> }
> }
>
> -static void ioapic_init(GSIState *gsi_state)
> -{
> - DeviceState *dev;
> - SysBusDevice *d;
> - unsigned int i;
> -
> - if (kvm_irqchip_in_kernel()) {
> - dev = qdev_create(NULL, "kvm-ioapic");
> - } else {
> - dev = qdev_create(NULL, "ioapic");
> - }
> - /* FIXME: this should be under the piix3. */
> - object_property_add_child(object_resolve_path("i440fx", NULL),
> - "ioapic", OBJECT(dev), NULL);
> - qdev_init_nofail(dev);
> - d = sysbus_from_qdev(dev);
> - sysbus_mmio_map(d, 0, 0xfec00000);
> -
> - for (i = 0; i < IOAPIC_NUM_PINS; i++) {
> - gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> - }
> -}
> -
> /* PC hardware initialisation */
> static void pc_init1(MemoryRegion *system_memory,
> MemoryRegion *system_io,
> @@ -220,7 +197,7 @@ static void pc_init1(MemoryRegion *system_memory,
> gsi_state->i8259_irq[i] = i8259[i];
> }
> if (pci_enabled) {
> - ioapic_init(gsi_state);
> + ioapic_init_gsi(gsi_state, "i440fx");
> }
>
> pc_register_ferr_irq(gsi[13]);
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 05/21] pc, pc_piix: split out pc nic initialization
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (4 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 06/21] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:39 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 07/21] pc/piix_pci: factor out smram/pam logic Jason Baron
` (14 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 15 +++++++++++++++
hw/pc.h | 1 +
hw/pc_piix.c | 9 +--------
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 7e7e0e2..fef39ba 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1123,6 +1123,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
*floppy = fdctrl_init_isa(isa_bus, fd);
}
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
+{
+ int i;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+ pc_init_ne2k_isa(isa_bus, nd);
+ } else {
+ pci_nic_init_nofail(nd, "e1000", NULL);
+ }
+ }
+}
+
void pc_pci_device_init(PCIBus *pci_bus)
{
int max_bus;
diff --git a/hw/pc.h b/hw/pc.h
index e4db071..d0feb20 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -125,6 +125,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device,
ISADevice *floppy, BusState *ide0, BusState *ide1,
ISADevice *s);
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index fd5898f..87ca60b 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -233,14 +233,7 @@ static void pc_init1(MemoryRegion *system_memory,
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
- for(i = 0; i < nb_nics; i++) {
- NICInfo *nd = &nd_table[i];
-
- if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
- pc_init_ne2k_isa(isa_bus, nd);
- else
- pci_nic_init_nofail(nd, "e1000", NULL);
- }
+ pc_nic_init(isa_bus, pci_bus);
ide_drive_get(hd, MAX_IDE_BUS);
if (pci_enabled) {
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 05/21] pc, pc_piix: split out pc nic initialization
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 05/21] pc, pc_piix: split out pc nic initialization Jason Baron
@ 2012-10-09 7:39 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:39 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out pc nic initialization.
> This simplifies the pc initialization and will reduce the code
> duplication of q35 pc initialization.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/pc.c | 15 +++++++++++++++
> hw/pc.h | 1 +
> hw/pc_piix.c | 9 +--------
> 3 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 7e7e0e2..fef39ba 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1123,6 +1123,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
> *floppy = fdctrl_init_isa(isa_bus, fd);
> }
>
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
> +{
> + int i;
> +
> + for (i = 0; i < nb_nics; i++) {
> + NICInfo *nd = &nd_table[i];
> +
> + if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
> + pc_init_ne2k_isa(isa_bus, nd);
> + } else {
> + pci_nic_init_nofail(nd, "e1000", NULL);
> + }
> + }
> +}
> +
> void pc_pci_device_init(PCIBus *pci_bus)
> {
> int max_bus;
> diff --git a/hw/pc.h b/hw/pc.h
> index e4db071..d0feb20 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -125,6 +125,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
> const char *boot_device,
> ISADevice *floppy, BusState *ide0, BusState *ide1,
> ISADevice *s);
> +void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
> void pc_pci_device_init(PCIBus *pci_bus);
>
> typedef void (*cpu_set_smm_t)(int smm, void *arg);
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index fd5898f..87ca60b 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -233,14 +233,7 @@ static void pc_init1(MemoryRegion *system_memory,
> /* init basic PC hardware */
> pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
>
> - for(i = 0; i < nb_nics; i++) {
> - NICInfo *nd = &nd_table[i];
> -
> - if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
> - pc_init_ne2k_isa(isa_bus, nd);
> - else
> - pci_nic_init_nofail(nd, "e1000", NULL);
> - }
> + pc_nic_init(isa_bus, pci_bus);
>
> ide_drive_get(hd, MAX_IDE_BUS);
> if (pci_enabled) {
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 07/21] pc/piix_pci: factor out smram/pam logic
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (5 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 05/21] pc, pc_piix: split out pc nic initialization Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:47 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
` (13 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jbaron@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/i386/Makefile.objs | 1 +
hw/pam.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/pam.h | 98 ++++++++++++++++++++++++++++++++++++++++
hw/piix_pci.c | 65 ++++----------------------
4 files changed, 229 insertions(+), 55 deletions(-)
create mode 100644 hw/pam.c
create mode 100644 hw/pam.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 8c764bb..2f0c172 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
+obj-y += pam.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
diff --git a/hw/pam.c b/hw/pam.c
new file mode 100644
index 0000000..9ec5861
--- /dev/null
+++ b/hw/pam.c
@@ -0,0 +1,120 @@
+/*
+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ */
+
+#include "sysemu.h"
+#include "pam.h"
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled)
+{
+ bool smram_enabled;
+
+ smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
+ (smram & SMRAM_D_OPEN));
+ memory_region_set_enabled(smram_region, !smram_enabled);
+}
+
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region)
+{
+ uint8_t smm_enabled = (smm != 0);
+ if (*host_smm_enabled != smm_enabled) {
+ *host_smm_enabled = smm_enabled;
+ smram_update(smram_region, smram, *host_smm_enabled);
+ }
+}
+
+static void pam_update_seg(PAMMemoryRegion *mem, uint32_t start, uint32_t size,
+ MemoryRegion *ram_memory,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory, uint8_t attr)
+{
+ if (mem->initialized) {
+ memory_region_del_subregion(system_memory, &mem->mem);
+ memory_region_destroy(&mem->mem);
+ }
+
+ switch (attr) {
+ case PAM_ATTR_WE | PAM_ATTR_RE:
+ /* RAM */
+ memory_region_init_alias(&mem->mem, "pam-ram", ram_memory,
+ start, size);
+ break;
+ case PAM_ATTR_RE:
+ /* ROM (XXX: not quite correct) */
+ memory_region_init_alias(&mem->mem, "pam-rom", ram_memory,
+ start, size);
+ memory_region_set_readonly(&mem->mem, true);
+ break;
+ case PAM_ATTR_WE:
+ case 0:
+ /* XXX: should distinguish read/write cases */
+ memory_region_init_alias(&mem->mem, "pam-pci", pci_address_space,
+ start, size);
+ break;
+ default:
+ abort();
+ break;
+ }
+ memory_region_add_subregion_overlap(system_memory, start, &mem->mem, 1);
+ mem->initialized = true;
+
+}
+
+static uint8_t pam_attr(uint8_t val, int hi)
+{
+ return (val >> ((!!hi) * 4)) & PAM_ATTR_MASK;
+}
+
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
+ MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory)
+{
+ uint32_t phys_addr;
+ int map_idx;
+
+ assert(0 <= idx && idx <= PAM_IDX_MAX);
+
+ if (idx == 0) {
+ pam_update_seg(&mem[0], PAM_BIOS_BASE, PAM_BIOS_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 1));
+ return;
+ }
+
+ map_idx = (idx - 1) * 2;
+
+ phys_addr = PAM_EXPAN_BASE + PAM_EXPAN_SIZE * map_idx;
+ pam_update_seg(&mem[map_idx + 1], phys_addr, PAM_EXPAN_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 0));
+
+ phys_addr += PAM_EXPAN_SIZE;
+ pam_update_seg(&mem[map_idx + 2], phys_addr, PAM_EXPAN_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 1));
+}
diff --git a/hw/pam.h b/hw/pam.h
new file mode 100644
index 0000000..ce89a2a
--- /dev/null
+++ b/hw/pam.h
@@ -0,0 +1,98 @@
+#ifndef QEMU_PAM_H
+#define QEMU_PAM_H
+
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * SMRAM memory area and PAM memory area in Legacy address range for PC.
+ * PAM: Programmable Attribute Map registers
+ *
+ * 0xa0000 - 0xbffff compatible SMRAM
+ *
+ * 0xc0000 - 0xc3fff Expansion area memory segments
+ * 0xc4000 - 0xc7fff
+ * 0xc8000 - 0xcbfff
+ * 0xcc000 - 0xcffff
+ * 0xd0000 - 0xd7fff
+ * 0xd8000 - 0xdbfff
+ * 0xdc000 - 0xdffff
+ * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
+ * 0xe4000 - 0xe7fff
+ * 0xe8000 - 0xebfff
+ * 0xec000 - 0xeffff
+ *
+ * 0xf0000 - 0xfffff System BIOS Area Memory Segments
+ */
+
+#include "qemu-common.h"
+#include "memory.h"
+
+#define SMRAM_C_BASE 0xa0000
+#define SMRAM_C_END 0xc0000
+#define SMRAM_C_SIZE 0x20000
+
+
+#define PAM_EXPAN_BASE 0xc0000
+#define PAM_EXPAN_SIZE 0x04000
+
+#define PAM_EXBIOS_BASE 0xe0000
+#define PAM_EXBIOS_SIZE 0x04000
+
+#define PAM_BIOS_BASE 0xf0000
+#define PAM_BIOS_END 0xfffff
+/* 64KB: Intel 3 series express chipset family p. 58*/
+#define PAM_BIOS_SIZE 0x10000
+
+/* PAM registers: log nibble and high nibble*/
+#define PAM_ATTR_WE ((uint8_t)2)
+#define PAM_ATTR_RE ((uint8_t)1)
+#define PAM_ATTR_MASK ((uint8_t)3)
+
+#define PAM_IDX_MAX 6 /* pam0 - pam6 */
+
+/* SMRAM register */
+#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+
+typedef struct PAMMemoryRegion {
+ MemoryRegion mem;
+ bool initialized;
+} PAMMemoryRegion;
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled);
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region);
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
+ MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory);
+
+#endif /* QEMU_PAM_H */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 537fc19..02b161d 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -30,6 +30,7 @@
#include "sysbus.h"
#include "range.h"
#include "xen.h"
+#include "pam.h"
/*
* I440FX chipset data sheet.
@@ -68,11 +69,6 @@ typedef struct PIIX3State {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
-typedef struct PAMMemoryRegion {
- MemoryRegion mem;
- bool initialized;
-} PAMMemoryRegion;
-
struct PCII440FXState {
PCIDevice dev;
MemoryRegion *system_memory;
@@ -105,56 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
- PAMMemoryRegion *mem)
-{
- if (mem->initialized) {
- memory_region_del_subregion(d->system_memory, &mem->mem);
- memory_region_destroy(&mem->mem);
- }
-
- // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
- switch(r) {
- case 3:
- /* RAM */
- memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
- start, end - start);
- break;
- case 1:
- /* ROM (XXX: not quite correct) */
- memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
- start, end - start);
- memory_region_set_readonly(&mem->mem, true);
- break;
- case 2:
- case 0:
- /* XXX: should distinguish read/write cases */
- memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
- start, end - start);
- break;
- }
- memory_region_add_subregion_overlap(d->system_memory,
- start, &mem->mem, 1);
- mem->initialized = true;
-}
-
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
- int i, r;
- uint32_t smram;
- bool smram_enabled;
+ int i;
memory_region_transaction_begin();
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
- &d->pam_regions[0]);
- for(i = 0; i < 12; i++) {
- r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
- &d->pam_regions[i+1]);
+ for (i = 0; i <= PAM_IDX_MAX; i++) {
+ pam_update(&d->pam_regions[0], i, d->dev.config[I440FX_PAM + i],
+ d->ram_memory, d->pci_address_space, d->system_memory);
}
- smram = d->dev.config[I440FX_SMRAM];
- smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
- memory_region_set_enabled(&d->smram_region, !smram_enabled);
+ smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
memory_region_transaction_commit();
}
@@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
{
PCII440FXState *d = arg;
- val = (val != 0);
- if (d->smm_enabled != val) {
- d->smm_enabled = val;
- i440fx_update_memory_mappings(d);
- }
+ memory_region_transaction_begin();
+ smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
+ &d->smram_region);
+ memory_region_transaction_commit();
}
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 07/21] pc/piix_pci: factor out smram/pam logic
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 07/21] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-10-09 7:47 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:47 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out smram/pam logic for later use.
> Which will be used by q35 too.
>
> [jbaron@redhat.com: changes for updated memory API]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/i386/Makefile.objs | 1 +
> hw/pam.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pam.h | 98 ++++++++++++++++++++++++++++++++++++++++
> hw/piix_pci.c | 65 ++++----------------------
> 4 files changed, 229 insertions(+), 55 deletions(-)
> create mode 100644 hw/pam.c
> create mode 100644 hw/pam.h
>
> diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
> index 8c764bb..2f0c172 100644
> --- a/hw/i386/Makefile.objs
> +++ b/hw/i386/Makefile.objs
> @@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
> obj-y += debugcon.o multiboot.o
> obj-y += pc_piix.o
> obj-y += pc_sysfw.o
> +obj-y += pam.o
> obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
> diff --git a/hw/pam.c b/hw/pam.c
> new file mode 100644
> index 0000000..9ec5861
> --- /dev/null
> +++ b/hw/pam.c
> @@ -0,0 +1,120 @@
> +/*
> + * QEMU i440FX/PIIX3 PCI Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + * Split out from piix_pci.c
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + */
> +
> +#include "sysemu.h"
> +#include "pam.h"
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled)
> +{
> + bool smram_enabled;
> +
> + smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
> + (smram & SMRAM_D_OPEN));
> + memory_region_set_enabled(smram_region, !smram_enabled);
> +}
> +
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region)
> +{
> + uint8_t smm_enabled = (smm != 0);
> + if (*host_smm_enabled != smm_enabled) {
> + *host_smm_enabled = smm_enabled;
> + smram_update(smram_region, smram, *host_smm_enabled);
> + }
> +}
> +
> +static void pam_update_seg(PAMMemoryRegion *mem, uint32_t start, uint32_t size,
> + MemoryRegion *ram_memory,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory, uint8_t attr)
> +{
> + if (mem->initialized) {
> + memory_region_del_subregion(system_memory, &mem->mem);
> + memory_region_destroy(&mem->mem);
> + }
> +
> + switch (attr) {
> + case PAM_ATTR_WE | PAM_ATTR_RE:
> + /* RAM */
> + memory_region_init_alias(&mem->mem, "pam-ram", ram_memory,
> + start, size);
> + break;
> + case PAM_ATTR_RE:
> + /* ROM (XXX: not quite correct) */
> + memory_region_init_alias(&mem->mem, "pam-rom", ram_memory,
> + start, size);
> + memory_region_set_readonly(&mem->mem, true);
> + break;
> + case PAM_ATTR_WE:
> + case 0:
> + /* XXX: should distinguish read/write cases */
> + memory_region_init_alias(&mem->mem, "pam-pci", pci_address_space,
> + start, size);
> + break;
> + default:
> + abort();
> + break;
> + }
> + memory_region_add_subregion_overlap(system_memory, start, &mem->mem, 1);
> + mem->initialized = true;
> +
> +}
> +
> +static uint8_t pam_attr(uint8_t val, int hi)
> +{
> + return (val >> ((!!hi) * 4)) & PAM_ATTR_MASK;
> +}
> +
> +void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
> + MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory)
> +{
> + uint32_t phys_addr;
> + int map_idx;
> +
> + assert(0 <= idx && idx <= PAM_IDX_MAX);
> +
> + if (idx == 0) {
> + pam_update_seg(&mem[0], PAM_BIOS_BASE, PAM_BIOS_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 1));
> + return;
> + }
> +
> + map_idx = (idx - 1) * 2;
> +
> + phys_addr = PAM_EXPAN_BASE + PAM_EXPAN_SIZE * map_idx;
> + pam_update_seg(&mem[map_idx + 1], phys_addr, PAM_EXPAN_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 0));
> +
> + phys_addr += PAM_EXPAN_SIZE;
> + pam_update_seg(&mem[map_idx + 2], phys_addr, PAM_EXPAN_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 1));
> +}
> diff --git a/hw/pam.h b/hw/pam.h
> new file mode 100644
> index 0000000..ce89a2a
> --- /dev/null
> +++ b/hw/pam.h
> @@ -0,0 +1,98 @@
> +#ifndef QEMU_PAM_H
> +#define QEMU_PAM_H
> +
> +/*
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +/*
> + * Split out from piix_pci.c
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * SMRAM memory area and PAM memory area in Legacy address range for PC.
> + * PAM: Programmable Attribute Map registers
> + *
> + * 0xa0000 - 0xbffff compatible SMRAM
> + *
> + * 0xc0000 - 0xc3fff Expansion area memory segments
> + * 0xc4000 - 0xc7fff
> + * 0xc8000 - 0xcbfff
> + * 0xcc000 - 0xcffff
> + * 0xd0000 - 0xd7fff
> + * 0xd8000 - 0xdbfff
> + * 0xdc000 - 0xdffff
> + * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
> + * 0xe4000 - 0xe7fff
> + * 0xe8000 - 0xebfff
> + * 0xec000 - 0xeffff
> + *
> + * 0xf0000 - 0xfffff System BIOS Area Memory Segments
> + */
> +
> +#include "qemu-common.h"
> +#include "memory.h"
> +
> +#define SMRAM_C_BASE 0xa0000
> +#define SMRAM_C_END 0xc0000
> +#define SMRAM_C_SIZE 0x20000
> +
> +
> +#define PAM_EXPAN_BASE 0xc0000
> +#define PAM_EXPAN_SIZE 0x04000
> +
> +#define PAM_EXBIOS_BASE 0xe0000
> +#define PAM_EXBIOS_SIZE 0x04000
> +
> +#define PAM_BIOS_BASE 0xf0000
> +#define PAM_BIOS_END 0xfffff
> +/* 64KB: Intel 3 series express chipset family p. 58*/
> +#define PAM_BIOS_SIZE 0x10000
> +
> +/* PAM registers: log nibble and high nibble*/
> +#define PAM_ATTR_WE ((uint8_t)2)
> +#define PAM_ATTR_RE ((uint8_t)1)
> +#define PAM_ATTR_MASK ((uint8_t)3)
> +
> +#define PAM_IDX_MAX 6 /* pam0 - pam6 */
> +
> +/* SMRAM register */
> +#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
> +#define SMRAM_D_CLS ((uint8_t)(1 << 5))
> +#define SMRAM_D_LCK ((uint8_t)(1 << 4))
> +#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
> +#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
> +#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
> +
> +typedef struct PAMMemoryRegion {
> + MemoryRegion mem;
> + bool initialized;
> +} PAMMemoryRegion;
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled);
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region);
> +void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
> + MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory);
> +
> +#endif /* QEMU_PAM_H */
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 537fc19..02b161d 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -30,6 +30,7 @@
> #include "sysbus.h"
> #include "range.h"
> #include "xen.h"
> +#include "pam.h"
>
> /*
> * I440FX chipset data sheet.
> @@ -68,11 +69,6 @@ typedef struct PIIX3State {
> int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> } PIIX3State;
>
> -typedef struct PAMMemoryRegion {
> - MemoryRegion mem;
> - bool initialized;
> -} PAMMemoryRegion;
> -
> struct PCII440FXState {
> PCIDevice dev;
> MemoryRegion *system_memory;
> @@ -105,56 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> return (pci_intx + slot_addend) & 3;
> }
>
> -static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
> - PAMMemoryRegion *mem)
> -{
> - if (mem->initialized) {
> - memory_region_del_subregion(d->system_memory, &mem->mem);
> - memory_region_destroy(&mem->mem);
> - }
> -
> - // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
> - switch(r) {
> - case 3:
> - /* RAM */
> - memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
> - start, end - start);
> - break;
> - case 1:
> - /* ROM (XXX: not quite correct) */
> - memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
> - start, end - start);
> - memory_region_set_readonly(&mem->mem, true);
> - break;
> - case 2:
> - case 0:
> - /* XXX: should distinguish read/write cases */
> - memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
> - start, end - start);
> - break;
> - }
> - memory_region_add_subregion_overlap(d->system_memory,
> - start, &mem->mem, 1);
> - mem->initialized = true;
> -}
> -
> static void i440fx_update_memory_mappings(PCII440FXState *d)
> {
> - int i, r;
> - uint32_t smram;
> - bool smram_enabled;
> + int i;
>
> memory_region_transaction_begin();
> - update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
> - &d->pam_regions[0]);
> - for(i = 0; i < 12; i++) {
> - r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
> - update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
> - &d->pam_regions[i+1]);
> + for (i = 0; i <= PAM_IDX_MAX; i++) {
> + pam_update(&d->pam_regions[0], i, d->dev.config[I440FX_PAM + i],
> + d->ram_memory, d->pci_address_space, d->system_memory);
> }
> - smram = d->dev.config[I440FX_SMRAM];
> - smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
> - memory_region_set_enabled(&d->smram_region, !smram_enabled);
> + smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
> memory_region_transaction_commit();
> }
>
> @@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
> {
> PCII440FXState *d = arg;
>
> - val = (val != 0);
> - if (d->smm_enabled != val) {
> - d->smm_enabled = val;
> - i440fx_update_memory_mappings(d);
> - }
> + memory_region_transaction_begin();
> + smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
> + &d->smram_region);
> + memory_region_transaction_commit();
> }
>
>
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (6 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 07/21] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:48 ` Paolo Bonzini
2012-10-13 8:31 ` Blue Swirl
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 09/21] pci: Add class 0xc05 as 'SMBus' Jason Baron
` (12 subsequent siblings)
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
Adds pci id constants which will be used by q35.
[jbaron@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci_ids.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c..4017eb7 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -106,6 +106,7 @@
#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
#define PCI_DEVICE_ID_INTEL_82801D 0x24CD
#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
+#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
@ 2012-10-09 7:48 ` Paolo Bonzini
2012-10-13 8:31 ` Blue Swirl
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:48 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Adds pci id constants which will be used by q35.
>
> [jbaron@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pci_ids.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
No need really to keep PCI_CLASS_SERIAL_SMBUS in the subject and note it
in the commit message, IMHO. But it doesn't really matter.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index 301bf1c..4017eb7 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -106,6 +106,7 @@
> #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
> #define PCI_DEVICE_ID_INTEL_82801D 0x24CD
> #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
> +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
> #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
> #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
> #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
2012-10-09 7:48 ` Paolo Bonzini
@ 2012-10-13 8:31 ` Blue Swirl
1 sibling, 0 replies; 65+ messages in thread
From: Blue Swirl @ 2012-10-13 8:31 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, armbru, kraxel
On Tue, Oct 9, 2012 at 3:30 AM, Jason Baron <jbaron@redhat.com> wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Adds pci id constants which will be used by q35.
>
> [jbaron@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pci_ids.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index 301bf1c..4017eb7 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -106,6 +106,7 @@
> #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
> #define PCI_DEVICE_ID_INTEL_82801D 0x24CD
> #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
> +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
In Linux pci_ids.h the ID numbers are kept sorted, so this should be
placed between PCI_DEVICE_ID_INTEL_82801AA_5 and
PCI_DEVICE_ID_INTEL_82801D.
> #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
> #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
> #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
> --
> 1.7.1
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 09/21] pci: Add class 0xc05 as 'SMBus'
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (7 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 08/21] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:49 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 10/21] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
` (11 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
[jbaron@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 1 +
hw/pci_ids.h | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index c457d50..62276ef 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] =
{ 0x0c02, "SSA controller", "ssa"},
{ 0x0c03, "USB controller", "usb"},
{ 0x0c04, "Fibre channel controller", "fibre-channel"},
+ { 0x0c05, "SMBus"},
{ 0, NULL}
};
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 4017eb7..6deeac0 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -31,6 +31,7 @@
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_CLASS_SERIAL_USB 0x0c03
+#define PCI_CLASS_SERIAL_SMBUS 0x0c05
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 09/21] pci: Add class 0xc05 as 'SMBus'
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 09/21] pci: Add class 0xc05 as 'SMBus' Jason Baron
@ 2012-10-09 7:49 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:49 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> [jbaron@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/pci.c | 1 +
> hw/pci_ids.h | 1 +
> 2 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index c457d50..62276ef 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] =
> { 0x0c02, "SSA controller", "ssa"},
> { 0x0c03, "USB controller", "usb"},
> { 0x0c04, "Fibre channel controller", "fibre-channel"},
> + { 0x0c05, "SMBus"},
> { 0, NULL}
> };
>
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index 4017eb7..6deeac0 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -31,6 +31,7 @@
> #define PCI_CLASS_SYSTEM_OTHER 0x0880
>
> #define PCI_CLASS_SERIAL_USB 0x0c03
> +#define PCI_CLASS_SERIAL_SMBUS 0x0c05
>
> #define PCI_CLASS_BRIDGE_HOST 0x0600
> #define PCI_CLASS_BRIDGE_ISA 0x0601
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 10/21] pcie: pass pcie window size to pcie_host_mmcfg_update()
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (8 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 09/21] pci: Add class 0xc05 as 'SMBus' Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:52 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 11/21] pcie: Convert PCIExpressHost to use the QOM Jason Baron
` (10 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pcie_host.c | 21 ++++++++++++---------
hw/pcie_host.h | 8 +++++---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index 28bbe72..e2fd276 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e, uint32_t size)
+int pcie_host_init(PCIExpressHost *e)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->size = size;
- memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
memory_region_del_subregion(get_system_memory(), &e->mmio);
+ memory_region_destroy(&e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
+ uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr)
+ target_phys_addr_t addr,
+ uint32_t size)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr);
+ pcie_host_mmcfg_map(e, addr, size);
}
}
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 0074508..2faa54e 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -39,11 +39,13 @@ struct PCIExpressHost {
MemoryRegion mmio;
};
-int pcie_host_init(PCIExpressHost *e, uint32_t size);
+int pcie_host_init(PCIExpressHost *e);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
+ uint32_t size);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr);
+ target_phys_addr_t addr,
+ uint32_t size);
#endif /* PCIE_HOST_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 10/21] pcie: pass pcie window size to pcie_host_mmcfg_update()
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 10/21] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
@ 2012-10-09 7:52 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:52 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> This allows q35 to pass/set the size of the pcie window in its update routine.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pcie_host.c | 21 ++++++++++++---------
> hw/pcie_host.h | 8 +++++---
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/hw/pcie_host.c b/hw/pcie_host.c
> index 28bbe72..e2fd276 100644
> --- a/hw/pcie_host.c
> +++ b/hw/pcie_host.c
> @@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
> /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
> #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
>
> -int pcie_host_init(PCIExpressHost *e, uint32_t size)
> +int pcie_host_init(PCIExpressHost *e)
> {
> - assert(!(size & (size - 1))); /* power of 2 */
> - assert(size >= PCIE_MMCFG_SIZE_MIN);
> - assert(size <= PCIE_MMCFG_SIZE_MAX);
> e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
> - e->size = size;
> - memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
>
> return 0;
> }
> @@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e)
> {
> if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
> memory_region_del_subregion(get_system_memory(), &e->mmio);
> + memory_region_destroy(&e->mmio);
> e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
> }
> }
>
> -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
> +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
> + uint32_t size)
> {
> + assert(!(size & (size - 1))); /* power of 2 */
> + assert(size >= PCIE_MMCFG_SIZE_MIN);
> + assert(size <= PCIE_MMCFG_SIZE_MAX);
> + e->size = size;
> + memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
> e->base_addr = addr;
> memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
> }
>
> void pcie_host_mmcfg_update(PCIExpressHost *e,
> int enable,
> - target_phys_addr_t addr)
> + target_phys_addr_t addr,
> + uint32_t size)
> {
> pcie_host_mmcfg_unmap(e);
> if (enable) {
> - pcie_host_mmcfg_map(e, addr);
> + pcie_host_mmcfg_map(e, addr, size);
> }
> }
> diff --git a/hw/pcie_host.h b/hw/pcie_host.h
> index 0074508..2faa54e 100644
> --- a/hw/pcie_host.h
> +++ b/hw/pcie_host.h
> @@ -39,11 +39,13 @@ struct PCIExpressHost {
> MemoryRegion mmio;
> };
>
> -int pcie_host_init(PCIExpressHost *e, uint32_t size);
> +int pcie_host_init(PCIExpressHost *e);
> void pcie_host_mmcfg_unmap(PCIExpressHost *e);
> -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
> +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
> + uint32_t size);
These two functions perhaps could be made static, but it can be done in
a separate patch.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> void pcie_host_mmcfg_update(PCIExpressHost *e,
> int enable,
> - target_phys_addr_t addr);
> + target_phys_addr_t addr,
> + uint32_t size);
>
> #endif /* PCIE_HOST_H */
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 11/21] pcie: Convert PCIExpressHost to use the QOM.
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (9 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 10/21] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:52 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 12/21] q35: Introduce q35 pc based chipset emulator Jason Baron
` (9 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Let's use PCIExpressHost with QOM.
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pcie_host.c | 14 ++++++++++++++
hw/pcie_host.h | 4 ++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2fd276..027ba05 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -145,3 +145,17 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
pcie_host_mmcfg_map(e, addr, size);
}
}
+
+static const TypeInfo pcie_host_type_info = {
+ .name = TYPE_PCIE_HOST_BRIDGE,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .abstract = true,
+ .instance_size = sizeof(PCIExpressHost),
+};
+
+static void pcie_host_register_types(void)
+{
+ type_register_static(&pcie_host_type_info);
+}
+
+type_init(pcie_host_register_types)
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 2faa54e..2494c71 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -24,6 +24,10 @@
#include "pci_host.h"
#include "memory.h"
+#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
+#define PCIE_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+
struct PCIExpressHost {
PCIHostState pci;
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 11/21] pcie: Convert PCIExpressHost to use the QOM.
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 11/21] pcie: Convert PCIExpressHost to use the QOM Jason Baron
@ 2012-10-09 7:52 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:52 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> Let's use PCIExpressHost with QOM.
>
> Acked-by: Andreas Färber <afaerber@suse.de>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pcie_host.c | 14 ++++++++++++++
> hw/pcie_host.h | 4 ++++
> 2 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pcie_host.c b/hw/pcie_host.c
> index e2fd276..027ba05 100644
> --- a/hw/pcie_host.c
> +++ b/hw/pcie_host.c
> @@ -145,3 +145,17 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> pcie_host_mmcfg_map(e, addr, size);
> }
> }
> +
> +static const TypeInfo pcie_host_type_info = {
> + .name = TYPE_PCIE_HOST_BRIDGE,
> + .parent = TYPE_PCI_HOST_BRIDGE,
> + .abstract = true,
> + .instance_size = sizeof(PCIExpressHost),
> +};
> +
> +static void pcie_host_register_types(void)
> +{
> + type_register_static(&pcie_host_type_info);
> +}
> +
> +type_init(pcie_host_register_types)
> diff --git a/hw/pcie_host.h b/hw/pcie_host.h
> index 2faa54e..2494c71 100644
> --- a/hw/pcie_host.h
> +++ b/hw/pcie_host.h
> @@ -24,6 +24,10 @@
> #include "pci_host.h"
> #include "memory.h"
>
> +#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
> +#define PCIE_HOST_BRIDGE(obj) \
> + OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
> +
> struct PCIExpressHost {
> PCIHostState pci;
>
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 12/21] q35: Introduce q35 pc based chipset emulator
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (10 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 11/21] pcie: Convert PCIExpressHost to use the QOM Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-11 14:47 ` Michael S. Tsirkin
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 13/21] q35: Re-base q35 Jason Baron
` (8 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
pc q35 based chipset emulator to support pci express natively.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 315 ++++++++++++++++++++
hw/acpi_ich9.h | 53 ++++
hw/pc_q35.c | 378 ++++++++++++++++++++++++
hw/pci_ids.h | 14 +
hw/q35.c | 877 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/q35.h | 272 ++++++++++++++++++
hw/q35_smbus.c | 154 ++++++++++
7 files changed, 2063 insertions(+), 0 deletions(-)
create mode 100644 hw/acpi_ich9.c
create mode 100644 hw/acpi_ich9.h
create mode 100644 hw/pc_q35.c
create mode 100644 hw/q35.c
create mode 100644 hw/q35.h
create mode 100644 hw/q35_smbus.c
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
new file mode 100644
index 0000000..59c0807
--- /dev/null
+++ b/hw/acpi_ich9.c
@@ -0,0 +1,315 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "acpi.h"
+
+#include "q35.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define ICH9_DEBUG(fmt, ...) \
+do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
+#else
+#define ICH9_DEBUG(fmt, ...) do { } while (0)
+#endif
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val);
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
+
+static void pm_update_sci(ICH9_LPCPmRegs *pm)
+{
+ int sci_level, pm1a_sts;
+
+ pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+
+ sci_level = (((pm1a_sts & pm->pm1a.en) &
+ (ACPI_BITMASK_RT_CLOCK_ENABLE |
+ ACPI_BITMASK_POWER_BUTTON_ENABLE |
+ ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
+ ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ qemu_set_irq(pm->irq, sci_level);
+
+ /* schedule a timer interruption if needed */
+ acpi_pm_tmr_update(&pm->tmr,
+ (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
+ !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
+}
+
+static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
+{
+ ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
+ pm_update_sci(pm);
+}
+
+static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+ acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
+ break;
+ default:
+ break;
+ }
+
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val = 0;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+ val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_STS:
+ acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
+ pm_update_sci(pm);
+ break;
+ case ICH9_PMIO_PM1_EN:
+ pm->pm1a.en = val;
+ pm_update_sci(pm);
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
+ break;
+ default:
+ pm_ioport_write_fallback(opaque, addr, 2, val);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_STS:
+ val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ break;
+ case ICH9_PMIO_PM1_EN:
+ val = pm->pm1a.en;
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ val = pm->pm1_cnt.cnt;
+ break;
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 2);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_SMI_EN:
+ pm->smi_en = val;
+ break;
+ default:
+ pm_ioport_write_fallback(opaque, addr, 4, val);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_TMR:
+ val = acpi_pm_tmr_get(&pm->tmr);
+ break;
+ case ICH9_PMIO_SMI_EN:
+ val = pm->smi_en;
+ break;
+
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 4);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val)
+ {
+ int subsize = (len == 4) ? 2 : 1;
+ IOPortWriteFunc *ioport_write =
+ (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
+
+ int i;
+
+ for (i = 0; i < len; i += subsize) {
+ ioport_write(opaque, addr, val);
+ val >>= 8 * subsize;
+ }
+}
+
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
+{
+ int subsize = (len == 4) ? 2 : 1;
+ IOPortReadFunc *ioport_read =
+ (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
+
+ uint32_t val;
+ int i;
+
+ val = 0;
+ for (i = 0; i < len; i += subsize) {
+ val <<= 8 * subsize;
+ val |= ioport_read(opaque, addr);
+ }
+
+ return val;
+}
+
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
+{
+ ICH9_DEBUG("to 0x%x\n", pm_io_base);
+
+ assert((pm_io_base & ICH9_PMIO_MASK) == 0);
+
+ if (pm->pm_io_base != 0) {
+ isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
+ }
+
+ /* don't map at 0 */
+ if (pm_io_base == 0) {
+ return;
+ }
+
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
+
+ pm->pm_io_base = pm_io_base;
+ acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
+}
+
+static int ich9_pm_post_load(void *opaque, int version_id)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t pm_io_base = pm->pm_io_base;
+ pm->pm_io_base = 0;
+ ich9_pm_iospace_update(pm, pm_io_base);
+ return 0;
+}
+
+#define VMSTATE_GPE_ARRAY(_field, _state) \
+ { \
+ .name = (stringify(_field)), \
+ .version_id = 0, \
+ .num = ICH9_PMIO_GPE0_LEN, \
+ .info = &vmstate_info_uint8, \
+ .size = sizeof(uint8_t), \
+ .flags = VMS_ARRAY | VMS_POINTER, \
+ .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
+ }
+
+const VMStateDescription vmstate_ich9_pm = {
+ .name = "ich9_pm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = ich9_pm_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
+ VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
+ VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
+ VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pm_reset(void *opaque)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ ich9_pm_iospace_update(pm, 0);
+
+ acpi_pm1_evt_reset(&pm->pm1a);
+ acpi_pm1_cnt_reset(&pm->pm1_cnt);
+ acpi_pm_tmr_reset(&pm->tmr);
+ acpi_gpe_reset(&pm->gpe0);
+
+ pm_update_sci(pm);
+}
+
+static void pm_powerdown(void *opaque, int irq, int power_failing)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
+ ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
+
+ acpi_pm1_evt_power_down(pm1a, tmr);
+}
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
+{
+ acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
+ acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
+ acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
+
+ pm->irq = sci_irq;
+ qemu_register_reset(pm_reset, pm);
+ qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
+}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
new file mode 100644
index 0000000..f55c0e9
--- /dev/null
+++ b/hw/acpi_ich9.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU GMCH/ICH9 LPC PM Emulation
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_ACPI_ICH9_H
+#define HW_ACPI_ICH9_H
+
+#include "acpi.h"
+
+typedef struct ICH9_LPCPmRegs {
+ ACPIPM1EVT pm1a;
+
+ /*
+ * In ich9 spec says that pm1_cnt register is 32bit width and
+ * that the upper 16bits are reserved and unused.
+ * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
+ */
+ ACPIPM1CNT pm1_cnt;
+
+ ACPIPMTimer tmr;
+
+ ACPIGPE gpe0;
+
+ uint32_t smi_en;
+ uint32_t smi_sts;
+
+ qemu_irq irq; /* SCI */
+
+ uint32_t pm_io_base;
+} ICH9_LPCPmRegs;
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm,
+ qemu_irq sci_irq, qemu_irq cmos_s3_resume);
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base);
+extern const VMStateDescription vmstate_ich9_pm;
+
+#endif /* HW_ACPI_ICH9_H */
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 0000000..4f75d97
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,378 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2009, 2010
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+#include "hw.h"
+#include "arch_init.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "ioh3420.h"
+#include "xio3130_upstream.h"
+#include "xio3130_downstream.h"
+#include "block.h"
+#include "blockdev.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"
+#include "ide.h"
+#include "usb-uhci.h"
+
+#include "q35.h"
+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS 6
+
+#define I21154_REV 0x05
+#define I21154_PI 0x00
+
+static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
+{
+ const PCIP2PBridgeInit init = {
+ .bus = bus,
+ .devfn = devfn,
+ .multifunction = multifunction,
+
+ .bus_name = bus_name,
+ .map_irq = pci_swizzle_map_irq_fn,
+ };
+ const PCIP2PBridgeProp prop = {
+ .vendor_id = PCI_VENDOR_ID_DEC,
+ .device_id = PCI_DEVICE_ID_DEC_21154,
+ .revision_id = I21154_REV,
+ .prog_interface = I21154_PI,
+ };
+ return pci_p2pbr_create_simple(&init, &prop);
+}
+
+static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
+{
+ uint8_t dev;
+ uint8_t sec_bus;
+ uint8_t port = 0;
+ uint8_t chassis = 0;
+ uint16_t slot = 0;
+ uint8_t upstream_port;
+ PCIESlot *s;
+ uint8_t fn;
+ PCIESlot *root_port;
+ PCIBus *root_port_bus;
+ char buf[16];
+
+ /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
+ of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
+#define Q35_P2P_BRDIGE_DEV_BASE 28
+#define Q35_P2P_BRDIGE_DEV_MAX 32
+#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
+ for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
+ PCIBridge *br;
+ sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+ }
+
+ /* PCIe root port b0:d1:f0 in GMCH.
+ * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
+ */
+ sec_bus = 32;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+
+
+ /* more slots. ICH9 doesn't have those, but many slots are wanted. */
+//#define Q35_MANY_SLOTS
+#undef Q35_MANY_SLOTS
+
+#ifdef Q35_MANY_SLOTS
+#define Q35_NR_ROOTPORT 6
+#define Q35_NR_UPSTREAM 8
+#define Q35_NR_DOWNSTREAM 16
+#else
+#define Q35_NR_ROOTPORT 1
+#define Q35_NR_UPSTREAM 1
+#define Q35_NR_DOWNSTREAM 1
+#endif
+
+ /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
+ for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
+ sec_bus++;
+ port++;
+ slot++;
+
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ }
+
+ /* PCIe root port b0:d24:f0 */
+ sec_bus++;
+ port++;
+ slot++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
+
+ /* 8 * 16 = 128 slots */
+ upstream_port = 0;
+ for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
+ PCIEPort *upstream;
+ PCIBus *upstream_bus;
+ uint16_t downstream_port;
+
+ uint8_t ds_dev_max;
+ uint8_t ds_dev;
+ uint8_t ds_fn_max;
+ uint8_t ds_fn;
+
+ /* PCIe upstream port d0:f[0-7] */
+ sec_bus++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
+ true, buf, pci_swizzle_map_irq_fn,
+ upstream_port);
+
+ upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
+ upstream_port++;
+
+ /* PCIe downstream port */
+ downstream_port = 0;
+ ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
+ ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
+
+ for (ds_dev = 0; ds_dev <= ds_dev_max &&
+ downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
+ for (ds_fn = 0; ds_fn <= ds_fn_max &&
+ downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
+ sec_bus++;
+ slot++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+
+ xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
+ true, buf, pci_swizzle_map_irq_fn,
+ downstream_port, chassis, slot);
+ downstream_port++;
+ }
+ }
+ }
+
+ /* PCIe root port b0:d28:f[0-6] in ICH9.
+ * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
+ * for them.
+ */
+ for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
+ sec_bus++;
+ port++;
+ slot++;
+
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
+ buf, pci_swizzle_map_irq_fn,
+ port, chassis, slot);
+ }
+}
+
+static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
+ DeviceState **gmch_host_p,
+ PCIBus **host_bus_p, PCIBus **pci_bus_p,
+ PCIDevice **lpc_p)
+{
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+ PCIBus *pci_bus;
+
+ PCIDevice *gmch_state;
+ PCIDevice *lpc;
+
+ /* create pci host bus */
+ host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
+ gmch_state = gmch_init(gmch_host, host_bus);
+
+ /* create conventional pci bus: pcie2pci bridge */
+ pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
+ ICH9_D2P_BRIDGE_FUNC),
+ ICH9_D2P_SECONDARY_DEFAULT);
+
+ /* create child pci/pcie buses */
+ pc_q35_bridge_init(host_bus, pci_bus);
+
+ /* create ISA bus */
+ lpc = gmch_lpc_init(gmch_host, host_bus);
+
+ *gmch_host_p = gmch_host;
+ *host_bus_p = host_bus;
+ *pci_bus_p = pci_bus;
+ *lpc_p = lpc;
+}
+
+static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
+ DeviceState *gmch_host,
+ PCIBus *host_bus, PCIBus *pci_bus,
+ PCIDevice *lpc)
+{
+ qemu_irq *cmos_s3;
+ PCIDevice *ahci;
+ DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
+
+ /* connect pm stuff to lpc */
+ cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
+ ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
+
+ /* ahci and SATA device */
+ ide_drive_get(hd, MAX_SATA_PORTS);
+ ahci = pci_create_simple_multifunction(host_bus,
+ PCI_DEVFN(ICH9_SATA1_DEV,
+ ICH9_SATA1_FUNC),
+ true, "ich9-ahci");
+ pci_ahci_ide_create_devs(ahci, hd);
+ idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
+ idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
+
+ if (usb_enabled) {
+ /* Should we create 6 UHCI according to ich9 spec? */
+ pci_create_simple_multifunction(
+ host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
+ true, "ich9-usb-uhci1");
+ /* XXX: EHCI */
+ }
+
+ /* TODO: Populate SPD eeprom data. */
+ smbus_eeprom_init(ich9_smb_init(host_bus,
+ PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
+ 0xb100),
+ 8, NULL, 0);
+}
+
+/* PC hardware initialisation */
+static void pc_q35_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
+{
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+ PCIBus *pci_bus;
+ PCIDevice *lpc;
+ qemu_irq *isa_irq;
+ IsaIrqState *isa_irq_state;
+ BusState *idebus[MAX_SATA_PORTS];
+ ISADevice *rtc_state;
+ MemoryRegion *pci_memory;
+ MemoryRegion *rom_memory;
+ MemoryRegion *ram_memory;
+
+ pc_cpus_init(cpu_model);
+
+ /* FIXME: add kvm clock ? */
+
+ if (ram_size >= 0xe0000000) {
+ above_4g_mem_size = ram_size - 0xe0000000;
+ below_4g_mem_size = 0xe0000000;
+ } else {
+ above_4g_mem_size = 0;
+ below_4g_mem_size = ram_size;
+ }
+
+ /* pci enabled */
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+ rom_memory = pci_memory;
+
+ /* allocate ram and load rom/bios */
+ pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+
+ /* irq lines */
+ isa_irq = pc_isa_irq(&isa_irq_state);
+ ioapic_init(isa_irq_state);
+
+ pc_q35_init_early(isa_irq, isa_irq_state,
+ &gmch_host, &host_bus, &pci_bus, &lpc);
+ isa_bus_irqs(isa_irq);
+ pc_register_ferr_irq(isa_get_irq(13));
+
+ /* init basic PC hardware */
+ pc_basic_device_init(isa_irq, &rtc_state, false);
+
+ pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
+
+ pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
+ idebus[0], idebus[1], rtc_state);
+
+ /* the rest devices to which pci devfn is automatically assigned */
+ pc_vga_init(host_bus);
+ audio_init(isa_irq, pci_bus);
+ pc_nic_init(pci_bus);
+ pc_pci_device_init(pci_bus);
+}
+
+static QEMUMachine pc_q35_machine = {
+ .name = "pc_q35",
+ .desc = "Q35 chipset PC",
+ .init = pc_q35_init,
+ .max_cpus = 255,
+};
+
+static void pc_q35_machine_init(void)
+{
+ qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 6deeac0..50744dd 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -36,6 +36,7 @@
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_PCI 0x0604
+#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
@@ -115,6 +116,17 @@
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
+
+#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
+
#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934
#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935
#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936
@@ -125,6 +137,8 @@
#define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
diff --git a/hw/q35.c b/hw/q35.c
new file mode 100644
index 0000000..1776ac3
--- /dev/null
+++ b/hw/q35.c
@@ -0,0 +1,877 @@
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ * Copyright (c) 2009, 2010, 2011
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on piix_pci.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+
+
+struct ICH9_LPCState;
+
+typedef struct ICH9_LPCIrqState {
+ struct ICH9_LPCState *lpc;
+ qemu_irq *pic;
+ qemu_irq *ioapic;
+} ICH9_LPCIrqState;
+
+typedef struct GMCH_PCIHost {
+ PCIExpressHost host;
+
+ PCIDevice *dev;
+ ICH9_LPCIrqState irq_state;
+} GMCH_PCIHost;
+
+typedef struct GMCH_PCIState {
+ PCIDevice d;
+ /*
+ * GMCH_PCIHost *gmch_host;
+ * In order to get GMCH_PCIHost
+ * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+ */
+
+ PAM pam;
+} GMCH_PCIState;
+
+typedef struct ICH9_LPCState {
+ /* ICH9 LPC PCI to ISA bridge */
+ PCIDevice d;
+
+ /* (pci device, intx) -> pirq
+ * In real chipset case, the unused slots are never used
+ * as ICH9 supports only D25-D32 irq routing.
+ * On the other hand in qemu case, any slot/function can be populated
+ * via command line option.
+ * So fallback interrupt routing for any devices in any slots is necessary.
+ */
+ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+
+ APMState apm;
+ ICH9_LPCPmRegs pm;
+ uint32_t sci_level; /* track sci level */
+
+ /* 10.1 Chipset Configuration registers(Memory Space)
+ which is pointed by RCBA */
+ uint8_t chip_config[ICH9_CC_SIZE];
+ int rbca_index;
+} ICH9_LPCState;
+
+
+/****************************************************************************
+ * GMCH PCI host
+ */
+/* ich9 irq */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
+static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
+
+static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
+{
+ SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
+ PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
+ PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
+ return DO_UPCAST(GMCH_PCIHost, host, pcie);
+}
+
+static int gmch_pcihost_initfn(SysBusDevice *dev)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
+
+ pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
+ pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
+
+ if (pcie_host_init(&s->host) < 0) {
+ abort();
+ }
+
+ return 0;
+}
+
+static SysBusDeviceInfo gmch_pcihost_info = {
+ .init = gmch_pcihost_initfn,
+ .qdev.name = "gmch-pcihost",
+ .qdev.size = sizeof(GMCH_PCIHost),
+ .qdev.no_user = 1,
+ .qdev.props = (Property[]) {
+ {
+ .name = "MCFG",
+ .info = &qdev_prop_uint64,
+ .offset = offsetof(GMCH_PCIHost, host.base_addr),
+ .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
+ },
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+/* host bridge */
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic)
+{
+ DeviceState *dev;
+ GMCH_PCIHost *s;
+ PCIBus *b;
+
+ dev = qdev_create(NULL, "gmch-pcihost");
+ s = gmch_pcihost_from_qdev(dev);
+ s->irq_state.pic = pic;
+ s->irq_state.ioapic = ioapic;
+
+ b = pci_bus_new(dev, "pcie.0", 0);
+ pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
+ ICH9_LPC_NB_PIRQS);
+ s->host.pci.bus = b;
+ qdev_init_nofail(dev);
+
+ *gmch_hostp = dev;
+ return b;
+}
+
+
+/****************************************************************************
+ * GMCH
+ */
+static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
+{
+ return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
+}
+
+/* PCIE MMCFG */
+static void gmch_update_pciexbar(GMCH_PCIState *gs)
+{
+ PCIDevice *pci_dev = &gs->d;
+ BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+ DeviceState *qdev = bus->parent;
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
+
+ uint64_t pciexbar;
+ int enable;
+ uint64_t addr;
+ uint64_t addr_mask;
+ uint32_t length;
+
+ pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
+ enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
+
+ addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
+ switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
+ length = 256 * 1024 * 1024;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
+ length = 128 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
+ GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
+ length = 64 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
+ default:
+ enable = 0;
+ length = 0;
+ abort();
+ break;
+ }
+ addr = pciexbar & addr_mask;
+
+ pcie_host_mmcfg_update(&s->host, enable, addr, length);
+}
+
+/* PAM */
+static void gmch_update_pam(GMCH_PCIState *gs)
+{
+ int i;
+ for (i = 0; i <= PAM_IDX_MAX; i++) {
+ pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
+ }
+}
+
+/* SMRAM */
+static void gmch_update_smram(GMCH_PCIState *gs)
+{
+ smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+ GMCH_PCIState *gs = arg;
+ smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ /* XXX: implement SMRAM.D_LOCK */
+ pci_default_write_config(d, address, val, len);
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
+ GMCH_HOST_BRIDGE_PAM_SIZE)) {
+ gmch_update_pam(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
+ gmch_update_pciexbar(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
+ GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
+ gmch_update_smram(gs);
+ }
+}
+
+static void gmch_update(GMCH_PCIState *gs)
+{
+ gmch_update_pciexbar(gs);
+ gmch_update_pam(gs);
+ gmch_update_smram(gs);
+}
+
+static int gmch_post_load(void *opaque, int version_id)
+{
+ GMCH_PCIState *gs = opaque;
+ gmch_update(gs);
+ return 0;
+}
+
+static const VMStateDescription vmstate_gmch = {
+ .name = "gmch",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = gmch_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
+ VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void gmch_reset(DeviceState *qdev)
+{
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+
+ d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
+
+ gmch_update(gs);
+}
+
+static int gmch_initfn(PCIDevice *d)
+{
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
+ pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+
+ cpu_smm_register(&gmch_set_smm, gs);
+ pam_init_memory_mappings(&gs->pam);
+
+ return 0;
+}
+
+static PCIDeviceInfo gmch_info = {
+ .qdev.name = "gmch",
+ .qdev.desc = "Host bridge",
+ .qdev.size = sizeof(GMCH_PCIState),
+ .qdev.vmsd = &vmstate_gmch,
+ .qdev.no_user = 1,
+ .init = gmch_initfn,
+ .config_write = gmch_write_config,
+ .qdev.reset = gmch_reset,
+};
+
+/* host bridge */
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ PCIDevice *d;
+
+ d = pci_create_simple_multifunction(b, 0, false, "gmch");
+ s->dev = d;
+
+ return d;
+}
+
+/*****************************************************************************/
+/* ICH9 DMI-to-PCI bridge */
+#define I82801ba_SSVID_OFFSET 0x50
+#define I82801ba_SSVID_SVID 0
+#define I82801ba_SSVID_SSID 0
+
+static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
+{
+ const PCIP2PBridgeInit init = {
+ .bus = bus,
+ .devfn = devfn,
+ .multifunction = multifunction,
+
+ .bus_name = bus_name,
+ .map_irq = pci_swizzle_map_irq_fn,
+ };
+ const PCIP2PBridgeProp prop = {
+ .vendor_id = PCI_VENDOR_ID_INTEL,
+ .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
+ .revision_id = ICH9_D2P_A2_REVISION,
+ .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
+
+ .ssvid_cap = I82801ba_SSVID_OFFSET,
+ .svid = I82801ba_SSVID_SVID,
+ .ssid = I82801ba_SSVID_SSID,
+ };
+ return pci_p2pbr_create_simple(&init, &prop);
+}
+
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
+{
+ PCIBridge *br;
+ char buf[16];
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ br = i82801ba11_init(bus, devfn, buf, true);
+ if (br == NULL) {
+ return NULL;
+ }
+ return pci_bridge_get_sec_bus(br);
+}
+
+
+/*****************************************************************************/
+/* ICH9 LPC PCI to ISA bridge */
+
+static void ich9_lpc_reset(DeviceState *qdev);
+
+static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
+{
+ return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
+}
+
+/* chipset configuration register
+ * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
+ * are used.
+ * Although it's not pci configuration space, it's little endian as Intel.
+ */
+
+static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
+{
+ int intx;
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
+ }
+}
+
+static void ich9_cc_update(ICH9_LPCState *lpc)
+{
+ int slot;
+ int reg_offset;
+ int intx;
+
+ /* D{25 - 31}IR, but D30IR is read only to 0. */
+ for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
+ if (slot != 30) {
+ ich9_cc_update_ir(lpc->irr[slot],
+ lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+ }
+ }
+
+ /*
+ * D30: DMI2PCI bridge
+ * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
+ * are connected to pirq lines. Our choice is PIRQ[E-H].
+ * INT[A-D] are connected to PIRQ[E-H]
+ */
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ lpc->irr[30][intx] = intx + 4;
+ }
+}
+
+static void ich9_cc_init(ICH9_LPCState *lpc)
+{
+ int slot;
+ int intx;
+
+ /* the default irq routing is arbitrary as long as it matches with
+ * acpi irq routing table.
+ * The one that is incompatible with piix_pci(= bochs) one is
+ * intentionally chosen to let the users know that the different
+ * board is used.
+ *
+ * int[A-D] -> pirq[E-F]
+ * avoid pirq A-D because they are used for pci express port
+ */
+ for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
+ }
+ }
+ ich9_cc_update(lpc);
+}
+
+static void ich9_cc_reset(ICH9_LPCState *lpc)
+{
+ uint8_t *c = lpc->chip_config;
+
+ memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
+
+ pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
+
+ ich9_cc_update(lpc);
+}
+
+static void ich9_cc_addr_len(uint32_t *addr, int *len)
+{
+ *addr &= ICH9_CC_ADDR_MASK;
+ if (*addr + *len >= ICH9_CC_SIZE) {
+ *len = ICH9_CC_SIZE - *addr;
+ }
+}
+
+/* val: little endian */
+static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
+ uint32_t val, int len)
+{
+ ich9_cc_addr_len(&addr, &len);
+ memcpy(lpc->chip_config + addr, &val, len);
+}
+
+/* return value: little endian */
+static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
+{
+ uint32_t val = 0;
+ ich9_cc_addr_len(&addr, &len);
+ memcpy(&val, lpc->chip_config + addr, len);
+ return val;
+}
+
+#define ICH9_CC_MMIO_WRITE(type, len) \
+ static void ich9_cc_mmio_write ## type \
+ (void *opaque, target_phys_addr_t addr, uint32_t val) \
+ { \
+ ich9_cc_write(opaque, addr, val, len); \
+ }
+
+#define ICH9_CC_MMIO_READ(type, len) \
+ static uint32_t ich9_cc_mmio_read ## type \
+ (void *opaque, target_phys_addr_t addr) \
+ { \
+ return ich9_cc_read(opaque, addr, len); \
+ }
+
+ICH9_CC_MMIO_WRITE(b, 1)
+ICH9_CC_MMIO_WRITE(w, 2)
+ICH9_CC_MMIO_WRITE(l, 4)
+
+ICH9_CC_MMIO_READ(b, 1)
+ICH9_CC_MMIO_READ(w, 2)
+ICH9_CC_MMIO_READ(l, 4)
+
+static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
+ ich9_cc_mmio_writeb,
+ ich9_cc_mmio_writew,
+ ich9_cc_mmio_writel,
+};
+
+static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
+ ich9_cc_mmio_readb,
+ ich9_cc_mmio_readw,
+ ich9_cc_mmio_readl,
+};
+
+/* IRQ routing */
+/* */
+static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
+{
+ *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
+ *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
+}
+
+static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
+ int *pic_irq, int *pic_dis)
+{
+ switch (irq_num) {
+ case 0 ... 3: /* A-D */
+ ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + irq_num],
+ pic_irq, pic_dis);
+ return;
+ case 4 ... 7: /* E-H */
+ ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (irq_num - 4)],
+ pic_irq, pic_dis);
+ return;
+ default:
+ break;
+ }
+ abort();
+}
+
+/* pic_irq: i8254 irq 0-15 */
+static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
+{
+ GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int i, pic_level;
+
+ /* The pic level is the logical OR of all the PCI irqs mapped to it */
+ pic_level = 0;
+ for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
+ int tmp_irq;
+ int tmp_dis;
+ ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
+ if (!tmp_dis && pic_irq == tmp_irq) {
+ pic_level |= pci_bus_get_irq_level(s->host.pci.bus, i);
+ }
+ }
+ if (pic_irq == ich9_lpc_sci_irq(lpc)) {
+ pic_level |= lpc->sci_level;
+ }
+
+ qemu_set_irq(irq_state->pic[pic_irq], pic_level);
+}
+
+/* pirq: pirq[A-H] 0-7*/
+static void ich9_lpc_update_by_pirq(ICH9_LPCIrqState *irq_state, int pirq)
+{
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int pic_irq;
+ int pic_dis;
+
+ ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
+ assert(pic_irq < ICH9_LPC_PIC_NUM_PINS);
+ if (pic_dis) {
+ return;
+ }
+
+ ich9_lpc_update_pic(irq_state, pic_irq);
+}
+
+/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
+static int ich9_pirq_to_gsi(int pirq)
+{
+ return pirq + ICH9_LPC_PIC_NUM_PINS;
+}
+
+static int ich9_gsi_to_pirq(int gsi)
+{
+ return gsi - ICH9_LPC_PIC_NUM_PINS;
+}
+
+static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
+{
+ GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int level;
+
+ level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ if (gsi == ich9_lpc_sci_irq(lpc)) {
+ level |= lpc->sci_level;
+ }
+
+ qemu_set_irq(irq_state->ioapic[gsi], level);
+}
+
+/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
+ a given device irq pin. */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+ return irq_state->lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
+}
+
+static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+
+ assert(0 <= pirq);
+ assert(pirq < ICH9_LPC_NB_PIRQS);
+
+ ich9_lpc_update_apic(irq_state, ich9_pirq_to_gsi(pirq));
+ ich9_lpc_update_by_pirq(irq_state, pirq);
+}
+
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
+{
+ switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
+ ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
+ case ICH9_LPC_ACPI_CTRL_9:
+ return 9;
+ case ICH9_LPC_ACPI_CTRL_10:
+ return 10;
+ case ICH9_LPC_ACPI_CTRL_11:
+ return 11;
+ case ICH9_LPC_ACPI_CTRL_20:
+ return 20;
+ case ICH9_LPC_ACPI_CTRL_21:
+ return 21;
+ default:
+ /* reserved */
+ break;
+ }
+ return -1;
+}
+
+static void ich9_set_sci(void *opaque, int irq_num, int level)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int irq;
+
+ assert(irq_num == 0);
+ level = !!level;
+ if (level == lpc->sci_level) {
+ return;
+ }
+ lpc->sci_level = level;
+
+ irq = ich9_lpc_sci_irq(lpc);
+ if (irq < 0) {
+ return;
+ }
+
+ ich9_lpc_update_apic(irq_state, irq);
+ if (irq < ICH9_LPC_PIC_NUM_PINS) {
+ ich9_lpc_update_pic(irq_state, irq);
+ }
+}
+
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
+ qemu_irq cmos_s3)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
+ qemu_irq *sci_irq;
+
+ sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
+ ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3);
+
+ ich9_lpc_reset(&lpc->d.qdev);
+}
+
+/* APM */
+static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
+{
+ ICH9_LPCState *lpc = arg;
+
+ /* ACPI specs 3.0, 4.7.2.5 */
+ acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
+ val == ICH9_APM_ACPI_ENABLE,
+ val == ICH9_APM_ACPI_DISABLE);
+
+ /* SMI_EN = PMBASE + 30. SMI control and enable register */
+ if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ }
+}
+
+/* config:PMBASE */
+static void
+ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
+{
+ uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
+ pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
+
+ ich9_pm_iospace_update(&lpc->pm, pm_io_base);
+}
+
+/* config:RBCA */
+static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
+{
+ uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
+
+ if (rbca_old & ICH9_LPC_RCBA_EN) {
+ cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
+ ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
+ }
+ if (rbca & ICH9_LPC_RCBA_EN) {
+ cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
+ ICH9_CC_SIZE, lpc->rbca_index);
+ }
+}
+
+static int ich9_lpc_post_load(void *opaque, int version_id)
+{
+ ICH9_LPCState *lpc = opaque;
+
+ ich9_lpc_pmbase_update(lpc);
+ ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
+ return 0;
+}
+
+static void ich9_lpc_config_write(PCIDevice *d,
+ uint32_t addr, uint32_t val, int len)
+{
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+
+ pci_default_write_config(d, addr, val, len);
+ if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) {
+ ich9_lpc_pmbase_update(lpc);
+ }
+ if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
+ ich9_lpc_rcba_update(lpc, rbca_old);
+ }
+}
+
+static void ich9_lpc_reset(DeviceState *qdev)
+{
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ for (i = 0; i < 4; i++) {
+ pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
+
+ pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
+ pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
+
+ ich9_cc_reset(lpc);
+
+ ich9_lpc_pmbase_update(lpc);
+ ich9_lpc_rcba_update(lpc, rbca_old);
+
+ lpc->sci_level = 0;
+}
+
+static int ich9_lpc_initfn(PCIDevice *d)
+{
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+
+ isa_bus_new(&d->qdev);
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
+ pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
+
+ pci_set_long(d->wmask + ICH9_LPC_PMBASE,
+ ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
+
+ lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
+ ich9_cc_mmio_write,
+ lpc, DEVICE_LITTLE_ENDIAN);
+
+ ich9_cc_init(lpc);
+ apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
+ return 0;
+}
+
+static const VMStateDescription vmstate_ich9_lpc = {
+ .name = "ICH9LPC",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = ich9_lpc_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(d, ICH9_LPCState),
+ VMSTATE_STRUCT(apm, ICH9_LPCState, 0, vmstate_apm, APMState),
+ VMSTATE_STRUCT(pm, ICH9_LPCState, 0, vmstate_ich9_pm, ICH9_LPCPmRegs),
+ VMSTATE_UINT8_ARRAY(chip_config, ICH9_LPCState, ICH9_CC_SIZE),
+ VMSTATE_UINT32(sci_level, ICH9_LPCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ PCIDevice *d;
+ ICH9_LPCState *lpc;
+
+ d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
+ ICH9_LPC_FUNC),
+ true, "ICH9 LPC");
+ lpc = ich9_lpc_from_pci(d);
+ s->irq_state.lpc = lpc;
+ return &lpc->d;
+}
+
+static PCIDeviceInfo ich9_lpc_info = {
+ .qdev.name = "ICH9 LPC",
+ .qdev.desc = "ICH9 LPC bridge",
+ .qdev.size = sizeof(ICH9_LPCState),
+ .qdev.vmsd = &vmstate_ich9_lpc,
+ .qdev.no_user = 1,
+ .init = ich9_lpc_initfn,
+ .config_write = ich9_lpc_config_write,
+ .qdev.reset = ich9_lpc_reset,
+};
+
+static void q35_register(void)
+{
+ sysbus_register_withprop(&gmch_pcihost_info);
+ pci_qdev_register(&gmch_info);
+ pci_qdev_register(&ich9_lpc_info);
+}
+device_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
new file mode 100644
index 0000000..be2e96b
--- /dev/null
+++ b/hw/q35.h
@@ -0,0 +1,272 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "sysbus.h"
+#include "acpi_ich9.h"
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic);
+
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
+ qemu_irq cmos_s3);
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+
+#define Q35_MASK(bit, ms_bit, ls_bit) \
+((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define GMCH_HOST_BRIDGE "GMCH"
+
+#define GMCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
+#define GMCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
+
+/* D0:F0 configuration space */
+#define GMCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
+
+#define GMCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
+#define GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit 35:28 */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
+
+#define GMCH_HOST_BRIDGE_PAM_NB 7
+#define GMCH_HOST_BRIDGE_PAM_SIZE 7
+#define GMCH_HOST_BRIDGE_PAM0 0x90
+#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
+#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
+#define GMCH_HOST_BRIDGE_PAM1 0x91
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM2 0x92
+#define GMCH_HOST_BRIDGE_PAM3 0x93
+#define GMCH_HOST_BRIDGE_PAM4 0x94
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM5 0x95
+#define GMCH_HOST_BRIDGE_PAM6 0x96
+#define GMCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
+#define GMCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
+#define GMCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
+#define GMCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
+#define GMCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
+
+#define GMCH_HOST_BRDIGE_SMRAM 0x9d
+#define GMCH_HOST_BRDIGE_SMRAM_SIZE 1
+#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
+#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
+
+#define GMCH_HOST_BRIDGE_ESMRAMC 0x9e
+#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
+
+/* D1:F0 PCIE* port*/
+#define GMCH_PCIE_DEV 1
+#define GMCH_PCIE_FUNC 0
+
+/*
+ * ich9 part
+ */
+
+/* ICH9: Chipset Configuration Registers */
+#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
+#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
+
+#define ICH9_CC
+#define ICH9_CC_D28IP 0x310C
+#define ICH9_CC_D28IP_SHIFT 4
+#define ICH9_CC_D28IP_MASK 0xf
+#define ICH9_CC_D28IP_DEFAULT 0x00214321
+#define ICH9_CC_D31IR 0x3140
+#define ICH9_CC_D30IR 0x3142
+#define ICH9_CC_D29IR 0x3144
+#define ICH9_CC_D28IR 0x3146
+#define ICH9_CC_D27IR 0x3148
+#define ICH9_CC_D26IR 0x314C
+#define ICH9_CC_D25IR 0x3150
+#define ICH9_CC_DIR_DEFAULT 0x3210
+#define ICH9_CC_D30IR_DEFAULT 0x0
+#define ICH9_CC_DIR_SHIFT 4
+#define ICH9_CC_DIR_MASK 0x7
+#define ICH9_CC_OIC 0x31FF
+#define ICH9_CC_OIC_AEN 0x1
+
+/* D28:F[0-5] */
+#define ICH9_PCIE_DEV 28
+#define ICH9_PCIE_FUNC_MAX 6
+
+
+/* D29:F0 USB UHCI Controller #1 */
+#define ICH9_USB_UHCI1_DEV 29
+#define ICH9_USB_UHCI1_FUNC 0
+
+/* D30:F0 DMI-to-PCI brdige */
+#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
+#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
+
+#define ICH9_D2P_BRIDGE_DEV 30
+#define ICH9_D2P_BRIDGE_FUNC 0
+
+#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
+
+#define ICH9_D2P_A2_REVISION 0x92
+
+
+/* D31:F1 LPC controller */
+#define ICH9_A2_LPC "ICH9 A2 LPC"
+#define ICH9_A2_LPC_SAVEVM_VERSION 0
+
+#define ICH9_LPC_DEV 31
+#define ICH9_LPC_FUNC 0
+
+#define ICH9_A2_LPC_REVISION 0x2
+#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
+
+#define ICH9_LPC_PMBASE 0x40
+#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
+#define ICH9_LPC_PMBASE_RTE 0x1
+#define ICH9_LPC_PMBASE_DEFAULT 0x1
+#define ICH9_LPC_ACPI_CTRL 0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
+#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
+#define ICH9_LPC_ACPI_CTRL_9 0x0
+#define ICH9_LPC_ACPI_CTRL_10 0x1
+#define ICH9_LPC_ACPI_CTRL_11 0x2
+#define ICH9_LPC_ACPI_CTRL_20 0x4
+#define ICH9_LPC_ACPI_CTRL_21 0x5
+#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
+
+#define ICH9_LPC_PIRQA_ROUT 0x60
+#define ICH9_LPC_PIRQB_ROUT 0x61
+#define ICH9_LPC_PIRQC_ROUT 0x62
+#define ICH9_LPC_PIRQD_ROUT 0x63
+
+#define ICH9_LPC_PIRQE_ROUT 0x68
+#define ICH9_LPC_PIRQF_ROUT 0x69
+#define ICH9_LPC_PIRQG_ROUT 0x6a
+#define ICH9_LPC_PIRQH_ROUT 0x6b
+
+#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
+#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
+#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
+
+#define ICH9_LPC_RCBA 0xf0
+#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
+#define ICH9_LPC_RCBA_EN 0x1
+#define ICH9_LPC_RCBA_DEFAULT 0x0
+
+#define ICH9_LPC_PIC_NUM_PINS 16
+#define ICH9_LPC_IOAPIC_NUM_PINS 24
+
+/* D31:F2 SATA Controller #1 */
+#define ICH9_SATA1_DEV 31
+#define ICH9_SATA1_FUNC 2
+
+/* D30:F1 power management I/O registers
+ offset from the address ICH9_LPC_PMBASE */
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_SIZE 128
+#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
+
+#define ICH9_PMIO_PM1_STS 0x00
+#define ICH9_PMIO_PM1_EN 0x02
+#define ICH9_PMIO_PM1_CNT 0x04
+#define ICH9_PMIO_PM1_TMR 0x08
+#define ICH9_PMIO_GPE0_STS 0x20
+#define ICH9_PMIO_GPE0_EN 0x28
+#define ICH9_PMIO_GPE0_LEN 16
+#define ICH9_PMIO_SMI_EN 0x30
+#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
+#define ICH9_PMIO_SMI_STS 0x34
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE 0x2
+#define ICH9_APM_ACPI_DISABLE 0x3
+
+
+/* D31:F3 SMBus controller */
+#define ICH9_A2_SMB_REVISION 0x02
+#define ICH9_SMB_PI 0x00
+
+#define ICH9_SMB_SMBMBAR0 0x10
+#define ICH9_SMB_SMBMBAR1 0x14
+#define ICH9_SMB_SMBM_BAR 0
+#define ICH9_SMB_SMBM_SIZE (1 << 8)
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_SMB_BASE_BAR 4
+#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
+#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
+#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
+#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
+
+/* D31:F3 SMBus I/O and memory mapped I/O registers */
+#define ICH9_SMB_DEV 31
+#define ICH9_SMB_FUNC 3
+
+#define ICH9_SMB_HST_STS 0x00
+#define ICH9_SMB_HST_CNT 0x02
+#define ICH9_SMB_HST_CMD 0x03
+#define ICH9_SMB_XMIT_SLVA 0x04
+#define ICH9_SMB_HST_D0 0x05
+#define ICH9_SMB_HST_D1 0x06
+#define ICH9_SMB_HOST_BLOCK_DB 0x07
+
+#endif /* HW_Q35_H */
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
new file mode 100644
index 0000000..fe445ac
--- /dev/null
+++ b/hw/q35_smbus.c
@@ -0,0 +1,154 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c, but heavily rewritten.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pm_smbus.h"
+#include "pci.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
+
+#include "q35.h"
+
+typedef struct ICH9_SMBState {
+ PCIDevice dev;
+
+ PMSMBus smb;
+} ICH9_SMBState;
+
+static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
+{
+ return DO_UPCAST(ICH9_SMBState, dev, pci_dev);
+}
+
+static const VMStateDescription vmstate_ich9_smbus = {
+ .name = "ich9_smb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, struct ICH9_SMBState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ smb_ioport_writeb(&s->smb, offset, val);
+ }
+}
+
+static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ return smb_ioport_readb(&s->smb, offset);
+ }
+
+ return 0xff;
+}
+
+static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
+ uint64_t addr, uint64_t size, int type)
+{
+ ICH9_SMBState *s = ich9_pci_to_smb(dev);
+
+ assert(size == ICH9_SMB_SMB_BASE_SIZE);
+ assert(type == PCI_BASE_ADDRESS_SPACE_IO);
+
+ register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
+ register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
+}
+
+static int ich9_smb_initfn(PCIDevice *d)
+{
+ ICH9_SMBState *s = ich9_pci_to_smb(d);
+
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
+
+ pci_set_word(d->wmask + PCI_STATUS,
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+
+ pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
+ pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
+ pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
+
+ /* TODO? D31IP.SMIP in chipset configuration space */
+ pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
+
+ pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+
+ /*
+ * update parameters based on
+ * paralell_hds[0]
+ * serial_hds[0]
+ * serial_hds[0]
+ * fdc
+ *
+ * Is there any OS that depends on them?
+ */
+
+ /* TODO smb_io_base */
+ pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+ /* TODO bar0, bar1: 64bit BAR support*/
+ pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
+ ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
+ &ich9_smb_map_ioport);
+
+ pm_smbus_init(&d->qdev, &s->smb);
+ return 0;
+}
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
+{
+ PCIDevice *d =
+ pci_create_simple_multifunction(bus, devfn, true, "ICH9 SMB");
+ ICH9_SMBState *s = ich9_pci_to_smb(d);
+ return s->smb.smbus;
+}
+
+static PCIDeviceInfo ich9_smb_info = {
+ .qdev.name = "ICH9 SMB",
+ .qdev.desc = "ICH9 SMBUS Bridge",
+ .qdev.size = sizeof(ICH9_SMBState),
+ .qdev.vmsd = &vmstate_ich9_smbus,
+ .qdev.no_user = 1,
+ .init = ich9_smb_initfn,
+};
+
+static void ich9_smb_register(void)
+{
+ pci_qdev_register(&ich9_smb_info);
+}
+
+device_init(ich9_smb_register);
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 12/21] q35: Introduce q35 pc based chipset emulator
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 12/21] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-10-11 14:47 ` Michael S. Tsirkin
0 siblings, 0 replies; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 14:47 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 08, 2012 at 11:30:32PM -0400, Jason Baron wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> pc q35 based chipset emulator to support pci express natively.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Preferable to smash this with the next patch, this split
along historical rather than logical lines
complicates review.
> ---
> hw/acpi_ich9.c | 315 ++++++++++++++++++++
> hw/acpi_ich9.h | 53 ++++
> hw/pc_q35.c | 378 ++++++++++++++++++++++++
> hw/pci_ids.h | 14 +
> hw/q35.c | 877 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/q35.h | 272 ++++++++++++++++++
> hw/q35_smbus.c | 154 ++++++++++
> 7 files changed, 2063 insertions(+), 0 deletions(-)
> create mode 100644 hw/acpi_ich9.c
> create mode 100644 hw/acpi_ich9.h
> create mode 100644 hw/pc_q35.c
> create mode 100644 hw/q35.c
> create mode 100644 hw/q35.h
> create mode 100644 hw/q35_smbus.c
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> new file mode 100644
> index 0000000..59c0807
> --- /dev/null
> +++ b/hw/acpi_ich9.c
> @@ -0,0 +1,315 @@
> +/*
> + * ACPI implementation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +/*
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This is based on acpi.c.
> + */
> +#include "hw.h"
> +#include "pc.h"
> +#include "pci.h"
> +#include "qemu-timer.h"
> +#include "sysemu.h"
> +#include "acpi.h"
> +
> +#include "q35.h"
> +
> +//#define DEBUG
> +
> +#ifdef DEBUG
> +#define ICH9_DEBUG(fmt, ...) \
> +do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
> +#else
> +#define ICH9_DEBUG(fmt, ...) do { } while (0)
> +#endif
> +
> +static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
> + uint32_t val);
> +static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
> +
> +static void pm_update_sci(ICH9_LPCPmRegs *pm)
> +{
> + int sci_level, pm1a_sts;
> +
> + pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
> +
> + sci_level = (((pm1a_sts & pm->pm1a.en) &
> + (ACPI_BITMASK_RT_CLOCK_ENABLE |
> + ACPI_BITMASK_POWER_BUTTON_ENABLE |
> + ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> + ACPI_BITMASK_TIMER_ENABLE)) != 0);
> + qemu_set_irq(pm->irq, sci_level);
> +
> + /* schedule a timer interruption if needed */
> + acpi_pm_tmr_update(&pm->tmr,
> + (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
> + !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
> +}
> +
> +static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
> +{
> + ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
> + pm_update_sci(pm);
> +}
> +
> +static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> + acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
> + break;
> + default:
> + break;
> + }
> +
> + ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
> +}
> +
> +static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t val = 0;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> + val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
> + break;
> + default:
> + val = 0;
> + break;
> + }
> + ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
> + return val;
> +}
> +
> +static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_PM1_STS:
> + acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
> + pm_update_sci(pm);
> + break;
> + case ICH9_PMIO_PM1_EN:
> + pm->pm1a.en = val;
> + pm_update_sci(pm);
> + break;
> + case ICH9_PMIO_PM1_CNT:
> + acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
> + break;
> + default:
> + pm_ioport_write_fallback(opaque, addr, 2, val);
> + break;
> + }
> + ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
> +}
> +
> +static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t val;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_PM1_STS:
> + val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
> + break;
> + case ICH9_PMIO_PM1_EN:
> + val = pm->pm1a.en;
> + break;
> + case ICH9_PMIO_PM1_CNT:
> + val = pm->pm1_cnt.cnt;
> + break;
> + default:
> + val = pm_ioport_read_fallback(opaque, addr, 2);
> + break;
> + }
> + ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
> + return val;
> +}
> +
> +static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_SMI_EN:
> + pm->smi_en = val;
> + break;
> + default:
> + pm_ioport_write_fallback(opaque, addr, 4, val);
> + break;
> + }
> + ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
> +}
> +
> +static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t val;
> +
> + switch (addr & ICH9_PMIO_MASK) {
> + case ICH9_PMIO_PM1_TMR:
> + val = acpi_pm_tmr_get(&pm->tmr);
> + break;
> + case ICH9_PMIO_SMI_EN:
> + val = pm->smi_en;
> + break;
> +
> + default:
> + val = pm_ioport_read_fallback(opaque, addr, 4);
> + break;
> + }
> + ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
> + return val;
> +}
> +
> +static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
> + uint32_t val)
> + {
> + int subsize = (len == 4) ? 2 : 1;
> + IOPortWriteFunc *ioport_write =
> + (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
> +
> + int i;
> +
> + for (i = 0; i < len; i += subsize) {
> + ioport_write(opaque, addr, val);
> + val >>= 8 * subsize;
> + }
> +}
> +
> +static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
> +{
> + int subsize = (len == 4) ? 2 : 1;
> + IOPortReadFunc *ioport_read =
> + (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
> +
> + uint32_t val;
> + int i;
> +
> + val = 0;
> + for (i = 0; i < len; i += subsize) {
> + val <<= 8 * subsize;
> + val |= ioport_read(opaque, addr);
> + }
> +
> + return val;
> +}
> +
> +void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
> +{
> + ICH9_DEBUG("to 0x%x\n", pm_io_base);
> +
> + assert((pm_io_base & ICH9_PMIO_MASK) == 0);
> +
> + if (pm->pm_io_base != 0) {
> + isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
> + }
> +
> + /* don't map at 0 */
> + if (pm_io_base == 0) {
> + return;
> + }
> +
> + register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
> + register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
> + register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
> + register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
> + register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
> + register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
> +
> + pm->pm_io_base = pm_io_base;
> + acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
> +}
> +
> +static int ich9_pm_post_load(void *opaque, int version_id)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t pm_io_base = pm->pm_io_base;
> + pm->pm_io_base = 0;
> + ich9_pm_iospace_update(pm, pm_io_base);
> + return 0;
> +}
> +
> +#define VMSTATE_GPE_ARRAY(_field, _state) \
> + { \
> + .name = (stringify(_field)), \
> + .version_id = 0, \
> + .num = ICH9_PMIO_GPE0_LEN, \
> + .info = &vmstate_info_uint8, \
> + .size = sizeof(uint8_t), \
> + .flags = VMS_ARRAY | VMS_POINTER, \
> + .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
> + }
> +
> +const VMStateDescription vmstate_ich9_pm = {
> + .name = "ich9_pm",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .post_load = ich9_pm_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
> + VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
> + VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
> + VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
> + VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
> + VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
> + VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
> + VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
> + VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void pm_reset(void *opaque)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + ich9_pm_iospace_update(pm, 0);
> +
> + acpi_pm1_evt_reset(&pm->pm1a);
> + acpi_pm1_cnt_reset(&pm->pm1_cnt);
> + acpi_pm_tmr_reset(&pm->tmr);
> + acpi_gpe_reset(&pm->gpe0);
> +
> + pm_update_sci(pm);
> +}
> +
> +static void pm_powerdown(void *opaque, int irq, int power_failing)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
> + ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
> +
> + acpi_pm1_evt_power_down(pm1a, tmr);
> +}
> +
> +void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> +{
> + acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
> + acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
> + acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
> +
> + pm->irq = sci_irq;
> + qemu_register_reset(pm_reset, pm);
> + qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
> +}
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> new file mode 100644
> index 0000000..f55c0e9
> --- /dev/null
> +++ b/hw/acpi_ich9.h
> @@ -0,0 +1,53 @@
> +/*
> + * QEMU GMCH/ICH9 LPC PM Emulation
> + *
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +
> +#ifndef HW_ACPI_ICH9_H
> +#define HW_ACPI_ICH9_H
> +
> +#include "acpi.h"
> +
> +typedef struct ICH9_LPCPmRegs {
> + ACPIPM1EVT pm1a;
> +
> + /*
> + * In ich9 spec says that pm1_cnt register is 32bit width and
> + * that the upper 16bits are reserved and unused.
> + * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
> + */
> + ACPIPM1CNT pm1_cnt;
> +
> + ACPIPMTimer tmr;
> +
> + ACPIGPE gpe0;
> +
> + uint32_t smi_en;
> + uint32_t smi_sts;
> +
> + qemu_irq irq; /* SCI */
> +
> + uint32_t pm_io_base;
> +} ICH9_LPCPmRegs;
> +
> +void ich9_pm_init(ICH9_LPCPmRegs *pm,
> + qemu_irq sci_irq, qemu_irq cmos_s3_resume);
> +void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base);
> +extern const VMStateDescription vmstate_ich9_pm;
> +
> +#endif /* HW_ACPI_ICH9_H */
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> new file mode 100644
> index 0000000..4f75d97
> --- /dev/null
> +++ b/hw/pc_q35.c
> @@ -0,0 +1,378 @@
> +/*
> + * QEMU PC System Emulator
> + *
> + * Copyright (c) 2003-2004 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +/*
> + * Q35 chipset based pc system emulator
> + *
> + * Copyright (c) 2009, 2010
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This is based on pc.c, but heavily modified.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +#include "hw.h"
> +#include "arch_init.h"
> +#include "pc.h"
> +#include "fdc.h"
> +#include "pci.h"
> +#include "pci_bridge.h"
> +#include "pci_p2pbr.h"
> +#include "ioh3420.h"
> +#include "xio3130_upstream.h"
> +#include "xio3130_downstream.h"
> +#include "block.h"
> +#include "blockdev.h"
> +#include "sysemu.h"
> +#include "audio/audio.h"
> +#include "net.h"
> +#include "smbus.h"
> +#include "boards.h"
> +#include "monitor.h"
> +#include "fw_cfg.h"
> +#include "hpet_emul.h"
> +#include "watchdog.h"
> +#include "smbios.h"
> +#include "ide.h"
> +#include "usb-uhci.h"
> +
> +#include "q35.h"
> +
> +/* ICH9 AHCI has 6 ports */
> +#define MAX_SATA_PORTS 6
> +
> +#define I21154_REV 0x05
> +#define I21154_PI 0x00
> +
> +static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> + bool multifunction)
> +{
> + const PCIP2PBridgeInit init = {
> + .bus = bus,
> + .devfn = devfn,
> + .multifunction = multifunction,
> +
> + .bus_name = bus_name,
> + .map_irq = pci_swizzle_map_irq_fn,
> + };
> + const PCIP2PBridgeProp prop = {
> + .vendor_id = PCI_VENDOR_ID_DEC,
> + .device_id = PCI_DEVICE_ID_DEC_21154,
> + .revision_id = I21154_REV,
> + .prog_interface = I21154_PI,
> + };
> + return pci_p2pbr_create_simple(&init, &prop);
> +}
> +
> +static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> +{
> + uint8_t dev;
> + uint8_t sec_bus;
> + uint8_t port = 0;
> + uint8_t chassis = 0;
> + uint16_t slot = 0;
> + uint8_t upstream_port;
> + PCIESlot *s;
> + uint8_t fn;
> + PCIESlot *root_port;
> + PCIBus *root_port_bus;
> + char buf[16];
> +
> + /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
> + of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
> +#define Q35_P2P_BRDIGE_DEV_BASE 28
> +#define Q35_P2P_BRDIGE_DEV_MAX 32
> +#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
> + for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
> + PCIBridge *br;
> + sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
> +
> + snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> + br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
> + }
> +
> + /* PCIe root port b0:d1:f0 in GMCH.
> + * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
> + */
> + sec_bus = 32;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> +
> +
> + /* more slots. ICH9 doesn't have those, but many slots are wanted. */
> +//#define Q35_MANY_SLOTS
> +#undef Q35_MANY_SLOTS
> +
> +#ifdef Q35_MANY_SLOTS
> +#define Q35_NR_ROOTPORT 6
> +#define Q35_NR_UPSTREAM 8
> +#define Q35_NR_DOWNSTREAM 16
> +#else
> +#define Q35_NR_ROOTPORT 1
> +#define Q35_NR_UPSTREAM 1
> +#define Q35_NR_DOWNSTREAM 1
> +#endif
> +
> + /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
> + for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
> + sec_bus++;
> + port++;
> + slot++;
> +
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + }
> +
> + /* PCIe root port b0:d24:f0 */
> + sec_bus++;
> + port++;
> + slot++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
> +
> + /* 8 * 16 = 128 slots */
> + upstream_port = 0;
> + for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
> + PCIEPort *upstream;
> + PCIBus *upstream_bus;
> + uint16_t downstream_port;
> +
> + uint8_t ds_dev_max;
> + uint8_t ds_dev;
> + uint8_t ds_fn_max;
> + uint8_t ds_fn;
> +
> + /* PCIe upstream port d0:f[0-7] */
> + sec_bus++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
> + true, buf, pci_swizzle_map_irq_fn,
> + upstream_port);
> +
> + upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
> + upstream_port++;
> +
> + /* PCIe downstream port */
> + downstream_port = 0;
> + ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
> + ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
> +
> + for (ds_dev = 0; ds_dev <= ds_dev_max &&
> + downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
> + for (ds_fn = 0; ds_fn <= ds_fn_max &&
> + downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
> + sec_bus++;
> + slot++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> +
> + xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
> + true, buf, pci_swizzle_map_irq_fn,
> + downstream_port, chassis, slot);
> + downstream_port++;
> + }
> + }
> + }
> +
> + /* PCIe root port b0:d28:f[0-6] in ICH9.
> + * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
> + * for them.
> + */
> + for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
> + sec_bus++;
> + port++;
> + slot++;
> +
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
> + buf, pci_swizzle_map_irq_fn,
> + port, chassis, slot);
> + }
> +}
> +
> +static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
> + DeviceState **gmch_host_p,
> + PCIBus **host_bus_p, PCIBus **pci_bus_p,
> + PCIDevice **lpc_p)
> +{
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> + PCIBus *pci_bus;
> +
> + PCIDevice *gmch_state;
> + PCIDevice *lpc;
> +
> + /* create pci host bus */
> + host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
> + gmch_state = gmch_init(gmch_host, host_bus);
> +
> + /* create conventional pci bus: pcie2pci bridge */
> + pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
> + ICH9_D2P_BRIDGE_FUNC),
> + ICH9_D2P_SECONDARY_DEFAULT);
> +
> + /* create child pci/pcie buses */
> + pc_q35_bridge_init(host_bus, pci_bus);
> +
> + /* create ISA bus */
> + lpc = gmch_lpc_init(gmch_host, host_bus);
> +
> + *gmch_host_p = gmch_host;
> + *host_bus_p = host_bus;
> + *pci_bus_p = pci_bus;
> + *lpc_p = lpc;
> +}
> +
> +static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
> + DeviceState *gmch_host,
> + PCIBus *host_bus, PCIBus *pci_bus,
> + PCIDevice *lpc)
> +{
> + qemu_irq *cmos_s3;
> + PCIDevice *ahci;
> + DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
> +
> + /* connect pm stuff to lpc */
> + cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
> + ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
> +
> + /* ahci and SATA device */
> + ide_drive_get(hd, MAX_SATA_PORTS);
> + ahci = pci_create_simple_multifunction(host_bus,
> + PCI_DEVFN(ICH9_SATA1_DEV,
> + ICH9_SATA1_FUNC),
> + true, "ich9-ahci");
> + pci_ahci_ide_create_devs(ahci, hd);
> + idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
> + idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
> +
> + if (usb_enabled) {
> + /* Should we create 6 UHCI according to ich9 spec? */
> + pci_create_simple_multifunction(
> + host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
> + true, "ich9-usb-uhci1");
> + /* XXX: EHCI */
> + }
> +
> + /* TODO: Populate SPD eeprom data. */
> + smbus_eeprom_init(ich9_smb_init(host_bus,
> + PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
> + 0xb100),
> + 8, NULL, 0);
> +}
> +
> +/* PC hardware initialisation */
> +static void pc_q35_init(ram_addr_t ram_size,
> + const char *boot_device,
> + const char *kernel_filename,
> + const char *kernel_cmdline,
> + const char *initrd_filename,
> + const char *cpu_model)
> +{
> + ram_addr_t below_4g_mem_size, above_4g_mem_size;
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> + PCIBus *pci_bus;
> + PCIDevice *lpc;
> + qemu_irq *isa_irq;
> + IsaIrqState *isa_irq_state;
> + BusState *idebus[MAX_SATA_PORTS];
> + ISADevice *rtc_state;
> + MemoryRegion *pci_memory;
> + MemoryRegion *rom_memory;
> + MemoryRegion *ram_memory;
> +
> + pc_cpus_init(cpu_model);
> +
> + /* FIXME: add kvm clock ? */
> +
> + if (ram_size >= 0xe0000000) {
> + above_4g_mem_size = ram_size - 0xe0000000;
> + below_4g_mem_size = 0xe0000000;
> + } else {
> + above_4g_mem_size = 0;
> + below_4g_mem_size = ram_size;
> + }
> +
> + /* pci enabled */
> + pci_memory = g_new(MemoryRegion, 1);
> + memory_region_init(pci_memory, "pci", INT64_MAX);
> + rom_memory = pci_memory;
> +
> + /* allocate ram and load rom/bios */
> + pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
> + initrd_filename, below_4g_mem_size, above_4g_mem_size,
> + rom_memory, &ram_memory);
> +
> + /* irq lines */
> + isa_irq = pc_isa_irq(&isa_irq_state);
> + ioapic_init(isa_irq_state);
> +
> + pc_q35_init_early(isa_irq, isa_irq_state,
> + &gmch_host, &host_bus, &pci_bus, &lpc);
> + isa_bus_irqs(isa_irq);
> + pc_register_ferr_irq(isa_get_irq(13));
> +
> + /* init basic PC hardware */
> + pc_basic_device_init(isa_irq, &rtc_state, false);
> +
> + pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
> +
> + pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
> + idebus[0], idebus[1], rtc_state);
> +
> + /* the rest devices to which pci devfn is automatically assigned */
> + pc_vga_init(host_bus);
> + audio_init(isa_irq, pci_bus);
> + pc_nic_init(pci_bus);
> + pc_pci_device_init(pci_bus);
> +}
> +
> +static QEMUMachine pc_q35_machine = {
> + .name = "pc_q35",
> + .desc = "Q35 chipset PC",
> + .init = pc_q35_init,
> + .max_cpus = 255,
> +};
> +
> +static void pc_q35_machine_init(void)
> +{
> + qemu_register_machine(&pc_q35_machine);
> +}
> +
> +machine_init(pc_q35_machine_init);
> diff --git a/hw/pci_ids.h b/hw/pci_ids.h
> index 6deeac0..50744dd 100644
> --- a/hw/pci_ids.h
> +++ b/hw/pci_ids.h
> @@ -36,6 +36,7 @@
> #define PCI_CLASS_BRIDGE_HOST 0x0600
> #define PCI_CLASS_BRIDGE_ISA 0x0601
> #define PCI_CLASS_BRIDGE_PCI 0x0604
> +#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
> #define PCI_CLASS_BRIDGE_OTHER 0x0680
>
> #define PCI_CLASS_COMMUNICATION_OTHER 0x0780
> @@ -115,6 +116,17 @@
> #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
> #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
> #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
> +
> +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
> +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
> +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
> +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
> +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
> +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
> +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
> +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
> +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
> +
> #define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934
> #define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935
> #define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936
> @@ -125,6 +137,8 @@
> #define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
> #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
>
> +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
> +
> #define PCI_VENDOR_ID_XEN 0x5853
> #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
>
> diff --git a/hw/q35.c b/hw/q35.c
> new file mode 100644
> index 0000000..1776ac3
> --- /dev/null
> +++ b/hw/q35.c
> @@ -0,0 +1,877 @@
> +/*
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +/*
> + * QEMU GMCH/ICH9 PCI Bridge Emulation
> + *
> + * Copyright (c) 2009, 2010, 2011
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This is based on piix_pci.c, but heavily modified.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +
> +#include "hw.h"
> +#include "range.h"
> +#include "isa.h"
> +#include "sysbus.h"
> +#include "pc.h"
> +#include "apm.h"
> +#include "apic.h"
> +#include "pci.h"
> +#include "pcie_host.h"
> +#include "pci_bridge.h"
> +#include "pci_p2pbr.h"
> +#include "q35.h"
> +#include "acpi.h"
> +#include "acpi_ich9.h"
> +#include "pam.h"
> +
> +
> +struct ICH9_LPCState;
> +
> +typedef struct ICH9_LPCIrqState {
> + struct ICH9_LPCState *lpc;
> + qemu_irq *pic;
> + qemu_irq *ioapic;
> +} ICH9_LPCIrqState;
> +
> +typedef struct GMCH_PCIHost {
> + PCIExpressHost host;
> +
> + PCIDevice *dev;
> + ICH9_LPCIrqState irq_state;
> +} GMCH_PCIHost;
> +
> +typedef struct GMCH_PCIState {
> + PCIDevice d;
> + /*
> + * GMCH_PCIHost *gmch_host;
> + * In order to get GMCH_PCIHost
> + * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
> + */
> +
> + PAM pam;
> +} GMCH_PCIState;
> +
> +typedef struct ICH9_LPCState {
> + /* ICH9 LPC PCI to ISA bridge */
> + PCIDevice d;
> +
> + /* (pci device, intx) -> pirq
> + * In real chipset case, the unused slots are never used
> + * as ICH9 supports only D25-D32 irq routing.
> + * On the other hand in qemu case, any slot/function can be populated
> + * via command line option.
> + * So fallback interrupt routing for any devices in any slots is necessary.
> + */
> + uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
> +
> + APMState apm;
> + ICH9_LPCPmRegs pm;
> + uint32_t sci_level; /* track sci level */
> +
> + /* 10.1 Chipset Configuration registers(Memory Space)
> + which is pointed by RCBA */
> + uint8_t chip_config[ICH9_CC_SIZE];
> + int rbca_index;
> +} ICH9_LPCState;
> +
> +
> +/****************************************************************************
> + * GMCH PCI host
> + */
> +/* ich9 irq */
> +static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
> +static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
> +static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
> +
> +static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
> +{
> + SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
> + PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
> + PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
> + return DO_UPCAST(GMCH_PCIHost, host, pcie);
> +}
> +
> +static int gmch_pcihost_initfn(SysBusDevice *dev)
> +{
> + GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
> +
> + pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
> + pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
> +
> + if (pcie_host_init(&s->host) < 0) {
> + abort();
> + }
> +
> + return 0;
> +}
> +
> +static SysBusDeviceInfo gmch_pcihost_info = {
> + .init = gmch_pcihost_initfn,
> + .qdev.name = "gmch-pcihost",
> + .qdev.size = sizeof(GMCH_PCIHost),
> + .qdev.no_user = 1,
> + .qdev.props = (Property[]) {
> + {
> + .name = "MCFG",
> + .info = &qdev_prop_uint64,
> + .offset = offsetof(GMCH_PCIHost, host.base_addr),
> + .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
> + },
> + DEFINE_PROP_END_OF_LIST(),
> + },
> +};
> +
> +/* host bridge */
> +PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> + qemu_irq *pic, qemu_irq *ioapic)
> +{
> + DeviceState *dev;
> + GMCH_PCIHost *s;
> + PCIBus *b;
> +
> + dev = qdev_create(NULL, "gmch-pcihost");
> + s = gmch_pcihost_from_qdev(dev);
> + s->irq_state.pic = pic;
> + s->irq_state.ioapic = ioapic;
> +
> + b = pci_bus_new(dev, "pcie.0", 0);
> + pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
> + ICH9_LPC_NB_PIRQS);
> + s->host.pci.bus = b;
> + qdev_init_nofail(dev);
> +
> + *gmch_hostp = dev;
> + return b;
> +}
> +
> +
> +/****************************************************************************
> + * GMCH
> + */
> +static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
> +{
> + return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
> +}
> +
> +/* PCIE MMCFG */
> +static void gmch_update_pciexbar(GMCH_PCIState *gs)
> +{
> + PCIDevice *pci_dev = &gs->d;
> + BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
> + DeviceState *qdev = bus->parent;
> + GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
> +
> + uint64_t pciexbar;
> + int enable;
> + uint64_t addr;
> + uint64_t addr_mask;
> + uint32_t length;
> +
> + pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
> + enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
> +
> + addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
> + switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
> + length = 256 * 1024 * 1024;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
> + length = 128 * 1024 * 1024;
> + addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
> + GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
> + length = 64 * 1024 * 1024;
> + addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
> + break;
> + case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
> + default:
> + enable = 0;
> + length = 0;
> + abort();
> + break;
> + }
> + addr = pciexbar & addr_mask;
> +
> + pcie_host_mmcfg_update(&s->host, enable, addr, length);
> +}
> +
> +/* PAM */
> +static void gmch_update_pam(GMCH_PCIState *gs)
> +{
> + int i;
> + for (i = 0; i <= PAM_IDX_MAX; i++) {
> + pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
> + }
> +}
> +
> +/* SMRAM */
> +static void gmch_update_smram(GMCH_PCIState *gs)
> +{
> + smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
> +}
> +
> +static void gmch_set_smm(int smm, void *arg)
> +{
> + GMCH_PCIState *gs = arg;
> + smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
> +}
> +
> +static void gmch_write_config(PCIDevice *d,
> + uint32_t address, uint32_t val, int len)
> +{
> + GMCH_PCIState *gs = gmch_from_pci(d);
> +
> + /* XXX: implement SMRAM.D_LOCK */
> + pci_default_write_config(d, address, val, len);
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
> + GMCH_HOST_BRIDGE_PAM_SIZE)) {
> + gmch_update_pam(gs);
> + }
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
> + GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
> + gmch_update_pciexbar(gs);
> + }
> +
> + if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
> + GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
> + gmch_update_smram(gs);
> + }
> +}
> +
> +static void gmch_update(GMCH_PCIState *gs)
> +{
> + gmch_update_pciexbar(gs);
> + gmch_update_pam(gs);
> + gmch_update_smram(gs);
> +}
> +
> +static int gmch_post_load(void *opaque, int version_id)
> +{
> + GMCH_PCIState *gs = opaque;
> + gmch_update(gs);
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_gmch = {
> + .name = "gmch",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .post_load = gmch_post_load,
> + .fields = (VMStateField []) {
> + VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
> + VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void gmch_reset(DeviceState *qdev)
> +{
> + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> + GMCH_PCIState *gs = gmch_from_pci(d);
> +
> + pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
> + GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
> +
> + d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
> +
> + gmch_update(gs);
> +}
> +
> +static int gmch_initfn(PCIDevice *d)
> +{
> + GMCH_PCIState *gs = gmch_from_pci(d);
> +
> + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> + pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
> + pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
> + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
> +
> + cpu_smm_register(&gmch_set_smm, gs);
> + pam_init_memory_mappings(&gs->pam);
> +
> + return 0;
> +}
> +
> +static PCIDeviceInfo gmch_info = {
> + .qdev.name = "gmch",
> + .qdev.desc = "Host bridge",
> + .qdev.size = sizeof(GMCH_PCIState),
> + .qdev.vmsd = &vmstate_gmch,
> + .qdev.no_user = 1,
> + .init = gmch_initfn,
> + .config_write = gmch_write_config,
> + .qdev.reset = gmch_reset,
> +};
> +
> +/* host bridge */
> +PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
> +{
> + GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> + PCIDevice *d;
> +
> + d = pci_create_simple_multifunction(b, 0, false, "gmch");
> + s->dev = d;
> +
> + return d;
> +}
> +
> +/*****************************************************************************/
> +/* ICH9 DMI-to-PCI bridge */
> +#define I82801ba_SSVID_OFFSET 0x50
> +#define I82801ba_SSVID_SVID 0
> +#define I82801ba_SSVID_SSID 0
> +
> +static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
> + bool multifunction)
> +{
> + const PCIP2PBridgeInit init = {
> + .bus = bus,
> + .devfn = devfn,
> + .multifunction = multifunction,
> +
> + .bus_name = bus_name,
> + .map_irq = pci_swizzle_map_irq_fn,
> + };
> + const PCIP2PBridgeProp prop = {
> + .vendor_id = PCI_VENDOR_ID_INTEL,
> + .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
> + .revision_id = ICH9_D2P_A2_REVISION,
> + .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
> +
> + .ssvid_cap = I82801ba_SSVID_OFFSET,
> + .svid = I82801ba_SSVID_SVID,
> + .ssid = I82801ba_SSVID_SSID,
> + };
> + return pci_p2pbr_create_simple(&init, &prop);
> +}
> +
> +PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
> +{
> + PCIBridge *br;
> + char buf[16];
> +
> + snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> + br = i82801ba11_init(bus, devfn, buf, true);
> + if (br == NULL) {
> + return NULL;
> + }
> + return pci_bridge_get_sec_bus(br);
> +}
> +
> +
> +/*****************************************************************************/
> +/* ICH9 LPC PCI to ISA bridge */
> +
> +static void ich9_lpc_reset(DeviceState *qdev);
> +
> +static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
> +{
> + return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
> +}
> +
> +/* chipset configuration register
> + * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
> + * are used.
> + * Although it's not pci configuration space, it's little endian as Intel.
> + */
> +
> +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> +{
> + int intx;
> + for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> + irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
> + }
> +}
> +
> +static void ich9_cc_update(ICH9_LPCState *lpc)
> +{
> + int slot;
> + int reg_offset;
> + int intx;
> +
> + /* D{25 - 31}IR, but D30IR is read only to 0. */
> + for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> + if (slot != 30) {
> + ich9_cc_update_ir(lpc->irr[slot],
> + lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> + }
> + }
> +
> + /*
> + * D30: DMI2PCI bridge
> + * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
> + * are connected to pirq lines. Our choice is PIRQ[E-H].
> + * INT[A-D] are connected to PIRQ[E-H]
> + */
> + for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> + lpc->irr[30][intx] = intx + 4;
> + }
> +}
> +
> +static void ich9_cc_init(ICH9_LPCState *lpc)
> +{
> + int slot;
> + int intx;
> +
> + /* the default irq routing is arbitrary as long as it matches with
> + * acpi irq routing table.
> + * The one that is incompatible with piix_pci(= bochs) one is
> + * intentionally chosen to let the users know that the different
> + * board is used.
> + *
> + * int[A-D] -> pirq[E-F]
> + * avoid pirq A-D because they are used for pci express port
> + */
> + for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
> + for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> + lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
> + }
> + }
> + ich9_cc_update(lpc);
> +}
> +
> +static void ich9_cc_reset(ICH9_LPCState *lpc)
> +{
> + uint8_t *c = lpc->chip_config;
> +
> + memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
> +
> + pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
> + pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
> +
> + ich9_cc_update(lpc);
> +}
> +
> +static void ich9_cc_addr_len(uint32_t *addr, int *len)
> +{
> + *addr &= ICH9_CC_ADDR_MASK;
> + if (*addr + *len >= ICH9_CC_SIZE) {
> + *len = ICH9_CC_SIZE - *addr;
> + }
> +}
> +
> +/* val: little endian */
> +static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
> + uint32_t val, int len)
> +{
> + ich9_cc_addr_len(&addr, &len);
> + memcpy(lpc->chip_config + addr, &val, len);
> +}
> +
> +/* return value: little endian */
> +static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
> +{
> + uint32_t val = 0;
> + ich9_cc_addr_len(&addr, &len);
> + memcpy(&val, lpc->chip_config + addr, len);
> + return val;
> +}
> +
> +#define ICH9_CC_MMIO_WRITE(type, len) \
> + static void ich9_cc_mmio_write ## type \
> + (void *opaque, target_phys_addr_t addr, uint32_t val) \
> + { \
> + ich9_cc_write(opaque, addr, val, len); \
> + }
> +
> +#define ICH9_CC_MMIO_READ(type, len) \
> + static uint32_t ich9_cc_mmio_read ## type \
> + (void *opaque, target_phys_addr_t addr) \
> + { \
> + return ich9_cc_read(opaque, addr, len); \
> + }
> +
> +ICH9_CC_MMIO_WRITE(b, 1)
> +ICH9_CC_MMIO_WRITE(w, 2)
> +ICH9_CC_MMIO_WRITE(l, 4)
> +
> +ICH9_CC_MMIO_READ(b, 1)
> +ICH9_CC_MMIO_READ(w, 2)
> +ICH9_CC_MMIO_READ(l, 4)
> +
> +static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
> + ich9_cc_mmio_writeb,
> + ich9_cc_mmio_writew,
> + ich9_cc_mmio_writel,
> +};
> +
> +static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
> + ich9_cc_mmio_readb,
> + ich9_cc_mmio_readw,
> + ich9_cc_mmio_readl,
> +};
> +
> +/* IRQ routing */
> +/* */
> +static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
> +{
> + *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
> + *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
> +}
> +
> +static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
> + int *pic_irq, int *pic_dis)
> +{
> + switch (irq_num) {
> + case 0 ... 3: /* A-D */
> + ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + irq_num],
> + pic_irq, pic_dis);
> + return;
> + case 4 ... 7: /* E-H */
> + ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (irq_num - 4)],
> + pic_irq, pic_dis);
> + return;
> + default:
> + break;
> + }
> + abort();
> +}
> +
> +/* pic_irq: i8254 irq 0-15 */
> +static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
> +{
> + GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
> + ICH9_LPCState *lpc = irq_state->lpc;
> + int i, pic_level;
> +
> + /* The pic level is the logical OR of all the PCI irqs mapped to it */
> + pic_level = 0;
> + for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
> + int tmp_irq;
> + int tmp_dis;
> + ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
> + if (!tmp_dis && pic_irq == tmp_irq) {
> + pic_level |= pci_bus_get_irq_level(s->host.pci.bus, i);
> + }
> + }
> + if (pic_irq == ich9_lpc_sci_irq(lpc)) {
> + pic_level |= lpc->sci_level;
> + }
> +
> + qemu_set_irq(irq_state->pic[pic_irq], pic_level);
> +}
> +
> +/* pirq: pirq[A-H] 0-7*/
> +static void ich9_lpc_update_by_pirq(ICH9_LPCIrqState *irq_state, int pirq)
> +{
> + ICH9_LPCState *lpc = irq_state->lpc;
> + int pic_irq;
> + int pic_dis;
> +
> + ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
> + assert(pic_irq < ICH9_LPC_PIC_NUM_PINS);
> + if (pic_dis) {
> + return;
> + }
> +
> + ich9_lpc_update_pic(irq_state, pic_irq);
> +}
> +
> +/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
> +static int ich9_pirq_to_gsi(int pirq)
> +{
> + return pirq + ICH9_LPC_PIC_NUM_PINS;
> +}
> +
> +static int ich9_gsi_to_pirq(int gsi)
> +{
> + return gsi - ICH9_LPC_PIC_NUM_PINS;
> +}
> +
> +static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
> +{
> + GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
> + ICH9_LPCState *lpc = irq_state->lpc;
> + int level;
> +
> + level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
> + if (gsi == ich9_lpc_sci_irq(lpc)) {
> + level |= lpc->sci_level;
> + }
> +
> + qemu_set_irq(irq_state->ioapic[gsi], level);
> +}
> +
> +/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
> + a given device irq pin. */
> +static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx)
> +{
> + ICH9_LPCIrqState *irq_state = opaque;
> + return irq_state->lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
> +}
> +
> +static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
> +{
> + ICH9_LPCIrqState *irq_state = opaque;
> +
> + assert(0 <= pirq);
> + assert(pirq < ICH9_LPC_NB_PIRQS);
> +
> + ich9_lpc_update_apic(irq_state, ich9_pirq_to_gsi(pirq));
> + ich9_lpc_update_by_pirq(irq_state, pirq);
> +}
> +
> +static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
> +{
> + switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
> + ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
> + case ICH9_LPC_ACPI_CTRL_9:
> + return 9;
> + case ICH9_LPC_ACPI_CTRL_10:
> + return 10;
> + case ICH9_LPC_ACPI_CTRL_11:
> + return 11;
> + case ICH9_LPC_ACPI_CTRL_20:
> + return 20;
> + case ICH9_LPC_ACPI_CTRL_21:
> + return 21;
> + default:
> + /* reserved */
> + break;
> + }
> + return -1;
> +}
> +
> +static void ich9_set_sci(void *opaque, int irq_num, int level)
> +{
> + ICH9_LPCIrqState *irq_state = opaque;
> + ICH9_LPCState *lpc = irq_state->lpc;
> + int irq;
> +
> + assert(irq_num == 0);
> + level = !!level;
> + if (level == lpc->sci_level) {
> + return;
> + }
> + lpc->sci_level = level;
> +
> + irq = ich9_lpc_sci_irq(lpc);
> + if (irq < 0) {
> + return;
> + }
> +
> + ich9_lpc_update_apic(irq_state, irq);
> + if (irq < ICH9_LPC_PIC_NUM_PINS) {
> + ich9_lpc_update_pic(irq_state, irq);
> + }
> +}
> +
> +void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
> + qemu_irq cmos_s3)
> +{
> + GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> + ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
> + qemu_irq *sci_irq;
> +
> + sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
> + ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3);
> +
> + ich9_lpc_reset(&lpc->d.qdev);
> +}
> +
> +/* APM */
> +static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
> +{
> + ICH9_LPCState *lpc = arg;
> +
> + /* ACPI specs 3.0, 4.7.2.5 */
> + acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
> + val == ICH9_APM_ACPI_ENABLE,
> + val == ICH9_APM_ACPI_DISABLE);
> +
> + /* SMI_EN = PMBASE + 30. SMI control and enable register */
> + if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
> + cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
> + }
> +}
> +
> +/* config:PMBASE */
> +static void
> +ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
> +{
> + uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
> + pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
> +
> + ich9_pm_iospace_update(&lpc->pm, pm_io_base);
> +}
> +
> +/* config:RBCA */
> +static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
> +{
> + uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
> +
> + if (rbca_old & ICH9_LPC_RCBA_EN) {
> + cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
> + ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
> + }
> + if (rbca & ICH9_LPC_RCBA_EN) {
> + cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
> + ICH9_CC_SIZE, lpc->rbca_index);
> + }
> +}
> +
> +static int ich9_lpc_post_load(void *opaque, int version_id)
> +{
> + ICH9_LPCState *lpc = opaque;
> +
> + ich9_lpc_pmbase_update(lpc);
> + ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
> + return 0;
> +}
> +
> +static void ich9_lpc_config_write(PCIDevice *d,
> + uint32_t addr, uint32_t val, int len)
> +{
> + ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> + uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
> +
> + pci_default_write_config(d, addr, val, len);
> + if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) {
> + ich9_lpc_pmbase_update(lpc);
> + }
> + if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
> + ich9_lpc_rcba_update(lpc, rbca_old);
> + }
> +}
> +
> +static void ich9_lpc_reset(DeviceState *qdev)
> +{
> + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> + ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> + uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
> + int i;
> +
> + for (i = 0; i < 4; i++) {
> + pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
> + ICH9_LPC_PIRQ_ROUT_DEFAULT);
> + }
> + for (i = 0; i < 4; i++) {
> + pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
> + ICH9_LPC_PIRQ_ROUT_DEFAULT);
> + }
> + pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
> +
> + pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
> + pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
> +
> + ich9_cc_reset(lpc);
> +
> + ich9_lpc_pmbase_update(lpc);
> + ich9_lpc_rcba_update(lpc, rbca_old);
> +
> + lpc->sci_level = 0;
> +}
> +
> +static int ich9_lpc_initfn(PCIDevice *d)
> +{
> + ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> +
> + isa_bus_new(&d->qdev);
> + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> + pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
> + pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
> + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
> +
> + pci_set_long(d->wmask + ICH9_LPC_PMBASE,
> + ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
> +
> + lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
> + ich9_cc_mmio_write,
> + lpc, DEVICE_LITTLE_ENDIAN);
> +
> + ich9_cc_init(lpc);
> + apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_ich9_lpc = {
> + .name = "ICH9LPC",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .post_load = ich9_lpc_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_PCI_DEVICE(d, ICH9_LPCState),
> + VMSTATE_STRUCT(apm, ICH9_LPCState, 0, vmstate_apm, APMState),
> + VMSTATE_STRUCT(pm, ICH9_LPCState, 0, vmstate_ich9_pm, ICH9_LPCPmRegs),
> + VMSTATE_UINT8_ARRAY(chip_config, ICH9_LPCState, ICH9_CC_SIZE),
> + VMSTATE_UINT32(sci_level, ICH9_LPCState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
> +{
> + GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> + PCIDevice *d;
> + ICH9_LPCState *lpc;
> +
> + d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
> + ICH9_LPC_FUNC),
> + true, "ICH9 LPC");
> + lpc = ich9_lpc_from_pci(d);
> + s->irq_state.lpc = lpc;
> + return &lpc->d;
> +}
> +
> +static PCIDeviceInfo ich9_lpc_info = {
> + .qdev.name = "ICH9 LPC",
> + .qdev.desc = "ICH9 LPC bridge",
> + .qdev.size = sizeof(ICH9_LPCState),
> + .qdev.vmsd = &vmstate_ich9_lpc,
> + .qdev.no_user = 1,
> + .init = ich9_lpc_initfn,
> + .config_write = ich9_lpc_config_write,
> + .qdev.reset = ich9_lpc_reset,
> +};
> +
> +static void q35_register(void)
> +{
> + sysbus_register_withprop(&gmch_pcihost_info);
> + pci_qdev_register(&gmch_info);
> + pci_qdev_register(&ich9_lpc_info);
> +}
> +device_init(q35_register);
> diff --git a/hw/q35.h b/hw/q35.h
> new file mode 100644
> index 0000000..be2e96b
> --- /dev/null
> +++ b/hw/q35.h
> @@ -0,0 +1,272 @@
> +/*
> + * q35.h
> + *
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +
> +#ifndef HW_Q35_H
> +#define HW_Q35_H
> +
> +#include "sysbus.h"
> +#include "acpi_ich9.h"
> +
> +PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> + qemu_irq *pic, qemu_irq *ioapic);
> +
> +PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
> +PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
> +PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
> +void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
> + qemu_irq cmos_s3);
> +
> +i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
> +
> +#define Q35_MASK(bit, ms_bit, ls_bit) \
> +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
> +
> +/*
> + * gmch part
> + */
> +
> +/* PCI configuration */
> +#define GMCH_HOST_BRIDGE "GMCH"
> +
> +#define GMCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
> +#define GMCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
> +
> +/* D0:F0 configuration space */
> +#define GMCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
> +
> +#define GMCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit 35:28 */
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
> +#define GMCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
> +
> +#define GMCH_HOST_BRIDGE_PAM_NB 7
> +#define GMCH_HOST_BRIDGE_PAM_SIZE 7
> +#define GMCH_HOST_BRIDGE_PAM0 0x90
> +#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
> +#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
> +#define GMCH_HOST_BRIDGE_PAM1 0x91
> +#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
> +#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
> +#define GMCH_HOST_BRIDGE_PAM2 0x92
> +#define GMCH_HOST_BRIDGE_PAM3 0x93
> +#define GMCH_HOST_BRIDGE_PAM4 0x94
> +#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
> +#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
> +#define GMCH_HOST_BRIDGE_PAM5 0x95
> +#define GMCH_HOST_BRIDGE_PAM6 0x96
> +#define GMCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
> +#define GMCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
> +#define GMCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
> +#define GMCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
> +#define GMCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
> +
> +#define GMCH_HOST_BRDIGE_SMRAM 0x9d
> +#define GMCH_HOST_BRDIGE_SMRAM_SIZE 1
> +#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
> +#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
> +#define GMCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
> +#define GMCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
> +#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
> +#define GMCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
> +#define GMCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
> +#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
> +#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
> +
> +#define GMCH_HOST_BRIDGE_ESMRAMC 0x9e
> +#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
> +#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
> +
> +/* D1:F0 PCIE* port*/
> +#define GMCH_PCIE_DEV 1
> +#define GMCH_PCIE_FUNC 0
> +
> +/*
> + * ich9 part
> + */
> +
> +/* ICH9: Chipset Configuration Registers */
> +#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
> +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
> +
> +#define ICH9_CC
> +#define ICH9_CC_D28IP 0x310C
> +#define ICH9_CC_D28IP_SHIFT 4
> +#define ICH9_CC_D28IP_MASK 0xf
> +#define ICH9_CC_D28IP_DEFAULT 0x00214321
> +#define ICH9_CC_D31IR 0x3140
> +#define ICH9_CC_D30IR 0x3142
> +#define ICH9_CC_D29IR 0x3144
> +#define ICH9_CC_D28IR 0x3146
> +#define ICH9_CC_D27IR 0x3148
> +#define ICH9_CC_D26IR 0x314C
> +#define ICH9_CC_D25IR 0x3150
> +#define ICH9_CC_DIR_DEFAULT 0x3210
> +#define ICH9_CC_D30IR_DEFAULT 0x0
> +#define ICH9_CC_DIR_SHIFT 4
> +#define ICH9_CC_DIR_MASK 0x7
> +#define ICH9_CC_OIC 0x31FF
> +#define ICH9_CC_OIC_AEN 0x1
> +
> +/* D28:F[0-5] */
> +#define ICH9_PCIE_DEV 28
> +#define ICH9_PCIE_FUNC_MAX 6
> +
> +
> +/* D29:F0 USB UHCI Controller #1 */
> +#define ICH9_USB_UHCI1_DEV 29
> +#define ICH9_USB_UHCI1_FUNC 0
> +
> +/* D30:F0 DMI-to-PCI brdige */
> +#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
> +#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
> +
> +#define ICH9_D2P_BRIDGE_DEV 30
> +#define ICH9_D2P_BRIDGE_FUNC 0
> +
> +#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
> +
> +#define ICH9_D2P_A2_REVISION 0x92
> +
> +
> +/* D31:F1 LPC controller */
> +#define ICH9_A2_LPC "ICH9 A2 LPC"
> +#define ICH9_A2_LPC_SAVEVM_VERSION 0
> +
> +#define ICH9_LPC_DEV 31
> +#define ICH9_LPC_FUNC 0
> +
> +#define ICH9_A2_LPC_REVISION 0x2
> +#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
> +
> +#define ICH9_LPC_PMBASE 0x40
> +#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
> +#define ICH9_LPC_PMBASE_RTE 0x1
> +#define ICH9_LPC_PMBASE_DEFAULT 0x1
> +#define ICH9_LPC_ACPI_CTRL 0x44
> +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
> +#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
> +#define ICH9_LPC_ACPI_CTRL_9 0x0
> +#define ICH9_LPC_ACPI_CTRL_10 0x1
> +#define ICH9_LPC_ACPI_CTRL_11 0x2
> +#define ICH9_LPC_ACPI_CTRL_20 0x4
> +#define ICH9_LPC_ACPI_CTRL_21 0x5
> +#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
> +
> +#define ICH9_LPC_PIRQA_ROUT 0x60
> +#define ICH9_LPC_PIRQB_ROUT 0x61
> +#define ICH9_LPC_PIRQC_ROUT 0x62
> +#define ICH9_LPC_PIRQD_ROUT 0x63
> +
> +#define ICH9_LPC_PIRQE_ROUT 0x68
> +#define ICH9_LPC_PIRQF_ROUT 0x69
> +#define ICH9_LPC_PIRQG_ROUT 0x6a
> +#define ICH9_LPC_PIRQH_ROUT 0x6b
> +
> +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
> +#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
> +#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
> +
> +#define ICH9_LPC_RCBA 0xf0
> +#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
> +#define ICH9_LPC_RCBA_EN 0x1
> +#define ICH9_LPC_RCBA_DEFAULT 0x0
> +
> +#define ICH9_LPC_PIC_NUM_PINS 16
> +#define ICH9_LPC_IOAPIC_NUM_PINS 24
> +
> +/* D31:F2 SATA Controller #1 */
> +#define ICH9_SATA1_DEV 31
> +#define ICH9_SATA1_FUNC 2
> +
> +/* D30:F1 power management I/O registers
> + offset from the address ICH9_LPC_PMBASE */
> +
> +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
> +#define ICH9_PMIO_SIZE 128
> +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
> +
> +#define ICH9_PMIO_PM1_STS 0x00
> +#define ICH9_PMIO_PM1_EN 0x02
> +#define ICH9_PMIO_PM1_CNT 0x04
> +#define ICH9_PMIO_PM1_TMR 0x08
> +#define ICH9_PMIO_GPE0_STS 0x20
> +#define ICH9_PMIO_GPE0_EN 0x28
> +#define ICH9_PMIO_GPE0_LEN 16
> +#define ICH9_PMIO_SMI_EN 0x30
> +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
> +#define ICH9_PMIO_SMI_STS 0x34
> +
> +/* FADT ACPI_ENABLE/ACPI_DISABLE */
> +#define ICH9_APM_ACPI_ENABLE 0x2
> +#define ICH9_APM_ACPI_DISABLE 0x3
> +
> +
> +/* D31:F3 SMBus controller */
> +#define ICH9_A2_SMB_REVISION 0x02
> +#define ICH9_SMB_PI 0x00
> +
> +#define ICH9_SMB_SMBMBAR0 0x10
> +#define ICH9_SMB_SMBMBAR1 0x14
> +#define ICH9_SMB_SMBM_BAR 0
> +#define ICH9_SMB_SMBM_SIZE (1 << 8)
> +#define ICH9_SMB_SMB_BASE 0x20
> +#define ICH9_SMB_SMB_BASE_BAR 4
> +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
> +#define ICH9_SMB_HOSTC 0x40
> +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
> +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
> +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
> +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
> +
> +/* D31:F3 SMBus I/O and memory mapped I/O registers */
> +#define ICH9_SMB_DEV 31
> +#define ICH9_SMB_FUNC 3
> +
> +#define ICH9_SMB_HST_STS 0x00
> +#define ICH9_SMB_HST_CNT 0x02
> +#define ICH9_SMB_HST_CMD 0x03
> +#define ICH9_SMB_XMIT_SLVA 0x04
> +#define ICH9_SMB_HST_D0 0x05
> +#define ICH9_SMB_HST_D1 0x06
> +#define ICH9_SMB_HOST_BLOCK_DB 0x07
> +
> +#endif /* HW_Q35_H */
> diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
> new file mode 100644
> index 0000000..fe445ac
> --- /dev/null
> +++ b/hw/q35_smbus.c
> @@ -0,0 +1,154 @@
> +/*
> + * ACPI implementation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +/*
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This is based on acpi.c, but heavily rewritten.
> + */
> +#include "hw.h"
> +#include "pc.h"
> +#include "pm_smbus.h"
> +#include "pci.h"
> +#include "sysemu.h"
> +#include "i2c.h"
> +#include "smbus.h"
> +
> +#include "q35.h"
> +
> +typedef struct ICH9_SMBState {
> + PCIDevice dev;
> +
> + PMSMBus smb;
> +} ICH9_SMBState;
> +
> +static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
> +{
> + return DO_UPCAST(ICH9_SMBState, dev, pci_dev);
> +}
> +
> +static const VMStateDescription vmstate_ich9_smbus = {
> + .name = "ich9_smb",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_PCI_DEVICE(dev, struct ICH9_SMBState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> +{
> + ICH9_SMBState *s = opaque;
> + uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
> +
> + if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
> + uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
> + smb_ioport_writeb(&s->smb, offset, val);
> + }
> +}
> +
> +static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
> +{
> + ICH9_SMBState *s = opaque;
> + uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
> +
> + if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
> + uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
> + return smb_ioport_readb(&s->smb, offset);
> + }
> +
> + return 0xff;
> +}
> +
> +static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
> + uint64_t addr, uint64_t size, int type)
> +{
> + ICH9_SMBState *s = ich9_pci_to_smb(dev);
> +
> + assert(size == ICH9_SMB_SMB_BASE_SIZE);
> + assert(type == PCI_BASE_ADDRESS_SPACE_IO);
> +
> + register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
> + register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
> +}
> +
> +static int ich9_smb_initfn(PCIDevice *d)
> +{
> + ICH9_SMBState *s = ich9_pci_to_smb(d);
> +
> + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> + pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
> +
> + pci_set_word(d->wmask + PCI_STATUS,
> + PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> +
> + pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
> + pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
> + pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
> +
> + /* TODO? D31IP.SMIP in chipset configuration space */
> + pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
> +
> + pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
> +
> + /*
> + * update parameters based on
> + * paralell_hds[0]
> + * serial_hds[0]
> + * serial_hds[0]
> + * fdc
> + *
> + * Is there any OS that depends on them?
> + */
> +
> + /* TODO smb_io_base */
> + pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
> + /* TODO bar0, bar1: 64bit BAR support*/
> + pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
> + ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
> + &ich9_smb_map_ioport);
> +
> + pm_smbus_init(&d->qdev, &s->smb);
> + return 0;
> +}
> +
> +i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
> +{
> + PCIDevice *d =
> + pci_create_simple_multifunction(bus, devfn, true, "ICH9 SMB");
> + ICH9_SMBState *s = ich9_pci_to_smb(d);
> + return s->smb.smbus;
> +}
> +
> +static PCIDeviceInfo ich9_smb_info = {
> + .qdev.name = "ICH9 SMB",
> + .qdev.desc = "ICH9 SMBUS Bridge",
> + .qdev.size = sizeof(ICH9_SMBState),
> + .qdev.vmsd = &vmstate_ich9_smbus,
> + .qdev.no_user = 1,
> + .init = ich9_smb_initfn,
> +};
> +
> +static void ich9_smb_register(void)
> +{
> + pci_qdev_register(&ich9_smb_info);
> +}
> +
> +device_init(ich9_smb_register);
> --
> 1.7.1
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 13/21] q35: Re-base q35
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (11 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 12/21] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 14/21] q35: Suppress SMM BIOS initialization under KVM Jason Baron
` (7 subsequent siblings)
20 siblings, 0 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Rebase q35 - memory api updates, acpi updates, qom, update pci window 0xb0000000
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 98 +++++-----
hw/acpi_ich9.h | 18 +-
hw/i386/Makefile.objs | 1 +
hw/pc.h | 2 +
hw/pc_piix.c | 4 +-
hw/pc_q35.c | 203 ++++++++++++------
hw/q35.c | 566 +++++++++++++++++++++++++++----------------------
hw/q35.h | 92 ++++++++-
hw/q35_smbus.c | 78 ++++---
9 files changed, 644 insertions(+), 418 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 59c0807..9e78b60 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -18,6 +18,7 @@
/*
* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on acpi.c.
*/
@@ -43,13 +44,13 @@ static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
uint32_t val);
static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
-static void pm_update_sci(ICH9_LPCPmRegs *pm)
+static void pm_update_sci(ICH9LPCPMRegs *pm)
{
int sci_level, pm1a_sts;
- pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
- sci_level = (((pm1a_sts & pm->pm1a.en) &
+ sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
(ACPI_BITMASK_RT_CLOCK_ENABLE |
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
@@ -57,24 +58,24 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
qemu_set_irq(pm->irq, sci_level);
/* schedule a timer interruption if needed */
- acpi_pm_tmr_update(&pm->tmr,
- (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
+ acpi_pm_tmr_update(&pm->acpi_regs,
+ (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
!(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
}
-static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
+static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
- ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
+ ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
pm_update_sci(pm);
}
static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
- acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
+ acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
break;
default:
break;
@@ -85,12 +86,12 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
uint32_t val = 0;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
- val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
+ val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
break;
default:
val = 0;
@@ -102,19 +103,19 @@ static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_STS:
- acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
+ acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
pm_update_sci(pm);
break;
case ICH9_PMIO_PM1_EN:
- pm->pm1a.en = val;
+ pm->acpi_regs.pm1.evt.en = val;
pm_update_sci(pm);
break;
case ICH9_PMIO_PM1_CNT:
- acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
+ acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
break;
default:
pm_ioport_write_fallback(opaque, addr, 2, val);
@@ -125,18 +126,18 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
uint32_t val;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_STS:
- val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
break;
case ICH9_PMIO_PM1_EN:
- val = pm->pm1a.en;
+ val = pm->acpi_regs.pm1.evt.en;
break;
case ICH9_PMIO_PM1_CNT:
- val = pm->pm1_cnt.cnt;
+ val = pm->acpi_regs.pm1.cnt.cnt;
break;
default:
val = pm_ioport_read_fallback(opaque, addr, 2);
@@ -148,7 +149,7 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_SMI_EN:
@@ -163,12 +164,12 @@ static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
uint32_t val;
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_TMR:
- val = acpi_pm_tmr_get(&pm->tmr);
+ val = acpi_pm_tmr_get(&pm->acpi_regs);
break;
case ICH9_PMIO_SMI_EN:
val = pm->smi_en;
@@ -215,7 +216,7 @@ static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
return val;
}
-void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
+void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
{
ICH9_DEBUG("to 0x%x\n", pm_io_base);
@@ -238,12 +239,12 @@ void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
pm->pm_io_base = pm_io_base;
- acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
+ acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
}
static int ich9_pm_post_load(void *opaque, int version_id)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
uint32_t pm_io_base = pm->pm_io_base;
pm->pm_io_base = 0;
ich9_pm_iospace_update(pm, pm_io_base);
@@ -268,48 +269,47 @@ const VMStateDescription vmstate_ich9_pm = {
.minimum_version_id_old = 1,
.post_load = ich9_pm_post_load,
.fields = (VMStateField[]) {
- VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
- VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
- VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
- VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
- VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
- VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
- VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
- VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
- VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
+ VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
+ VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
+ VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
+ VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
VMSTATE_END_OF_LIST()
}
};
static void pm_reset(void *opaque)
{
- ICH9_LPCPmRegs *pm = opaque;
+ ICH9LPCPMRegs *pm = opaque;
ich9_pm_iospace_update(pm, 0);
- acpi_pm1_evt_reset(&pm->pm1a);
- acpi_pm1_cnt_reset(&pm->pm1_cnt);
- acpi_pm_tmr_reset(&pm->tmr);
- acpi_gpe_reset(&pm->gpe0);
+ acpi_pm1_evt_reset(&pm->acpi_regs);
+ acpi_pm1_cnt_reset(&pm->acpi_regs);
+ acpi_pm_tmr_reset(&pm->acpi_regs);
+ acpi_gpe_reset(&pm->acpi_regs);
pm_update_sci(pm);
}
-static void pm_powerdown(void *opaque, int irq, int power_failing)
+static void pm_powerdown_req(Notifier *n, void *opaque)
{
- ICH9_LPCPmRegs *pm = opaque;
- ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
- ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
+ ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
- acpi_pm1_evt_power_down(pm1a, tmr);
+ acpi_pm1_evt_power_down(&pm->acpi_regs);
}
-void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
+void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
- acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
- acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
- acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
+ acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
+ acpi_pm1_cnt_init(&pm->acpi_regs);
+ acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
pm->irq = sci_irq;
qemu_register_reset(pm_reset, pm);
- qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
+ pm->powerdown_notifier.notify = pm_powerdown_req;
+ qemu_register_powerdown_notifier(&pm->powerdown_notifier);
}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
index f55c0e9..180c406 100644
--- a/hw/acpi_ich9.h
+++ b/hw/acpi_ich9.h
@@ -23,31 +23,25 @@
#include "acpi.h"
-typedef struct ICH9_LPCPmRegs {
- ACPIPM1EVT pm1a;
-
+typedef struct ICH9LPCPMRegs {
/*
* In ich9 spec says that pm1_cnt register is 32bit width and
* that the upper 16bits are reserved and unused.
* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
*/
- ACPIPM1CNT pm1_cnt;
-
- ACPIPMTimer tmr;
-
- ACPIGPE gpe0;
-
+ ACPIREGS acpi_regs;
uint32_t smi_en;
uint32_t smi_sts;
qemu_irq irq; /* SCI */
uint32_t pm_io_base;
-} ICH9_LPCPmRegs;
+ Notifier powerdown_notifier;
+} ICH9LPCPMRegs;
-void ich9_pm_init(ICH9_LPCPmRegs *pm,
+void ich9_pm_init(ICH9LPCPMRegs *pm,
qemu_irq sci_irq, qemu_irq cmos_s3_resume);
-void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base);
+void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
#endif /* HW_ACPI_ICH9_H */
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 2f0c172..f24dc6b 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -7,6 +7,7 @@ obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
obj-y += pam.o
+obj-y += pc_q35.o q35.o q35_smbus.o acpi_ich9.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
diff --git a/hw/pc.h b/hw/pc.h
index c78923c..125c1fd 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -69,6 +69,8 @@ int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon);
void irq_info(Monitor *mon);
+void kvm_piix3_gsi_handler(void *opaque, int n, int level);
+void kvm_piix3_setup_irq_routing(bool pci_enabled);
/* Global System Interrupts */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 668dccf..e133630 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -53,7 +53,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
-static void kvm_piix3_setup_irq_routing(bool pci_enabled)
+void kvm_piix3_setup_irq_routing(bool pci_enabled)
{
#ifdef CONFIG_KVM
KVMState *s = kvm_state;
@@ -82,7 +82,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
#endif /* CONFIG_KVM */
}
-static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
+void kvm_piix3_gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 4f75d97..b6a619a 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -27,6 +27,7 @@
* Copyright (c) 2009, 2010
* Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on pc.c, but heavily modified.
*
@@ -49,7 +50,6 @@
#include "fdc.h"
#include "pci.h"
#include "pci_bridge.h"
-#include "pci_p2pbr.h"
#include "ioh3420.h"
#include "xio3130_upstream.h"
#include "xio3130_downstream.h"
@@ -66,36 +66,16 @@
#include "watchdog.h"
#include "smbios.h"
#include "ide.h"
-#include "usb-uhci.h"
+#include "mc146818rtc.h"
+#include "xen.h"
+#include "kvm.h"
#include "q35.h"
+#include "exec-memory.h"
/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS 6
-#define I21154_REV 0x05
-#define I21154_PI 0x00
-
-static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction)
-{
- const PCIP2PBridgeInit init = {
- .bus = bus,
- .devfn = devfn,
- .multifunction = multifunction,
-
- .bus_name = bus_name,
- .map_irq = pci_swizzle_map_irq_fn,
- };
- const PCIP2PBridgeProp prop = {
- .vendor_id = PCI_VENDOR_ID_DEC,
- .device_id = PCI_DEVICE_ID_DEC_21154,
- .revision_id = I21154_REV,
- .prog_interface = I21154_PI,
- };
- return pci_p2pbr_create_simple(&init, &prop);
-}
-
static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
{
uint8_t dev;
@@ -104,7 +84,6 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
uint8_t chassis = 0;
uint16_t slot = 0;
uint8_t upstream_port;
- PCIESlot *s;
uint8_t fn;
PCIESlot *root_port;
PCIBus *root_port_bus;
@@ -116,11 +95,10 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
#define Q35_P2P_BRDIGE_DEV_MAX 32
#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
- PCIBridge *br;
sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
- br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+ i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
}
/* PCIe root port b0:d1:f0 in GMCH.
@@ -128,8 +106,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
*/
sec_bus = 32;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
- buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
/* more slots. ICH9 doesn't have those, but many slots are wanted. */
@@ -153,8 +131,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
slot++;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
- buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
}
/* PCIe root port b0:d24:f0 */
@@ -219,27 +197,38 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
slot++;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
- buf, pci_swizzle_map_irq_fn,
- port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
+ buf, pci_swizzle_map_irq_fn,
+ port, chassis, slot);
}
}
-static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
+static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
DeviceState **gmch_host_p,
PCIBus **host_bus_p, PCIBus **pci_bus_p,
- PCIDevice **lpc_p)
+ PCIDevice **lpc_p, ISABus **isa_bus,
+ MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io,
+ MemoryRegion *ram_memory,
+ ram_addr_t below_4g_mem_size,
+ ram_addr_t above_4g_mem_size)
{
+ target_phys_addr_t pci_hole64_size;
DeviceState *gmch_host;
PCIBus *host_bus;
PCIBus *pci_bus;
PCIDevice *gmch_state;
PCIDevice *lpc;
+ GMCHPCIState *gmps;
+ ICH9LPCState *ich9_lpc;
/* create pci host bus */
- host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
+ host_bus = gmch_host_init(&gmch_host, gsi, gsi_state->ioapic_irq,
+ pci_address_space, address_space_io);
gmch_state = gmch_init(gmch_host, host_bus);
+ gmps = GMCH_PCI_DEVICE(gmch_state);
/* create conventional pci bus: pcie2pci bridge */
pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
@@ -252,10 +241,53 @@ static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
/* create ISA bus */
lpc = gmch_lpc_init(gmch_host, host_bus);
+ gmps->ram_memory = ram_memory;
+ gmps->pci_address_space = pci_address_space;
+ gmps->system_memory = system_memory;
+ /* pci */
+ memory_region_init_alias(&gmps->pci_hole, "pci-hole",
+ gmps->pci_address_space,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size);
+ memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
+ &gmps->pci_hole);
+ pci_hole64_size = (sizeof(target_phys_addr_t) == 4 ? 0 :
+ ((uint64_t)1 << 62));
+ memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
+ gmps->pci_address_space,
+ 0x100000000ULL + above_4g_mem_size,
+ pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(gmps->system_memory,
+ 0x100000000ULL + above_4g_mem_size,
+ &gmps->pci_hole_64bit);
+ }
+
+ /* smram */
+ memory_region_init_alias(&gmps->smram_region, "smram-region",
+ pci_address_space, 0xa0000, 0x20000);
+ memory_region_add_subregion_overlap(system_memory, 0xa0000,
+ &gmps->smram_region, 1);
+ memory_region_set_enabled(&gmps->smram_region, false);
+
*gmch_host_p = gmch_host;
*host_bus_p = host_bus;
*pci_bus_p = pci_bus;
*lpc_p = lpc;
+ ich9_lpc = ICH9_LPC_DEVICE(lpc);
+ *isa_bus = ich9_lpc->isa_bus;
+}
+
+
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ * BIOS will read it and start S3 resume at POST Entry */
+static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
+{
+ ISADevice *s = opaque;
+
+ if (level) {
+ rtc_set_memory(s, 0xF, 0xFE);
+ }
}
static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
@@ -271,13 +303,13 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
- /* ahci and SATA device */
- ide_drive_get(hd, MAX_SATA_PORTS);
+ /* ahci and SATA device, for q35 1 ahci controller is built-in */
+ ahci_drive_get(hd, 1);
ahci = pci_create_simple_multifunction(host_bus,
PCI_DEVFN(ICH9_SATA1_DEV,
ICH9_SATA1_FUNC),
true, "ich9-ahci");
- pci_ahci_ide_create_devs(ahci, hd);
+ pci_ahci_create_devs(ahci, hd);
idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
@@ -309,58 +341,96 @@ static void pc_q35_init(ram_addr_t ram_size,
PCIBus *host_bus;
PCIBus *pci_bus;
PCIDevice *lpc;
- qemu_irq *isa_irq;
- IsaIrqState *isa_irq_state;
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
+ ISADevice *floppy;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
MemoryRegion *ram_memory;
+ GSIState *gsi_state;
+ ISABus *isa_bus;
+ int pci_enabled = 1;
+ qemu_irq *cpu_irq;
+ qemu_irq *gsi;
+ qemu_irq *i8259;
+ int i;
pc_cpus_init(cpu_model);
- /* FIXME: add kvm clock ? */
-
- if (ram_size >= 0xe0000000) {
- above_4g_mem_size = ram_size - 0xe0000000;
- below_4g_mem_size = 0xe0000000;
+ if (ram_size >= 0xb0000000) {
+ above_4g_mem_size = ram_size - 0xb0000000;
+ below_4g_mem_size = 0xb0000000;
} else {
above_4g_mem_size = 0;
below_4g_mem_size = ram_size;
}
/* pci enabled */
- pci_memory = g_new(MemoryRegion, 1);
- memory_region_init(pci_memory, "pci", INT64_MAX);
- rom_memory = pci_memory;
+ if (pci_enabled) {
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+ rom_memory = pci_memory;
+ } else {
+ pci_memory = NULL;
+ rom_memory = get_system_memory();
+ }
/* allocate ram and load rom/bios */
- pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
- initrd_filename, below_4g_mem_size, above_4g_mem_size,
- rom_memory, &ram_memory);
+ if (!xen_enabled()) {
+ pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+ }
/* irq lines */
- isa_irq = pc_isa_irq(&isa_irq_state);
- ioapic_init(isa_irq_state);
+ gsi_state = g_malloc0(sizeof(*gsi_state));
+ if (kvm_irqchip_in_kernel()) {
+ kvm_piix3_setup_irq_routing(pci_enabled);
+ gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+ GSI_NUM_PINS);
+ } else {
+ gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ }
+
+ pc_q35_init_early(gsi, gsi_state,
+ &gmch_host, &host_bus, &pci_bus, &lpc, &isa_bus,
+ get_system_memory(), pci_memory, get_system_io(),
+ ram_memory, below_4g_mem_size, above_4g_mem_size);
+ isa_bus_irqs(isa_bus, gsi);
- pc_q35_init_early(isa_irq, isa_irq_state,
- &gmch_host, &host_bus, &pci_bus, &lpc);
- isa_bus_irqs(isa_irq);
- pc_register_ferr_irq(isa_get_irq(13));
+ if (kvm_irqchip_in_kernel()) {
+ i8259 = kvm_i8259_init(isa_bus);
+ } else if (xen_enabled()) {
+ i8259 = xen_interrupt_controller_init();
+ } else {
+ cpu_irq = pc_allocate_cpu_irq();
+ i8259 = i8259_init(isa_bus, cpu_irq[0]);
+ }
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ gsi_state->i8259_irq[i] = i8259[i];
+ }
+ if (pci_enabled) {
+ ioapic_init_gsi(gsi_state, NULL);
+ }
+
+ pc_register_ferr_irq(gsi[13]);
/* init basic PC hardware */
- pc_basic_device_init(isa_irq, &rtc_state, false);
+ pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
- idebus[0], idebus[1], rtc_state);
+ floppy, idebus[0], idebus[1], rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
- pc_vga_init(host_bus);
- audio_init(isa_irq, pci_bus);
- pc_nic_init(pci_bus);
- pc_pci_device_init(pci_bus);
+ pc_vga_init(isa_bus, host_bus);
+ audio_init(isa_bus, pci_bus);
+ pc_nic_init(isa_bus, pci_bus);
+ if (pci_enabled) {
+ pc_pci_device_init(pci_bus);
+ }
}
static QEMUMachine pc_q35_machine = {
@@ -368,6 +438,7 @@ static QEMUMachine pc_q35_machine = {
.desc = "Q35 chipset PC",
.init = pc_q35_init,
.max_cpus = 255,
+ .mach_if = IF_AHCI,
};
static void pc_q35_machine_init(void)
diff --git a/hw/q35.c b/hw/q35.c
index 1776ac3..ff570ce 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -25,6 +25,7 @@
* Copyright (c) 2009, 2010, 2011
* Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on piix_pci.c, but heavily modified.
*
@@ -52,85 +53,39 @@
#include "pci.h"
#include "pcie_host.h"
#include "pci_bridge.h"
-#include "pci_p2pbr.h"
#include "q35.h"
#include "acpi.h"
#include "acpi_ich9.h"
#include "pam.h"
+#include "pci_internals.h"
+#include "exec-memory.h"
+#include "isa.h"
+#include "qemu-common.h"
-struct ICH9_LPCState;
-
-typedef struct ICH9_LPCIrqState {
- struct ICH9_LPCState *lpc;
- qemu_irq *pic;
- qemu_irq *ioapic;
-} ICH9_LPCIrqState;
-
-typedef struct GMCH_PCIHost {
- PCIExpressHost host;
-
- PCIDevice *dev;
- ICH9_LPCIrqState irq_state;
-} GMCH_PCIHost;
-
-typedef struct GMCH_PCIState {
- PCIDevice d;
- /*
- * GMCH_PCIHost *gmch_host;
- * In order to get GMCH_PCIHost
- * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
- */
-
- PAM pam;
-} GMCH_PCIState;
-
-typedef struct ICH9_LPCState {
- /* ICH9 LPC PCI to ISA bridge */
- PCIDevice d;
-
- /* (pci device, intx) -> pirq
- * In real chipset case, the unused slots are never used
- * as ICH9 supports only D25-D32 irq routing.
- * On the other hand in qemu case, any slot/function can be populated
- * via command line option.
- * So fallback interrupt routing for any devices in any slots is necessary.
- */
- uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
-
- APMState apm;
- ICH9_LPCPmRegs pm;
- uint32_t sci_level; /* track sci level */
-
- /* 10.1 Chipset Configuration registers(Memory Space)
- which is pointed by RCBA */
- uint8_t chip_config[ICH9_CC_SIZE];
- int rbca_index;
-} ICH9_LPCState;
-
/****************************************************************************
* GMCH PCI host
*/
/* ich9 irq */
-static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
+static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
-static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
-
-static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
-{
- SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
- PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
- PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
- return DO_UPCAST(GMCH_PCIHost, host, pcie);
-}
+static int ich9_lpc_sci_irq(ICH9LPCState *lpc);
static int gmch_pcihost_initfn(SysBusDevice *dev)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
+ PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
+
+ memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
+ "pci-conf-idx", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_ADDR, 4);
- pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
- pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
+ memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
+ "pci-conf-data", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_DATA, 4);
if (pcie_host_init(&s->host) < 0) {
abort();
@@ -139,36 +94,52 @@ static int gmch_pcihost_initfn(SysBusDevice *dev)
return 0;
}
-static SysBusDeviceInfo gmch_pcihost_info = {
- .init = gmch_pcihost_initfn,
- .qdev.name = "gmch-pcihost",
- .qdev.size = sizeof(GMCH_PCIHost),
- .qdev.no_user = 1,
- .qdev.props = (Property[]) {
- {
- .name = "MCFG",
- .info = &qdev_prop_uint64,
- .offset = offsetof(GMCH_PCIHost, host.base_addr),
- .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
- },
- DEFINE_PROP_END_OF_LIST(),
- },
+static Property gmch_props[] = {
+ DEFINE_PROP_UINT64("MCFG", GMCHPCIHost, host.base_addr,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static Property gmch_pcihost_properties[] = {
+ DEFINE_PROP_PTR("lpc state", GMCHPCIHost, irq_state.lpc),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void gmch_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = gmch_pcihost_initfn;
+ dc->props = gmch_props;
+ dc->no_user = 1;
+ dc->props = gmch_pcihost_properties;
+}
+
+static const TypeInfo gmch_pcihost_info = {
+ .name = TYPE_GMCH_HOST_DEVICE,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(GMCHPCIHost),
+ .class_init = gmch_pcihost_class_init,
};
/* host bridge */
PCIBus *gmch_host_init(DeviceState **gmch_hostp,
- qemu_irq *pic, qemu_irq *ioapic)
+ qemu_irq *pic, qemu_irq *ioapic,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io)
{
DeviceState *dev;
- GMCH_PCIHost *s;
+ GMCHPCIHost *s;
PCIBus *b;
- dev = qdev_create(NULL, "gmch-pcihost");
- s = gmch_pcihost_from_qdev(dev);
+ dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
+ s = GMCH_HOST_DEVICE(dev);
s->irq_state.pic = pic;
s->irq_state.ioapic = ioapic;
- b = pci_bus_new(dev, "pcie.0", 0);
+ b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
+ address_space_io, 0);
pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
ICH9_LPC_NB_PIRQS);
s->host.pci.bus = b;
@@ -180,20 +151,16 @@ PCIBus *gmch_host_init(DeviceState **gmch_hostp,
/****************************************************************************
- * GMCH
+ * GMCH D0:F0
*/
-static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
-{
- return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
-}
/* PCIE MMCFG */
-static void gmch_update_pciexbar(GMCH_PCIState *gs)
+static void gmch_update_pciexbar(GMCHPCIState *gs)
{
PCIDevice *pci_dev = &gs->d;
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
DeviceState *qdev = bus->parent;
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(qdev);
uint64_t pciexbar;
int enable;
@@ -231,30 +198,42 @@ static void gmch_update_pciexbar(GMCH_PCIState *gs)
}
/* PAM */
-static void gmch_update_pam(GMCH_PCIState *gs)
+static void gmch_update_pam(GMCHPCIState *gs)
{
int i;
+
+ memory_region_transaction_begin();
for (i = 0; i <= PAM_IDX_MAX; i++) {
- pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
+ pam_update(&gs->pam_regions[0], i,
+ gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i],
+ gs->ram_memory, gs->pci_address_space, gs->system_memory);
}
+ memory_region_transaction_commit();
}
/* SMRAM */
-static void gmch_update_smram(GMCH_PCIState *gs)
+static void gmch_update_smram(GMCHPCIState *gs)
{
- smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+ memory_region_transaction_begin();
+ smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ gs->smm_enabled);
+ memory_region_transaction_commit();
}
static void gmch_set_smm(int smm, void *arg)
{
- GMCH_PCIState *gs = arg;
- smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+ GMCHPCIState *gs = arg;
+
+ memory_region_transaction_begin();
+ smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ &gs->smram_region);
+ memory_region_transaction_commit();
}
static void gmch_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
- GMCH_PCIState *gs = gmch_from_pci(d);
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(d, address, val, len);
@@ -275,7 +254,7 @@ static void gmch_write_config(PCIDevice *d,
}
}
-static void gmch_update(GMCH_PCIState *gs)
+static void gmch_update(GMCHPCIState *gs)
{
gmch_update_pciexbar(gs);
gmch_update_pam(gs);
@@ -284,7 +263,7 @@ static void gmch_update(GMCH_PCIState *gs)
static int gmch_post_load(void *opaque, int version_id)
{
- GMCH_PCIState *gs = opaque;
+ GMCHPCIState *gs = opaque;
gmch_update(gs);
return 0;
}
@@ -296,16 +275,16 @@ static const VMStateDescription vmstate_gmch = {
.minimum_version_id_old = 1,
.post_load = gmch_post_load,
.fields = (VMStateField []) {
- VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
- VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
+ VMSTATE_PCI_DEVICE(d, GMCHPCIState),
+ VMSTATE_UINT8(smm_enabled, GMCHPCIState),
VMSTATE_END_OF_LIST()
}
};
static void gmch_reset(DeviceState *qdev)
{
- PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
- GMCH_PCIState *gs = gmch_from_pci(d);
+ PCIDevice *d = PCI_DEVICE(qdev);
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
@@ -315,39 +294,46 @@ static void gmch_reset(DeviceState *qdev)
gmch_update(gs);
}
-static int gmch_initfn(PCIDevice *d)
+static int pci_gmch_initfn(PCIDevice *d)
{
- GMCH_PCIState *gs = gmch_from_pci(d);
-
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
- pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+ GMCHPCIState *gs = GMCH_PCI_DEVICE(d);
cpu_smm_register(&gmch_set_smm, gs);
- pam_init_memory_mappings(&gs->pam);
return 0;
}
-static PCIDeviceInfo gmch_info = {
- .qdev.name = "gmch",
- .qdev.desc = "Host bridge",
- .qdev.size = sizeof(GMCH_PCIState),
- .qdev.vmsd = &vmstate_gmch,
- .qdev.no_user = 1,
- .init = gmch_initfn,
- .config_write = gmch_write_config,
- .qdev.reset = gmch_reset,
+static void pci_gmch_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ k->init = pci_gmch_initfn;
+ k->config_write = gmch_write_config;
+ dc->reset = gmch_reset;
+ dc->desc = "Host bridge";
+ dc->vmsd = &vmstate_gmch;
+ dc->no_user = 1;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
+ k->revision = GMCH_HOST_BRIDGE_REVISION_DEFUALT;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+}
+
+static const TypeInfo pci_gmch_info = {
+ .name = TYPE_GMCH_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(GMCHPCIState),
+ .class_init = pci_gmch_class_init,
};
/* host bridge */
PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
PCIDevice *d;
- d = pci_create_simple_multifunction(b, 0, false, "gmch");
+ d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
s->dev = d;
return d;
@@ -359,54 +345,135 @@ PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
#define I82801ba_SSVID_SVID 0
#define I82801ba_SSVID_SSID 0
-static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction)
+typedef struct I82801b11Bridge {
+ PCIBridge br;
+} I82801b11Bridge;
+
+static int i82801b11_bridge_initfn(PCIDevice *d)
{
- const PCIP2PBridgeInit init = {
- .bus = bus,
- .devfn = devfn,
- .multifunction = multifunction,
+ int rc;
+
+ rc = pci_bridge_initfn(d);
+ if (rc < 0) {
+ return rc;
+ }
+
+ rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
+ I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);
+ if (rc < 0) {
+ goto err_bridge;
+ }
+ return 0;
- .bus_name = bus_name,
- .map_irq = pci_swizzle_map_irq_fn,
- };
- const PCIP2PBridgeProp prop = {
- .vendor_id = PCI_VENDOR_ID_INTEL,
- .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
- .revision_id = ICH9_D2P_A2_REVISION,
- .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
+err_bridge:
+ pci_bridge_exitfn(d);
- .ssvid_cap = I82801ba_SSVID_OFFSET,
- .svid = I82801ba_SSVID_SVID,
- .ssid = I82801ba_SSVID_SSID,
- };
- return pci_p2pbr_create_simple(&init, &prop);
+ return rc;
}
+static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->is_bridge = 1;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
+ k->revision = ICH9_D2P_A2_REVISION;
+ k->init = i82801b11_bridge_initfn;
+}
+
+static const TypeInfo i82801b11_bridge_info = {
+ .name = "i82801b11-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(I82801b11Bridge),
+ .class_init = i82801b11_bridge_class_init,
+};
+
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
{
+ PCIDevice *d;
PCIBridge *br;
char buf[16];
+ DeviceState *qdev;
- snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
- br = i82801ba11_init(bus, devfn, buf, true);
- if (br == NULL) {
+ d = pci_create_multifunction(bus, devfn, true, "i82801b11-bridge");
+ if (!d) {
return NULL;
}
+ br = DO_UPCAST(PCIBridge, dev, d);
+ qdev = &br->dev.qdev;
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn);
+ qdev_init_nofail(qdev);
+
return pci_bridge_get_sec_bus(br);
}
+/*****************************************************************************/
+/* i21154 pci bridge*/
+
+typedef struct I21154Bridge {
+ PCIBridge br;
+} I21154Bridge;
+
+static int i21154_bridge_initfn(PCIDevice *d)
+{
+ int rc;
+
+ rc = pci_bridge_initfn(d);
+ if (rc < 0) {
+ return rc;
+ }
+
+ return 0;
+}
+#define I21154_REV 0x05
+#define I21154_PI 0x00
-/*****************************************************************************/
-/* ICH9 LPC PCI to ISA bridge */
+static void i21154_bridge_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-static void ich9_lpc_reset(DeviceState *qdev);
+ k->is_bridge = 1;
+ k->vendor_id = PCI_VENDOR_ID_DEC;
+ k->device_id = PCI_DEVICE_ID_DEC_21154;
+ k->revision = I21154_REV;
+ k->init = i21154_bridge_initfn;
+}
-static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
+static const TypeInfo i21154_bridge_info = {
+ .name = "i21154-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(I21154Bridge),
+ .class_init = i21154_bridge_class_init,
+};
+
+PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
{
- return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
+ PCIDevice *d;
+ PCIBridge *br;
+ DeviceState *qdev;
+
+ d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
+ if (!d) {
+ return NULL;
+ }
+ br = DO_UPCAST(PCIBridge, dev, d);
+ qdev = &br->dev.qdev;
+
+ pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
+ qdev_init_nofail(qdev);
+
+ return br;
}
+/*****************************************************************************/
+/* ICH9 LPC PCI to ISA bridge */
+
+static void ich9_lpc_reset(DeviceState *qdev);
+
/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
@@ -421,7 +488,7 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
}
}
-static void ich9_cc_update(ICH9_LPCState *lpc)
+static void ich9_cc_update(ICH9LPCState *lpc)
{
int slot;
int reg_offset;
@@ -446,7 +513,7 @@ static void ich9_cc_update(ICH9_LPCState *lpc)
}
}
-static void ich9_cc_init(ICH9_LPCState *lpc)
+static void ich9_cc_init(ICH9LPCState *lpc)
{
int slot;
int intx;
@@ -468,7 +535,7 @@ static void ich9_cc_init(ICH9_LPCState *lpc)
ich9_cc_update(lpc);
}
-static void ich9_cc_reset(ICH9_LPCState *lpc)
+static void ich9_cc_reset(ICH9LPCState *lpc)
{
uint8_t *c = lpc->chip_config;
@@ -485,7 +552,7 @@ static void ich9_cc_reset(ICH9_LPCState *lpc)
ich9_cc_update(lpc);
}
-static void ich9_cc_addr_len(uint32_t *addr, int *len)
+static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
{
*addr &= ICH9_CC_ADDR_MASK;
if (*addr + *len >= ICH9_CC_SIZE) {
@@ -494,56 +561,27 @@ static void ich9_cc_addr_len(uint32_t *addr, int *len)
}
/* val: little endian */
-static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
- uint32_t val, int len)
+static void ich9_cc_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
+ ICH9LPCState *lpc = (ICH9LPCState *)opaque;
+
ich9_cc_addr_len(&addr, &len);
memcpy(lpc->chip_config + addr, &val, len);
}
/* return value: little endian */
-static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
+static uint64_t ich9_cc_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
+ ICH9LPCState *lpc = (ICH9LPCState *)opaque;
+
uint32_t val = 0;
ich9_cc_addr_len(&addr, &len);
memcpy(&val, lpc->chip_config + addr, len);
return val;
}
-#define ICH9_CC_MMIO_WRITE(type, len) \
- static void ich9_cc_mmio_write ## type \
- (void *opaque, target_phys_addr_t addr, uint32_t val) \
- { \
- ich9_cc_write(opaque, addr, val, len); \
- }
-
-#define ICH9_CC_MMIO_READ(type, len) \
- static uint32_t ich9_cc_mmio_read ## type \
- (void *opaque, target_phys_addr_t addr) \
- { \
- return ich9_cc_read(opaque, addr, len); \
- }
-
-ICH9_CC_MMIO_WRITE(b, 1)
-ICH9_CC_MMIO_WRITE(w, 2)
-ICH9_CC_MMIO_WRITE(l, 4)
-
-ICH9_CC_MMIO_READ(b, 1)
-ICH9_CC_MMIO_READ(w, 2)
-ICH9_CC_MMIO_READ(l, 4)
-
-static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
- ich9_cc_mmio_writeb,
- ich9_cc_mmio_writew,
- ich9_cc_mmio_writel,
-};
-
-static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
- ich9_cc_mmio_readb,
- ich9_cc_mmio_readw,
- ich9_cc_mmio_readl,
-};
-
/* IRQ routing */
/* */
static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
@@ -552,7 +590,7 @@ static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
*pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
}
-static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
+static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int irq_num,
int *pic_irq, int *pic_dis)
{
switch (irq_num) {
@@ -571,10 +609,10 @@ static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
}
/* pic_irq: i8254 irq 0-15 */
-static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
+static void ich9_lpc_update_pic(ICH9LPCIrqState *irq_state, int pic_irq)
{
- GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
- ICH9_LPCState *lpc = irq_state->lpc;
+ GMCHPCIHost *s = container_of(irq_state, GMCHPCIHost, irq_state);
+ ICH9LPCState *lpc = irq_state->lpc;
int i, pic_level;
/* The pic level is the logical OR of all the PCI irqs mapped to it */
@@ -595,9 +633,9 @@ static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
}
/* pirq: pirq[A-H] 0-7*/
-static void ich9_lpc_update_by_pirq(ICH9_LPCIrqState *irq_state, int pirq)
+static void ich9_lpc_update_by_pirq(ICH9LPCIrqState *irq_state, int pirq)
{
- ICH9_LPCState *lpc = irq_state->lpc;
+ ICH9LPCState *lpc = irq_state->lpc;
int pic_irq;
int pic_dis;
@@ -621,10 +659,10 @@ static int ich9_gsi_to_pirq(int gsi)
return gsi - ICH9_LPC_PIC_NUM_PINS;
}
-static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
+static void ich9_lpc_update_apic(ICH9LPCIrqState *irq_state, int gsi)
{
- GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
- ICH9_LPCState *lpc = irq_state->lpc;
+ GMCHPCIHost *s = container_of(irq_state, GMCHPCIHost, irq_state);
+ ICH9LPCState *lpc = irq_state->lpc;
int level;
level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
@@ -637,15 +675,20 @@ static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
a given device irq pin. */
-static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx)
+static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
{
- ICH9_LPCIrqState *irq_state = opaque;
- return irq_state->lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
+ BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+ DeviceState *qdev = bus->parent;
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(qdev);
+ ICH9LPCIrqState *irq_state = &s->irq_state;
+ ICH9LPCState *lpc = (ICH9LPCState *)irq_state->lpc;
+
+ return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}
static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
{
- ICH9_LPCIrqState *irq_state = opaque;
+ ICH9LPCIrqState *irq_state = opaque;
assert(0 <= pirq);
assert(pirq < ICH9_LPC_NB_PIRQS);
@@ -654,7 +697,7 @@ static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
ich9_lpc_update_by_pirq(irq_state, pirq);
}
-static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
+static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
{
switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
@@ -677,8 +720,8 @@ static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
static void ich9_set_sci(void *opaque, int irq_num, int level)
{
- ICH9_LPCIrqState *irq_state = opaque;
- ICH9_LPCState *lpc = irq_state->lpc;
+ ICH9LPCIrqState *irq_state = opaque;
+ ICH9LPCState *lpc = irq_state->lpc;
int irq;
assert(irq_num == 0);
@@ -702,8 +745,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
qemu_irq cmos_s3)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
- ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
+ ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq *sci_irq;
sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
@@ -713,12 +756,14 @@ void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
}
/* APM */
+
+
static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
{
- ICH9_LPCState *lpc = arg;
+ ICH9LPCState *lpc = arg;
/* ACPI specs 3.0, 4.7.2.5 */
- acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
+ acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
val == ICH9_APM_ACPI_ENABLE,
val == ICH9_APM_ACPI_DISABLE);
@@ -730,7 +775,7 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
/* config:PMBASE */
static void
-ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
+ich9_lpc_pmbase_update(ICH9LPCState *lpc)
{
uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
@@ -739,23 +784,23 @@ ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
}
/* config:RBCA */
-static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
+static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old)
{
uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
if (rbca_old & ICH9_LPC_RCBA_EN) {
- cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
- ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem);
}
if (rbca & ICH9_LPC_RCBA_EN) {
- cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
- ICH9_CC_SIZE, lpc->rbca_index);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ rbca & ICH9_LPC_RCBA_BA_MASK,
+ &lpc->rbca_mem, 1);
}
}
static int ich9_lpc_post_load(void *opaque, int version_id)
{
- ICH9_LPCState *lpc = opaque;
+ ICH9LPCState *lpc = opaque;
ich9_lpc_pmbase_update(lpc);
ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
@@ -765,7 +810,7 @@ static int ich9_lpc_post_load(void *opaque, int version_id)
static void ich9_lpc_config_write(PCIDevice *d,
uint32_t addr, uint32_t val, int len)
{
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
pci_default_write_config(d, addr, val, len);
@@ -779,8 +824,8 @@ static void ich9_lpc_config_write(PCIDevice *d,
static void ich9_lpc_reset(DeviceState *qdev)
{
- PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ PCIDevice *d = PCI_DEVICE(qdev);
+ ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
int i;
@@ -805,22 +850,26 @@ static void ich9_lpc_reset(DeviceState *qdev)
lpc->sci_level = 0;
}
+static const MemoryRegionOps rbca_mmio_ops = {
+ .read = ich9_cc_read,
+ .write = ich9_cc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static int ich9_lpc_initfn(PCIDevice *d)
{
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
+ ISABus *isa_bus;
- isa_bus_new(&d->qdev);
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
- pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
+ isa_bus = isa_bus_new(&d->qdev, get_system_io());
pci_set_long(d->wmask + ICH9_LPC_PMBASE,
ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
- lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
- ich9_cc_mmio_write,
- lpc, DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&lpc->rbca_mem, &rbca_mmio_ops, lpc,
+ "lpc-rbca-mmio", ICH9_CC_SIZE);
+
+ lpc->isa_bus = isa_bus;
ich9_cc_init(lpc);
apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
@@ -834,44 +883,61 @@ static const VMStateDescription vmstate_ich9_lpc = {
.minimum_version_id_old = 1,
.post_load = ich9_lpc_post_load,
.fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(d, ICH9_LPCState),
- VMSTATE_STRUCT(apm, ICH9_LPCState, 0, vmstate_apm, APMState),
- VMSTATE_STRUCT(pm, ICH9_LPCState, 0, vmstate_ich9_pm, ICH9_LPCPmRegs),
- VMSTATE_UINT8_ARRAY(chip_config, ICH9_LPCState, ICH9_CC_SIZE),
- VMSTATE_UINT32(sci_level, ICH9_LPCState),
+ VMSTATE_PCI_DEVICE(d, ICH9LPCState),
+ VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
+ VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
+ VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
+ VMSTATE_UINT32(sci_level, ICH9LPCState),
VMSTATE_END_OF_LIST()
}
};
PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ GMCHPCIHost *s = GMCH_HOST_DEVICE(gmch_host);
PCIDevice *d;
- ICH9_LPCState *lpc;
+ ICH9LPCState *lpc;
d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC),
- true, "ICH9 LPC");
- lpc = ich9_lpc_from_pci(d);
+ true, TYPE_ICH9_LPC_DEVICE);
+ lpc = ICH9_LPC_DEVICE(d);
s->irq_state.lpc = lpc;
return &lpc->d;
}
-static PCIDeviceInfo ich9_lpc_info = {
- .qdev.name = "ICH9 LPC",
- .qdev.desc = "ICH9 LPC bridge",
- .qdev.size = sizeof(ICH9_LPCState),
- .qdev.vmsd = &vmstate_ich9_lpc,
- .qdev.no_user = 1,
- .init = ich9_lpc_initfn,
- .config_write = ich9_lpc_config_write,
- .qdev.reset = ich9_lpc_reset,
+static void ich9_lpc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->reset = ich9_lpc_reset;
+ k->init = ich9_lpc_initfn;
+ dc->vmsd = &vmstate_ich9_lpc;
+ dc->no_user = 1;
+ k->config_write = ich9_lpc_config_write;
+ dc->desc = "ICH9 LPC bridge";
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
+ k->revision = ICH9_A2_LPC_REVISION;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+
+}
+
+static const TypeInfo ich9_lpc_info = {
+ .name = TYPE_ICH9_LPC_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(struct ICH9LPCState),
+ .class_init = ich9_lpc_class_init,
};
static void q35_register(void)
{
- sysbus_register_withprop(&gmch_pcihost_info);
- pci_qdev_register(&gmch_info);
- pci_qdev_register(&ich9_lpc_info);
+ type_register_static(&pci_gmch_info);
+ type_register_static(&gmch_pcihost_info);
+ type_register_static(&i82801b11_bridge_info);
+ type_register_static(&i21154_bridge_info);
+ type_register_static(&ich9_lpc_info);
}
-device_init(q35_register);
+
+type_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
index be2e96b..75c8f0e 100644
--- a/hw/q35.h
+++ b/hw/q35.h
@@ -21,19 +21,104 @@
#ifndef HW_Q35_H
#define HW_Q35_H
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
-PCIBus *gmch_host_init(DeviceState **gmch_hostp,
- qemu_irq *pic, qemu_irq *ioapic);
+#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
+
+#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
+#define GMCH_HOST_DEVICE(obj) \
+ OBJECT_CHECK(GMCHPCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
+
+#define TYPE_GMCH_PCI_DEVICE "gmch"
+#define GMCH_PCI_DEVICE(obj) \
+ OBJECT_CHECK(GMCHPCIState, (obj), TYPE_GMCH_PCI_DEVICE)
+
+#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
+#define ICH9_LPC_DEVICE(obj) \
+ OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
+
+typedef struct ICH9LPCState {
+ /* ICH9 LPC PCI to ISA bridge */
+ PCIDevice d;
+
+ /* (pci device, intx) -> pirq
+ * In real chipset case, the unused slots are never used
+ * as ICH9 supports only D25-D32 irq routing.
+ * On the other hand in qemu case, any slot/function can be populated
+ * via command line option.
+ * So fallback interrupt routing for any devices in any slots is necessary.
+ */
+ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+
+ APMState apm;
+ ICH9LPCPMRegs pm;
+ uint32_t sci_level; /* track sci level */
+
+ /* 10.1 Chipset Configuration registers(Memory Space)
+ which is pointed by RCBA */
+ uint8_t chip_config[ICH9_CC_SIZE];
+ /* isa bus */
+ ISABus *isa_bus;
+ MemoryRegion rbca_mem;
+} ICH9LPCState;
+
+typedef struct ICH9LPCIrqState {
+ /* points to ICH9LPCState */
+ void *lpc;
+ qemu_irq *pic;
+ qemu_irq *ioapic;
+} ICH9LPCIrqState;
+
+typedef struct GMCHPCIHost {
+ PCIExpressHost host;
+ PCIDevice *dev;
+ ICH9LPCIrqState irq_state;
+} GMCHPCIHost;
+
+typedef struct GMCHPCIState {
+ PCIDevice d;
+ /*
+ * GMCH_PCIHost *gmch_host;
+ * In order to get GMCH_PCIHost
+ * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+ */
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *system_memory;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ uint8_t smm_enabled;
+} GMCHPCIState;
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io);
PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
qemu_irq cmos_s3);
-
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction);
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
@@ -124,7 +209,6 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
*/
/* ICH9: Chipset Configuration Registers */
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
#define ICH9_CC
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
index fe445ac..5efbe6c 100644
--- a/hw/q35_smbus.c
+++ b/hw/q35_smbus.c
@@ -18,6 +18,7 @@
/*
* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on acpi.c, but heavily rewritten.
*/
@@ -35,6 +36,7 @@ typedef struct ICH9_SMBState {
PCIDevice dev;
PMSMBus smb;
+ MemoryRegion mem_bar;
} ICH9_SMBState;
static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
@@ -53,7 +55,8 @@ static const VMStateDescription vmstate_ich9_smbus = {
}
};
-static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+static void ich9_smb_ioport_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
ICH9_SMBState *s = opaque;
uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
@@ -64,7 +67,8 @@ static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+static uint64_t ich9_smb_ioport_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
ICH9_SMBState *s = opaque;
uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
@@ -77,32 +81,22 @@ static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
return 0xff;
}
-static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
- uint64_t addr, uint64_t size, int type)
-{
- ICH9_SMBState *s = ich9_pci_to_smb(dev);
-
- assert(size == ICH9_SMB_SMB_BASE_SIZE);
- assert(type == PCI_BASE_ADDRESS_SPACE_IO);
-
- register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
- register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
-}
+static const MemoryRegionOps lpc_smb_mmio_ops = {
+ .read = ich9_smb_ioport_readb,
+ .write = ich9_smb_ioport_writeb,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
-static int ich9_smb_initfn(PCIDevice *d)
+static int ich9_smbus_initfn(PCIDevice *d)
{
ICH9_SMBState *s = ich9_pci_to_smb(d);
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
-
pci_set_word(d->wmask + PCI_STATUS,
- PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
-
- pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
- pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
- pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
-
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
/* TODO? D31IP.SMIP in chipset configuration space */
pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
@@ -121,14 +115,30 @@ static int ich9_smb_initfn(PCIDevice *d)
/* TODO smb_io_base */
pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
/* TODO bar0, bar1: 64bit BAR support*/
- pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
- ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
- &ich9_smb_map_ioport);
+ memory_region_init_io(&s->mem_bar, &lpc_smb_mmio_ops, s, "ich9-smbus-bar",
+ ICH9_SMB_SMB_BASE_SIZE);
+ pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
+ &s->mem_bar);
pm_smbus_init(&d->qdev, &s->smb);
return 0;
}
+static void ich9_smb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
+ k->revision = ICH9_A2_SMB_REVISION;
+ k->class_id = PCI_CLASS_SERIAL_SMBUS;
+ dc->no_user = 1;
+ dc->vmsd = &vmstate_ich9_smbus;
+ dc->desc = "ICH9 SMBUS Bridge";
+ k->init = ich9_smbus_initfn;
+}
+
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
@@ -137,18 +147,16 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
return s->smb.smbus;
}
-static PCIDeviceInfo ich9_smb_info = {
- .qdev.name = "ICH9 SMB",
- .qdev.desc = "ICH9 SMBUS Bridge",
- .qdev.size = sizeof(ICH9_SMBState),
- .qdev.vmsd = &vmstate_ich9_smbus,
- .qdev.no_user = 1,
- .init = ich9_smb_initfn,
+static const TypeInfo ich9_smb_info = {
+ .name = "ICH9 SMB",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(ICH9_SMBState),
+ .class_init = ich9_smb_class_init,
};
static void ich9_smb_register(void)
{
- pci_qdev_register(&ich9_smb_info);
+ type_register_static(&ich9_smb_info);
}
-device_init(ich9_smb_register);
+type_init(ich9_smb_register);
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* [Qemu-devel] [PATCH v2 14/21] q35: Suppress SMM BIOS initialization under KVM
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (12 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 13/21] q35: Re-base q35 Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:53 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 15/21] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
` (6 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 9e78b60..1412ad3 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -28,6 +28,7 @@
#include "qemu-timer.h"
#include "sysemu.h"
#include "acpi.h"
+#include "kvm.h"
#include "q35.h"
@@ -292,6 +293,12 @@ static void pm_reset(void *opaque)
acpi_pm_tmr_reset(&pm->acpi_regs);
acpi_gpe_reset(&pm->acpi_regs);
+ if (kvm_enabled()) {
+ /* Mark SMM as already inited to prevent SMM from running. KVM does not
+ * support SMM mode. */
+ pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
+ }
+
pm_update_sci(pm);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 14/21] q35: Suppress SMM BIOS initialization under KVM
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 14/21] q35: Suppress SMM BIOS initialization under KVM Jason Baron
@ 2012-10-09 7:53 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:53 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Same as for i44fx: KVM does not support SMM yet. Signal it initialized
> to Seabios to avoid failures.
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/acpi_ich9.c | 7 +++++++
> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 9e78b60..1412ad3 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -28,6 +28,7 @@
> #include "qemu-timer.h"
> #include "sysemu.h"
> #include "acpi.h"
> +#include "kvm.h"
>
> #include "q35.h"
>
> @@ -292,6 +293,12 @@ static void pm_reset(void *opaque)
> acpi_pm_tmr_reset(&pm->acpi_regs);
> acpi_gpe_reset(&pm->acpi_regs);
>
> + if (kvm_enabled()) {
> + /* Mark SMM as already inited to prevent SMM from running. KVM does not
> + * support SMM mode. */
> + pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
> + }
> +
> pm_update_sci(pm);
> }
>
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 15/21] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (13 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 14/21] q35: Suppress SMM BIOS initialization under KVM Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:53 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 17/21] q35: Add kvmclock support Jason Baron
` (5 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index ff570ce..5d256cb 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -663,9 +663,11 @@ static void ich9_lpc_update_apic(ICH9LPCIrqState *irq_state, int gsi)
{
GMCHPCIHost *s = container_of(irq_state, GMCHPCIHost, irq_state);
ICH9LPCState *lpc = irq_state->lpc;
- int level;
+ int level = 0;
- level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ if (gsi >= ICH9_LPC_PIC_NUM_PINS) {
+ level |= pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ }
if (gsi == ich9_lpc_sci_irq(lpc)) {
level |= lpc->sci_level;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 15/21] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 15/21] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
@ 2012-10-09 7:53 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:53 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
> an assertion.
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/q35.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/q35.c b/hw/q35.c
> index ff570ce..5d256cb 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -663,9 +663,11 @@ static void ich9_lpc_update_apic(ICH9LPCIrqState *irq_state, int gsi)
> {
> GMCHPCIHost *s = container_of(irq_state, GMCHPCIHost, irq_state);
> ICH9LPCState *lpc = irq_state->lpc;
> - int level;
> + int level = 0;
>
> - level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
> + if (gsi >= ICH9_LPC_PIC_NUM_PINS) {
> + level |= pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
> + }
> if (gsi == ich9_lpc_sci_irq(lpc)) {
> level |= lpc->sci_level;
> }
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 17/21] q35: Add kvmclock support
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (14 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 15/21] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:54 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
` (4 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc_q35.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index b6a619a..48083bb 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include "mc146818rtc.h"
#include "xen.h"
#include "kvm.h"
+#include "kvm/clock.h"
#include "q35.h"
#include "exec-memory.h"
@@ -357,6 +358,8 @@ static void pc_q35_init(ram_addr_t ram_size,
pc_cpus_init(cpu_model);
+ kvmclock_create();
+
if (ram_size >= 0xb0000000) {
above_4g_mem_size = ram_size - 0xb0000000;
below_4g_mem_size = 0xb0000000;
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 17/21] q35: Add kvmclock support
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 17/21] q35: Add kvmclock support Jason Baron
@ 2012-10-09 7:54 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:54 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pc_q35.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index b6a619a..48083bb 100644
> --- a/hw/pc_q35.c
> +++ b/hw/pc_q35.c
> @@ -69,6 +69,7 @@
> #include "mc146818rtc.h"
> #include "xen.h"
> #include "kvm.h"
> +#include "kvm/clock.h"
>
> #include "q35.h"
> #include "exec-memory.h"
> @@ -357,6 +358,8 @@ static void pc_q35_init(ram_addr_t ram_size,
>
> pc_cpus_init(cpu_model);
>
> + kvmclock_create();
> +
> if (ram_size >= 0xb0000000) {
> above_4g_mem_size = ram_size - 0xb0000000;
> below_4g_mem_size = 0xb0000000;
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (15 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 17/21] q35: Add kvmclock support Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:54 ` Paolo Bonzini
2012-10-11 14:53 ` Michael S. Tsirkin
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 19/21] Add a fallback bios file search, if -L fails Jason Baron
` (3 subsequent siblings)
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jan Kiszka <jan.kiszka@siemens.com>
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35_smbus.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
index 5efbe6c..dd64aa2 100644
--- a/hw/q35_smbus.c
+++ b/hw/q35_smbus.c
@@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d)
pci_set_word(d->wmask + PCI_STATUS,
PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+ pci_set_word(d->w1cmask + PCI_STATUS,
+ pci_get_word(d->w1cmask + PCI_STATUS) &
+ ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY));
+
/* TODO? D31IP.SMIP in chipset configuration space */
pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
@ 2012-10-09 7:54 ` Paolo Bonzini
2012-10-11 14:53 ` Michael S. Tsirkin
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:54 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Both bits are added to the write-1-to-clear mask by default. As the
> smbus device does not allow writes at all, we have to remove it from
> that mask, also to avoid triggering a runtime assertion.
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/q35_smbus.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
> index 5efbe6c..dd64aa2 100644
> --- a/hw/q35_smbus.c
> +++ b/hw/q35_smbus.c
> @@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d)
>
> pci_set_word(d->wmask + PCI_STATUS,
> PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> + pci_set_word(d->w1cmask + PCI_STATUS,
> + pci_get_word(d->w1cmask + PCI_STATUS) &
> + ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY));
> +
> /* TODO? D31IP.SMIP in chipset configuration space */
> pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
>
>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
2012-10-09 7:54 ` Paolo Bonzini
@ 2012-10-11 14:53 ` Michael S. Tsirkin
2012-10-19 15:13 ` Jason Baron
1 sibling, 1 reply; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 14:53 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 08, 2012 at 11:30:36PM -0400, Jason Baron wrote:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Both bits are added to the write-1-to-clear mask by default. As the
> smbus device does not allow writes at all, we have to remove it from
> that mask, also to avoid triggering a runtime assertion.
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Yes but a bugger question for me is why are these writeable
while spec says they are W1C?
Could you please add a code comment explaining that?
> ---
> hw/q35_smbus.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
> index 5efbe6c..dd64aa2 100644
> --- a/hw/q35_smbus.c
> +++ b/hw/q35_smbus.c
> @@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d)
>
> pci_set_word(d->wmask + PCI_STATUS,
> PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> + pci_set_word(d->w1cmask + PCI_STATUS,
> + pci_get_word(d->w1cmask + PCI_STATUS) &
> + ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY));
> +
> /* TODO? D31IP.SMIP in chipset configuration space */
> pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
>
> --
> 1.7.1
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-10-11 14:53 ` Michael S. Tsirkin
@ 2012-10-19 15:13 ` Jason Baron
2012-10-19 16:17 ` Isaku Yamahata
0 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-19 15:13 UTC (permalink / raw)
To: Michael S. Tsirkin, yamahata
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 04:53:24PM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 11:30:36PM -0400, Jason Baron wrote:
> > From: Jan Kiszka <jan.kiszka@siemens.com>
> >
> > Both bits are added to the write-1-to-clear mask by default. As the
> > smbus device does not allow writes at all, we have to remove it from
> > that mask, also to avoid triggering a runtime assertion.
> >
> > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>
> Yes but a bugger question for me is why are these writeable
> while spec says they are W1C?
> Could you please add a code comment explaining that?
>
Spec has these bits as: 'R/WC'. So I think you are right. We should drop
the wmask setting. Also, I think the setting of w1cmask is inverted.
Shouldn't we be setting the bits in w1cmask, not clearing them?
Yamahata, any reason not to drop the setting of wmask here?
Thanks,
-Jason
> > ---
> > hw/q35_smbus.c | 4 ++++
> > 1 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
> > index 5efbe6c..dd64aa2 100644
> > --- a/hw/q35_smbus.c
> > +++ b/hw/q35_smbus.c
> > @@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d)
> >
> > pci_set_word(d->wmask + PCI_STATUS,
> > PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> > + pci_set_word(d->w1cmask + PCI_STATUS,
> > + pci_get_word(d->w1cmask + PCI_STATUS) &
> > + ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY));
> > +
> > /* TODO? D31IP.SMIP in chipset configuration space */
> > pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
> >
> > --
> > 1.7.1
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-10-19 15:13 ` Jason Baron
@ 2012-10-19 16:17 ` Isaku Yamahata
0 siblings, 0 replies; 65+ messages in thread
From: Isaku Yamahata @ 2012-10-19 16:17 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, Michael S. Tsirkin, jan.kiszka, qemu-devel,
agraf, blauwirbel, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, armbru, kraxel
On Fri, Oct 19, 2012 at 11:13:53AM -0400, Jason Baron wrote:
> On Thu, Oct 11, 2012 at 04:53:24PM +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 08, 2012 at 11:30:36PM -0400, Jason Baron wrote:
> > > From: Jan Kiszka <jan.kiszka@siemens.com>
> > >
> > > Both bits are added to the write-1-to-clear mask by default. As the
> > > smbus device does not allow writes at all, we have to remove it from
> > > that mask, also to avoid triggering a runtime assertion.
> > >
> > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> > > Signed-off-by: Jason Baron <jbaron@redhat.com>
> >
> > Yes but a bugger question for me is why are these writeable
> > while spec says they are W1C?
> > Could you please add a code comment explaining that?
> >
>
> Spec has these bits as: 'R/WC'. So I think you are right. We should drop
> the wmask setting. Also, I think the setting of w1cmask is inverted.
> Shouldn't we be setting the bits in w1cmask, not clearing them?
>
> Yamahata, any reason not to drop the setting of wmask here?
No reason. Let's drop it.
--
yamahata
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 19/21] Add a fallback bios file search, if -L fails.
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (16 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 16/21] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:59 ` Paolo Bonzini
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31 Jason Baron
` (2 subsequent siblings)
20 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
vl.c | 36 +++++++++++++++++++++++++-----------
1 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/vl.c b/vl.c
index 77af809..704cff9 100644
--- a/vl.c
+++ b/vl.c
@@ -177,6 +177,7 @@ int main(int argc, char **argv)
#define MAX_VIRTIO_CONSOLES 1
static const char *data_dir;
+static const char *data_dir_fallback;
const char *bios_name = NULL;
enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
DisplayType display_type = DT_DEFAULT;
@@ -1882,16 +1883,16 @@ static int balloon_parse(const char *arg)
return -1;
}
-char *qemu_find_file(int type, const char *name)
+static char *qemu_find_file_in_dir(int type, const char *name, const char *dir)
{
int len;
const char *subdir;
char *buf;
- /* Try the name as a straight path first */
- if (access(name, R_OK) == 0) {
- return g_strdup(name);
+ if (!dir) {
+ return NULL;
}
+
switch (type) {
case QEMU_FILE_TYPE_BIOS:
subdir = "";
@@ -1902,9 +1903,9 @@ char *qemu_find_file(int type, const char *name)
default:
abort();
}
- len = strlen(data_dir) + strlen(name) + strlen(subdir) + 2;
+ len = strlen(dir) + strlen(name) + strlen(subdir) + 2;
buf = g_malloc0(len);
- snprintf(buf, len, "%s/%s%s", data_dir, subdir, name);
+ snprintf(buf, len, "%s/%s%s", dir, subdir, name);
if (access(buf, R_OK)) {
g_free(buf);
return NULL;
@@ -1912,6 +1913,21 @@ char *qemu_find_file(int type, const char *name)
return buf;
}
+char *qemu_find_file(int type, const char *name)
+{
+ char *filename;
+
+ /* Try the name as a straight path first */
+ if (access(name, R_OK) == 0) {
+ return g_strdup(name);
+ }
+ filename = qemu_find_file_in_dir(type, name, data_dir);
+ if (!filename) {
+ filename = qemu_find_file_in_dir(type, name, data_dir_fallback);
+ }
+ return filename;
+}
+
static int device_help_func(QemuOpts *opts, void *opaque)
{
return qdev_device_help(opts);
@@ -3349,12 +3365,10 @@ int main(int argc, char **argv, char **envp)
/* If no data_dir is specified then try to find it relative to the
executable path. */
- if (!data_dir) {
- data_dir = os_find_datadir(argv[0]);
- }
+ data_dir_fallback = os_find_datadir(argv[0]);
/* If all else fails use the install path specified when building. */
- if (!data_dir) {
- data_dir = CONFIG_QEMU_DATADIR;
+ if (!data_dir_fallback) {
+ data_dir_fallback = CONFIG_QEMU_DATADIR;
}
/*
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 19/21] Add a fallback bios file search, if -L fails.
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 19/21] Add a fallback bios file search, if -L fails Jason Baron
@ 2012-10-09 7:59 ` Paolo Bonzini
0 siblings, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:59 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
> the search fails. Add infrastructure such that the search will continue in
> the default paths, if not found in the -L path.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> vl.c | 36 +++++++++++++++++++++++++-----------
> 1 files changed, 25 insertions(+), 11 deletions(-)
>
> diff --git a/vl.c b/vl.c
> index 77af809..704cff9 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -177,6 +177,7 @@ int main(int argc, char **argv)
> #define MAX_VIRTIO_CONSOLES 1
>
> static const char *data_dir;
> +static const char *data_dir_fallback;
> const char *bios_name = NULL;
> enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
> DisplayType display_type = DT_DEFAULT;
> @@ -1882,16 +1883,16 @@ static int balloon_parse(const char *arg)
> return -1;
> }
>
> -char *qemu_find_file(int type, const char *name)
> +static char *qemu_find_file_in_dir(int type, const char *name, const char *dir)
> {
> int len;
> const char *subdir;
> char *buf;
>
> - /* Try the name as a straight path first */
> - if (access(name, R_OK) == 0) {
> - return g_strdup(name);
> + if (!dir) {
> + return NULL;
> }
> +
> switch (type) {
> case QEMU_FILE_TYPE_BIOS:
> subdir = "";
> @@ -1902,9 +1903,9 @@ char *qemu_find_file(int type, const char *name)
> default:
> abort();
> }
> - len = strlen(data_dir) + strlen(name) + strlen(subdir) + 2;
> + len = strlen(dir) + strlen(name) + strlen(subdir) + 2;
> buf = g_malloc0(len);
> - snprintf(buf, len, "%s/%s%s", data_dir, subdir, name);
> + snprintf(buf, len, "%s/%s%s", dir, subdir, name);
> if (access(buf, R_OK)) {
> g_free(buf);
> return NULL;
> @@ -1912,6 +1913,21 @@ char *qemu_find_file(int type, const char *name)
> return buf;
> }
>
> +char *qemu_find_file(int type, const char *name)
> +{
> + char *filename;
> +
> + /* Try the name as a straight path first */
> + if (access(name, R_OK) == 0) {
> + return g_strdup(name);
> + }
> + filename = qemu_find_file_in_dir(type, name, data_dir);
> + if (!filename) {
> + filename = qemu_find_file_in_dir(type, name, data_dir_fallback);
> + }
> + return filename;
> +}
> +
> static int device_help_func(QemuOpts *opts, void *opaque)
> {
> return qdev_device_help(opts);
> @@ -3349,12 +3365,10 @@ int main(int argc, char **argv, char **envp)
>
> /* If no data_dir is specified then try to find it relative to the
> executable path. */
> - if (!data_dir) {
> - data_dir = os_find_datadir(argv[0]);
> - }
> + data_dir_fallback = os_find_datadir(argv[0]);
> /* If all else fails use the install path specified when building. */
> - if (!data_dir) {
> - data_dir = CONFIG_QEMU_DATADIR;
> + if (!data_dir_fallback) {
> + data_dir_fallback = CONFIG_QEMU_DATADIR;
> }
>
> /*
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (17 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 19/21] Add a fallback bios file search, if -L fails Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 7:58 ` Paolo Bonzini
2012-10-11 14:49 ` Michael S. Tsirkin
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table Jason Baron
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug Jason Baron
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Isaku Yamahata <yamahata@valinux.co.jp>
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35.c | 29 ++++++++++++++++++++---------
1 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index 5d256cb..e4f313e 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -480,7 +480,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
* Although it's not pci configuration space, it's little endian as Intel.
*/
-static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
+static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
{
int intx;
for (intx = 0; intx < PCI_NUM_PINS; intx++) {
@@ -491,15 +491,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
static void ich9_cc_update(ICH9LPCState *lpc)
{
int slot;
- int reg_offset;
- int intx;
+ int pci_intx;
+
+ const int reg_offsets[] = {
+ ICH9_CC_D25IR,
+ ICH9_CC_D26IR,
+ ICH9_CC_D27IR,
+ ICH9_CC_D28IR,
+ ICH9_CC_D29IR,
+ ICH9_CC_D30IR,
+ ICH9_CC_D31IR,
+ };
+ const int *offset;
/* D{25 - 31}IR, but D30IR is read only to 0. */
- for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
- if (slot != 30) {
- ich9_cc_update_ir(lpc->irr[slot],
- lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+ for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
+ if (slot == 30) {
+ continue;
}
+ ich9_cc_update_ir(lpc->irr[slot],
+ pci_get_word(lpc->chip_config + *offset));
}
/*
@@ -508,8 +519,8 @@ static void ich9_cc_update(ICH9LPCState *lpc)
* are connected to pirq lines. Our choice is PIRQ[E-H].
* INT[A-D] are connected to PIRQ[E-H]
*/
- for (intx = 0; intx < PCI_NUM_PINS; intx++) {
- lpc->irr[30][intx] = intx + 4;
+ for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
+ lpc->irr[30][pci_intx] = pci_intx + 4;
}
}
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31 Jason Baron
@ 2012-10-09 7:58 ` Paolo Bonzini
2012-10-11 14:49 ` Michael S. Tsirkin
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 7:58 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
>
> Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> hw/q35.c | 29 ++++++++++++++++++++---------
> 1 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/hw/q35.c b/hw/q35.c
> index 5d256cb..e4f313e 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -480,7 +480,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
> * Although it's not pci configuration space, it's little endian as Intel.
> */
>
> -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
> {
> int intx;
> for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> @@ -491,15 +491,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> static void ich9_cc_update(ICH9LPCState *lpc)
> {
> int slot;
> - int reg_offset;
> - int intx;
> + int pci_intx;
> +
> + const int reg_offsets[] = {
> + ICH9_CC_D25IR,
> + ICH9_CC_D26IR,
> + ICH9_CC_D27IR,
> + ICH9_CC_D28IR,
> + ICH9_CC_D29IR,
> + ICH9_CC_D30IR,
> + ICH9_CC_D31IR,
> + };
> + const int *offset;
>
> /* D{25 - 31}IR, but D30IR is read only to 0. */
> - for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> - if (slot != 30) {
> - ich9_cc_update_ir(lpc->irr[slot],
> - lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> + for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
> + if (slot == 30) {
> + continue;
> }
> + ich9_cc_update_ir(lpc->irr[slot],
> + pci_get_word(lpc->chip_config + *offset));
> }
>
> /*
> @@ -508,8 +519,8 @@ static void ich9_cc_update(ICH9LPCState *lpc)
> * are connected to pirq lines. Our choice is PIRQ[E-H].
> * INT[A-D] are connected to PIRQ[E-H]
> */
> - for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> - lpc->irr[30][intx] = intx + 4;
> + for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
> + lpc->irr[30][pci_intx] = pci_intx + 4;
> }
> }
>
>
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31 Jason Baron
2012-10-09 7:58 ` Paolo Bonzini
@ 2012-10-11 14:49 ` Michael S. Tsirkin
1 sibling, 0 replies; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 14:49 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 08, 2012 at 11:30:37PM -0400, Jason Baron wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
>
> Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Probably should be smashed into the original patch too?
More contained so less critical.
> ---
> hw/q35.c | 29 ++++++++++++++++++++---------
> 1 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/hw/q35.c b/hw/q35.c
> index 5d256cb..e4f313e 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -480,7 +480,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
> * Although it's not pci configuration space, it's little endian as Intel.
> */
>
> -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
> {
> int intx;
> for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> @@ -491,15 +491,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> static void ich9_cc_update(ICH9LPCState *lpc)
> {
> int slot;
> - int reg_offset;
> - int intx;
> + int pci_intx;
> +
> + const int reg_offsets[] = {
> + ICH9_CC_D25IR,
> + ICH9_CC_D26IR,
> + ICH9_CC_D27IR,
> + ICH9_CC_D28IR,
> + ICH9_CC_D29IR,
> + ICH9_CC_D30IR,
> + ICH9_CC_D31IR,
> + };
> + const int *offset;
>
> /* D{25 - 31}IR, but D30IR is read only to 0. */
> - for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> - if (slot != 30) {
> - ich9_cc_update_ir(lpc->irr[slot],
> - lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> + for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
> + if (slot == 30) {
> + continue;
> }
> + ich9_cc_update_ir(lpc->irr[slot],
> + pci_get_word(lpc->chip_config + *offset));
> }
>
> /*
> @@ -508,8 +519,8 @@ static void ich9_cc_update(ICH9LPCState *lpc)
> * are connected to pirq lines. Our choice is PIRQ[E-H].
> * INT[A-D] are connected to PIRQ[E-H]
> */
> - for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> - lpc->irr[30][intx] = intx + 4;
> + for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
> + lpc->irr[30][pci_intx] = pci_intx + 4;
> }
> }
>
> --
> 1.7.1
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (18 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 18/21] q35: Fix irr initialization for slots 25..31 Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 8:02 ` Paolo Bonzini
2012-10-13 8:33 ` Blue Swirl
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug Jason Baron
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 19 +++++++++++++++++++
hw/pc.h | 2 ++
hw/pc_piix.c | 7 +++++++
hw/pc_q35.c | 7 +++++++
4 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index f5fbd0c..4ee41a1 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1172,3 +1172,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
}
}
+
+int find_and_load_dsdt(const char *dsdt_name)
+{
+ char *filename;
+ char buf[1024];
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
+ if (!filename) {
+ return -1;
+ }
+ snprintf(buf, 1024, "file=%s", filename);
+ g_free(filename);
+ if (acpi_table_add(buf) < 0) {
+ fprintf(stderr, "Wrong acpi table provided\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/hw/pc.h b/hw/pc.h
index 125c1fd..5e93ae1 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -227,5 +227,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
#define E820_UNUSABLE 5
int e820_add_entry(uint64_t, uint64_t, uint32_t);
+int find_and_load_dsdt(const char *dsdt_name);
+
#endif
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index e133630..06bb40e 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -126,6 +126,13 @@ static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *rom_memory;
void *fw_cfg = NULL;
+ /* let's first see if we can find the proper dsdt */
+ if (find_and_load_dsdt("acpi-dsdt.aml")) {
+ fprintf(stderr, "Couldn't find piix dsdt table!\n"
+ "Try updating your bios.\n");
+ exit(1);
+ }
+
pc_cpus_init(cpu_model);
if (kvmclock_enabled) {
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 48083bb..1f96af0 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -356,6 +356,13 @@ static void pc_q35_init(ram_addr_t ram_size,
qemu_irq *i8259;
int i;
+ /* let's first see if we can find the proper dsdt */
+ if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
+ fprintf(stderr, "Couldn't find q35 dsdt table!\n"
+ "Try updating your bios.\n");
+ exit(1);
+ }
+
pc_cpus_init(cpu_model);
kvmclock_create();
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table Jason Baron
@ 2012-10-09 8:02 ` Paolo Bonzini
2012-10-09 8:29 ` Paolo Bonzini
2012-10-09 20:06 ` Jason Baron
2012-10-13 8:33 ` Blue Swirl
1 sibling, 2 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 8:02 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> Automatically, locate the required q35 dsdt table on load. Otherwise we error
> out. This could be done in the bios, but its harder to produce a good error
> message.
Not just for q35, so the commit message is wrong, but the patch is
otherwise good.
We should import the source code for the DSDT from SeaBIOS, and support
building it + installing it. You made this a hard failure, so it has to
be done before this patch goes in, doesn't it?
Paolo
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pc.c | 19 +++++++++++++++++++
> hw/pc.h | 2 ++
> hw/pc_piix.c | 7 +++++++
> hw/pc_q35.c | 7 +++++++
> 4 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index f5fbd0c..4ee41a1 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1172,3 +1172,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
> gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> }
> }
> +
> +int find_and_load_dsdt(const char *dsdt_name)
> +{
> + char *filename;
> + char buf[1024];
> +
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
> + if (!filename) {
> + return -1;
> + }
> + snprintf(buf, 1024, "file=%s", filename);
> + g_free(filename);
> + if (acpi_table_add(buf) < 0) {
> + fprintf(stderr, "Wrong acpi table provided\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> diff --git a/hw/pc.h b/hw/pc.h
> index 125c1fd..5e93ae1 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -227,5 +227,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
> #define E820_UNUSABLE 5
>
> int e820_add_entry(uint64_t, uint64_t, uint32_t);
> +int find_and_load_dsdt(const char *dsdt_name);
> +
>
> #endif
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index e133630..06bb40e 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -126,6 +126,13 @@ static void pc_init1(MemoryRegion *system_memory,
> MemoryRegion *rom_memory;
> void *fw_cfg = NULL;
>
> + /* let's first see if we can find the proper dsdt */
> + if (find_and_load_dsdt("acpi-dsdt.aml")) {
> + fprintf(stderr, "Couldn't find piix dsdt table!\n"
> + "Try updating your bios.\n");
> + exit(1);
> + }
> +
> pc_cpus_init(cpu_model);
>
> if (kvmclock_enabled) {
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index 48083bb..1f96af0 100644
> --- a/hw/pc_q35.c
> +++ b/hw/pc_q35.c
> @@ -356,6 +356,13 @@ static void pc_q35_init(ram_addr_t ram_size,
> qemu_irq *i8259;
> int i;
>
> + /* let's first see if we can find the proper dsdt */
> + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
> + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
> + "Try updating your bios.\n");
> + exit(1);
> + }
> +
> pc_cpus_init(cpu_model);
>
> kvmclock_create();
>
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table
2012-10-09 8:02 ` Paolo Bonzini
@ 2012-10-09 8:29 ` Paolo Bonzini
2012-10-09 20:06 ` Jason Baron
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 8:29 UTC (permalink / raw)
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, agraf, blauwirbel, yamahata, juzhang, kevin, avi,
mkletzan, lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 10:02, Paolo Bonzini ha scritto:
> Il 09/10/2012 05:30, Jason Baron ha scritto:
>> From: Jason Baron <jbaron@redhat.com>
>>
>> Automatically, locate the required q35 dsdt table on load. Otherwise we error
>> out. This could be done in the bios, but its harder to produce a good error
>> message.
>
> Not just for q35, so the commit message is wrong, but the patch is
> otherwise good.
>
> We should import the source code for the DSDT from SeaBIOS, and support
> building it + installing it. You made this a hard failure, so it has to
> be done before this patch goes in, doesn't it?
Ah, having reviewed the SeaBIOS series I now see that you're keeping the
code in SeaBIOS but installing it alongside bios.bin. This makes sense
since, at least for backwards compatibility, the PIIX DSDT will remain
in bios.bin for a while.
However, you still need to patch QEMU's roms/Makefile to copy the .aml
files to pc-bios, and the Makefile to install it (in both cases, just
grep for bios.bin).
Paolo
>
> Paolo
>
>> Signed-off-by: Jason Baron <jbaron@redhat.com>
>> ---
>> hw/pc.c | 19 +++++++++++++++++++
>> hw/pc.h | 2 ++
>> hw/pc_piix.c | 7 +++++++
>> hw/pc_q35.c | 7 +++++++
>> 4 files changed, 35 insertions(+), 0 deletions(-)
>>
>> diff --git a/hw/pc.c b/hw/pc.c
>> index f5fbd0c..4ee41a1 100644
>> --- a/hw/pc.c
>> +++ b/hw/pc.c
>> @@ -1172,3 +1172,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
>> gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
>> }
>> }
>> +
>> +int find_and_load_dsdt(const char *dsdt_name)
>> +{
>> + char *filename;
>> + char buf[1024];
>> +
>> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
>> + if (!filename) {
>> + return -1;
>> + }
>> + snprintf(buf, 1024, "file=%s", filename);
>> + g_free(filename);
>> + if (acpi_table_add(buf) < 0) {
>> + fprintf(stderr, "Wrong acpi table provided\n");
>> + return -1;
>> + }
>> +
>> + return 0;
>> +}
>> diff --git a/hw/pc.h b/hw/pc.h
>> index 125c1fd..5e93ae1 100644
>> --- a/hw/pc.h
>> +++ b/hw/pc.h
>> @@ -227,5 +227,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
>> #define E820_UNUSABLE 5
>>
>> int e820_add_entry(uint64_t, uint64_t, uint32_t);
>> +int find_and_load_dsdt(const char *dsdt_name);
>> +
>>
>> #endif
>> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
>> index e133630..06bb40e 100644
>> --- a/hw/pc_piix.c
>> +++ b/hw/pc_piix.c
>> @@ -126,6 +126,13 @@ static void pc_init1(MemoryRegion *system_memory,
>> MemoryRegion *rom_memory;
>> void *fw_cfg = NULL;
>>
>> + /* let's first see if we can find the proper dsdt */
>> + if (find_and_load_dsdt("acpi-dsdt.aml")) {
>> + fprintf(stderr, "Couldn't find piix dsdt table!\n"
>> + "Try updating your bios.\n");
>> + exit(1);
>> + }
>> +
>> pc_cpus_init(cpu_model);
>>
>> if (kvmclock_enabled) {
>> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
>> index 48083bb..1f96af0 100644
>> --- a/hw/pc_q35.c
>> +++ b/hw/pc_q35.c
>> @@ -356,6 +356,13 @@ static void pc_q35_init(ram_addr_t ram_size,
>> qemu_irq *i8259;
>> int i;
>>
>> + /* let's first see if we can find the proper dsdt */
>> + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
>> + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
>> + "Try updating your bios.\n");
>> + exit(1);
>> + }
>> +
>> pc_cpus_init(cpu_model);
>>
>> kvmclock_create();
>>
>
>
>
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table
2012-10-09 8:02 ` Paolo Bonzini
2012-10-09 8:29 ` Paolo Bonzini
@ 2012-10-09 20:06 ` Jason Baron
1 sibling, 0 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 20:06 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
On Tue, Oct 09, 2012 at 10:02:50AM +0200, Paolo Bonzini wrote:
> Il 09/10/2012 05:30, Jason Baron ha scritto:
> > From: Jason Baron <jbaron@redhat.com>
> >
> > Automatically, locate the required q35 dsdt table on load. Otherwise we error
> > out. This could be done in the bios, but its harder to produce a good error
> > message.
>
> Not just for q35, so the commit message is wrong, but the patch is
> otherwise good.
>
> We should import the source code for the DSDT from SeaBIOS, and support
> building it + installing it. You made this a hard failure, so it has to
> be done before this patch goes in, doesn't it?
>
Right, so perhaps this patch is held off until the SeaBIOS changes are
in place, and q35 can still be invoked via -acpitable file=<q35 dsdttable>,
in the meantime.
On the other hand, this patch will work with the '-L' option supplied to
the updated SeaBIOS dir, without the .aml built into qemu. That seems
reasonable to me as well.
Thanks,
-Jason
> Paolo
>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > ---
> > hw/pc.c | 19 +++++++++++++++++++
> > hw/pc.h | 2 ++
> > hw/pc_piix.c | 7 +++++++
> > hw/pc_q35.c | 7 +++++++
> > 4 files changed, 35 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/pc.c b/hw/pc.c
> > index f5fbd0c..4ee41a1 100644
> > --- a/hw/pc.c
> > +++ b/hw/pc.c
> > @@ -1172,3 +1172,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
> > gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> > }
> > }
> > +
> > +int find_and_load_dsdt(const char *dsdt_name)
> > +{
> > + char *filename;
> > + char buf[1024];
> > +
> > + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
> > + if (!filename) {
> > + return -1;
> > + }
> > + snprintf(buf, 1024, "file=%s", filename);
> > + g_free(filename);
> > + if (acpi_table_add(buf) < 0) {
> > + fprintf(stderr, "Wrong acpi table provided\n");
> > + return -1;
> > + }
> > +
> > + return 0;
> > +}
> > diff --git a/hw/pc.h b/hw/pc.h
> > index 125c1fd..5e93ae1 100644
> > --- a/hw/pc.h
> > +++ b/hw/pc.h
> > @@ -227,5 +227,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
> > #define E820_UNUSABLE 5
> >
> > int e820_add_entry(uint64_t, uint64_t, uint32_t);
> > +int find_and_load_dsdt(const char *dsdt_name);
> > +
> >
> > #endif
> > diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> > index e133630..06bb40e 100644
> > --- a/hw/pc_piix.c
> > +++ b/hw/pc_piix.c
> > @@ -126,6 +126,13 @@ static void pc_init1(MemoryRegion *system_memory,
> > MemoryRegion *rom_memory;
> > void *fw_cfg = NULL;
> >
> > + /* let's first see if we can find the proper dsdt */
> > + if (find_and_load_dsdt("acpi-dsdt.aml")) {
> > + fprintf(stderr, "Couldn't find piix dsdt table!\n"
> > + "Try updating your bios.\n");
> > + exit(1);
> > + }
> > +
> > pc_cpus_init(cpu_model);
> >
> > if (kvmclock_enabled) {
> > diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> > index 48083bb..1f96af0 100644
> > --- a/hw/pc_q35.c
> > +++ b/hw/pc_q35.c
> > @@ -356,6 +356,13 @@ static void pc_q35_init(ram_addr_t ram_size,
> > qemu_irq *i8259;
> > int i;
> >
> > + /* let's first see if we can find the proper dsdt */
> > + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
> > + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
> > + "Try updating your bios.\n");
> > + exit(1);
> > + }
> > +
> > pc_cpus_init(cpu_model);
> >
> > kvmclock_create();
> >
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table Jason Baron
2012-10-09 8:02 ` Paolo Bonzini
@ 2012-10-13 8:33 ` Blue Swirl
1 sibling, 0 replies; 65+ messages in thread
From: Blue Swirl @ 2012-10-13 8:33 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, pbonzini, lcapitulino,
afaerber, armbru, kraxel
On Tue, Oct 9, 2012 at 3:30 AM, Jason Baron <jbaron@redhat.com> wrote:
> From: Jason Baron <jbaron@redhat.com>
>
> Automatically, locate the required q35 dsdt table on load. Otherwise we error
> out. This could be done in the bios, but its harder to produce a good error
> message.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pc.c | 19 +++++++++++++++++++
> hw/pc.h | 2 ++
> hw/pc_piix.c | 7 +++++++
> hw/pc_q35.c | 7 +++++++
> 4 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index f5fbd0c..4ee41a1 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -1172,3 +1172,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
> gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
> }
> }
> +
> +int find_and_load_dsdt(const char *dsdt_name)
> +{
> + char *filename;
> + char buf[1024];
> +
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
> + if (!filename) {
> + return -1;
> + }
> + snprintf(buf, 1024, "file=%s", filename);
Please use sizeof(buf) instead of 1024, or introduce a constant.
> + g_free(filename);
> + if (acpi_table_add(buf) < 0) {
> + fprintf(stderr, "Wrong acpi table provided\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> diff --git a/hw/pc.h b/hw/pc.h
> index 125c1fd..5e93ae1 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -227,5 +227,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);
> #define E820_UNUSABLE 5
>
> int e820_add_entry(uint64_t, uint64_t, uint32_t);
> +int find_and_load_dsdt(const char *dsdt_name);
> +
>
> #endif
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index e133630..06bb40e 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -126,6 +126,13 @@ static void pc_init1(MemoryRegion *system_memory,
> MemoryRegion *rom_memory;
> void *fw_cfg = NULL;
>
> + /* let's first see if we can find the proper dsdt */
> + if (find_and_load_dsdt("acpi-dsdt.aml")) {
> + fprintf(stderr, "Couldn't find piix dsdt table!\n"
> + "Try updating your bios.\n");
> + exit(1);
> + }
> +
> pc_cpus_init(cpu_model);
>
> if (kvmclock_enabled) {
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index 48083bb..1f96af0 100644
> --- a/hw/pc_q35.c
> +++ b/hw/pc_q35.c
> @@ -356,6 +356,13 @@ static void pc_q35_init(ram_addr_t ram_size,
> qemu_irq *i8259;
> int i;
>
> + /* let's first see if we can find the proper dsdt */
> + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
> + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
> + "Try updating your bios.\n");
> + exit(1);
> + }
> +
> pc_cpus_init(cpu_model);
>
> kvmclock_create();
> --
> 1.7.1
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-09 3:30 [Qemu-devel] [PATCH v2 00/21] q35 qemu support Jason Baron
` (19 preceding siblings ...)
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 20/21] q35: automatically load the q35 dsdt table Jason Baron
@ 2012-10-09 3:30 ` Jason Baron
2012-10-09 8:04 ` Paolo Bonzini
2012-10-11 10:57 ` Michael S. Tsirkin
20 siblings, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-09 3:30 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, juzhang, mst, jan.kiszka, armbru, agraf, blauwirbel,
yamahata, alex.williamson, kevin, avi, mkletzan, pbonzini,
lcapitulino, afaerber, kraxel
From: Jason Baron <jbaron@redhat.com>
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
hw/acpi_ich9.h | 10 +++
2 files changed, 181 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 1412ad3..412c9c1 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#define ICH9_DEBUG(fmt, ...) do { } while (0)
#endif
+#define PCI_UP_BASE 0xae00
+#define PCI_DOWN_BASE 0xae04
+#define PCI_EJ_BASE 0xae08
+#define PCI_RMV_BASE 0xae0c
+#define ICH9_PCI_HOTPLUG_STATUS 2
+
+
static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
uint32_t val);
static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
@@ -55,7 +62,10 @@ static void pm_update_sci(ICH9LPCPMRegs *pm)
(ACPI_BITMASK_RT_CLOCK_ENABLE |
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
- ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
+ (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0])
+ & ICH9_PCI_HOTPLUG_STATUS) != 0);
+
qemu_set_irq(pm->irq, sci_level);
/* schedule a timer interruption if needed */
@@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
+ pm_update_sci(pm);
break;
default:
break;
@@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = {
}
};
+static void acpi_ich9_eject_slot(ICH9LPCPMRegs *opaque, unsigned slots)
+{
+ BusChild *kid, *next;
+ ICH9LPCPMRegs *pm = opaque;
+ ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
+ PCIDevice *s = PCI_DEVICE(lpc);
+ BusState *bus = qdev_get_parent_bus(&s->qdev);
+ int slot = ffs(slots) - 1;
+ bool slot_free = true;
+
+ /* Mark request as complete */
+ pm->pci0_status.down &= ~(1U << slot);
+
+ QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+ DeviceState *qdev = kid->child;
+ PCIDevice *dev = PCI_DEVICE(qdev);
+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
+ if (PCI_SLOT(dev->devfn) == slot) {
+ if (pc->no_hotplug) {
+ slot_free = false;
+ } else {
+ qdev_free(qdev);
+ }
+ }
+ }
+ if (slot_free) {
+ pm->pci0_slot_device_present &= ~(1U << slot);
+ }
+}
+
+static void acpi_ich9_update_hotplug(ICH9LPCPMRegs *pm)
+{
+ ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
+ PCIDevice *dev = PCI_DEVICE(lpc);
+ BusState *bus = qdev_get_parent_bus(&dev->qdev);
+ BusChild *kid, *next;
+
+ /* Execute any pending removes during reset */
+ while (pm->pci0_status.down) {
+ acpi_ich9_eject_slot(pm, pm->pci0_status.down);
+ }
+
+ pm->pci0_hotplug_enable = ~0;
+ pm->pci0_slot_device_present = 0;
+
+ QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+ DeviceState *qdev = kid->child;
+ PCIDevice *pdev = PCI_DEVICE(qdev);
+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
+ int slot = PCI_SLOT(pdev->devfn);
+
+ if (pc->no_hotplug) {
+ pm->pci0_hotplug_enable &= ~(1U << slot);
+ }
+
+ pm->pci0_slot_device_present |= (1U << slot);
+ }
+}
+
static void pm_reset(void *opaque)
{
ICH9LPCPMRegs *pm = opaque;
@@ -300,6 +370,7 @@ static void pm_reset(void *opaque)
}
pm_update_sci(pm);
+ acpi_ich9_update_hotplug(pm);
}
static void pm_powerdown_req(Notifier *n, void *opaque)
@@ -309,6 +380,104 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
+static uint32_t pci_up_read(void *opaque, uint32_t addr)
+{
+ ICH9LPCPMRegs *pm = opaque;
+ uint32_t val;
+
+ /* Manufacture an "up" value to cause a device check on any hotplug
+ * slot with a device. Extra device checks are harmless. */
+ val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable;
+
+ ICH9_DEBUG("pci_up_read %x\n", val);
+ return val;
+}
+
+static uint32_t pci_down_read(void *opaque, uint32_t addr)
+{
+ ICH9LPCPMRegs *pm = opaque;
+ uint32_t val = pm->pci0_status.down;
+
+ ICH9_DEBUG("pci_down_read %x\n", val);
+ return val;
+}
+
+static uint32_t pci_features_read(void *opaque, uint32_t addr)
+{
+ /* No feature defined yet */
+ ICH9_DEBUG("pci_features_read %x\n", 0);
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ acpi_ich9_eject_slot(opaque, val);
+
+ ICH9_DEBUG("pciej write %x <== %d\n", addr, val);
+}
+
+static uint32_t pcirmv_read(void *opaque, uint32_t addr)
+{
+ ICH9LPCPMRegs *pm = opaque;
+
+ return pm->pci0_hotplug_enable;
+}
+
+static void enable_device(ICH9LPCPMRegs *pm, int slot)
+{
+ pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
+ pm->pci0_slot_device_present |= (1U << slot);
+}
+
+static void disable_device(ICH9LPCPMRegs *pm, int slot)
+{
+ pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
+ pm->pci0_status.down |= (1U << slot);
+}
+
+static int ich9_device_hotplug(DeviceState *qdev, PCIDevice *dev,
+ PCIHotplugState state)
+{
+ int slot = PCI_SLOT(dev->devfn);
+ ICH9LPCState *lpc = DO_UPCAST(ICH9LPCState, d,
+ PCI_DEVICE(qdev));
+ ICH9LPCPMRegs *pm = &lpc->pm;
+
+ /* Don't send event when device is enabled during qemu machine creation:
+ * it is present on boot, no hotplug event is necessary. We do send an
+ * event when the device is disabled later. */
+ if (state == PCI_COLDPLUG_ENABLED) {
+ pm->pci0_slot_device_present |= (1U << slot);
+ return 0;
+ }
+
+ if (state == PCI_HOTPLUG_ENABLED) {
+ enable_device(pm, slot);
+ } else {
+ disable_device(pm, slot);
+ }
+
+ pm_update_sci(pm);
+
+ return 0;
+}
+
+static void ich9_acpi_system_hot_add_init(ICH9LPCPMRegs *s)
+{
+ ICH9LPCState *lpc = container_of(s, ICH9LPCState, pm);
+ PCIDevice *pdev = PCI_DEVICE(lpc);
+
+ register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
+ register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
+
+ register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
+
+ pci_bus_hotplug(pdev->bus, ich9_device_hotplug, &pdev->qdev);
+}
+
void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
@@ -319,4 +488,5 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
qemu_register_reset(pm_reset, pm);
pm->powerdown_notifier.notify = pm_powerdown_req;
qemu_register_powerdown_notifier(&pm->powerdown_notifier);
+ ich9_acpi_system_hot_add_init(pm);
}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
index 180c406..b4e2aff 100644
--- a/hw/acpi_ich9.h
+++ b/hw/acpi_ich9.h
@@ -23,6 +23,11 @@
#include "acpi.h"
+struct pci_status {
+ uint32_t up; /* deprecated, maintained for migration compatibility */
+ uint32_t down;
+};
+
typedef struct ICH9LPCPMRegs {
/*
* In ich9 spec says that pm1_cnt register is 32bit width and
@@ -37,6 +42,11 @@ typedef struct ICH9LPCPMRegs {
uint32_t pm_io_base;
Notifier powerdown_notifier;
+
+ /* for pci hotplug */
+ struct pci_status pci0_status;
+ uint32_t pci0_hotplug_enable;
+ uint32_t pci0_slot_device_present;
} ICH9LPCPMRegs;
void ich9_pm_init(ICH9LPCPMRegs *pm,
--
1.7.1
^ permalink raw reply related [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug Jason Baron
@ 2012-10-09 8:04 ` Paolo Bonzini
2012-10-11 10:57 ` Michael S. Tsirkin
1 sibling, 0 replies; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-09 8:04 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 09/10/2012 05:30, Jason Baron ha scritto:
> From: Jason Baron <jbaron@redhat.com>
>
> Add piix style acpi hotplug to q35.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Not a thorough review, but it looks good.
Paolo
> ---
> hw/acpi_ich9.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> hw/acpi_ich9.h | 10 +++
> 2 files changed, 181 insertions(+), 1 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 1412ad3..412c9c1 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
> #define ICH9_DEBUG(fmt, ...) do { } while (0)
> #endif
>
> +#define PCI_UP_BASE 0xae00
> +#define PCI_DOWN_BASE 0xae04
> +#define PCI_EJ_BASE 0xae08
> +#define PCI_RMV_BASE 0xae0c
> +#define ICH9_PCI_HOTPLUG_STATUS 2
> +
> +
> static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
> uint32_t val);
> static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
> @@ -55,7 +62,10 @@ static void pm_update_sci(ICH9LPCPMRegs *pm)
> (ACPI_BITMASK_RT_CLOCK_ENABLE |
> ACPI_BITMASK_POWER_BUTTON_ENABLE |
> ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> - ACPI_BITMASK_TIMER_ENABLE)) != 0);
> + ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
> + (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0])
> + & ICH9_PCI_HOTPLUG_STATUS) != 0);
> +
> qemu_set_irq(pm->irq, sci_level);
>
> /* schedule a timer interruption if needed */
> @@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
> + pm_update_sci(pm);
> break;
> default:
> break;
> @@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = {
> }
> };
>
> +static void acpi_ich9_eject_slot(ICH9LPCPMRegs *opaque, unsigned slots)
> +{
> + BusChild *kid, *next;
> + ICH9LPCPMRegs *pm = opaque;
> + ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
> + PCIDevice *s = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&s->qdev);
> + int slot = ffs(slots) - 1;
> + bool slot_free = true;
> +
> + /* Mark request as complete */
> + pm->pci0_status.down &= ~(1U << slot);
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *dev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
> + if (PCI_SLOT(dev->devfn) == slot) {
> + if (pc->no_hotplug) {
> + slot_free = false;
> + } else {
> + qdev_free(qdev);
> + }
> + }
> + }
> + if (slot_free) {
> + pm->pci0_slot_device_present &= ~(1U << slot);
> + }
> +}
> +
> +static void acpi_ich9_update_hotplug(ICH9LPCPMRegs *pm)
> +{
> + ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
> + PCIDevice *dev = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&dev->qdev);
> + BusChild *kid, *next;
> +
> + /* Execute any pending removes during reset */
> + while (pm->pci0_status.down) {
> + acpi_ich9_eject_slot(pm, pm->pci0_status.down);
> + }
> +
> + pm->pci0_hotplug_enable = ~0;
> + pm->pci0_slot_device_present = 0;
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *pdev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
> + int slot = PCI_SLOT(pdev->devfn);
> +
> + if (pc->no_hotplug) {
> + pm->pci0_hotplug_enable &= ~(1U << slot);
> + }
> +
> + pm->pci0_slot_device_present |= (1U << slot);
> + }
> +}
> +
> static void pm_reset(void *opaque)
> {
> ICH9LPCPMRegs *pm = opaque;
> @@ -300,6 +370,7 @@ static void pm_reset(void *opaque)
> }
>
> pm_update_sci(pm);
> + acpi_ich9_update_hotplug(pm);
> }
>
> static void pm_powerdown_req(Notifier *n, void *opaque)
> @@ -309,6 +380,104 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
> acpi_pm1_evt_power_down(&pm->acpi_regs);
> }
>
> +static uint32_t pci_up_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> + uint32_t val;
> +
> + /* Manufacture an "up" value to cause a device check on any hotplug
> + * slot with a device. Extra device checks are harmless. */
> + val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable;
> +
> + ICH9_DEBUG("pci_up_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_down_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> + uint32_t val = pm->pci0_status.down;
> +
> + ICH9_DEBUG("pci_down_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_features_read(void *opaque, uint32_t addr)
> +{
> + /* No feature defined yet */
> + ICH9_DEBUG("pci_features_read %x\n", 0);
> + return 0;
> +}
> +
> +static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + acpi_ich9_eject_slot(opaque, val);
> +
> + ICH9_DEBUG("pciej write %x <== %d\n", addr, val);
> +}
> +
> +static uint32_t pcirmv_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> +
> + return pm->pci0_hotplug_enable;
> +}
> +
> +static void enable_device(ICH9LPCPMRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_slot_device_present |= (1U << slot);
> +}
> +
> +static void disable_device(ICH9LPCPMRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_status.down |= (1U << slot);
> +}
> +
> +static int ich9_device_hotplug(DeviceState *qdev, PCIDevice *dev,
> + PCIHotplugState state)
> +{
> + int slot = PCI_SLOT(dev->devfn);
> + ICH9LPCState *lpc = DO_UPCAST(ICH9LPCState, d,
> + PCI_DEVICE(qdev));
> + ICH9LPCPMRegs *pm = &lpc->pm;
> +
> + /* Don't send event when device is enabled during qemu machine creation:
> + * it is present on boot, no hotplug event is necessary. We do send an
> + * event when the device is disabled later. */
> + if (state == PCI_COLDPLUG_ENABLED) {
> + pm->pci0_slot_device_present |= (1U << slot);
> + return 0;
> + }
> +
> + if (state == PCI_HOTPLUG_ENABLED) {
> + enable_device(pm, slot);
> + } else {
> + disable_device(pm, slot);
> + }
> +
> + pm_update_sci(pm);
> +
> + return 0;
> +}
> +
> +static void ich9_acpi_system_hot_add_init(ICH9LPCPMRegs *s)
> +{
> + ICH9LPCState *lpc = container_of(s, ICH9LPCState, pm);
> + PCIDevice *pdev = PCI_DEVICE(lpc);
> +
> + register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
> + register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
> +
> + register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
> + register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
> +
> + register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
> +
> + pci_bus_hotplug(pdev->bus, ich9_device_hotplug, &pdev->qdev);
> +}
> +
> void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> {
> acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
> @@ -319,4 +488,5 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> qemu_register_reset(pm_reset, pm);
> pm->powerdown_notifier.notify = pm_powerdown_req;
> qemu_register_powerdown_notifier(&pm->powerdown_notifier);
> + ich9_acpi_system_hot_add_init(pm);
> }
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> index 180c406..b4e2aff 100644
> --- a/hw/acpi_ich9.h
> +++ b/hw/acpi_ich9.h
> @@ -23,6 +23,11 @@
>
> #include "acpi.h"
>
> +struct pci_status {
> + uint32_t up; /* deprecated, maintained for migration compatibility */
> + uint32_t down;
> +};
> +
> typedef struct ICH9LPCPMRegs {
> /*
> * In ich9 spec says that pm1_cnt register is 32bit width and
> @@ -37,6 +42,11 @@ typedef struct ICH9LPCPMRegs {
>
> uint32_t pm_io_base;
> Notifier powerdown_notifier;
> +
> + /* for pci hotplug */
> + struct pci_status pci0_status;
> + uint32_t pci0_hotplug_enable;
> + uint32_t pci0_slot_device_present;
> } ICH9LPCPMRegs;
>
> void ich9_pm_init(ICH9LPCPMRegs *pm,
>
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-09 3:30 ` [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug Jason Baron
2012-10-09 8:04 ` Paolo Bonzini
@ 2012-10-11 10:57 ` Michael S. Tsirkin
2012-10-11 14:21 ` Jason Baron
1 sibling, 1 reply; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 10:57 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> From: Jason Baron <jbaron@redhat.com>
>
> Add piix style acpi hotplug to q35.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Something I don't understand here: this only handles hotplug
of devices behind the root, no?
Don't we need support for hotplug/hot remove of devices behind
bridges?
> ---
> hw/acpi_ich9.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> hw/acpi_ich9.h | 10 +++
> 2 files changed, 181 insertions(+), 1 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 1412ad3..412c9c1 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
> #define ICH9_DEBUG(fmt, ...) do { } while (0)
> #endif
>
> +#define PCI_UP_BASE 0xae00
> +#define PCI_DOWN_BASE 0xae04
> +#define PCI_EJ_BASE 0xae08
> +#define PCI_RMV_BASE 0xae0c
> +#define ICH9_PCI_HOTPLUG_STATUS 2
> +
> +
> static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
> uint32_t val);
> static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
> @@ -55,7 +62,10 @@ static void pm_update_sci(ICH9LPCPMRegs *pm)
> (ACPI_BITMASK_RT_CLOCK_ENABLE |
> ACPI_BITMASK_POWER_BUTTON_ENABLE |
> ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> - ACPI_BITMASK_TIMER_ENABLE)) != 0);
> + ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
> + (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0])
> + & ICH9_PCI_HOTPLUG_STATUS) != 0);
> +
> qemu_set_irq(pm->irq, sci_level);
>
> /* schedule a timer interruption if needed */
> @@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
> + pm_update_sci(pm);
> break;
> default:
> break;
> @@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = {
> }
> };
>
> +static void acpi_ich9_eject_slot(ICH9LPCPMRegs *opaque, unsigned slots)
> +{
> + BusChild *kid, *next;
> + ICH9LPCPMRegs *pm = opaque;
> + ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
> + PCIDevice *s = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&s->qdev);
> + int slot = ffs(slots) - 1;
> + bool slot_free = true;
> +
> + /* Mark request as complete */
> + pm->pci0_status.down &= ~(1U << slot);
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *dev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
> + if (PCI_SLOT(dev->devfn) == slot) {
> + if (pc->no_hotplug) {
> + slot_free = false;
> + } else {
> + qdev_free(qdev);
> + }
> + }
> + }
> + if (slot_free) {
> + pm->pci0_slot_device_present &= ~(1U << slot);
> + }
> +}
> +
> +static void acpi_ich9_update_hotplug(ICH9LPCPMRegs *pm)
> +{
> + ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
> + PCIDevice *dev = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&dev->qdev);
> + BusChild *kid, *next;
> +
> + /* Execute any pending removes during reset */
> + while (pm->pci0_status.down) {
> + acpi_ich9_eject_slot(pm, pm->pci0_status.down);
> + }
> +
> + pm->pci0_hotplug_enable = ~0;
> + pm->pci0_slot_device_present = 0;
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *pdev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
> + int slot = PCI_SLOT(pdev->devfn);
> +
> + if (pc->no_hotplug) {
> + pm->pci0_hotplug_enable &= ~(1U << slot);
> + }
> +
> + pm->pci0_slot_device_present |= (1U << slot);
> + }
> +}
> +
> static void pm_reset(void *opaque)
> {
> ICH9LPCPMRegs *pm = opaque;
> @@ -300,6 +370,7 @@ static void pm_reset(void *opaque)
> }
>
> pm_update_sci(pm);
> + acpi_ich9_update_hotplug(pm);
> }
>
> static void pm_powerdown_req(Notifier *n, void *opaque)
> @@ -309,6 +380,104 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
> acpi_pm1_evt_power_down(&pm->acpi_regs);
> }
>
> +static uint32_t pci_up_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> + uint32_t val;
> +
> + /* Manufacture an "up" value to cause a device check on any hotplug
> + * slot with a device. Extra device checks are harmless. */
> + val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable;
> +
> + ICH9_DEBUG("pci_up_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_down_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> + uint32_t val = pm->pci0_status.down;
> +
> + ICH9_DEBUG("pci_down_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_features_read(void *opaque, uint32_t addr)
> +{
> + /* No feature defined yet */
> + ICH9_DEBUG("pci_features_read %x\n", 0);
> + return 0;
> +}
> +
> +static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + acpi_ich9_eject_slot(opaque, val);
> +
> + ICH9_DEBUG("pciej write %x <== %d\n", addr, val);
> +}
> +
> +static uint32_t pcirmv_read(void *opaque, uint32_t addr)
> +{
> + ICH9LPCPMRegs *pm = opaque;
> +
> + return pm->pci0_hotplug_enable;
> +}
> +
> +static void enable_device(ICH9LPCPMRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_slot_device_present |= (1U << slot);
> +}
> +
> +static void disable_device(ICH9LPCPMRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_status.down |= (1U << slot);
> +}
> +
> +static int ich9_device_hotplug(DeviceState *qdev, PCIDevice *dev,
> + PCIHotplugState state)
> +{
> + int slot = PCI_SLOT(dev->devfn);
> + ICH9LPCState *lpc = DO_UPCAST(ICH9LPCState, d,
> + PCI_DEVICE(qdev));
> + ICH9LPCPMRegs *pm = &lpc->pm;
> +
> + /* Don't send event when device is enabled during qemu machine creation:
> + * it is present on boot, no hotplug event is necessary. We do send an
> + * event when the device is disabled later. */
> + if (state == PCI_COLDPLUG_ENABLED) {
> + pm->pci0_slot_device_present |= (1U << slot);
> + return 0;
> + }
> +
> + if (state == PCI_HOTPLUG_ENABLED) {
> + enable_device(pm, slot);
> + } else {
> + disable_device(pm, slot);
> + }
> +
> + pm_update_sci(pm);
> +
> + return 0;
> +}
> +
> +static void ich9_acpi_system_hot_add_init(ICH9LPCPMRegs *s)
> +{
> + ICH9LPCState *lpc = container_of(s, ICH9LPCState, pm);
> + PCIDevice *pdev = PCI_DEVICE(lpc);
> +
> + register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
> + register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
> +
> + register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
> + register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
> +
> + register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
> +
> + pci_bus_hotplug(pdev->bus, ich9_device_hotplug, &pdev->qdev);
> +}
> +
> void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> {
> acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
> @@ -319,4 +488,5 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> qemu_register_reset(pm_reset, pm);
> pm->powerdown_notifier.notify = pm_powerdown_req;
> qemu_register_powerdown_notifier(&pm->powerdown_notifier);
> + ich9_acpi_system_hot_add_init(pm);
> }
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> index 180c406..b4e2aff 100644
> --- a/hw/acpi_ich9.h
> +++ b/hw/acpi_ich9.h
> @@ -23,6 +23,11 @@
>
> #include "acpi.h"
>
> +struct pci_status {
> + uint32_t up; /* deprecated, maintained for migration compatibility */
> + uint32_t down;
> +};
> +
> typedef struct ICH9LPCPMRegs {
> /*
> * In ich9 spec says that pm1_cnt register is 32bit width and
> @@ -37,6 +42,11 @@ typedef struct ICH9LPCPMRegs {
>
> uint32_t pm_io_base;
> Notifier powerdown_notifier;
> +
> + /* for pci hotplug */
> + struct pci_status pci0_status;
> + uint32_t pci0_hotplug_enable;
> + uint32_t pci0_slot_device_present;
> } ICH9LPCPMRegs;
>
> void ich9_pm_init(ICH9LPCPMRegs *pm,
> --
> 1.7.1
^ permalink raw reply [flat|nested] 65+ messages in thread* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 10:57 ` Michael S. Tsirkin
@ 2012-10-11 14:21 ` Jason Baron
2012-10-11 14:46 ` Michael S. Tsirkin
0 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-11 14:21 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> > From: Jason Baron <jbaron@redhat.com>
> >
> > Add piix style acpi hotplug to q35.
> >
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>
> Something I don't understand here: this only handles hotplug
> of devices behind the root, no?
> Don't we need support for hotplug/hot remove of devices behind
> bridges?
>
Yes, this only handles acpi hotplug of devices behind the root. I'm
trying to reach minimal set of q35 patches that we can build upon. I
think that this patch gives us at least the same functionality as piix
does. (Plus there is pcie hotplug).
As you know, I have a proof of concept patch series providing a second
level of hotplug behind bridges. Unfortunately, it was based on the
static acpi tables, before Paolo made the hotplug table generation
dynamic. So it needs quite a bit of re-work. But I know that it should
work :)
Thanks,
-Jason
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 14:21 ` Jason Baron
@ 2012-10-11 14:46 ` Michael S. Tsirkin
2012-10-11 14:54 ` Paolo Bonzini
2012-10-11 15:34 ` Jason Baron
0 siblings, 2 replies; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 14:46 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 10:21:22AM -0400, Jason Baron wrote:
> On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> > > From: Jason Baron <jbaron@redhat.com>
> > >
> > > Add piix style acpi hotplug to q35.
> > >
> > > Signed-off-by: Jason Baron <jbaron@redhat.com>
> >
> > Something I don't understand here: this only handles hotplug
> > of devices behind the root, no?
> > Don't we need support for hotplug/hot remove of devices behind
> > bridges?
> >
>
> Yes, this only handles acpi hotplug of devices behind the root. I'm
> trying to reach minimal set of q35 patches that we can build upon. I
> think that this patch gives us at least the same functionality as piix
> does. (Plus there is pcie hotplug).
>
> As you know, I have a proof of concept patch series providing a second
> level of hotplug behind bridges. Unfortunately, it was based on the
> static acpi tables, before Paolo made the hotplug table generation
> dynamic. So it needs quite a bit of re-work. But I know that it should
> work :)
>
> Thanks,
>
> -Jason
Yes. Reason I ask is because q35 is adding bridges by default now.
Would it be possible to only add them if requested on command line by user
instead? I realize some guests expect devices at specific slots
but this does not apply to bridges I think?
It would also be nice to add comments explaining why
specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
etc.
Also - will adding this code now mean that when adding bridges
we'll need to add compatibility code in bios/qemu in the future?
--
MST
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 14:46 ` Michael S. Tsirkin
@ 2012-10-11 14:54 ` Paolo Bonzini
2012-10-11 15:40 ` Jason Baron
2012-10-11 15:34 ` Jason Baron
1 sibling, 1 reply; 65+ messages in thread
From: Paolo Bonzini @ 2012-10-11 14:54 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru, kraxel
Il 11/10/2012 16:46, Michael S. Tsirkin ha scritto:
> Yes. Reason I ask is because q35 is adding bridges by default now.
> Would it be possible to only add them if requested on command line by user
> instead?
Can you just use shpc or pcie hotplug on those bridges?
> I realize some guests expect devices at specific slots
> but this does not apply to bridges I think?
>
> It would also be nice to add comments explaining why
> specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> etc.
>
> Also - will adding this code now mean that when adding bridges
> we'll need to add compatibility code in bios/qemu in the future?
It will need SSDT changes. One ugliness of Jason's patch was that it
introduced a massive chain of 32*32 Ifs in the SSDT. Changing it to use
LoadTable shouldn't be hard. Then you can patch out the LoadTable (e.g.
_INI -> INI_) based on what QEMU tells you is a bridge or not.
Paolo
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 14:54 ` Paolo Bonzini
@ 2012-10-11 15:40 ` Jason Baron
0 siblings, 0 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-11 15:40 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, alex.williamson, Michael S. Tsirkin, jan.kiszka,
qemu-devel, agraf, blauwirbel, yamahata, juzhang, kevin, avi,
mkletzan, lcapitulino, afaerber, armbru, kraxel
On Thu, Oct 11, 2012 at 04:54:53PM +0200, Paolo Bonzini wrote:
> Il 11/10/2012 16:46, Michael S. Tsirkin ha scritto:
> > Yes. Reason I ask is because q35 is adding bridges by default now.
> > Would it be possible to only add them if requested on command line by user
> > instead?
>
> Can you just use shpc or pcie hotplug on those bridges?
>
Yes, I've tested pcie hotplug minimally, but it seems to work so far.
> > I realize some guests expect devices at specific slots
> > but this does not apply to bridges I think?
> >
> > It would also be nice to add comments explaining why
> > specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> > etc.
> >
> > Also - will adding this code now mean that when adding bridges
> > we'll need to add compatibility code in bios/qemu in the future?
>
> It will need SSDT changes. One ugliness of Jason's patch was that it
> introduced a massive chain of 32*32 Ifs in the SSDT. Changing it to use
> LoadTable shouldn't be hard. Then you can patch out the LoadTable (e.g.
> _INI -> INI_) based on what QEMU tells you is a bridge or not.
>
> Paolo
>
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 14:46 ` Michael S. Tsirkin
2012-10-11 14:54 ` Paolo Bonzini
@ 2012-10-11 15:34 ` Jason Baron
2012-10-11 20:40 ` Michael S. Tsirkin
2012-10-12 7:27 ` Gerd Hoffmann
1 sibling, 2 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-11 15:34 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 04:46:56PM +0200, Michael S. Tsirkin wrote:
> On Thu, Oct 11, 2012 at 10:21:22AM -0400, Jason Baron wrote:
> > On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> > > On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> > > > From: Jason Baron <jbaron@redhat.com>
> > > >
> > > > Add piix style acpi hotplug to q35.
> > > >
> > > > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > >
> > > Something I don't understand here: this only handles hotplug
> > > of devices behind the root, no?
> > > Don't we need support for hotplug/hot remove of devices behind
> > > bridges?
> > >
> >
> > Yes, this only handles acpi hotplug of devices behind the root. I'm
> > trying to reach minimal set of q35 patches that we can build upon. I
> > think that this patch gives us at least the same functionality as piix
> > does. (Plus there is pcie hotplug).
> >
> > As you know, I have a proof of concept patch series providing a second
> > level of hotplug behind bridges. Unfortunately, it was based on the
> > static acpi tables, before Paolo made the hotplug table generation
> > dynamic. So it needs quite a bit of re-work. But I know that it should
> > work :)
> >
> > Thanks,
> >
> > -Jason
>
> Yes. Reason I ask is because q35 is adding bridges by default now.
> Would it be possible to only add them if requested on command line by user
> instead? I realize some guests expect devices at specific slots
> but this does not apply to bridges I think?
>
I just tried out getting rid of the bridges by default.
So 'lspci' goes from:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:02.0 VGA compatible controller: Cirrus Logic GD 5446
00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
00:17.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:18.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.1 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.2 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.3 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.4 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1c.5 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
03:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Upstream) (rev 02)
04:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (rev 01)
0c:1c.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
0c:1d.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
0c:1e.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
0c:1f.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
To:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 VGA compatible controller: Cirrus Logic GD 5446
00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
Windows and Linux guests seem fine with either layout. Slots 1-2 are
specific to my setup. So this is a pretty minimal set.
I think that providing the minimal set of devices is good, since it
allows the user to configure things as much as possible. So I am in
favor of this more minimal set. My only hesitation is that we pull out,
or that I have not included some important piece h/w at a specific slot
that a guest might need. Thus potentially breaking existing setups.
Perhaps, that might mean a new machine type in the future, if we've
messed up?
These devices and slots are pulled from the Intel docs on ICH9 and Q35
specs. See:
http://www.intel.com/content/www/us/en/io/io-controller-hub-9-datasheet.html
Perhaps, Yamahata can comment further on the specific set of bridges?
> It would also be nice to add comments explaining why
> specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> etc.
Right, its basically just pulled from the Intel spec as mentioned above.
>
> Also - will adding this code now mean that when adding bridges
> we'll need to add compatibility code in bios/qemu in the future?
>
I don't think so, but maybe you can elaborate this concern more
specifically?
Thanks,
-Jason
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 15:34 ` Jason Baron
@ 2012-10-11 20:40 ` Michael S. Tsirkin
2012-10-12 15:27 ` Jason Baron
2012-10-12 7:27 ` Gerd Hoffmann
1 sibling, 1 reply; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-11 20:40 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 11:34:08AM -0400, Jason Baron wrote:
> On Thu, Oct 11, 2012 at 04:46:56PM +0200, Michael S. Tsirkin wrote:
> > On Thu, Oct 11, 2012 at 10:21:22AM -0400, Jason Baron wrote:
> > > On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> > > > On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> > > > > From: Jason Baron <jbaron@redhat.com>
> > > > >
> > > > > Add piix style acpi hotplug to q35.
> > > > >
> > > > > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > > >
> > > > Something I don't understand here: this only handles hotplug
> > > > of devices behind the root, no?
> > > > Don't we need support for hotplug/hot remove of devices behind
> > > > bridges?
> > > >
> > >
> > > Yes, this only handles acpi hotplug of devices behind the root. I'm
> > > trying to reach minimal set of q35 patches that we can build upon. I
> > > think that this patch gives us at least the same functionality as piix
> > > does. (Plus there is pcie hotplug).
> > >
> > > As you know, I have a proof of concept patch series providing a second
> > > level of hotplug behind bridges. Unfortunately, it was based on the
> > > static acpi tables, before Paolo made the hotplug table generation
> > > dynamic. So it needs quite a bit of re-work. But I know that it should
> > > work :)
> > >
> > > Thanks,
> > >
> > > -Jason
> >
> > Yes. Reason I ask is because q35 is adding bridges by default now.
> > Would it be possible to only add them if requested on command line by user
> > instead? I realize some guests expect devices at specific slots
> > but this does not apply to bridges I think?
> >
>
> I just tried out getting rid of the bridges by default.
>
> So 'lspci' goes from:
>
> 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
> 00:01.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:02.0 VGA compatible controller: Cirrus Logic GD 5446
> 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> 00:17.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:18.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.1 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.2 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.3 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.4 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.5 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
> 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
> 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
> 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
> 03:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Upstream) (rev 02)
> 04:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (rev 01)
> 0c:1c.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1d.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1e.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1f.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
>
> To:
>
> 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
> 00:01.0 VGA compatible controller: Cirrus Logic GD 5446
> 00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
> 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
> 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
> 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
> 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
>
>
> Windows and Linux guests seem fine with either layout. Slots 1-2 are
> specific to my setup. So this is a pretty minimal set.
I guess we can remove the PCI bridge too?
One interesting side effect here is that there are less free pci slots
on root bus now. I guess at minimum management needs to be taught about
this, and I'm not sure how.
> I think that providing the minimal set of devices is good, since it
> allows the user to configure things as much as possible. So I am in
> favor of this more minimal set. My only hesitation is that we pull out,
> or that I have not included some important piece h/w at a specific slot
> that a guest might need. Thus potentially breaking existing setups.
> Perhaps, that might mean a new machine type in the future, if we've
> messed up?
Yes, that's one solution.
> These devices and slots are pulled from the Intel docs on ICH9 and Q35
> specs. See:
>
> http://www.intel.com/content/www/us/en/io/io-controller-hub-9-datasheet.html
>
> Perhaps, Yamahata can comment further on the specific set of bridges?
>
> > It would also be nice to add comments explaining why
> > specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> > etc.
>
> Right, its basically just pulled from the Intel spec as mentioned above.
>
> >
> > Also - will adding this code now mean that when adding bridges
> > we'll need to add compatibility code in bios/qemu in the future?
> >
>
> I don't think so, but maybe you can elaborate this concern more
> specifically?
>
> Thanks,
>
> -Jason
Just this: can same bios work on this interface and the one
you intend for hotplug behind bridge? Or will we need to version
interface?
--
MST
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 20:40 ` Michael S. Tsirkin
@ 2012-10-12 15:27 ` Jason Baron
2012-10-13 23:03 ` Michael S. Tsirkin
0 siblings, 1 reply; 65+ messages in thread
From: Jason Baron @ 2012-10-12 15:27 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Thu, Oct 11, 2012 at 10:40:04PM +0200, Michael S. Tsirkin wrote:
> > Windows and Linux guests seem fine with either layout. Slots 1-2 are
> > specific to my setup. So this is a pretty minimal set.
>
> I guess we can remove the PCI bridge too?
>
maybe. Perhaps, we can have a very basic set of devices, and have easy
ways to specify various default setups, as I've suggested in a separate
mail.
> One interesting side effect here is that there are less free pci slots
> on root bus now. I guess at minimum management needs to be taught about
> this, and I'm not sure how.
>
> > I think that providing the minimal set of devices is good, since it
> > allows the user to configure things as much as possible. So I am in
> > favor of this more minimal set. My only hesitation is that we pull out,
> > or that I have not included some important piece h/w at a specific slot
> > that a guest might need. Thus potentially breaking existing setups.
> > Perhaps, that might mean a new machine type in the future, if we've
> > messed up?
>
> Yes, that's one solution.
>
> > These devices and slots are pulled from the Intel docs on ICH9 and Q35
> > specs. See:
> >
> > http://www.intel.com/content/www/us/en/io/io-controller-hub-9-datasheet.html
> >
> > Perhaps, Yamahata can comment further on the specific set of bridges?
> >
> > > It would also be nice to add comments explaining why
> > > specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> > > etc.
> >
> > Right, its basically just pulled from the Intel spec as mentioned above.
> >
> > >
> > > Also - will adding this code now mean that when adding bridges
> > > we'll need to add compatibility code in bios/qemu in the future?
> > >
> >
> > I don't think so, but maybe you can elaborate this concern more
> > specifically?
> >
> > Thanks,
> >
> > -Jason
>
> Just this: can same bios work on this interface and the one
> you intend for hotplug behind bridge? Or will we need to version
> interface?
>
hmm...I wasn't aware of this contraint. Since we control the version of
SeaBIOS in qemu, is this really a problem? And it was suggested that
qemu is the only consumer of the acpi tables.
The current hotplug code doesn't seem to be versioned. Has this caused
problems?
In terms of the interface itself, yes, I think ideally it would be
changed.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-12 15:27 ` Jason Baron
@ 2012-10-13 23:03 ` Michael S. Tsirkin
0 siblings, 0 replies; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-13 23:03 UTC (permalink / raw)
To: Jason Baron
Cc: agraf, aliguori, juzhang, jan.kiszka, qemu-devel, armbru,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, kraxel
On Fri, Oct 12, 2012 at 11:27:21AM -0400, Jason Baron wrote:
> On Thu, Oct 11, 2012 at 10:40:04PM +0200, Michael S. Tsirkin wrote:
> > > Windows and Linux guests seem fine with either layout. Slots 1-2 are
> > > specific to my setup. So this is a pretty minimal set.
> >
> > I guess we can remove the PCI bridge too?
> >
>
> maybe. Perhaps, we can have a very basic set of devices, and have easy
> ways to specify various default setups, as I've suggested in a separate
> mail.
>
> > One interesting side effect here is that there are less free pci slots
> > on root bus now. I guess at minimum management needs to be taught about
> > this, and I'm not sure how.
> >
> > > I think that providing the minimal set of devices is good, since it
> > > allows the user to configure things as much as possible. So I am in
> > > favor of this more minimal set. My only hesitation is that we pull out,
> > > or that I have not included some important piece h/w at a specific slot
> > > that a guest might need. Thus potentially breaking existing setups.
> > > Perhaps, that might mean a new machine type in the future, if we've
> > > messed up?
> >
> > Yes, that's one solution.
> >
> > > These devices and slots are pulled from the Intel docs on ICH9 and Q35
> > > specs. See:
> > >
> > > http://www.intel.com/content/www/us/en/io/io-controller-hub-9-datasheet.html
> > >
> > > Perhaps, Yamahata can comment further on the specific set of bridges?
> > >
> > > > It would also be nice to add comments explaining why
> > > > specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */
> > > > etc.
> > >
> > > Right, its basically just pulled from the Intel spec as mentioned above.
> > >
> > > >
> > > > Also - will adding this code now mean that when adding bridges
> > > > we'll need to add compatibility code in bios/qemu in the future?
> > > >
> > >
> > > I don't think so, but maybe you can elaborate this concern more
> > > specifically?
> > >
> > > Thanks,
> > >
> > > -Jason
> >
> > Just this: can same bios work on this interface and the one
> > you intend for hotplug behind bridge? Or will we need to version
> > interface?
> >
>
> hmm...I wasn't aware of this contraint. Since we control the version of
> SeaBIOS in qemu, is this really a problem? And it was suggested that
> qemu is the only consumer of the acpi tables.
Yes. But cross version live migration is what creates issues.
> The current hotplug code doesn't seem to be versioned. Has this caused
> problems?
Yes but in the end we found a way to be compatible.
> In terms of the interface itself, yes, I think ideally it would be
> changed.
>
> Thanks,
>
> -Jason
K good to know.
I think we can merge even with this knowledge as an interim step
assuming that we address this before we release qemu.
--
MST
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-11 15:34 ` Jason Baron
2012-10-11 20:40 ` Michael S. Tsirkin
@ 2012-10-12 7:27 ` Gerd Hoffmann
2012-10-12 9:39 ` Michael S. Tsirkin
1 sibling, 1 reply; 65+ messages in thread
From: Gerd Hoffmann @ 2012-10-12 7:27 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, Michael S. Tsirkin, jan.kiszka, qemu-devel,
agraf, blauwirbel, yamahata, alex.williamson, kevin, avi,
mkletzan, pbonzini, lcapitulino, afaerber, armbru
Hi,
>> Yes. Reason I ask is because q35 is adding bridges by default now.
>> Would it be possible to only add them if requested on command line by user
>> instead? I realize some guests expect devices at specific slots
>> but this does not apply to bridges I think?
>
> I just tried out getting rid of the bridges by default.
That clearly raises the question which devices should be created
automatically by -M q35. I think the devices which are part of the ich9
chipset should be there by default. /me looks at my laptop which
happens to have a ich9 chipset.
> So 'lspci' goes from:
>
> 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
Keep.
> 00:01.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
That looks bogous. Drop.
> 00:02.0 VGA compatible controller: Cirrus Logic GD 5446
Our default vga.
> 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
Real ich9 has the e1000 @ 00:19.0, so it would make sense to place one
there. Adding a default nic will probably create some headache though,
so maybe better don't.
> 00:17.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:18.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
Looks bogous too, drop.
> 00:1c.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.1 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.2 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.3 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
Real ich9 has these, keep.
> 00:1c.4 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
> 00:1c.5 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
Dunno. Not present in my laptop, other chipset variants might have more
pcie ports though ...
> 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
Present on real hardware, keep.
> 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02)
> 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02)
> 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
Keep.
> 03:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Upstream) (rev 02)
> 04:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (rev 01)
> 0c:1c.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1d.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1e.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
> 0c:1f.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05)
Drop them. I guess those are just there to simplify bridge device testing.
Real hardware also has:
00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio
Controller (rev 03)
Emulated by intel-hda.
00:1d.0 USB controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #1 (rev 03)
00:1d.1 USB controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #2 (rev 03)
00:1d.2 USB controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #3 (rev 03)
00:1d.7 USB controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI
Controller #1 (rev 03)
We can emulate those too (see docs/docs/ich9-ehci-uhci.cfg).
I think we should add audio+usb to q35.
cheers,
Gerd
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-12 7:27 ` Gerd Hoffmann
@ 2012-10-12 9:39 ` Michael S. Tsirkin
2012-10-12 10:06 ` Gerd Hoffmann
0 siblings, 1 reply; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-12 9:39 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, armbru
On Fri, Oct 12, 2012 at 09:27:02AM +0200, Gerd Hoffmann wrote:
> Hi,
>
> >> Yes. Reason I ask is because q35 is adding bridges by default now.
> >> Would it be possible to only add them if requested on command line by user
> >> instead? I realize some guests expect devices at specific slots
> >> but this does not apply to bridges I think?
> >
> > I just tried out getting rid of the bridges by default.
>
> That clearly raises the question which devices should be created
> automatically by -M q35. I think the devices which are part of the ich9
> chipset should be there by default. /me looks at my laptop which
> happens to have a ich9 chipset.
The reason this is a bad idea is very simple: we only have a way to add
devices not to remove them. So if you miss a device which your guest
needs, it is easy to add, but there is no way to remove.
> > So 'lspci' goes from:
> >
> > 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
>
> Keep.
>
> > 00:01.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02)
>
> That looks bogous. Drop.
>
> > 00:02.0 VGA compatible controller: Cirrus Logic GD 5446
>
> Our default vga.
>
> > 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>
> Real ich9 has the e1000 @ 00:19.0, so it would make sense to place one
> there. Adding a default nic will probably create some headache though,
> so maybe better don't.
And that's just one example. And it's not really e1000 at all.
Fact is, we don't emulate real hardware exactly.
So let's have a minimal machine and if you want to add e1000 audio etc,
you can do this. We can even teach management to do it with friendly
UI as opposed to cryptic machine types.
--
MST
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-12 9:39 ` Michael S. Tsirkin
@ 2012-10-12 10:06 ` Gerd Hoffmann
2012-10-12 10:39 ` Michael S. Tsirkin
2012-10-12 15:00 ` Jason Baron
0 siblings, 2 replies; 65+ messages in thread
From: Gerd Hoffmann @ 2012-10-12 10:06 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, armbru
Hi,
>>> I just tried out getting rid of the bridges by default.
>>
>> That clearly raises the question which devices should be created
>> automatically by -M q35. I think the devices which are part of the ich9
>> chipset should be there by default. /me looks at my laptop which
>> happens to have a ich9 chipset.
>
> The reason this is a bad idea is very simple: we only have a way to add
> devices not to remove them. So if you miss a device which your guest
> needs, it is easy to add, but there is no way to remove.
Why would you want remove devices? They don't harm when present. And
you can't remove them on real hardware either. Try ordering a ich9
without sound or usb ;)
>> Real ich9 has the e1000 @ 00:19.0, so it would make sense to place one
>> there. Adding a default nic will probably create some headache though,
>> so maybe better don't.
>
> And that's just one example.
It is problematic because the nic needs configuration and configuring a
builtin device is tricky. Also our e1000 model isn't the ich9 one.
Most other chipset devices are not problematic at all as they are just
controllers where you can attach stuff to (and by default there isn't
anything attached). This includes:
* pcie ports (waiting for pcie devices plugged in).
* ahci controller (waiting for disks/cdroms being attached).
* intel-hda (waiting for audio coded (hda-*) being attached).
* ehci+uhci (waiting for usb devices being plugged in).
The stuff being attached/plugged there needs configuration, but not the
controllers themself.
> Fact is, we don't emulate real hardware exactly.
But we try to.
> So let's have a minimal machine and if you want to add e1000 audio etc,
> you can do this. We can even teach management to do it with friendly
> UI as opposed to cryptic machine types.
/me disagrees.
cheers,
Gerd
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-12 10:06 ` Gerd Hoffmann
@ 2012-10-12 10:39 ` Michael S. Tsirkin
2012-10-12 15:00 ` Jason Baron
1 sibling, 0 replies; 65+ messages in thread
From: Michael S. Tsirkin @ 2012-10-12 10:39 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, qemu-devel, agraf,
blauwirbel, yamahata, alex.williamson, kevin, avi, mkletzan,
pbonzini, lcapitulino, afaerber, armbru
On Fri, Oct 12, 2012 at 12:06:44PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> >>> I just tried out getting rid of the bridges by default.
> >>
> >> That clearly raises the question which devices should be created
> >> automatically by -M q35. I think the devices which are part of the ich9
> >> chipset should be there by default. /me looks at my laptop which
> >> happens to have a ich9 chipset.
> >
> > The reason this is a bad idea is very simple: we only have a way to add
> > devices not to remove them. So if you miss a device which your guest
> > needs, it is easy to add, but there is no way to remove.
>
> Why would you want remove devices? They don't harm when present.
Yes they do, they increase attack surface on hypervisor.
--
MST
^ permalink raw reply [flat|nested] 65+ messages in thread
* Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug.
2012-10-12 10:06 ` Gerd Hoffmann
2012-10-12 10:39 ` Michael S. Tsirkin
@ 2012-10-12 15:00 ` Jason Baron
1 sibling, 0 replies; 65+ messages in thread
From: Jason Baron @ 2012-10-12 15:00 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, juzhang, Michael S. Tsirkin, jan.kiszka, qemu-devel,
agraf, blauwirbel, yamahata, alex.williamson, kevin, avi,
mkletzan, pbonzini, lcapitulino, afaerber, armbru
On Fri, Oct 12, 2012 at 12:06:44PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> >>> I just tried out getting rid of the bridges by default.
> >>
> >> That clearly raises the question which devices should be created
> >> automatically by -M q35. I think the devices which are part of the ich9
> >> chipset should be there by default. /me looks at my laptop which
> >> happens to have a ich9 chipset.
> >
> > The reason this is a bad idea is very simple: we only have a way to add
> > devices not to remove them. So if you miss a device which your guest
> > needs, it is easy to add, but there is no way to remove.
>
> Why would you want remove devices? They don't harm when present. And
> you can't remove them on real hardware either. Try ordering a ich9
> without sound or usb ;)
>
> >> Real ich9 has the e1000 @ 00:19.0, so it would make sense to place one
> >> there. Adding a default nic will probably create some headache though,
> >> so maybe better don't.
> >
> > And that's just one example.
>
> It is problematic because the nic needs configuration and configuring a
> builtin device is tricky. Also our e1000 model isn't the ich9 one.
>
> Most other chipset devices are not problematic at all as they are just
> controllers where you can attach stuff to (and by default there isn't
> anything attached). This includes:
>
> * pcie ports (waiting for pcie devices plugged in).
> * ahci controller (waiting for disks/cdroms being attached).
> * intel-hda (waiting for audio coded (hda-*) being attached).
> * ehci+uhci (waiting for usb devices being plugged in).
>
> The stuff being attached/plugged there needs configuration, but not the
> controllers themself.
>
> > Fact is, we don't emulate real hardware exactly.
>
> But we try to.
>
> > So let's have a minimal machine and if you want to add e1000 audio etc,
> > you can do this. We can even teach management to do it with friendly
> > UI as opposed to cryptic machine types.
>
> /me disagrees.
>
What if we have a 'basic' configuration as Michael suggests, but have an
easy way to specify that we want these additional built-in
controllers/bridges at their default slot.
For example, for q35 I can currently pass '-usb' and it will create a
uhci at slot 1d func 0. (I have small patch to add ehci as well).
Not sure if we have appropriate options we can piggy-back on for default
sound and bridges, but we can add these later, if this makese sense.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 65+ messages in thread