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From: Peter Rosin <peda@axentia.se>
To: "Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Takashi Iwai <tiwai@suse.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Kirill Marinushkin <kmarinushkin@birdec.com>,
	Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH] ASoC: pcm512x: Mend accesses to the I2S_1 and I2S_2 registers
Date: Tue, 21 Sep 2021 10:10:49 +0200	[thread overview]
Message-ID: <27f903d9-a74e-182e-b715-4124cf666f45@axentia.se> (raw)
In-Reply-To: <d9850534-df41-a6b3-48e2-34823f5866e9@axentia.se>

>> Can you try the attached patch w/o without the defaults for i2s_1/2?
>> Not even compile tested...
> 
> [added a couple of underscores]
> 
> I get this early during boot/probe
> [    1.506291] pcm512x 0-004c: pcm512x_set_fmt: failed to read I2S_1: -16
> [    1.512905] pcm512x 0-004c: pcm512x_set_fmt: failed to read PLL_EN: -16
> [    1.519517] pcm512x 0-004c: Failed to set data format: -16
> [    1.525045] pcm512x 0-004c: Failed to set data offset: -16
> 
> and then this later, triggered from userspace when an app opens
> the device
> [   14.620344] pcm512x 0-004c: pcm512x_hw_params: I2S_1: 0x2
> 
> So, reading *can* work.

I added some traces and verified that accesses to I2S_1/2 fail (as do
PLL_EN accesses) when the chip is in Powerdown mode (pcm512x_suspend
has set the RQPD bit in the POWER register), which it is when
pcm512x_set_fmt runs. During pcm512x_hw_params the chip is in Standby
mode instead (pcm512x_resume has cleared the RQPD bit, but the RQST
bit is set).

So, my patch seems wrong, and the I2S_1/2 accesses instead need to
move to some point where the chip is not in Powerdown mode.

Or, is the problem that pcm512x_set_fmt is called while the codec is
suspended and the chip thus is in Powerdown mode? Because, that
seems problematic to me?

Cheers,
Peter

WARNING: multiple messages have this Message-ID (diff)
From: Peter Rosin <peda@axentia.se>
To: "Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Kirill Marinushkin <kmarinushkin@birdec.com>,
	Takashi Iwai <tiwai@suse.com>
Subject: Re: [PATCH] ASoC: pcm512x: Mend accesses to the I2S_1 and I2S_2 registers
Date: Tue, 21 Sep 2021 10:10:49 +0200	[thread overview]
Message-ID: <27f903d9-a74e-182e-b715-4124cf666f45@axentia.se> (raw)
In-Reply-To: <d9850534-df41-a6b3-48e2-34823f5866e9@axentia.se>

>> Can you try the attached patch w/o without the defaults for i2s_1/2?
>> Not even compile tested...
> 
> [added a couple of underscores]
> 
> I get this early during boot/probe
> [    1.506291] pcm512x 0-004c: pcm512x_set_fmt: failed to read I2S_1: -16
> [    1.512905] pcm512x 0-004c: pcm512x_set_fmt: failed to read PLL_EN: -16
> [    1.519517] pcm512x 0-004c: Failed to set data format: -16
> [    1.525045] pcm512x 0-004c: Failed to set data offset: -16
> 
> and then this later, triggered from userspace when an app opens
> the device
> [   14.620344] pcm512x 0-004c: pcm512x_hw_params: I2S_1: 0x2
> 
> So, reading *can* work.

I added some traces and verified that accesses to I2S_1/2 fail (as do
PLL_EN accesses) when the chip is in Powerdown mode (pcm512x_suspend
has set the RQPD bit in the POWER register), which it is when
pcm512x_set_fmt runs. During pcm512x_hw_params the chip is in Standby
mode instead (pcm512x_resume has cleared the RQPD bit, but the RQST
bit is set).

So, my patch seems wrong, and the I2S_1/2 accesses instead need to
move to some point where the chip is not in Powerdown mode.

Or, is the problem that pcm512x_set_fmt is called while the codec is
suspended and the chip thus is in Powerdown mode? Because, that
seems problematic to me?

Cheers,
Peter

  reply	other threads:[~2021-09-21  8:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-20 14:49 [PATCH] ASoC: pcm512x: Mend accesses to the I2S_1 and I2S_2 registers Peter Rosin
2021-09-20 14:49 ` Peter Rosin
2021-09-20 18:37 ` Péter Ujfalusi
2021-09-20 19:37   ` Peter Rosin
2021-09-20 19:37     ` Peter Rosin
2021-09-20 21:29     ` Mark Brown
2021-09-20 21:29       ` Mark Brown
2021-09-21  6:37       ` Peter Rosin
2021-09-21  6:37         ` Peter Rosin
2021-09-21 11:11         ` Mark Brown
2021-09-21 11:11           ` Mark Brown
2021-09-21  4:20     ` Péter Ujfalusi
2021-09-21  4:20       ` Péter Ujfalusi
2021-09-21  6:52       ` Peter Rosin
2021-09-21  6:52         ` Peter Rosin
2021-09-21  8:10         ` Peter Rosin [this message]
2021-09-21  8:10           ` Peter Rosin
2021-09-21  8:48           ` Peter Rosin
2021-09-21  8:48             ` Peter Rosin
2021-09-21 12:01             ` Mark Brown
2021-09-21 12:01               ` Mark Brown
2021-09-21 13:30               ` Peter Rosin
2021-09-21 13:30                 ` Peter Rosin
2021-09-21 17:22                 ` Péter Ujfalusi
2021-09-21 15:25 ` Mark Brown
2021-09-21 15:25   ` Mark Brown

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