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From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission
Date: Fri, 9 Feb 2018 11:42:11 -0800	[thread overview]
Message-ID: <2832ff22-e0c8-85b9-c0ce-15b0cc3cdc72@linaro.org> (raw)
In-Reply-To: <1518053328-34687-1-git-send-email-mjc@sifive.com>

On 02/07/2018 05:28 PM, Michael Clark wrote:
>  create mode 100644 hw/riscv/Makefile.objs
>  create mode 100644 hw/riscv/riscv_elf.c
>  create mode 100644 hw/riscv/riscv_hart.c
>  create mode 100644 hw/riscv/riscv_htif.c
>  create mode 100644 hw/riscv/sifive_clint.c
>  create mode 100644 hw/riscv/sifive_e300.c
>  create mode 100644 hw/riscv/sifive_plic.c
>  create mode 100644 hw/riscv/sifive_prci.c
>  create mode 100644 hw/riscv/sifive_test.c
>  create mode 100644 hw/riscv/sifive_u500.c
>  create mode 100644 hw/riscv/sifive_uart.c
>  create mode 100644 hw/riscv/spike_v1_09.c
>  create mode 100644 hw/riscv/spike_v1_10.c
>  create mode 100644 hw/riscv/virt.c

I have no plans to review these last 9 patches.
They all look plausible to me, but I'm not so
up-to-date on best practices within hw/.


r~

  parent reply	other threads:[~2018-02-09 19:42 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-08  1:28 [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 01/23] RISC-V Maintainers Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 02/23] RISC-V ELF Machine Definition Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 03/23] RISC-V CPU Core Definition Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 04/23] RISC-V Disassembler Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 05/23] RISC-V CPU Helpers Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 06/23] Softfloat support for IEEE 754-201x minimumNumber/maximumNumber Michael Clark
2018-02-08 14:35   ` Richard Henderson
2018-02-08 21:03     ` Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 07/23] RISC-V FPU Support Michael Clark
2018-02-08 14:38   ` Richard Henderson
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 08/23] RISC-V GDB Stub Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation Michael Clark
2018-02-13 21:55   ` Emilio G. Cota
2018-02-13 22:10     ` Richard Henderson
2018-02-14  0:10       ` Emilio G. Cota
2018-02-14 19:14         ` Richard Henderson
2018-02-14 19:52           ` Emilio G. Cota
2018-02-14 21:13             ` Richard Henderson
2018-02-14 23:23               ` Emilio G. Cota
2018-02-13 21:57   ` Emilio G. Cota
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 10/23] RISC-V Physical Memory Protection Michael Clark
2018-02-08 14:40   ` Richard Henderson
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 11/23] RISC-V Linux User Emulation Michael Clark
2018-02-08 16:20   ` Richard Henderson
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console Michael Clark
2018-02-08 16:35   ` Richard Henderson
2018-02-09  7:33     ` Michael Clark
2018-02-09  8:09       ` Michael Clark
2018-02-09  9:08         ` Michael Clark
2018-02-09 19:38           ` Richard Henderson
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 13/23] RISC-V HART Array Michael Clark
2018-02-08 16:37   ` Richard Henderson
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 14/23] SiFive RISC-V CLINT Block Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 15/23] SiFive RISC-V PLIC Block Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 16/23] RISC-V Spike Machines Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 17/23] RISC-V VirtIO Machine Michael Clark
2018-02-08 10:36   ` Igor Mammedov
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 18/23] SiFive RISC-V UART Device Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 19/23] SiFive RISC-V PRCI Block Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 20/23] SiFive RISC-V Test Finisher Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 21/23] SiFive Freedom E300 RISC-V Machine Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 22/23] SiFive Freedom U500 " Michael Clark
2018-02-08  1:28 ` [Qemu-devel] [PATCH v5 23/23] RISC-V Build Infrastructure Michael Clark
2018-02-08  1:55 ` [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission Michael Clark
2018-02-08  1:56   ` Michael Clark
2018-02-08  2:04 ` no-reply
2018-02-09 19:42 ` Richard Henderson [this message]
2018-02-10  0:04   ` Michael Clark
2018-02-17 13:30 ` Richard W.M. Jones

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