[U-Boot] [PATCH 1/3] arm: mvebu: mcbin: dts: fix PCIe reset polarity

[U-Boot] [PATCH 1/3] arm: mvebu: mcbin: dts: fix PCIe reset polarity

[Baruch Siach]

The PCIe slot PERST signal is active low. Fix the gpio signal
description in the dts.

This happened to work because the pcie_dw_mvebu driver sets the reset
gpio level to 1 (high) to release the reset. The following commit will
fix that.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm/dts/armada-8040-mcbin.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 7e8e2f707ccf..5a046d9de474 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -132,7 +132,7 @@
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&cpm_pcie_reset_pins>;
-	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
 	status = "okay";
 };
 
-- 
2.20.1

[U-Boot] [PATCH 2/3] pcie: designware: mvebu: fix reset release polarity

[Baruch Siach]

The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.

Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 drivers/pci/pcie_dw_mvebu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 8081005c27ee..95fb41966fd6 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
 	 * using this GPIO.
 	 */
 	if (dm_gpio_is_valid(&reset_gpio)) {
-		dm_gpio_set_value(&reset_gpio, 1);
+		dm_gpio_set_value(&reset_gpio, 1); /* assert */
+		mdelay(200);
+		dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
 		mdelay(200);
 	}
 #else
-- 
2.20.1

[U-Boot] [PATCH 3/3] arm: mvebu: cf gt-8k: dts: add PCIe slot reset support

[Baruch Siach]

Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
on Clearfog GT-8K.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
 arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 498105f25f05..cdff44aca5af 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -99,6 +99,11 @@
 		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
 		     0xe  0xe  0 >;
 
+	cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+		marvell,pins = < 32 >;
+		marvell,function = <0>;
+	};
+
 	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
 		marvell,pins = < 47 >;
 		marvell,function = <0>;
@@ -120,6 +125,9 @@
 
 &cpm_pcie0 {
 	num-lanes = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_pcie_reset_pins>;
+	marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
-- 
2.20.1

[U-Boot] [PATCH 1/3] arm: mvebu: mcbin: dts: fix PCIe reset polarity

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> The PCIe slot PERST signal is active low. Fix the gpio signal
> description in the dts.
> 
> This happened to work because the pcie_dw_mvebu driver sets the reset
> gpio level to 1 (high) to release the reset. The following commit will
> fix that.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
>   arch/arm/dts/armada-8040-mcbin.dts | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
> index 7e8e2f707ccf..5a046d9de474 100644
> --- a/arch/arm/dts/armada-8040-mcbin.dts
> +++ b/arch/arm/dts/armada-8040-mcbin.dts
> @@ -132,7 +132,7 @@
>   	num-lanes = <4>;
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&cpm_pcie_reset_pins>;
> -	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
> +	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
>   	status = "okay";
>   };
>   
> 

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 2/3] pcie: designware: mvebu: fix reset release polarity

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> The dm_gpio_set_value() routine sets signal logical level, with
> GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
> (asserted), while reset inactive value is 0 (de-asserted). Fix the reset
> toggle code to set the correct reset logic value.
> 
> Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
>   drivers/pci/pcie_dw_mvebu.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
> index 8081005c27ee..95fb41966fd6 100644
> --- a/drivers/pci/pcie_dw_mvebu.c
> +++ b/drivers/pci/pcie_dw_mvebu.c
> @@ -489,7 +489,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev)
>   	 * using this GPIO.
>   	 */
>   	if (dm_gpio_is_valid(&reset_gpio)) {
> -		dm_gpio_set_value(&reset_gpio, 1);
> +		dm_gpio_set_value(&reset_gpio, 1); /* assert */
> +		mdelay(200);
> +		dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
>   		mdelay(200);
>   	}
>   #else
> 

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 3/3] arm: mvebu: cf gt-8k: dts: add PCIe slot reset support

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
> on Clearfog GT-8K.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
>   arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
> index 498105f25f05..cdff44aca5af 100644
> --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
> +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
> @@ -99,6 +99,11 @@
>   		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
>   		     0xe  0xe  0 >;
>   
> +	cpm_pcie_reset_pins: cpm-pcie-reset-pins {
> +		marvell,pins = < 32 >;
> +		marvell,function = <0>;
> +	};
> +
>   	cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
>   		marvell,pins = < 47 >;
>   		marvell,function = <0>;
> @@ -120,6 +125,9 @@
>   
>   &cpm_pcie0 {
>   	num-lanes = <1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&cpm_pcie_reset_pins>;
> +	marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
>   	status = "okay";
>   };
>   
> 

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

[U-Boot] [PATCH 1/3] arm: mvebu: mcbin: dts: fix PCIe reset polarity

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> The PCIe slot PERST signal is active low. Fix the gpio signal
> description in the dts.
> 
> This happened to work because the pcie_dw_mvebu driver sets the reset
> gpio level to 1 (high) to release the reset. The following commit will
> fix that.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied to u-boot-marvell/master

Thanks,
Stefan

[U-Boot] [PATCH 2/3] pcie: designware: mvebu: fix reset release polarity

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> The dm_gpio_set_value() routine sets signal logical level, with
> GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
> (asserted), while reset inactive value is 0 (de-asserted). Fix the reset
> toggle code to set the correct reset logic value.
> 
> Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied to u-boot-marvell/master

Thanks,
Stefan

[U-Boot] [PATCH 3/3] arm: mvebu: cf gt-8k: dts: add PCIe slot reset support

[Stefan Roese]

On 03.02.19 14:15, Baruch Siach wrote:
> Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
> on Clearfog GT-8K.
> 
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>

Applied to u-boot-marvell/master

Thanks,
Stefan