From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> To: "Mårten Lindahl" <marten.lindahl@axis.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Rob Herring" <robh+dt@kernel.org>, "Jaehoon Chung" <jh80.chung@samsung.com> Cc: Doug Anderson <dianders@google.com>, kernel@axis.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout Date: Thu, 2 Dec 2021 09:39:30 +0100 [thread overview] Message-ID: <2875d5c8-dc98-0e3c-41b8-c71bd439ced4@canonical.com> (raw) In-Reply-To: <20211201153804.27655-4-marten.lindahl@axis.com> On 01/12/2021 16:38, Mårten Lindahl wrote: > Current dw_mci driver supports a TMOUT register which consists of a 24 > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > 0xFFFFFF / 200000000 => ~84 ms > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > In this version the DATA_TIMEOUT field is split into two, which with the > same 200MHz clock as above will allow a maximum timeout of: > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > drivers/mmc/host/dw_mmc.h | 7 +++++++ > 3 files changed, 41 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > index cae7c94b5d6e..6ae9c0ec1282 100644 > --- a/drivers/mmc/host/dw_mmc-exynos.c > +++ b/drivers/mmc/host/dw_mmc-exynos.c > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > } > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > + /* Quirk needed for ARTPEC-8 SoCs */ > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > + } > + > host->bus_hz /= (priv->ciu_div + 1); > > return 0; > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index f2a14a434bef..45ea9fd97a6a 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > { > u32 clk_div, tmout; > u64 tmp; > + unsigned int tmp2; > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > if (clk_div == 0) > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > tmout = 0xFF; /* Set maximum */ > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > - if (!tmp || tmp > 0xFFFFFF) > - tmout |= (0xFFFFFF << 8); > - else > - tmout |= (tmp & 0xFFFFFF) << 8; > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > + /* > + * Extended HW timer (max = 0x6FFFFF2): > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > + */ > + if (!tmp || tmp > 0x6FFFFF2) > + tmout |= (0xFFFFFF << 8); > + else { > + /* TMOUT[10:8] */ > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > + tmout |= tmp2 << 8; > + > + /* TMOUT[31:11] */ > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > + tmout |= (tmp & 0xFFFFF8) << 8; > + } > + } else { > + if (!tmp || tmp > 0xFFFFFF) > + tmout |= (0xFFFFFF << 8); > + else > + tmout |= (tmp & 0xFFFFFF) << 8; > + } > > mci_writel(host, TMOUT, tmout); > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > if (drto_div == 0) > drto_div = 1; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > + ((drto_clks & 0xFFFFF8)); > + > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > host->bus_hz); > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > + > /* add a bit spare time */ > drto_ms += 10; > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index 771d5afa3136..071f4479f166 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > * @part_buf: Simple buffer for partial fifo reads/writes. > * @push_data: Pointer to FIFO push function. > * @pull_data: Pointer to FIFO pull function. > + * @quirks: Set of quirks that apply to specific versions of the IP. > * @vqmmc_enabled: Status of vqmmc, should be true or false. > * @irq_flags: The flags to be passed to request_irq. > * @irq: The irq value to be passed to request_irq. > @@ -223,6 +224,9 @@ struct dw_mci { > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > + /* Workaround flags */ No need for this comment - you already described the field in kerneldoc. > + u32 quirks; > + > bool vqmmc_enabled; > unsigned long irq_flags; /* IRQ flags */ > int irq; > @@ -274,6 +278,9 @@ struct dw_mci_board { > struct dma_pdata *data; > }; > > +/* Support for longer data read timeout */ > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) BIT() > + > #define DW_MMC_240A 0x240a > #define DW_MMC_280A 0x280a > > Best regards, Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> To: "Mårten Lindahl" <marten.lindahl@axis.com>, "Ulf Hansson" <ulf.hansson@linaro.org>, "Rob Herring" <robh+dt@kernel.org>, "Jaehoon Chung" <jh80.chung@samsung.com> Cc: Doug Anderson <dianders@google.com>, kernel@axis.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout Date: Thu, 2 Dec 2021 09:39:30 +0100 [thread overview] Message-ID: <2875d5c8-dc98-0e3c-41b8-c71bd439ced4@canonical.com> (raw) In-Reply-To: <20211201153804.27655-4-marten.lindahl@axis.com> On 01/12/2021 16:38, Mårten Lindahl wrote: > Current dw_mci driver supports a TMOUT register which consists of a 24 > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > 0xFFFFFF / 200000000 => ~84 ms > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > In this version the DATA_TIMEOUT field is split into two, which with the > same 200MHz clock as above will allow a maximum timeout of: > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > drivers/mmc/host/dw_mmc.h | 7 +++++++ > 3 files changed, 41 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > index cae7c94b5d6e..6ae9c0ec1282 100644 > --- a/drivers/mmc/host/dw_mmc-exynos.c > +++ b/drivers/mmc/host/dw_mmc-exynos.c > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > } > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > + /* Quirk needed for ARTPEC-8 SoCs */ > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > + } > + > host->bus_hz /= (priv->ciu_div + 1); > > return 0; > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index f2a14a434bef..45ea9fd97a6a 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > { > u32 clk_div, tmout; > u64 tmp; > + unsigned int tmp2; > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > if (clk_div == 0) > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > tmout = 0xFF; /* Set maximum */ > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > - if (!tmp || tmp > 0xFFFFFF) > - tmout |= (0xFFFFFF << 8); > - else > - tmout |= (tmp & 0xFFFFFF) << 8; > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > + /* > + * Extended HW timer (max = 0x6FFFFF2): > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > + */ > + if (!tmp || tmp > 0x6FFFFF2) > + tmout |= (0xFFFFFF << 8); > + else { > + /* TMOUT[10:8] */ > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > + tmout |= tmp2 << 8; > + > + /* TMOUT[31:11] */ > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > + tmout |= (tmp & 0xFFFFF8) << 8; > + } > + } else { > + if (!tmp || tmp > 0xFFFFFF) > + tmout |= (0xFFFFFF << 8); > + else > + tmout |= (tmp & 0xFFFFFF) << 8; > + } > > mci_writel(host, TMOUT, tmout); > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > if (drto_div == 0) > drto_div = 1; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > + ((drto_clks & 0xFFFFF8)); > + > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > host->bus_hz); > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > + > /* add a bit spare time */ > drto_ms += 10; > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index 771d5afa3136..071f4479f166 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > * @part_buf: Simple buffer for partial fifo reads/writes. > * @push_data: Pointer to FIFO push function. > * @pull_data: Pointer to FIFO pull function. > + * @quirks: Set of quirks that apply to specific versions of the IP. > * @vqmmc_enabled: Status of vqmmc, should be true or false. > * @irq_flags: The flags to be passed to request_irq. > * @irq: The irq value to be passed to request_irq. > @@ -223,6 +224,9 @@ struct dw_mci { > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > + /* Workaround flags */ No need for this comment - you already described the field in kerneldoc. > + u32 quirks; > + > bool vqmmc_enabled; > unsigned long irq_flags; /* IRQ flags */ > int irq; > @@ -274,6 +278,9 @@ struct dw_mci_board { > struct dma_pdata *data; > }; > > +/* Support for longer data read timeout */ > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) BIT() > + > #define DW_MMC_240A 0x240a > #define DW_MMC_280A 0x280a > > Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-02 8:39 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-01 15:38 [PATCH 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-01 15:38 ` [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-02 8:41 ` Krzysztof Kozlowski 2021-12-02 8:41 ` Krzysztof Kozlowski 2021-12-03 12:00 ` Marten Lindahl 2021-12-03 12:00 ` Marten Lindahl 2021-12-01 15:38 ` [PATCH 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-01 15:38 ` [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-02 8:39 ` Krzysztof Kozlowski [this message] 2021-12-02 8:39 ` Krzysztof Kozlowski 2021-12-03 12:02 ` Marten Lindahl 2021-12-03 12:02 ` Marten Lindahl 2021-12-01 15:38 ` [PATCH 4/4] mmc: dw_mmc: Do not wait for DTO in case of error Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl
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