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* [PATCH] amdgpu: fix multi-process hang issue
@ 2018-08-20  3:35 Emily Deng
       [not found] ` <1534736155-14643-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Emily Deng @ 2018-08-20  3:35 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Monk Liu

From: Monk Liu <Monk.Liu@amd.com>

SWDEV-146499: hang during multi vulkan process testing

cause:
the second frame's PREAMBLE_IB have clear-state
and LOAD actions, those actions ruin the pipeline
that is still doing process in the previous frame's
work-load IB.

fix:
need insert pipeline sync if have context switch for
SRIOV (because only SRIOV will report PREEMPTION flag
to UMD)

Change-Id: If676da7a9b0147114cd76d19b6035ed8033de449
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 5c22cfd..66efa85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -95,6 +95,12 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
 }
 
+static bool amdgpu_ib_has_preamble(struct amdgpu_ring *ring, bool ctx_switch) {
+	return (amdgpu_sriov_vf(ring->adev) &&
+			ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
+			ctx_switch);
+}
+
 /**
  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  *
@@ -123,7 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_ib *ib = &ibs[0];
 	struct dma_fence *tmp = NULL;
-	bool skip_preamble, need_ctx_switch;
+	bool need_ctx_switch;
 	unsigned patch_offset = ~0;
 	struct amdgpu_vm *vm;
 	uint64_t fence_ctx;
@@ -156,6 +162,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 		return -EINVAL;
 	}
 
+	need_ctx_switch = ring->current_ctx != fence_ctx;
+
 	alloc_size = ring->funcs->emit_frame_size + num_ibs *
 		ring->funcs->emit_ib_size;
 
@@ -167,6 +175,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	if (ring->funcs->emit_pipeline_sync && job &&
 	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
+		 amdgpu_ib_has_preamble(ring, need_ctx_switch) ||
 	     amdgpu_vm_need_pipeline_sync(ring, job))) {
 		need_pipe_sync = true;
 
@@ -200,8 +209,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 			amdgpu_asic_flush_hdp(adev, ring);
 	}
 
-	skip_preamble = ring->current_ctx == fence_ctx;
-	need_ctx_switch = ring->current_ctx != fence_ctx;
 	if (job && ring->funcs->emit_cntxcntl) {
 		if (need_ctx_switch)
 			status |= AMDGPU_HAVE_CTX_SWITCH;
@@ -215,7 +222,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 		/* drop preamble IBs if we don't have a context switch */
 		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-			skip_preamble &&
+			!need_ctx_switch &&
 			!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
 			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
 			continue;
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] amdgpu: fix multi-process hang issue
       [not found] ` <1534736155-14643-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
@ 2018-08-20 13:15   ` Christian König
       [not found]     ` <28a5c925-1445-18ea-52cd-afbc41bcc323-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2018-08-20 13:15 UTC (permalink / raw)
  To: Emily Deng, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Monk Liu

Am 20.08.2018 um 05:35 schrieb Emily Deng:
> From: Monk Liu <Monk.Liu@amd.com>
>
> SWDEV-146499: hang during multi vulkan process testing
>
> cause:
> the second frame's PREAMBLE_IB have clear-state
> and LOAD actions, those actions ruin the pipeline
> that is still doing process in the previous frame's
> work-load IB.
>
> fix:
> need insert pipeline sync if have context switch for
> SRIOV (because only SRIOV will report PREEMPTION flag
> to UMD)
>
> Change-Id: If676da7a9b0147114cd76d19b6035ed8033de449
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 15 +++++++++++----
>   1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 5c22cfd..66efa85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -95,6 +95,12 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
>   	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
>   }
>   
> +static bool amdgpu_ib_has_preamble(struct amdgpu_ring *ring, bool ctx_switch) {
> +	return (amdgpu_sriov_vf(ring->adev) &&
> +			ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
> +			ctx_switch);
> +}
> +

Well NAK, please merge that into amdgpu_ib_schedule() and drop the extra 
check for GFX, that will apply to compute queues as well.

>   /**
>    * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
>    *
> @@ -123,7 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   	struct amdgpu_device *adev = ring->adev;
>   	struct amdgpu_ib *ib = &ibs[0];
>   	struct dma_fence *tmp = NULL;
> -	bool skip_preamble, need_ctx_switch;
> +	bool need_ctx_switch;
>   	unsigned patch_offset = ~0;
>   	struct amdgpu_vm *vm;
>   	uint64_t fence_ctx;
> @@ -156,6 +162,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   		return -EINVAL;
>   	}
>   
> +	need_ctx_switch = ring->current_ctx != fence_ctx;
> +
>   	alloc_size = ring->funcs->emit_frame_size + num_ibs *
>   		ring->funcs->emit_ib_size;
>   
> @@ -167,6 +175,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   
>   	if (ring->funcs->emit_pipeline_sync && job &&
>   	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
> +		 amdgpu_ib_has_preamble(ring, need_ctx_switch) ||
>   	     amdgpu_vm_need_pipeline_sync(ring, job))) {
>   		need_pipe_sync = true;
>   
> @@ -200,8 +209,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   			amdgpu_asic_flush_hdp(adev, ring);
>   	}
>   
> -	skip_preamble = ring->current_ctx == fence_ctx;
> -	need_ctx_switch = ring->current_ctx != fence_ctx;
>   	if (job && ring->funcs->emit_cntxcntl) {
>   		if (need_ctx_switch)
>   			status |= AMDGPU_HAVE_CTX_SWITCH;
> @@ -215,7 +222,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   
>   		/* drop preamble IBs if we don't have a context switch */
>   		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
> -			skip_preamble &&
> +			!need_ctx_switch &&
>   			!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
>   			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */

Ok, please clean that up more carefully. All prerequisites which are not 
IB dependent should come before the loop.

BTW: The handling of AMDGPU_PREAMBLE_IB_PRESENT_FIRST in amdgpu_cs.c is 
completely broken as well.

Regards,
Christian.

>   			continue;

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH] amdgpu: fix multi-process hang issue
       [not found]     ` <28a5c925-1445-18ea-52cd-afbc41bcc323-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-08-21  1:57       ` Deng, Emily
  0 siblings, 0 replies; 6+ messages in thread
From: Deng, Emily @ 2018-08-21  1:57 UTC (permalink / raw)
  To: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Liu, Monk

>-----Original Message-----
>From: Christian König <ckoenig.leichtzumerken@gmail.com>
>Sent: Monday, August 20, 2018 9:15 PM
>To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>Cc: Liu, Monk <Monk.Liu@amd.com>
>Subject: Re: [PATCH] amdgpu: fix multi-process hang issue
>
>Am 20.08.2018 um 05:35 schrieb Emily Deng:
>> From: Monk Liu <Monk.Liu@amd.com>
>>
>> SWDEV-146499: hang during multi vulkan process testing
>>
>> cause:
>> the second frame's PREAMBLE_IB have clear-state and LOAD actions,
>> those actions ruin the pipeline that is still doing process in the
>> previous frame's work-load IB.
>>
>> fix:
>> need insert pipeline sync if have context switch for SRIOV (because
>> only SRIOV will report PREEMPTION flag to UMD)
>>
>> Change-Id: If676da7a9b0147114cd76d19b6035ed8033de449
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 15 +++++++++++----
>>   1 file changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> index 5c22cfd..66efa85 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
>> @@ -95,6 +95,12 @@ void amdgpu_ib_free(struct amdgpu_device *adev,
>struct amdgpu_ib *ib,
>>   	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
>>   }
>>
>> +static bool amdgpu_ib_has_preamble(struct amdgpu_ring *ring, bool
>ctx_switch) {
>> +	return (amdgpu_sriov_vf(ring->adev) &&
>> +			ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
>> +			ctx_switch);
>> +}
>> +
>
>Well NAK, please merge that into amdgpu_ib_schedule() and drop the extra
>check for GFX, that will apply to compute queues as well.
>
>>   /**
>>    * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
>>    *
>> @@ -123,7 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
>unsigned num_ibs,
>>   	struct amdgpu_device *adev = ring->adev;
>>   	struct amdgpu_ib *ib = &ibs[0];
>>   	struct dma_fence *tmp = NULL;
>> -	bool skip_preamble, need_ctx_switch;
>> +	bool need_ctx_switch;
>>   	unsigned patch_offset = ~0;
>>   	struct amdgpu_vm *vm;
>>   	uint64_t fence_ctx;
>> @@ -156,6 +162,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
>unsigned num_ibs,
>>   		return -EINVAL;
>>   	}
>>
>> +	need_ctx_switch = ring->current_ctx != fence_ctx;
>> +
>>   	alloc_size = ring->funcs->emit_frame_size + num_ibs *
>>   		ring->funcs->emit_ib_size;
>>
>> @@ -167,6 +175,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
>> unsigned num_ibs,
>>
>>   	if (ring->funcs->emit_pipeline_sync && job &&
>>   	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
>> +		 amdgpu_ib_has_preamble(ring, need_ctx_switch) ||
>>   	     amdgpu_vm_need_pipeline_sync(ring, job))) {
>>   		need_pipe_sync = true;
>>
>> @@ -200,8 +209,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
>unsigned num_ibs,
>>   			amdgpu_asic_flush_hdp(adev, ring);
>>   	}
>>
>> -	skip_preamble = ring->current_ctx == fence_ctx;
>> -	need_ctx_switch = ring->current_ctx != fence_ctx;
>>   	if (job && ring->funcs->emit_cntxcntl) {
>>   		if (need_ctx_switch)
>>   			status |= AMDGPU_HAVE_CTX_SWITCH; @@ -215,7
>+222,7 @@ int
>> amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>>
>>   		/* drop preamble IBs if we don't have a context switch */
>>   		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
>> -			skip_preamble &&
>> +			!need_ctx_switch &&
>>   			!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST)
>&&
>>   			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption,
>Preamble CE ib
>> must be inserted anyway */
>
>Ok, please clean that up more carefully. All prerequisites which are not IB
>dependent should come before the loop.
>
>BTW: The handling of AMDGPU_PREAMBLE_IB_PRESENT_FIRST in amdgpu_cs.c
>is completely broken as well.
Thanks, will refine more carefully.
>
>Regards,
>Christian.
>
>>   			continue;

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] amdgpu: fix multi-process hang issue
       [not found] ` <1534939678-11489-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
@ 2018-08-22 12:16   ` Christian König
  0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2018-08-22 12:16 UTC (permalink / raw)
  To: Emily Deng, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Monk Liu

Am 22.08.2018 um 14:07 schrieb Emily Deng:
> SWDEV-146499: hang during multi vulkan process testing
>
> cause:
> the second frame's PREAMBLE_IB have clear-state
> and LOAD actions, those actions ruin the pipeline
> that is still doing process in the previous frame's
> work-load IB.
>
> fix:
> need insert pipeline sync if have context switch for
> SRIOV (because only SRIOV will report PREEMPTION flag
> to UMD)
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>

Much better, patch is Reviewed-by: Christian König 
<christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 5c22cfd..47817e0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -165,8 +165,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   		return r;
>   	}
>   
> +	need_ctx_switch = ring->current_ctx != fence_ctx;
>   	if (ring->funcs->emit_pipeline_sync && job &&
>   	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
> +	     (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
>   	     amdgpu_vm_need_pipeline_sync(ring, job))) {
>   		need_pipe_sync = true;
>   
> @@ -201,7 +203,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   	}
>   
>   	skip_preamble = ring->current_ctx == fence_ctx;
> -	need_ctx_switch = ring->current_ctx != fence_ctx;
>   	if (job && ring->funcs->emit_cntxcntl) {
>   		if (need_ctx_switch)
>   			status |= AMDGPU_HAVE_CTX_SWITCH;

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH] amdgpu: fix multi-process hang issue
@ 2018-08-22 12:07 Emily Deng
       [not found] ` <1534939678-11489-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Emily Deng @ 2018-08-22 12:07 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Emily Deng, Monk Liu

SWDEV-146499: hang during multi vulkan process testing

cause:
the second frame's PREAMBLE_IB have clear-state
and LOAD actions, those actions ruin the pipeline
that is still doing process in the previous frame's
work-load IB.

fix:
need insert pipeline sync if have context switch for
SRIOV (because only SRIOV will report PREEMPTION flag
to UMD)

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 5c22cfd..47817e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -165,8 +165,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 		return r;
 	}
 
+	need_ctx_switch = ring->current_ctx != fence_ctx;
 	if (ring->funcs->emit_pipeline_sync && job &&
 	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
+	     (amdgpu_sriov_vf(adev) && need_ctx_switch) ||
 	     amdgpu_vm_need_pipeline_sync(ring, job))) {
 		need_pipe_sync = true;
 
@@ -201,7 +203,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	}
 
 	skip_preamble = ring->current_ctx == fence_ctx;
-	need_ctx_switch = ring->current_ctx != fence_ctx;
 	if (job && ring->funcs->emit_cntxcntl) {
 		if (need_ctx_switch)
 			status |= AMDGPU_HAVE_CTX_SWITCH;
-- 
2.7.4

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] amdgpu: fix multi-process hang issue
@ 2018-08-20  3:05 Emily Deng
  0 siblings, 0 replies; 6+ messages in thread
From: Emily Deng @ 2018-08-20  3:05 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Monk Liu

From: Monk Liu <Monk.Liu@amd.com>

SWDEV-146499: hang during multi vulkan process testing

cause:
the second frame's PREAMBLE_IB have clear-state
and LOAD actions, those actions ruin the pipeline
that is still doing process in the previous frame's
work-load IB.

fix:
need insert pipeline sync if have context switch for
SRIOV (because only SRIOV will report PREEMPTION flag
to UMD)

Change-Id: If676da7a9b0147114cd76d19b6035ed8033de449
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 5c22cfd..66efa85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -95,6 +95,12 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
 	amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
 }
 
+static bool amdgpu_ib_has_preamble(struct amdgpu_ring *ring, bool ctx_switch) {
+	return (amdgpu_sriov_vf(ring->adev) &&
+			ring->funcs->type == AMDGPU_RING_TYPE_GFX &&
+			ctx_switch);
+}
+
 /**
  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  *
@@ -123,7 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_ib *ib = &ibs[0];
 	struct dma_fence *tmp = NULL;
-	bool skip_preamble, need_ctx_switch;
+	bool need_ctx_switch;
 	unsigned patch_offset = ~0;
 	struct amdgpu_vm *vm;
 	uint64_t fence_ctx;
@@ -156,6 +162,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 		return -EINVAL;
 	}
 
+	need_ctx_switch = ring->current_ctx != fence_ctx;
+
 	alloc_size = ring->funcs->emit_frame_size + num_ibs *
 		ring->funcs->emit_ib_size;
 
@@ -167,6 +175,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	if (ring->funcs->emit_pipeline_sync && job &&
 	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||
+		 amdgpu_ib_has_preamble(ring, need_ctx_switch) ||
 	     amdgpu_vm_need_pipeline_sync(ring, job))) {
 		need_pipe_sync = true;
 
@@ -200,8 +209,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 			amdgpu_asic_flush_hdp(adev, ring);
 	}
 
-	skip_preamble = ring->current_ctx == fence_ctx;
-	need_ctx_switch = ring->current_ctx != fence_ctx;
 	if (job && ring->funcs->emit_cntxcntl) {
 		if (need_ctx_switch)
 			status |= AMDGPU_HAVE_CTX_SWITCH;
@@ -215,7 +222,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 		/* drop preamble IBs if we don't have a context switch */
 		if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
-			skip_preamble &&
+			!need_ctx_switch &&
 			!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
 			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
 			continue;
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-08-22 12:16 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-20  3:35 [PATCH] amdgpu: fix multi-process hang issue Emily Deng
     [not found] ` <1534736155-14643-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
2018-08-20 13:15   ` Christian König
     [not found]     ` <28a5c925-1445-18ea-52cd-afbc41bcc323-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-21  1:57       ` Deng, Emily
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2018-08-22 12:07 Emily Deng
     [not found] ` <1534939678-11489-1-git-send-email-Emily.Deng-5C7GfCeVMHo@public.gmane.org>
2018-08-22 12:16   ` Christian König
2018-08-20  3:05 Emily Deng

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