[U-Boot] [PATCH 1/2] fpga: zynqpl: Add support for zc7100 device.

[U-Boot] [PATCH 1/2] fpga: zynqpl: Add support for zc7100 device.

[Michal Simek]

- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 board/xilinx/zynq/board.c | 4 ++++
 drivers/fpga/zynqpl.c     | 2 +-
 include/zynqpl.h          | 5 +++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index b02c364..c2046cf 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -36,6 +36,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif

 int board_init(void)
@@ -58,6 +59,9 @@ int board_init(void)
 	case XILINX_ZYNQ_7045:
 		fpga = fpga045;
 		break;
+	case XILINX_ZYNQ_7100:
+		fpga = fpga100;
+		break;
 	}
 #endif

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 8feccde..6a5764f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -47,7 +47,7 @@
 #endif

 #ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ	/* 1 s */
+#define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
 #endif

 int zynq_info(Xilinx_desc *desc)
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 0247ef6..c5ea745 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -36,12 +36,14 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
 #define XILINX_ZYNQ_7045	0x11
+#define XILINX_ZYNQ_7100	0x16

 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE	16669920/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
 #define XILINX_XC7Z045_SIZE	106571232/8
+#define XILINX_XC7Z100_SIZE	139330784/8

 /* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
@@ -56,4 +58,7 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_XC7Z045_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }

+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+
 #endif /* _ZYNQPL_H_ */
--
1.8.2.3

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[U-Boot] [PATCH 2/2] fpga: zynqpl: Clear loopback mode during device init

[Michal Simek]

From: Soren Brinkmann <soren.brinkmann@xilinx.com>

Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.

In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

---
 drivers/fpga/zynqpl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 6a5764f..7f5d90f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -39,6 +39,7 @@
 #define DEVCFG_STATUS_DMA_CMD_Q_E	0x40000000
 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000
 #define DEVCFG_STATUS_PCFG_INIT		0x00000010
+#define DEVCFG_MCTRL_PCAP_LPBK		0x00000010
 #define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
 #define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001

@@ -216,6 +217,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		swap = SWAP_DONE;
 	}

+	/* Clear loopback bit */
+	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
+
 	if (!partialbit) {
 		zynq_slcr_devcfg_disable();

--
1.8.2.3

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