* [PATCH 01/30] q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty array
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:15 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 02/30] q800: introduce Q800MachineState Mark Cave-Ayland
` (28 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Ensure there is a space before the final closing brace for all global
properties.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index b35ecafbc7..1aead224e2 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -719,14 +719,14 @@ static void q800_init(MachineState *machine)
}
static GlobalProperty hw_compat_q800[] = {
- { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on"},
+ { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
{ "scsi-hd", "vendor", " SEAGATE" },
{ "scsi-hd", "product", " ST225N" },
{ "scsi-hd", "ver", "1.0 " },
- { "scsi-cd", "quirk_mode_page_apple_vendor", "on"},
- { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on"},
- { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on"},
- { "scsi-cd", "quirk_mode_page_truncated", "on"},
+ { "scsi-cd", "quirk_mode_page_apple_vendor", "on" },
+ { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" },
+ { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" },
+ { "scsi-cd", "quirk_mode_page_truncated", "on" },
{ "scsi-cd", "vendor", "MATSHITA" },
{ "scsi-cd", "product", "CD-ROM CR-8005" },
{ "scsi-cd", "ver", "1.0k" },
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 01/30] q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty array
2023-05-24 21:10 ` [PATCH 01/30] q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty array Mark Cave-Ayland
@ 2023-05-30 11:15 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:15 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Ensure there is a space before the final closing brace for all global
> properties.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index b35ecafbc7..1aead224e2 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -719,14 +719,14 @@ static void q800_init(MachineState *machine)
> }
>
> static GlobalProperty hw_compat_q800[] = {
> - { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on"},
> + { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
> { "scsi-hd", "vendor", " SEAGATE" },
> { "scsi-hd", "product", " ST225N" },
> { "scsi-hd", "ver", "1.0 " },
> - { "scsi-cd", "quirk_mode_page_apple_vendor", "on"},
> - { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on"},
> - { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on"},
> - { "scsi-cd", "quirk_mode_page_truncated", "on"},
> + { "scsi-cd", "quirk_mode_page_apple_vendor", "on" },
> + { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" },
> + { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" },
> + { "scsi-cd", "quirk_mode_page_truncated", "on" },
> { "scsi-cd", "vendor", "MATSHITA" },
> { "scsi-cd", "product", "CD-ROM CR-8005" },
> { "scsi-cd", "ver", "1.0k" },
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 02/30] q800: introduce Q800MachineState
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 01/30] q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty array Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:15 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 03/30] q800: rename q800_init() to q800_machine_init() Mark Cave-Ayland
` (27 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
This provides an overall container and owner for Machine-related objects such
as MemoryRegions.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
MAINTAINERS | 1 +
hw/m68k/q800.c | 2 ++
include/hw/m68k/q800.h | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 40 insertions(+)
create mode 100644 include/hw/m68k/q800.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c93ab0ee5..86a1b88863 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1234,6 +1234,7 @@ F: include/hw/misc/mac_via.h
F: include/hw/nubus/*
F: include/hw/display/macfb.h
F: include/hw/block/swim.h
+F: include/hw/m68k/q800.h
virt
M: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 1aead224e2..bdccd93c7f 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -38,6 +38,7 @@
#include "standard-headers/asm-m68k/bootinfo.h"
#include "standard-headers/asm-m68k/bootinfo-mac.h"
#include "bootinfo.h"
+#include "hw/m68k/q800.h"
#include "hw/misc/mac_via.h"
#include "hw/input/adb.h"
#include "hw/nubus/mac-nubus-bridge.h"
@@ -748,6 +749,7 @@ static void q800_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo q800_machine_typeinfo = {
.name = MACHINE_TYPE_NAME("q800"),
.parent = TYPE_MACHINE,
+ .instance_size = sizeof(Q800MachineState),
.class_init = q800_machine_class_init,
};
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
new file mode 100644
index 0000000000..560fd6f93d
--- /dev/null
+++ b/include/hw/m68k/q800.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU Motorla 680x0 Macintosh hardware System Emulator
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_Q800_H
+#define HW_Q800_H
+
+/*
+ * The main Q800 machine
+ */
+
+struct Q800MachineState {
+ MachineState parent_obj;
+};
+
+#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
+OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, q800, Q800_MACHINE, MachineState)
+
+#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 02/30] q800: introduce Q800MachineState
2023-05-24 21:10 ` [PATCH 02/30] q800: introduce Q800MachineState Mark Cave-Ayland
@ 2023-05-30 11:15 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:15 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> This provides an overall container and owner for Machine-related objects such
> as MemoryRegions.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> MAINTAINERS | 1 +
> hw/m68k/q800.c | 2 ++
> include/hw/m68k/q800.h | 37 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 40 insertions(+)
> create mode 100644 include/hw/m68k/q800.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1c93ab0ee5..86a1b88863 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1234,6 +1234,7 @@ F: include/hw/misc/mac_via.h
> F: include/hw/nubus/*
> F: include/hw/display/macfb.h
> F: include/hw/block/swim.h
> +F: include/hw/m68k/q800.h
>
> virt
> M: Laurent Vivier <laurent@vivier.eu>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 1aead224e2..bdccd93c7f 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -38,6 +38,7 @@
> #include "standard-headers/asm-m68k/bootinfo.h"
> #include "standard-headers/asm-m68k/bootinfo-mac.h"
> #include "bootinfo.h"
> +#include "hw/m68k/q800.h"
> #include "hw/misc/mac_via.h"
> #include "hw/input/adb.h"
> #include "hw/nubus/mac-nubus-bridge.h"
> @@ -748,6 +749,7 @@ static void q800_machine_class_init(ObjectClass *oc, void *data)
> static const TypeInfo q800_machine_typeinfo = {
> .name = MACHINE_TYPE_NAME("q800"),
> .parent = TYPE_MACHINE,
> + .instance_size = sizeof(Q800MachineState),
> .class_init = q800_machine_class_init,
> };
>
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> new file mode 100644
> index 0000000000..560fd6f93d
> --- /dev/null
> +++ b/include/hw/m68k/q800.h
> @@ -0,0 +1,37 @@
> +/*
> + * QEMU Motorla 680x0 Macintosh hardware System Emulator
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_Q800_H
> +#define HW_Q800_H
> +
> +/*
> + * The main Q800 machine
> + */
> +
> +struct Q800MachineState {
> + MachineState parent_obj;
> +};
> +
> +#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
> +OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, q800, Q800_MACHINE, MachineState)
> +
> +#endif
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 03/30] q800: rename q800_init() to q800_machine_init()
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 01/30] q800: fix up minor spacing issues in hw_compat_q800 GlobalProperty array Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 02/30] q800: introduce Q800MachineState Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:16 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 04/30] q800: move CPU object into Q800MachineState Mark Cave-Ayland
` (26 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
This will enable us later to distinguish between QOM initialisation and machine
initialisation.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index bdccd93c7f..976da06231 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -361,7 +361,7 @@ static uint8_t fake_mac_rom[] = {
0x60, 0xFE /* bras [self] */
};
-static void q800_init(MachineState *machine)
+static void q800_machine_init(MachineState *machine)
{
M68kCPU *cpu = NULL;
int linux_boot;
@@ -737,8 +737,9 @@ static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
static void q800_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "Macintosh Quadra 800";
- mc->init = q800_init;
+ mc->init = q800_machine_init;
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
mc->max_cpus = 1;
mc->block_default_type = IF_SCSI;
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 03/30] q800: rename q800_init() to q800_machine_init()
2023-05-24 21:10 ` [PATCH 03/30] q800: rename q800_init() to q800_machine_init() Mark Cave-Ayland
@ 2023-05-30 11:16 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:16 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> This will enable us later to distinguish between QOM initialisation and machine
> initialisation.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index bdccd93c7f..976da06231 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -361,7 +361,7 @@ static uint8_t fake_mac_rom[] = {
> 0x60, 0xFE /* bras [self] */
> };
>
> -static void q800_init(MachineState *machine)
> +static void q800_machine_init(MachineState *machine)
> {
> M68kCPU *cpu = NULL;
> int linux_boot;
> @@ -737,8 +737,9 @@ static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
> static void q800_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> +
> mc->desc = "Macintosh Quadra 800";
> - mc->init = q800_init;
> + mc->init = q800_machine_init;
> mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
> mc->max_cpus = 1;
> mc->block_default_type = IF_SCSI;
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 04/30] q800: move CPU object into Q800MachineState
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (2 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 03/30] q800: rename q800_init() to q800_machine_init() Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 8:07 ` Philippe Mathieu-Daudé
2023-05-30 11:18 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 05/30] q800: move ROM memory region to Q800MachineState Mark Cave-Ayland
` (25 subsequent siblings)
29 siblings, 2 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 10 +++++-----
include/hw/m68k/q800.h | 4 +++-
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 976da06231..ee6175ceb4 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -363,7 +363,7 @@ static uint8_t fake_mac_rom[] = {
static void q800_machine_init(MachineState *machine)
{
- M68kCPU *cpu = NULL;
+ Q800MachineState *m = Q800_MACHINE(machine);
int linux_boot;
int32_t kernel_size;
uint64_t elf_entry;
@@ -406,8 +406,8 @@ static void q800_machine_init(MachineState *machine)
}
/* init CPUs */
- cpu = M68K_CPU(cpu_create(machine->cpu_type));
- qemu_register_reset(main_cpu_reset, cpu);
+ m->cpu = M68K_CPU(cpu_create(machine->cpu_type));
+ qemu_register_reset(main_cpu_reset, m->cpu);
/* RAM */
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
@@ -429,7 +429,7 @@ static void q800_machine_init(MachineState *machine)
/* IRQ Glue */
glue = qdev_new(TYPE_GLUE);
- object_property_set_link(OBJECT(glue), "cpu", OBJECT(cpu), &error_abort);
+ object_property_set_link(OBJECT(glue), "cpu", OBJECT(m->cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
/* VIA 1 */
@@ -604,7 +604,7 @@ static void q800_machine_init(MachineState *machine)
macfb_mode = (NUBUS_MACFB(dev)->macfb).mode;
- cs = CPU(cpu);
+ cs = CPU(m->cpu);
if (linux_boot) {
uint64_t high;
void *param_blob, *param_ptr, *param_rng_seed;
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 560fd6f93d..5867c3ae33 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -29,9 +29,11 @@
struct Q800MachineState {
MachineState parent_obj;
+
+ M68kCPU *cpu;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
-OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, q800, Q800_MACHINE, MachineState)
+OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, Q800_MACHINE)
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 04/30] q800: move CPU object into Q800MachineState
2023-05-24 21:10 ` [PATCH 04/30] q800: move CPU object into Q800MachineState Mark Cave-Ayland
@ 2023-05-25 8:07 ` Philippe Mathieu-Daudé
2023-05-30 11:18 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 8:07 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 10 +++++-----
> include/hw/m68k/q800.h | 4 +++-
> 2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 976da06231..ee6175ceb4 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -363,7 +363,7 @@ static uint8_t fake_mac_rom[] = {
>
> static void q800_machine_init(MachineState *machine)
> {
> - M68kCPU *cpu = NULL;
> + Q800MachineState *m = Q800_MACHINE(machine);
> int linux_boot;
> int32_t kernel_size;
> uint64_t elf_entry;
> @@ -406,8 +406,8 @@ static void q800_machine_init(MachineState *machine)
> }
>
> /* init CPUs */
> - cpu = M68K_CPU(cpu_create(machine->cpu_type));
> - qemu_register_reset(main_cpu_reset, cpu);
> + m->cpu = M68K_CPU(cpu_create(machine->cpu_type));
> + qemu_register_reset(main_cpu_reset, m->cpu);
>
> /* RAM */
> memory_region_add_subregion(get_system_memory(), 0, machine->ram);
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 560fd6f93d..5867c3ae33 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -29,9 +29,11 @@
>
> struct Q800MachineState {
> MachineState parent_obj;
> +
> + M68kCPU *cpu;
This is a good opportunity to allocate M68kCPU in Q800MachineState
and call object_initialize_child/qdev_realize instead of cpu_create.
Can be done later, so meanwhile:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
> -OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, q800, Q800_MACHINE, MachineState)
> +OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, Q800_MACHINE)
>
> #endif
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 04/30] q800: move CPU object into Q800MachineState
2023-05-24 21:10 ` [PATCH 04/30] q800: move CPU object into Q800MachineState Mark Cave-Ayland
2023-05-25 8:07 ` Philippe Mathieu-Daudé
@ 2023-05-30 11:18 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:18 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 10 +++++-----
> include/hw/m68k/q800.h | 4 +++-
> 2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 976da06231..ee6175ceb4 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -363,7 +363,7 @@ static uint8_t fake_mac_rom[] = {
>
> static void q800_machine_init(MachineState *machine)
> {
> - M68kCPU *cpu = NULL;
> + Q800MachineState *m = Q800_MACHINE(machine);
> int linux_boot;
> int32_t kernel_size;
> uint64_t elf_entry;
> @@ -406,8 +406,8 @@ static void q800_machine_init(MachineState *machine)
> }
>
> /* init CPUs */
> - cpu = M68K_CPU(cpu_create(machine->cpu_type));
> - qemu_register_reset(main_cpu_reset, cpu);
> + m->cpu = M68K_CPU(cpu_create(machine->cpu_type));
> + qemu_register_reset(main_cpu_reset, m->cpu);
>
> /* RAM */
> memory_region_add_subregion(get_system_memory(), 0, machine->ram);
> @@ -429,7 +429,7 @@ static void q800_machine_init(MachineState *machine)
>
> /* IRQ Glue */
> glue = qdev_new(TYPE_GLUE);
> - object_property_set_link(OBJECT(glue), "cpu", OBJECT(cpu), &error_abort);
> + object_property_set_link(OBJECT(glue), "cpu", OBJECT(m->cpu), &error_abort);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
>
> /* VIA 1 */
> @@ -604,7 +604,7 @@ static void q800_machine_init(MachineState *machine)
>
> macfb_mode = (NUBUS_MACFB(dev)->macfb).mode;
>
> - cs = CPU(cpu);
> + cs = CPU(m->cpu);
> if (linux_boot) {
> uint64_t high;
> void *param_blob, *param_ptr, *param_rng_seed;
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 560fd6f93d..5867c3ae33 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -29,9 +29,11 @@
>
> struct Q800MachineState {
> MachineState parent_obj;
> +
> + M68kCPU *cpu;
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
> -OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, q800, Q800_MACHINE, MachineState)
> +OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, Q800_MACHINE)
>
> #endif
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 05/30] q800: move ROM memory region to Q800MachineState
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (3 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 04/30] q800: move CPU object into Q800MachineState Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 8:08 ` Philippe Mathieu-Daudé
2023-05-30 11:19 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 06/30] q800: move GLUE device " Mark Cave-Ayland
` (24 subsequent siblings)
29 siblings, 2 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 13 +++++--------
include/hw/m68k/q800.h | 1 +
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index ee6175ceb4..6a000ceb75 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -371,7 +371,6 @@ static void q800_machine_init(MachineState *machine)
int bios_size;
ram_addr_t initrd_base;
int32_t initrd_size;
- MemoryRegion *rom;
MemoryRegion *io;
MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
uint8_t *prom;
@@ -643,11 +642,10 @@ static void q800_machine_init(MachineState *machine)
BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride);
BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE);
- rom = g_malloc(sizeof(*rom));
- memory_region_init_ram_ptr(rom, NULL, "m68k_fake_mac.rom",
+ memory_region_init_ram_ptr(&m->rom, NULL, "m68k_fake_mac.rom",
sizeof(fake_mac_rom), fake_mac_rom);
- memory_region_set_readonly(rom, true);
- memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
+ memory_region_set_readonly(&m->rom, true);
+ memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
if (kernel_cmdline) {
BOOTINFOSTR(param_ptr, BI_COMMAND_LINE,
@@ -689,11 +687,10 @@ static void q800_machine_init(MachineState *machine)
} else {
uint8_t *ptr;
/* allocate and load BIOS */
- rom = g_malloc(sizeof(*rom));
- memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
+ memory_region_init_rom(&m->rom, NULL, "m68k_mac.rom", MACROM_SIZE,
&error_abort);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
+ memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
/* Load MacROM binary */
if (filename) {
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 5867c3ae33..2f3c720b8d 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -31,6 +31,7 @@ struct Q800MachineState {
MachineState parent_obj;
M68kCPU *cpu;
+ MemoryRegion rom;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 05/30] q800: move ROM memory region to Q800MachineState
2023-05-24 21:10 ` [PATCH 05/30] q800: move ROM memory region to Q800MachineState Mark Cave-Ayland
@ 2023-05-25 8:08 ` Philippe Mathieu-Daudé
2023-05-30 11:19 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 8:08 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 13 +++++--------
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 6 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 05/30] q800: move ROM memory region to Q800MachineState
2023-05-24 21:10 ` [PATCH 05/30] q800: move ROM memory region to Q800MachineState Mark Cave-Ayland
2023-05-25 8:08 ` Philippe Mathieu-Daudé
@ 2023-05-30 11:19 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:19 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 13 +++++--------
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index ee6175ceb4..6a000ceb75 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -371,7 +371,6 @@ static void q800_machine_init(MachineState *machine)
> int bios_size;
> ram_addr_t initrd_base;
> int32_t initrd_size;
> - MemoryRegion *rom;
> MemoryRegion *io;
> MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
> uint8_t *prom;
> @@ -643,11 +642,10 @@ static void q800_machine_init(MachineState *machine)
> BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride);
> BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE);
>
> - rom = g_malloc(sizeof(*rom));
> - memory_region_init_ram_ptr(rom, NULL, "m68k_fake_mac.rom",
> + memory_region_init_ram_ptr(&m->rom, NULL, "m68k_fake_mac.rom",
> sizeof(fake_mac_rom), fake_mac_rom);
> - memory_region_set_readonly(rom, true);
> - memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
> + memory_region_set_readonly(&m->rom, true);
> + memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
>
> if (kernel_cmdline) {
> BOOTINFOSTR(param_ptr, BI_COMMAND_LINE,
> @@ -689,11 +687,10 @@ static void q800_machine_init(MachineState *machine)
> } else {
> uint8_t *ptr;
> /* allocate and load BIOS */
> - rom = g_malloc(sizeof(*rom));
> - memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
> + memory_region_init_rom(&m->rom, NULL, "m68k_mac.rom", MACROM_SIZE,
> &error_abort);
> filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> - memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
> + memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
>
> /* Load MacROM binary */
> if (filename) {
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 5867c3ae33..2f3c720b8d 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -31,6 +31,7 @@ struct Q800MachineState {
> MachineState parent_obj;
>
> M68kCPU *cpu;
> + MemoryRegion rom;
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 06/30] q800: move GLUE device to Q800MachineState
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (4 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 05/30] q800: move ROM memory region to Q800MachineState Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:19 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 07/30] q800: introduce mac-io container memory region Mark Cave-Ayland
` (23 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 20 ++++++++++----------
include/hw/m68k/q800.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 6a000ceb75..c22a98d616 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -392,7 +392,6 @@ static void q800_machine_init(MachineState *machine)
SysBusDevice *sysbus;
BusState *adb_bus;
NubusBus *nubus;
- DeviceState *glue;
DriveInfo *dinfo;
uint8_t rng_seed[32];
@@ -427,9 +426,10 @@ static void q800_machine_init(MachineState *machine)
}
/* IRQ Glue */
- glue = qdev_new(TYPE_GLUE);
- object_property_set_link(OBJECT(glue), "cpu", OBJECT(m->cpu), &error_abort);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
+ m->glue = qdev_new(TYPE_GLUE);
+ object_property_set_link(OBJECT(m->glue), "cpu", OBJECT(m->cpu),
+ &error_abort);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(m->glue), &error_fatal);
/* VIA 1 */
via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
@@ -440,10 +440,10 @@ static void q800_machine_init(MachineState *machine)
sysbus = SYS_BUS_DEVICE(via1_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 1, VIA_BASE);
- sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1));
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA1));
/* A/UX mode */
qdev_connect_gpio_out(via1_dev, 0,
- qdev_get_gpio_in_named(glue, "auxmode", 0));
+ qdev_get_gpio_in_named(m->glue, "auxmode", 0));
adb_bus = qdev_get_child_bus(via1_dev, "adb.0");
dev = qdev_new(TYPE_ADB_KEYBOARD);
@@ -456,7 +456,7 @@ static void q800_machine_init(MachineState *machine)
sysbus = SYS_BUS_DEVICE(via2_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
- sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2));
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA2));
/* MACSONIC */
@@ -489,7 +489,7 @@ static void q800_machine_init(MachineState *machine)
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, SONIC_BASE);
- sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC));
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_SONIC));
memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
SONIC_PROM_SIZE, &error_fatal);
@@ -526,7 +526,7 @@ static void q800_machine_init(MachineState *machine)
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0));
sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
- qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC));
+ qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_ESCC));
sysbus_mmio_map(sysbus, 0, SCC_BASE);
/* SCSI */
@@ -581,7 +581,7 @@ static void q800_machine_init(MachineState *machine)
* Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
* IRQ via GLUE for use by SONIC Ethernet in classic mode
*/
- qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9,
+ qdev_connect_gpio_out(m->glue, GLUE_IRQ_NUBUS_9,
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
VIA2_NUBUS_IRQ_9));
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 2f3c720b8d..de02af53be 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -32,6 +32,7 @@ struct Q800MachineState {
M68kCPU *cpu;
MemoryRegion rom;
+ DeviceState *glue;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 06/30] q800: move GLUE device to Q800MachineState
2023-05-24 21:10 ` [PATCH 06/30] q800: move GLUE device " Mark Cave-Ayland
@ 2023-05-30 11:19 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:19 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 20 ++++++++++----------
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 6a000ceb75..c22a98d616 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -392,7 +392,6 @@ static void q800_machine_init(MachineState *machine)
> SysBusDevice *sysbus;
> BusState *adb_bus;
> NubusBus *nubus;
> - DeviceState *glue;
> DriveInfo *dinfo;
> uint8_t rng_seed[32];
>
> @@ -427,9 +426,10 @@ static void q800_machine_init(MachineState *machine)
> }
>
> /* IRQ Glue */
> - glue = qdev_new(TYPE_GLUE);
> - object_property_set_link(OBJECT(glue), "cpu", OBJECT(m->cpu), &error_abort);
> - sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
> + m->glue = qdev_new(TYPE_GLUE);
> + object_property_set_link(OBJECT(m->glue), "cpu", OBJECT(m->cpu),
> + &error_abort);
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(m->glue), &error_fatal);
>
> /* VIA 1 */
> via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
> @@ -440,10 +440,10 @@ static void q800_machine_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(via1_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 1, VIA_BASE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA1));
> /* A/UX mode */
> qdev_connect_gpio_out(via1_dev, 0,
> - qdev_get_gpio_in_named(glue, "auxmode", 0));
> + qdev_get_gpio_in_named(m->glue, "auxmode", 0));
>
> adb_bus = qdev_get_child_bus(via1_dev, "adb.0");
> dev = qdev_new(TYPE_ADB_KEYBOARD);
> @@ -456,7 +456,7 @@ static void q800_machine_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(via2_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA2));
>
> /* MACSONIC */
>
> @@ -489,7 +489,7 @@ static void q800_machine_init(MachineState *machine)
> sysbus = SYS_BUS_DEVICE(dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> sysbus_mmio_map(sysbus, 0, SONIC_BASE);
> - sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC));
> + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_SONIC));
>
> memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
> SONIC_PROM_SIZE, &error_fatal);
> @@ -526,7 +526,7 @@ static void q800_machine_init(MachineState *machine)
> sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0));
> sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
> qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
> - qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC));
> + qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_ESCC));
> sysbus_mmio_map(sysbus, 0, SCC_BASE);
>
> /* SCSI */
> @@ -581,7 +581,7 @@ static void q800_machine_init(MachineState *machine)
> * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
> * IRQ via GLUE for use by SONIC Ethernet in classic mode
> */
> - qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9,
> + qdev_connect_gpio_out(m->glue, GLUE_IRQ_NUBUS_9,
> qdev_get_gpio_in_named(via2_dev, "nubus-irq",
> VIA2_NUBUS_IRQ_9));
>
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 2f3c720b8d..de02af53be 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -32,6 +32,7 @@ struct Q800MachineState {
>
> M68kCPU *cpu;
> MemoryRegion rom;
> + DeviceState *glue;
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 07/30] q800: introduce mac-io container memory region
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (5 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 06/30] q800: move GLUE device " Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:23 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 08/30] q800: reimplement mac-io region aliasing using IO " Mark Cave-Ayland
` (22 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Move all devices from the IO region to within the container in preparation
for updating the IO aliasing mechanism.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 6 ++++++
include/hw/m68k/q800.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index c22a98d616..6399631ed0 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -410,6 +410,12 @@ static void q800_machine_init(MachineState *machine)
/* RAM */
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
+ /*
+ * Create container for all IO devices
+ */
+ memory_region_init(&m->macio, NULL, "mac-io", IO_SLICE);
+ memory_region_add_subregion(get_system_memory(), IO_BASE, &m->macio);
+
/*
* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index de02af53be..156872a124 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -33,6 +33,7 @@ struct Q800MachineState {
M68kCPU *cpu;
MemoryRegion rom;
DeviceState *glue;
+ MemoryRegion macio;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 07/30] q800: introduce mac-io container memory region
2023-05-24 21:10 ` [PATCH 07/30] q800: introduce mac-io container memory region Mark Cave-Ayland
@ 2023-05-30 11:23 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:23 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Move all devices from the IO region to within the container in preparation
> for updating the IO aliasing mechanism.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 6 ++++++
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index c22a98d616..6399631ed0 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -410,6 +410,12 @@ static void q800_machine_init(MachineState *machine)
> /* RAM */
> memory_region_add_subregion(get_system_memory(), 0, machine->ram);
>
> + /*
> + * Create container for all IO devices
> + */
> + memory_region_init(&m->macio, NULL, "mac-io", IO_SLICE);
> + memory_region_add_subregion(get_system_memory(), IO_BASE, &m->macio);
> +
> /*
> * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
> * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index de02af53be..156872a124 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -33,6 +33,7 @@ struct Q800MachineState {
> M68kCPU *cpu;
> MemoryRegion rom;
> DeviceState *glue;
> + MemoryRegion macio;
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 08/30] q800: reimplement mac-io region aliasing using IO memory region
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (6 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 07/30] q800: introduce mac-io container memory region Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:23 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 09/30] q800: add djMEMC memory controller Mark Cave-Ayland
` (21 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The current use of aliased memory regions causes us 2 problems: firstly the
output of "info qom-tree" is absolutely huge and difficult to read, and
secondly we have already reached the internal limit for memory regions as
adding any new memory region into the mac-io region causes QEMU to assert
with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE'
failed".
Implement the mac-io region aliasing using a single IO memory region that
applies IO_SLICE_MASK representing the maximum size of the aliased region and
then forwarding the access to the existing mac-io memory region using the
address space API.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 100 +++++++++++++++++++++++++++++++++--------
include/hw/m68k/q800.h | 1 +
2 files changed, 82 insertions(+), 19 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 6399631ed0..f15f1eaff9 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -59,6 +59,7 @@
#define IO_BASE 0x50000000
#define IO_SLICE 0x00040000
+#define IO_SLICE_MASK (IO_SLICE - 1)
#define IO_SIZE 0x04000000
#define VIA_BASE (IO_BASE + 0x00000)
@@ -361,6 +362,68 @@ static uint8_t fake_mac_rom[] = {
0x60, 0xFE /* bras [self] */
};
+static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ MemTxResult r;
+ uint32_t val;
+
+ addr &= IO_SLICE_MASK;
+ addr |= IO_BASE;
+
+ switch (size) {
+ case 4:
+ val = address_space_ldl_be(&address_space_memory, addr, attrs, &r);
+ break;
+ case 2:
+ val = address_space_lduw_be(&address_space_memory, addr, attrs, &r);
+ break;
+ case 1:
+ val = address_space_ldub(&address_space_memory, addr, attrs, &r);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ *data = val;
+ return r;
+}
+
+static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size, MemTxAttrs attrs)
+{
+ MemTxResult r;
+
+ addr &= IO_SLICE_MASK;
+ addr |= IO_BASE;
+
+ switch (size) {
+ case 4:
+ address_space_stl_be(&address_space_memory, addr, value, attrs, &r);
+ break;
+ case 2:
+ address_space_stw_be(&address_space_memory, addr, value, attrs, &r);
+ break;
+ case 1:
+ address_space_stb(&address_space_memory, addr, value, attrs, &r);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return r;
+}
+
+static const MemoryRegionOps macio_alias_ops = {
+ .read_with_attrs = macio_alias_read,
+ .write_with_attrs = macio_alias_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
static void q800_machine_init(MachineState *machine)
{
Q800MachineState *m = Q800_MACHINE(machine);
@@ -371,10 +434,8 @@ static void q800_machine_init(MachineState *machine)
int bios_size;
ram_addr_t initrd_base;
int32_t initrd_size;
- MemoryRegion *io;
MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
uint8_t *prom;
- const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
int i, checksum;
MacFbMode *macfb_mode;
ram_addr_t ram_size = machine->ram_size;
@@ -420,16 +481,10 @@ static void q800_machine_init(MachineState *machine)
* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
*/
- io = g_new(MemoryRegion, io_slice_nb);
- for (i = 0; i < io_slice_nb; i++) {
- char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
-
- memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
- IO_BASE, IO_SLICE);
- memory_region_add_subregion(get_system_memory(),
- IO_BASE + (i + 1) * IO_SLICE, &io[i]);
- g_free(name);
- }
+ memory_region_init_io(&m->macio_alias, NULL, &macio_alias_ops, &m->macio,
+ "mac-io.alias", IO_SIZE - IO_SLICE);
+ memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
+ &m->macio_alias);
/* IRQ Glue */
m->glue = qdev_new(TYPE_GLUE);
@@ -445,7 +500,8 @@ static void q800_machine_init(MachineState *machine)
}
sysbus = SYS_BUS_DEVICE(via1_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
- sysbus_mmio_map(sysbus, 1, VIA_BASE);
+ memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 1));
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA1));
/* A/UX mode */
qdev_connect_gpio_out(via1_dev, 0,
@@ -461,7 +517,8 @@ static void q800_machine_init(MachineState *machine)
via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
sysbus = SYS_BUS_DEVICE(via2_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
- sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
+ memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE,
+ sysbus_mmio_get_region(sysbus, 1));
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA2));
/* MACSONIC */
@@ -494,7 +551,8 @@ static void q800_machine_init(MachineState *machine)
OBJECT(get_system_memory()), &error_abort);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
- sysbus_mmio_map(sysbus, 0, SONIC_BASE);
+ memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 0));
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_SONIC));
memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
@@ -533,7 +591,8 @@ static void q800_machine_init(MachineState *machine)
sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_ESCC));
- sysbus_mmio_map(sysbus, 0, SCC_BASE);
+ memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 0));
/* SCSI */
@@ -553,8 +612,10 @@ static void q800_machine_init(MachineState *machine)
VIA2_IRQ_SCSI_BIT)));
sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
VIA2_IRQ_SCSI_DATA_BIT)));
- sysbus_mmio_map(sysbus, 0, ESP_BASE);
- sysbus_mmio_map(sysbus, 1, ESP_PDMA);
+ memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 0));
+ memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 1));
scsi_bus_legacy_handle_cmdline(&esp->bus);
@@ -562,7 +623,8 @@ static void q800_machine_init(MachineState *machine)
dev = qdev_new(TYPE_SWIM);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
+ memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
/* NuBus */
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 156872a124..8d788a7072 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -34,6 +34,7 @@ struct Q800MachineState {
MemoryRegion rom;
DeviceState *glue;
MemoryRegion macio;
+ MemoryRegion macio_alias;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 08/30] q800: reimplement mac-io region aliasing using IO memory region
2023-05-24 21:10 ` [PATCH 08/30] q800: reimplement mac-io region aliasing using IO " Mark Cave-Ayland
@ 2023-05-30 11:23 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:23 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> The current use of aliased memory regions causes us 2 problems: firstly the
> output of "info qom-tree" is absolutely huge and difficult to read, and
> secondly we have already reached the internal limit for memory regions as
> adding any new memory region into the mac-io region causes QEMU to assert
> with "phys_section_add: Assertion `map->sections_nb < TARGET_PAGE_SIZE'
> failed".
>
> Implement the mac-io region aliasing using a single IO memory region that
> applies IO_SLICE_MASK representing the maximum size of the aliased region and
> then forwarding the access to the existing mac-io memory region using the
> address space API.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 100 +++++++++++++++++++++++++++++++++--------
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 82 insertions(+), 19 deletions(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 6399631ed0..f15f1eaff9 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -59,6 +59,7 @@
>
> #define IO_BASE 0x50000000
> #define IO_SLICE 0x00040000
> +#define IO_SLICE_MASK (IO_SLICE - 1)
> #define IO_SIZE 0x04000000
>
> #define VIA_BASE (IO_BASE + 0x00000)
> @@ -361,6 +362,68 @@ static uint8_t fake_mac_rom[] = {
> 0x60, 0xFE /* bras [self] */
> };
>
> +static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *data,
> + unsigned size, MemTxAttrs attrs)
> +{
> + MemTxResult r;
> + uint32_t val;
> +
> + addr &= IO_SLICE_MASK;
> + addr |= IO_BASE;
> +
> + switch (size) {
> + case 4:
> + val = address_space_ldl_be(&address_space_memory, addr, attrs, &r);
> + break;
> + case 2:
> + val = address_space_lduw_be(&address_space_memory, addr, attrs, &r);
> + break;
> + case 1:
> + val = address_space_ldub(&address_space_memory, addr, attrs, &r);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + *data = val;
> + return r;
> +}
> +
> +static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size, MemTxAttrs attrs)
> +{
> + MemTxResult r;
> +
> + addr &= IO_SLICE_MASK;
> + addr |= IO_BASE;
> +
> + switch (size) {
> + case 4:
> + address_space_stl_be(&address_space_memory, addr, value, attrs, &r);
> + break;
> + case 2:
> + address_space_stw_be(&address_space_memory, addr, value, attrs, &r);
> + break;
> + case 1:
> + address_space_stb(&address_space_memory, addr, value, attrs, &r);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + return r;
> +}
> +
> +static const MemoryRegionOps macio_alias_ops = {
> + .read_with_attrs = macio_alias_read,
> + .write_with_attrs = macio_alias_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> static void q800_machine_init(MachineState *machine)
> {
> Q800MachineState *m = Q800_MACHINE(machine);
> @@ -371,10 +434,8 @@ static void q800_machine_init(MachineState *machine)
> int bios_size;
> ram_addr_t initrd_base;
> int32_t initrd_size;
> - MemoryRegion *io;
> MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
> uint8_t *prom;
> - const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
> int i, checksum;
> MacFbMode *macfb_mode;
> ram_addr_t ram_size = machine->ram_size;
> @@ -420,16 +481,10 @@ static void q800_machine_init(MachineState *machine)
> * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
> * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
> */
> - io = g_new(MemoryRegion, io_slice_nb);
> - for (i = 0; i < io_slice_nb; i++) {
> - char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
> -
> - memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
> - IO_BASE, IO_SLICE);
> - memory_region_add_subregion(get_system_memory(),
> - IO_BASE + (i + 1) * IO_SLICE, &io[i]);
> - g_free(name);
> - }
> + memory_region_init_io(&m->macio_alias, NULL, &macio_alias_ops, &m->macio,
> + "mac-io.alias", IO_SIZE - IO_SLICE);
> + memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
> + &m->macio_alias);
>
> /* IRQ Glue */
> m->glue = qdev_new(TYPE_GLUE);
> @@ -445,7 +500,8 @@ static void q800_machine_init(MachineState *machine)
> }
> sysbus = SYS_BUS_DEVICE(via1_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> - sysbus_mmio_map(sysbus, 1, VIA_BASE);
> + memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 1));
> sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA1));
> /* A/UX mode */
> qdev_connect_gpio_out(via1_dev, 0,
> @@ -461,7 +517,8 @@ static void q800_machine_init(MachineState *machine)
> via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
> sysbus = SYS_BUS_DEVICE(via2_dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> - sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
> + memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE,
> + sysbus_mmio_get_region(sysbus, 1));
> sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_VIA2));
>
> /* MACSONIC */
> @@ -494,7 +551,8 @@ static void q800_machine_init(MachineState *machine)
> OBJECT(get_system_memory()), &error_abort);
> sysbus = SYS_BUS_DEVICE(dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> - sysbus_mmio_map(sysbus, 0, SONIC_BASE);
> + memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 0));
> sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_SONIC));
>
> memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
> @@ -533,7 +591,8 @@ static void q800_machine_init(MachineState *machine)
> sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
> qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
> qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_ESCC));
> - sysbus_mmio_map(sysbus, 0, SCC_BASE);
> + memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 0));
>
> /* SCSI */
>
> @@ -553,8 +612,10 @@ static void q800_machine_init(MachineState *machine)
> VIA2_IRQ_SCSI_BIT)));
> sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
> VIA2_IRQ_SCSI_DATA_BIT)));
> - sysbus_mmio_map(sysbus, 0, ESP_BASE);
> - sysbus_mmio_map(sysbus, 1, ESP_PDMA);
> + memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 0));
> + memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 1));
>
> scsi_bus_legacy_handle_cmdline(&esp->bus);
>
> @@ -562,7 +623,8 @@ static void q800_machine_init(MachineState *machine)
>
> dev = qdev_new(TYPE_SWIM);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
> + memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE,
> + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
>
> /* NuBus */
>
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 156872a124..8d788a7072 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -34,6 +34,7 @@ struct Q800MachineState {
> MemoryRegion rom;
> DeviceState *glue;
> MemoryRegion macio;
> + MemoryRegion macio_alias;
> };
>
> #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 09/30] q800: add djMEMC memory controller
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (7 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 08/30] q800: reimplement mac-io region aliasing using IO " Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 8:12 ` Philippe Mathieu-Daudé
2023-05-24 21:10 ` [PATCH 10/30] q800: add machine id register Mark Cave-Ayland
` (20 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The djMEMC controller is used to store information related to the physical memory
configuration.
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
MAINTAINERS | 2 +
hw/m68k/Kconfig | 1 +
hw/m68k/q800.c | 9 +++
hw/misc/Kconfig | 3 +
hw/misc/djmemc.c | 154 +++++++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 +
include/hw/m68k/q800.h | 2 +
include/hw/misc/djmemc.h | 46 ++++++++++++
9 files changed, 222 insertions(+)
create mode 100644 hw/misc/djmemc.c
create mode 100644 include/hw/misc/djmemc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 86a1b88863..21ec70d00a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1227,6 +1227,7 @@ F: hw/misc/mac_via.c
F: hw/nubus/*
F: hw/display/macfb.c
F: hw/block/swim.c
+F: hw/misc/djmemc.c
F: hw/m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo-mac.h
@@ -1235,6 +1236,7 @@ F: include/hw/nubus/*
F: include/hw/display/macfb.h
F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
+F: include/hw/misc/djmemc.c
virt
M: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
index f839f8a030..330cfdfa2d 100644
--- a/hw/m68k/Kconfig
+++ b/hw/m68k/Kconfig
@@ -23,6 +23,7 @@ config Q800
select ESP
select DP8393X
select OR_IRQ
+ select DJMEMC
config M68K_VIRT
bool
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index f15f1eaff9..456407898e 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -40,6 +40,7 @@
#include "bootinfo.h"
#include "hw/m68k/q800.h"
#include "hw/misc/mac_via.h"
+#include "hw/misc/djmemc.h"
#include "hw/input/adb.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
@@ -66,6 +67,7 @@
#define SONIC_PROM_BASE (IO_BASE + 0x08000)
#define SONIC_BASE (IO_BASE + 0x0a000)
#define SCC_BASE (IO_BASE + 0x0c020)
+#define DJMEMC_BASE (IO_BASE + 0x0e000)
#define ESP_BASE (IO_BASE + 0x10000)
#define ESP_PDMA (IO_BASE + 0x10100)
#define ASC_BASE (IO_BASE + 0x14000)
@@ -492,6 +494,13 @@ static void q800_machine_init(MachineState *machine)
&error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(m->glue), &error_fatal);
+ /* djMEMC memory controller */
+ m->djmemc = qdev_new(TYPE_DJMEMC);
+ sysbus = SYS_BUS_DEVICE(m->djmemc);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 0));
+
/* VIA 1 */
via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
dinfo = drive_get(IF_MTD, 0, 0);
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 2ef5781ef8..7eaf955f88 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -180,4 +180,7 @@ config AXP209_PMU
bool
depends on I2C
+config DJMEMC
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c
new file mode 100644
index 0000000000..597e0d446c
--- /dev/null
+++ b/hw/misc/djmemc.c
@@ -0,0 +1,154 @@
+/*
+ * djMEMC, macintosh memory and interrupt controller
+ * (Quadra 610/650/800 & Centris 610/650)
+ *
+ * https://mac68k.info/wiki/display/mac68k/djMEMC+Information
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/misc/djmemc.h"
+#include "hw/qdev-properties.h"
+#include "trace.h"
+
+
+#define DJMEMC_INTERLEAVECONF 0x0
+#define DJMEMC_BANK0CONF 0x4
+#define DJMEMC_BANK1CONF 0x8
+#define DJMEMC_BANK2CONF 0xc
+#define DJMEMC_BANK3CONF 0x10
+#define DJMEMC_BANK4CONF 0x14
+#define DJMEMC_BANK5CONF 0x18
+#define DJMEMC_BANK6CONF 0x1c
+#define DJMEMC_BANK7CONF 0x20
+#define DJMEMC_BANK8CONF 0x24
+#define DJMEMC_BANK9CONF 0x28
+#define DJMEMC_MEMTOP 0x2c
+#define DJMEMC_CONFIG 0x30
+#define DJMEMC_REFRESH 0x34
+
+
+static uint64_t djmemc_read(void *opaque, hwaddr addr, unsigned size)
+{
+ DJMEMCState *s = opaque;
+ uint64_t val = 0;
+
+ switch (addr) {
+ case DJMEMC_INTERLEAVECONF:
+ case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
+ case DJMEMC_MEMTOP:
+ case DJMEMC_CONFIG:
+ case DJMEMC_REFRESH:
+ val = s->regs[addr >> 2];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented read addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+ }
+
+ trace_djmemc_read(addr, size, val);
+ return val;
+}
+
+static void djmemc_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ DJMEMCState *s = opaque;
+
+ trace_djmemc_write(addr, size, val);
+
+ switch (addr) {
+ case DJMEMC_INTERLEAVECONF:
+ case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
+ case DJMEMC_MEMTOP:
+ case DJMEMC_CONFIG:
+ case DJMEMC_REFRESH:
+ s->regs[addr >> 2] = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented write addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+ }
+}
+
+static const MemoryRegionOps djmemc_mmio_ops = {
+ .read = djmemc_read,
+ .write = djmemc_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void djmemc_init(Object *obj)
+{
+ DJMEMCState *s = DJMEMC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->mem_regs, obj, &djmemc_mmio_ops, s, "djMEMC",
+ DJMEMC_SIZE);
+ sysbus_init_mmio(sbd, &s->mem_regs);
+}
+
+static void djmemc_reset_hold(Object *obj)
+{
+ DJMEMCState *s = DJMEMC(obj);
+
+ memset(s->regs, 0, sizeof(s->regs));
+}
+
+static const VMStateDescription vmstate_djmemc = {
+ .name = "djMEMC",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, DJMEMCState, DJMEMC_NUM_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void djmemc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+ rc->phases.hold = djmemc_reset_hold;
+ dc->vmsd = &vmstate_djmemc;
+}
+
+static const TypeInfo djmemc_info = {
+ .name = TYPE_DJMEMC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(DJMEMCState),
+ .instance_init = djmemc_init,
+ .class_init = djmemc_class_init,
+};
+
+static void djmemc_register_types(void)
+{
+ type_register_static(&djmemc_info);
+}
+
+type_init(djmemc_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index a40245ad44..a2b5ca6fbc 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -20,6 +20,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+softmmu_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c'))
# virt devices
softmmu_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index c47876a902..bed14bd559 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -279,3 +279,7 @@ virt_ctrl_instance_init(void *dev) "ctrl: %p"
lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
+
+# djmemc.c
+djmemc_read(int reg, unsigned size, uint64_t value) "reg=0x%x size=%u value=0x%"PRIx64
+djmemc_write(int reg, unsigned size, uint64_t value) "reg=0x%x size=%u value=0x%"PRIx64
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 8d788a7072..d0e37cc665 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -33,6 +33,8 @@ struct Q800MachineState {
M68kCPU *cpu;
MemoryRegion rom;
DeviceState *glue;
+ DeviceState *djmemc;
+
MemoryRegion macio;
MemoryRegion macio_alias;
};
diff --git a/include/hw/misc/djmemc.h b/include/hw/misc/djmemc.h
new file mode 100644
index 0000000000..77776b0736
--- /dev/null
+++ b/include/hw/misc/djmemc.h
@@ -0,0 +1,46 @@
+/*
+ * djMEMC, macintosh memory and interrupt controller
+ * (Quadra 610/650/800 & Centris 610/650)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MISC_DJMEMC_H
+#define HW_MISC_DJMEMC_H
+
+#include "hw/sysbus.h"
+
+#define DJMEMC_SIZE 0x2000
+#define DJMEMC_NUM_REGS (0x38 / sizeof(uint32_t))
+
+#define DJMEMC_MAXBANKS 10
+
+struct DJMEMCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mem_regs;
+
+ /* Memory controller */
+ uint32_t regs[DJMEMC_NUM_REGS];
+};
+
+#define TYPE_DJMEMC "djMEMC"
+OBJECT_DECLARE_SIMPLE_TYPE(DJMEMCState, DJMEMC);
+
+#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 09/30] q800: add djMEMC memory controller
2023-05-24 21:10 ` [PATCH 09/30] q800: add djMEMC memory controller Mark Cave-Ayland
@ 2023-05-25 8:12 ` Philippe Mathieu-Daudé
2023-05-30 8:07 ` Mark Cave-Ayland
0 siblings, 1 reply; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 8:12 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> The djMEMC controller is used to store information related to the physical memory
> configuration.
>
> Co-developed-by: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> MAINTAINERS | 2 +
> hw/m68k/Kconfig | 1 +
> hw/m68k/q800.c | 9 +++
> hw/misc/Kconfig | 3 +
> hw/misc/djmemc.c | 154 +++++++++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> hw/misc/trace-events | 4 +
> include/hw/m68k/q800.h | 2 +
> include/hw/misc/djmemc.h | 46 ++++++++++++
> 9 files changed, 222 insertions(+)
> create mode 100644 hw/misc/djmemc.c
> create mode 100644 include/hw/misc/djmemc.h
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index f15f1eaff9..456407898e 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -40,6 +40,7 @@
> #include "bootinfo.h"
> #include "hw/m68k/q800.h"
> #include "hw/misc/mac_via.h"
> +#include "hw/misc/djmemc.h"
> #include "hw/input/adb.h"
> #include "hw/nubus/mac-nubus-bridge.h"
> #include "hw/display/macfb.h"
> @@ -66,6 +67,7 @@
> #define SONIC_PROM_BASE (IO_BASE + 0x08000)
> #define SONIC_BASE (IO_BASE + 0x0a000)
> #define SCC_BASE (IO_BASE + 0x0c020)
> +#define DJMEMC_BASE (IO_BASE + 0x0e000)
> #define ESP_BASE (IO_BASE + 0x10000)
> #define ESP_PDMA (IO_BASE + 0x10100)
> #define ASC_BASE (IO_BASE + 0x14000)
> @@ -492,6 +494,13 @@ static void q800_machine_init(MachineState *machine)
> &error_abort);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(m->glue), &error_fatal);
>
> + /* djMEMC memory controller */
> + m->djmemc = qdev_new(TYPE_DJMEMC);
> + sysbus = SYS_BUS_DEVICE(m->djmemc);
> + sysbus_realize_and_unref(sysbus, &error_fatal);
> + memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
> + sysbus_mmio_get_region(sysbus, 0));
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 8d788a7072..d0e37cc665 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -33,6 +33,8 @@ struct Q800MachineState {
> M68kCPU *cpu;
> MemoryRegion rom;
> DeviceState *glue;
> + DeviceState *djmemc;
While I like the simplicity of using pointer to common QOM parent
type, isn't the consensus to have QOM objects embed their children
state? Maybe we never agreed on that explicitly :) So here I'd rather:
DJMEMCState djmemc;
> MemoryRegion macio;
> MemoryRegion macio_alias;
> };
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 09/30] q800: add djMEMC memory controller
2023-05-25 8:12 ` Philippe Mathieu-Daudé
@ 2023-05-30 8:07 ` Mark Cave-Ayland
0 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-30 8:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, laurent, qemu-devel
On 25/05/2023 09:12, Philippe Mathieu-Daudé wrote:
> On 24/5/23 23:10, Mark Cave-Ayland wrote:
>> The djMEMC controller is used to store information related to the physical memory
>> configuration.
>>
>> Co-developed-by: Laurent Vivier <laurent@vivier.eu>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>> MAINTAINERS | 2 +
>> hw/m68k/Kconfig | 1 +
>> hw/m68k/q800.c | 9 +++
>> hw/misc/Kconfig | 3 +
>> hw/misc/djmemc.c | 154 +++++++++++++++++++++++++++++++++++++++
>> hw/misc/meson.build | 1 +
>> hw/misc/trace-events | 4 +
>> include/hw/m68k/q800.h | 2 +
>> include/hw/misc/djmemc.h | 46 ++++++++++++
>> 9 files changed, 222 insertions(+)
>> create mode 100644 hw/misc/djmemc.c
>> create mode 100644 include/hw/misc/djmemc.h
>
>
>> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
>> index f15f1eaff9..456407898e 100644
>> --- a/hw/m68k/q800.c
>> +++ b/hw/m68k/q800.c
>> @@ -40,6 +40,7 @@
>> #include "bootinfo.h"
>> #include "hw/m68k/q800.h"
>> #include "hw/misc/mac_via.h"
>> +#include "hw/misc/djmemc.h"
>> #include "hw/input/adb.h"
>> #include "hw/nubus/mac-nubus-bridge.h"
>> #include "hw/display/macfb.h"
>> @@ -66,6 +67,7 @@
>> #define SONIC_PROM_BASE (IO_BASE + 0x08000)
>> #define SONIC_BASE (IO_BASE + 0x0a000)
>> #define SCC_BASE (IO_BASE + 0x0c020)
>> +#define DJMEMC_BASE (IO_BASE + 0x0e000)
>> #define ESP_BASE (IO_BASE + 0x10000)
>> #define ESP_PDMA (IO_BASE + 0x10100)
>> #define ASC_BASE (IO_BASE + 0x14000)
>> @@ -492,6 +494,13 @@ static void q800_machine_init(MachineState *machine)
>> &error_abort);
>> sysbus_realize_and_unref(SYS_BUS_DEVICE(m->glue), &error_fatal);
>> + /* djMEMC memory controller */
>> + m->djmemc = qdev_new(TYPE_DJMEMC);
>> + sysbus = SYS_BUS_DEVICE(m->djmemc);
>> + sysbus_realize_and_unref(sysbus, &error_fatal);
>> + memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
>> + sysbus_mmio_get_region(sysbus, 0));
>
>
>> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
>> index 8d788a7072..d0e37cc665 100644
>> --- a/include/hw/m68k/q800.h
>> +++ b/include/hw/m68k/q800.h
>> @@ -33,6 +33,8 @@ struct Q800MachineState {
>> M68kCPU *cpu;
>> MemoryRegion rom;
>> DeviceState *glue;
>> + DeviceState *djmemc;
>
> While I like the simplicity of using pointer to common QOM parent
> type, isn't the consensus to have QOM objects embed their children
> state? Maybe we never agreed on that explicitly :) So here I'd rather:
>
> DJMEMCState djmemc;
That's a fair comment. In fact it seems that even outside of this series q800.c could
do with some better QOM parenting.
It's reasonably trivial to fix up the QOM tree within this series, although of course
it will make it a bit larger. Let me see if I can fix this for v2.
>> MemoryRegion macio;
>> MemoryRegion macio_alias;
>> };
ATB,
Mark.
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 10/30] q800: add machine id register
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (8 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 09/30] q800: add djMEMC memory controller Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 8:14 ` Philippe Mathieu-Daudé
2023-05-24 21:10 ` [PATCH 11/30] q800: implement additional machine id bits on VIA1 port A Mark Cave-Ayland
` (19 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
MacOS reads this address to identify the hardware.
This is a basic implementation returning the ID of Quadra 800.
Details:
http://mess.redump.net/mess/driver_info/mac_technical_notes
"There are 3 ID schemes [...]
The third and most scalable is a machine ID register at 0x5ffffffc.
The top word must be 0xa55a to be valid. Then bits 15-11 are 0 for
consumer Macs, 1 for portables, 2 for high-end 68k, and 3 for high-end
PowerPC. Bit 10 is 1 if additional ID bits appear elsewhere (e.g. in VIA1).
The rest of the bits are a per-model identifier.
Model Lower 16 bits of ID
...
Quadra/Centris 610/650/800 0x2BAD"
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 29 +++++++++++++++++++++++++++++
include/hw/m68k/q800.h | 1 +
2 files changed, 30 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 456407898e..c1d4b98cc0 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -91,6 +91,9 @@
#define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
BIT(0xe))
+/* Quadra 800 machine ID */
+#define Q800_MACHINE_ID 0xa55a2bad
+
/*
* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
* that performs a variety of functions (RAM management, clock generation, ...).
@@ -426,6 +429,27 @@ static const MemoryRegionOps macio_alias_ops = {
},
};
+static uint64_t machine_id_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return Q800_MACHINE_ID;
+}
+
+static void machine_id_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ return;
+}
+
+static const MemoryRegionOps machine_id_ops = {
+ .read = machine_id_read,
+ .write = machine_id_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static void q800_machine_init(MachineState *machine)
{
Q800MachineState *m = Q800_MACHINE(machine);
@@ -488,6 +512,11 @@ static void q800_machine_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
&m->macio_alias);
+ memory_region_init_io(&m->machine_id, NULL, &machine_id_ops, NULL,
+ "Machine ID", 4);
+ memory_region_add_subregion(get_system_memory(), 0x5ffffffc,
+ &m->machine_id);
+
/* IRQ Glue */
m->glue = qdev_new(TYPE_GLUE);
object_property_set_link(OBJECT(m->glue), "cpu", OBJECT(m->cpu),
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index d0e37cc665..e57aec849a 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -37,6 +37,7 @@ struct Q800MachineState {
MemoryRegion macio;
MemoryRegion macio_alias;
+ MemoryRegion machine_id;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 10/30] q800: add machine id register
2023-05-24 21:10 ` [PATCH 10/30] q800: add machine id register Mark Cave-Ayland
@ 2023-05-25 8:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 8:14 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> MacOS reads this address to identify the hardware.
>
> This is a basic implementation returning the ID of Quadra 800.
>
> Details:
>
> http://mess.redump.net/mess/driver_info/mac_technical_notes
>
> "There are 3 ID schemes [...]
> The third and most scalable is a machine ID register at 0x5ffffffc.
> The top word must be 0xa55a to be valid. Then bits 15-11 are 0 for
> consumer Macs, 1 for portables, 2 for high-end 68k, and 3 for high-end
> PowerPC. Bit 10 is 1 if additional ID bits appear elsewhere (e.g. in VIA1).
> The rest of the bits are a per-model identifier.
>
> Model Lower 16 bits of ID
> ...
> Quadra/Centris 610/650/800 0x2BAD"
>
> Co-developed-by: Laurent Vivier <laurent@vivier.eu>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 29 +++++++++++++++++++++++++++++
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 30 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 11/30] q800: implement additional machine id bits on VIA1 port A
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (9 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 10/30] q800: add machine id register Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 12/30] q800: add IOSB subsystem Mark Cave-Ayland
` (18 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 076d18e5fd..f90a22a067 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -114,6 +114,9 @@
#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID_MASK (VIA1A_CPUID0 | VIA1A_CPUID1 | \
+ VIA1A_CPUID2 | VIA1A_CPUID3)
+#define VIA1A_CPUID_Q800 (VIA1A_CPUID0 | VIA1A_CPUID2)
/*
* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
@@ -871,9 +874,18 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
MOS6522State *ms = MOS6522(s);
+ uint64_t ret;
addr = (addr >> 9) & 0xf;
- return mos6522_read(ms, addr, size);
+ ret = mos6522_read(ms, addr, size);
+ switch (addr) {
+ case VIA_REG_A:
+ case VIA_REG_ANH:
+ /* Quadra 800 Id */
+ ret = (ret & ~VIA1A_CPUID_MASK) | VIA1A_CPUID_Q800;
+ break;
+ }
+ return ret;
}
static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 12/30] q800: add IOSB subsystem
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (10 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 11/30] q800: implement additional machine id bits on VIA1 port A Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available Mark Cave-Ayland
` (17 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
It is needed because it defines the BIOSConfig area.
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
MAINTAINERS | 2 +
hw/m68k/Kconfig | 1 +
hw/m68k/q800.c | 10 +++
hw/misc/Kconfig | 3 +
hw/misc/iosb.c | 156 +++++++++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 ++
include/hw/misc/iosb.h | 41 +++++++++++
8 files changed, 218 insertions(+)
create mode 100644 hw/misc/iosb.c
create mode 100644 include/hw/misc/iosb.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 21ec70d00a..f151aaf99f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/nubus/*
F: hw/display/macfb.c
F: hw/block/swim.c
F: hw/misc/djmemc.c
+F: hw/misc/iosb.c
F: hw/m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo-mac.h
@@ -1237,6 +1238,7 @@ F: include/hw/display/macfb.h
F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
F: include/hw/misc/djmemc.c
+F: include/hw/misc/iosb.c
virt
M: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
index 330cfdfa2d..64fa70a0db 100644
--- a/hw/m68k/Kconfig
+++ b/hw/m68k/Kconfig
@@ -24,6 +24,7 @@ config Q800
select DP8393X
select OR_IRQ
select DJMEMC
+ select IOSB
config M68K_VIRT
bool
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index c1d4b98cc0..8310670ec2 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -41,6 +41,7 @@
#include "hw/m68k/q800.h"
#include "hw/misc/mac_via.h"
#include "hw/misc/djmemc.h"
+#include "hw/misc/iosb.h"
#include "hw/input/adb.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
@@ -71,6 +72,7 @@
#define ESP_BASE (IO_BASE + 0x10000)
#define ESP_PDMA (IO_BASE + 0x10100)
#define ASC_BASE (IO_BASE + 0x14000)
+#define IOSB_BASE (IO_BASE + 0x18000)
#define SWIM_BASE (IO_BASE + 0x1E000)
#define SONIC_PROM_SIZE 0x1000
@@ -530,6 +532,14 @@ static void q800_machine_init(MachineState *machine)
memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
+ /* IOSB subsystem */
+
+ dev = qdev_new(TYPE_IOSB);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ memory_region_add_subregion(&m->macio, IOSB_BASE - IO_BASE,
+ sysbus_mmio_get_region(sysbus, 0));
+
/* VIA 1 */
via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
dinfo = drive_get(IF_MTD, 0, 0);
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 7eaf955f88..c6c38102b1 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -183,4 +183,7 @@ config AXP209_PMU
config DJMEMC
bool
+config IOSB
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c
new file mode 100644
index 0000000000..f4f9b22d89
--- /dev/null
+++ b/hw/misc/iosb.c
@@ -0,0 +1,156 @@
+/*
+ * QEMU IOSB emulation
+ *
+ * Copyright (c) 2019 Laurent Vivier
+ * Copyright (c) 2022 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/sysbus.h"
+#include "hw/misc/iosb.h"
+#include "trace.h"
+
+#define IOSB_SIZE 0x2000
+
+#define IOSB_CONFIG 0x0
+#define IOSB_CONFIG2 0x100
+#define IOSB_SONIC_SCSI 0x200
+#define IOSB_REVISION 0x300
+#define IOSB_SCSI_RESID 0x400
+#define IOSB_BRIGHTNESS 0x500
+#define IOSB_TIMEOUT 0x600
+
+
+static uint64_t iosb_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ IOSBState *s = IOSB(opaque);
+ uint64_t val = 0;
+
+ switch (addr) {
+ case IOSB_CONFIG:
+ case IOSB_CONFIG2:
+ case IOSB_SONIC_SCSI:
+ case IOSB_REVISION:
+ case IOSB_SCSI_RESID:
+ case IOSB_BRIGHTNESS:
+ case IOSB_TIMEOUT:
+ val = s->regs[addr >> 8];
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented read addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+ }
+
+ trace_iosb_read(addr, size, val);
+ return val;
+}
+
+static void iosb_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IOSBState *s = IOSB(opaque);
+
+ switch (addr) {
+ case IOSB_CONFIG:
+ case IOSB_CONFIG2:
+ case IOSB_SONIC_SCSI:
+ case IOSB_REVISION:
+ case IOSB_SCSI_RESID:
+ case IOSB_BRIGHTNESS:
+ case IOSB_TIMEOUT:
+ s->regs[addr >> 8] = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented write addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+ }
+
+ trace_iosb_write(addr, size, val);
+}
+
+static const MemoryRegionOps iosb_mmio_ops = {
+ .read = iosb_read,
+ .write = iosb_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void iosb_reset_hold(Object *obj)
+{
+ IOSBState *s = IOSB(obj);
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* BCLK 33 MHz */
+ s->regs[IOSB_CONFIG >> 8] = 1;
+}
+
+static void iosb_init(Object *obj)
+{
+ IOSBState *s = IOSB(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init_io(&s->mem_regs, obj, &iosb_mmio_ops, s, "IOSB",
+ IOSB_SIZE);
+ sysbus_init_mmio(sbd, &s->mem_regs);
+}
+
+static const VMStateDescription vmstate_iosb = {
+ .name = "IOSB",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, IOSBState, IOSB_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void iosb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+ rc->phases.hold = iosb_reset_hold;
+ dc->vmsd = &vmstate_iosb;
+}
+
+static const TypeInfo iosb_info = {
+ .name = TYPE_IOSB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IOSBState),
+ .instance_init = iosb_init,
+ .class_init = iosb_class_init,
+};
+
+static void iosb_register_types(void)
+{
+ type_register_static(&iosb_info);
+}
+
+type_init(iosb_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index a2b5ca6fbc..fee56a2a9e 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,7 @@ softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
softmmu_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c'))
+softmmu_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c'))
# virt devices
softmmu_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index bed14bd559..85d2601de9 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -283,3 +283,7 @@ lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
# djmemc.c
djmemc_read(int reg, unsigned size, uint64_t value) "reg=0x%x size=%u value=0x%"PRIx64
djmemc_write(int reg, unsigned size, uint64_t value) "reg=0x%x size=%u value=0x%"PRIx64
+
+# iosb.c
+iosb_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
+iosb_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
diff --git a/include/hw/misc/iosb.h b/include/hw/misc/iosb.h
new file mode 100644
index 0000000000..09d9f3a32b
--- /dev/null
+++ b/include/hw/misc/iosb.h
@@ -0,0 +1,41 @@
+/*
+ * QEMU IOSB emulation
+ *
+ * Copyright (c) 2019 Laurent Vivier
+ * Copyright (c) 2022 Mark Cave-Ayland
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MEM_IOSB_H
+#define HW_MEM_IOSB_H
+
+#define IOSB_REGS 7
+
+struct IOSBState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mem_regs;
+ uint32_t regs[IOSB_REGS];
+};
+
+#define TYPE_IOSB "IOSB"
+OBJECT_DECLARE_SIMPLE_TYPE(IOSBState, IOSB);
+
+#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (11 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 12/30] q800: add IOSB subsystem Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 8:20 ` Philippe Mathieu-Daudé
2023-05-30 11:25 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 14/30] audio: add Apple Sound Chip (ASC) emulation Mark Cave-Ayland
` (16 subsequent siblings)
29 siblings, 2 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
MacOS attempts a series of writes and reads over the entire RAM area in order
to determine the amount of RAM within the machine. Allow accesses to the
entire RAM area ignoring writes and always reading zero for areas where there
is no physical RAM installed to allow MacOS to detect the memory size without
faulting.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++-
include/hw/m68k/q800.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 8310670ec2..d12aeaa20e 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -86,6 +86,9 @@
#define MAC_CLOCK 3686418
+/* Size of whole RAM area */
+#define RAM_SIZE 0x40000000
+
/*
* Slot 0x9 is reserved for use by the in-built framebuffer whilst only
* slots 0xc, 0xd and 0xe physically exist on the Quadra 800
@@ -452,6 +455,27 @@ static const MemoryRegionOps machine_id_ops = {
},
};
+static uint64_t ramio_read(void *opaque, hwaddr addr, unsigned size)
+{
+ return 0x0;
+}
+
+static void ramio_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ return;
+}
+
+static const MemoryRegionOps ramio_ops = {
+ .read = ramio_read,
+ .write = ramio_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
static void q800_machine_init(MachineState *machine)
{
Q800MachineState *m = Q800_MACHINE(machine);
@@ -497,7 +521,11 @@ static void q800_machine_init(MachineState *machine)
qemu_register_reset(main_cpu_reset, m->cpu);
/* RAM */
- memory_region_add_subregion(get_system_memory(), 0, machine->ram);
+ memory_region_init_io(&m->ramio, NULL, &ramio_ops, &m->ramio,
+ "ram", RAM_SIZE);
+ memory_region_add_subregion(get_system_memory(), 0x0, &m->ramio);
+
+ memory_region_add_subregion(&m->ramio, 0, machine->ram);
/*
* Create container for all IO devices
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index e57aec849a..0602d07d3d 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -34,6 +34,7 @@ struct Q800MachineState {
MemoryRegion rom;
DeviceState *glue;
DeviceState *djmemc;
+ MemoryRegion ramio;
MemoryRegion macio;
MemoryRegion macio_alias;
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available
2023-05-24 21:10 ` [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available Mark Cave-Ayland
@ 2023-05-25 8:20 ` Philippe Mathieu-Daudé
2023-05-30 11:25 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 8:20 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> MacOS attempts a series of writes and reads over the entire RAM area in order
> to determine the amount of RAM within the machine. Allow accesses to the
> entire RAM area ignoring writes and always reading zero for areas where there
> is no physical RAM installed to allow MacOS to detect the memory size without
> faulting.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++-
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 8310670ec2..d12aeaa20e 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -86,6 +86,9 @@
>
> #define MAC_CLOCK 3686418
>
> +/* Size of whole RAM area */
> +#define RAM_SIZE 0x40000000
> +
> /*
> * Slot 0x9 is reserved for use by the in-built framebuffer whilst only
> * slots 0xc, 0xd and 0xe physically exist on the Quadra 800
> @@ -452,6 +455,27 @@ static const MemoryRegionOps machine_id_ops = {
> },
> };
>
> +static uint64_t ramio_read(void *opaque, hwaddr addr, unsigned size)
> +{
Similar to empty_slot_init().
Personally I like to follow firmware detection using trace events here.
Maybe s/ramio/ram/.
> + return 0x0;
> +}
> static void q800_machine_init(MachineState *machine)
> {
> Q800MachineState *m = Q800_MACHINE(machine);
> @@ -497,7 +521,11 @@ static void q800_machine_init(MachineState *machine)
> qemu_register_reset(main_cpu_reset, m->cpu);
>
> /* RAM */
> - memory_region_add_subregion(get_system_memory(), 0, machine->ram);
> + memory_region_init_io(&m->ramio, NULL, &ramio_ops, &m->ramio,
> + "ram", RAM_SIZE);
> + memory_region_add_subregion(get_system_memory(), 0x0, &m->ramio);
> +
> + memory_region_add_subregion(&m->ramio, 0, machine->ram);
Yes!
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available
2023-05-24 21:10 ` [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available Mark Cave-Ayland
2023-05-25 8:20 ` Philippe Mathieu-Daudé
@ 2023-05-30 11:25 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:25 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> MacOS attempts a series of writes and reads over the entire RAM area in order
> to determine the amount of RAM within the machine. Allow accesses to the
> entire RAM area ignoring writes and always reading zero for areas where there
> is no physical RAM installed to allow MacOS to detect the memory size without
> faulting.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++-
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index 8310670ec2..d12aeaa20e 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -86,6 +86,9 @@
>
> #define MAC_CLOCK 3686418
>
> +/* Size of whole RAM area */
> +#define RAM_SIZE 0x40000000
> +
> /*
> * Slot 0x9 is reserved for use by the in-built framebuffer whilst only
> * slots 0xc, 0xd and 0xe physically exist on the Quadra 800
> @@ -452,6 +455,27 @@ static const MemoryRegionOps machine_id_ops = {
> },
> };
>
> +static uint64_t ramio_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + return 0x0;
> +}
> +
> +static void ramio_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned size)
> +{
> + return;
> +}
> +
> +static const MemoryRegionOps ramio_ops = {
> + .read = ramio_read,
> + .write = ramio_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4,
> + },
> +};
> +
> static void q800_machine_init(MachineState *machine)
> {
> Q800MachineState *m = Q800_MACHINE(machine);
> @@ -497,7 +521,11 @@ static void q800_machine_init(MachineState *machine)
> qemu_register_reset(main_cpu_reset, m->cpu);
>
> /* RAM */
> - memory_region_add_subregion(get_system_memory(), 0, machine->ram);
> + memory_region_init_io(&m->ramio, NULL, &ramio_ops, &m->ramio,
> + "ram", RAM_SIZE);
> + memory_region_add_subregion(get_system_memory(), 0x0, &m->ramio);
> +
> + memory_region_add_subregion(&m->ramio, 0, machine->ram);
>
> /*
> * Create container for all IO devices
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index e57aec849a..0602d07d3d 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -34,6 +34,7 @@ struct Q800MachineState {
> MemoryRegion rom;
> DeviceState *glue;
> DeviceState *djmemc;
> + MemoryRegion ramio;
>
> MemoryRegion macio;
> MemoryRegion macio_alias;
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 14/30] audio: add Apple Sound Chip (ASC) emulation
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (12 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 13/30] q800: allow accesses to RAM area even if less memory is available Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-29 11:43 ` Volker Rümelin
2023-05-24 21:10 ` [PATCH 15/30] asc: generate silence if FIFO empty but engine still running Mark Cave-Ayland
` (15 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The Apple Sound Chip was primarily used by the Macintosh II to generate sound
in hardware which was previously handled by the toolbox ROM with software
interrupts.
Implement both the standard ASC and also the enhanced ASC (EASC) functionality
which is used in the Quadra 800.
Note that whilst real ASC hardware uses AUDIO_FORMAT_S8, this implementation uses
AUDIO_FORMAT_U8 instead because AUDIO_FORMAT_S8 is rarely used and not supported
by some audio backends like PulseAudio and DirectSound when played directly with
-audiodev out.mixing-engine=off.
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Volker Rümelin <vr_qemu@t-online.de>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
MAINTAINERS | 2 +
hw/audio/Kconfig | 3 +
hw/audio/asc.c | 688 +++++++++++++++++++++++++++++++++++++++++
hw/audio/meson.build | 1 +
hw/audio/trace-events | 10 +
hw/m68k/Kconfig | 1 +
include/hw/audio/asc.h | 75 +++++
7 files changed, 780 insertions(+)
create mode 100644 hw/audio/asc.c
create mode 100644 include/hw/audio/asc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f151aaf99f..1b79ab7965 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1229,6 +1229,7 @@ F: hw/display/macfb.c
F: hw/block/swim.c
F: hw/misc/djmemc.c
F: hw/misc/iosb.c
+F: hw/audio/asc.c
F: hw/m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo-mac.h
@@ -1239,6 +1240,7 @@ F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
F: include/hw/misc/djmemc.c
F: include/hw/misc/iosb.c
+F: include/hw/audio/asc.h
virt
M: Laurent Vivier <laurent@vivier.eu>
diff --git a/hw/audio/Kconfig b/hw/audio/Kconfig
index e76c69ca7e..d0993514a1 100644
--- a/hw/audio/Kconfig
+++ b/hw/audio/Kconfig
@@ -47,3 +47,6 @@ config PL041
config CS4231
bool
+
+config ASC
+ bool
diff --git a/hw/audio/asc.c b/hw/audio/asc.c
new file mode 100644
index 0000000000..04194b1e43
--- /dev/null
+++ b/hw/audio/asc.c
@@ -0,0 +1,688 @@
+/*
+ * QEMU Apple Sound Chip emulation
+ *
+ * Apple Sound Chip (ASC) 344S0063
+ * Enhanced Apple Sound Chip (EASC) 343S1063
+ *
+ * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
+ * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "audio/audio.h"
+#include "hw/audio/asc.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+/*
+ * Linux doesn't provide information about ASC, see arch/m68k/mac/macboing.c
+ * and arch/m68k/include/asm/mac_asc.h
+ *
+ * best information is coming from MAME:
+ * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.h
+ * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.cpp
+ * Emulation by R. Belmont
+ * or MESS:
+ * http://mess.redump.net/mess/driver_info/easc
+ *
+ * 0x800: VERSION
+ * 0x801: MODE
+ * 1=FIFO mode,
+ * 2=wavetable mode
+ * 0x802: CONTROL
+ * bit 0=analog or PWM output,
+ * 1=stereo/mono,
+ * 7=processing time exceeded
+ * 0x803: FIFO MODE
+ * bit 7=clear FIFO,
+ * bit 1="non-ROM companding",
+ * bit 0="ROM companding")
+ * 0x804: FIFO IRQ STATUS
+ * bit 0=ch A 1/2 full,
+ * 1=ch A full,
+ * 2=ch B 1/2 full,
+ * 3=ch B full)
+ * 0x805: WAVETABLE CONTROL
+ * bits 0-3 wavetables 0-3 start
+ * 0x806: VOLUME
+ * bits 2-4 = 3 bit internal ASC volume,
+ * bits 5-7 = volume control sent to Sony sound chip
+ * 0x807: CLOCK RATE
+ * 0 = Mac 22257 Hz,
+ * 1 = undefined,
+ * 2 = 22050 Hz,
+ * 3 = 44100 Hz
+ * 0x80a: PLAY REC A
+ * 0x80f: TEST
+ * bits 6-7 = digital test,
+ * bits 4-5 = analog test
+ * 0x810: WAVETABLE 0 PHASE
+ * big-endian 9.15 fixed-point, only 24 bits valid
+ * 0x814: WAVETABLE 0 INCREMENT
+ * big-endian 9.15 fixed-point, only 24 bits valid
+ * 0x818: WAVETABLE 1 PHASE
+ * 0x81C: WAVETABLE 1 INCREMENT
+ * 0x820: WAVETABLE 2 PHASE
+ * 0x824: WAVETABLE 2 INCREMENT
+ * 0x828: WAVETABLE 3 PHASE
+ * 0x82C: WAVETABLE 3 INCREMENT
+ * 0x830: UNKNOWN START
+ * NetBSD writes Wavetable data here (are there more
+ * wavetables/channels than we know about?)
+ * 0x857: UNKNOWN END
+ */
+
+#define ASC_SIZE 0x2000
+
+enum {
+ ASC_VERSION = 0x00,
+ ASC_MODE = 0x01,
+ ASC_CONTROL = 0x02,
+ ASC_FIFOMODE = 0x03,
+ ASC_FIFOIRQ = 0x04,
+ ASC_WAVECTRL = 0x05,
+ ASC_VOLUME = 0x06,
+ ASC_CLOCK = 0x07,
+ ASC_PLAYRECA = 0x0a,
+ ASC_TEST = 0x0f,
+ ASC_WAVETABLE = 0x10
+};
+
+#define ASC_FIFO_STATUS_HALF_FULL 1
+#define ASC_FIFO_STATUS_FULL_EMPTY 2
+
+#define ASC_EXTREGS_FIFOCTRL 0x8
+#define ASC_EXTREGS_INTCTRL 0x9
+#define ASC_EXTREGS_CDXA_DECOMP_FILT 0x10
+
+
+static void asc_raise_irq(ASCState *s)
+{
+ qemu_set_irq(s->irq, 1);
+}
+
+static void asc_lower_irq(ASCState *s)
+{
+ qemu_set_irq(s->irq, 0);
+}
+
+static uint8_t asc_fifo_get(ASCFIFOState *fs)
+{
+ ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
+ bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
+ uint8_t val;
+
+ assert(fs->cnt);
+
+ val = fs->fifo[fs->rptr];
+ trace_asc_fifo_get('A' + fs->index, fs->rptr, fs->cnt, val);
+
+ fs->rptr++;
+ fs->rptr &= 0x3ff;
+ fs->cnt--;
+
+ if (fs->cnt <= 0x1ff) {
+ /* FIFO less than half full */
+ fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
+ } else {
+ /* FIFO more than half full */
+ fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
+ }
+
+ if (fs->cnt == 0x1ff && fifo_half_irq_enabled) {
+ /* Raise FIFO half full IRQ */
+ asc_raise_irq(s);
+ }
+
+ if (fs->cnt == 0) {
+ /* Raise FIFO empty IRQ */
+ fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
+ asc_raise_irq(s);
+ }
+
+ return val;
+}
+
+static int generate_fifo(ASCState *s, int maxsamples)
+{
+ uint8_t *buf = s->mixbuf;
+ int i, limit, count = 0;
+
+ limit = MIN(MAX(s->fifos[0].cnt, s->fifos[1].cnt), maxsamples);
+
+ /*
+ * If starting a new run with no FIFO data present, update the IRQ and
+ * continue
+ */
+ if (limit == 0 && s->fifos[0].int_status == 0 &&
+ s->fifos[1].int_status == 0) {
+ s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL |
+ ASC_FIFO_STATUS_FULL_EMPTY;
+ s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
+ ASC_FIFO_STATUS_FULL_EMPTY;
+
+ asc_raise_irq(s);
+ return 0;
+ }
+
+ while (count < limit) {
+ uint8_t val;
+ int16_t d, f0, f1;
+ int32_t t;
+ int shift, filter;
+ bool hasdata = true;
+
+ for (i = 0; i < 2; i++) {
+ ASCFIFOState *fs = &s->fifos[i];
+
+ switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) {
+ case 0x82:
+ /*
+ * CD-XA BRR mode: exit if there isn't enough data in the FIFO
+ * for a complete 15 byte packet
+ */
+ if (fs->xa_cnt == -1 && fs->cnt < 15) {
+ hasdata = false;
+ continue;
+ }
+
+ if (fs->xa_cnt == -1) {
+ /* Start of packet, get flags */
+ fs->xa_flags = asc_fifo_get(fs);
+ fs->xa_cnt = 0;
+ }
+
+ shift = fs->xa_flags & 0xf;
+ filter = fs->xa_flags >> 4;
+ f0 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
+ (filter << 1) + 1];
+ f1 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
+ (filter << 1)];
+ if ((fs->xa_cnt & 1) == 0) {
+ fs->xa_val = asc_fifo_get(fs);
+ d = (fs->xa_val & 0xf) << 12;
+ } else {
+ d = (fs->xa_val & 0xf0) << 8;
+ }
+ t = (d >> shift) + (((fs->xa_last[0] * f0) +
+ (fs->xa_last[1] * f1) + 32) >> 6);
+ if (t < -32768) {
+ t = -32768;
+ } else if (t > 32768) {
+ t = 32768;
+ }
+
+ /*
+ * CD-XA BRR generates 16-bit signed output, so convert to
+ * 8-bit before writing to buffer. Does real hardware do the
+ * same?
+ */
+ buf[count * 2 + i] = (uint8_t)(t / 256) ^ 0x80;
+ fs->xa_cnt++;
+
+ fs->xa_last[1] = fs->xa_last[0];
+ fs->xa_last[0] = (int16_t)t;
+
+ if (fs->xa_cnt == 28) {
+ /* End of packet */
+ fs->xa_cnt = -1;
+ }
+ break;
+
+ default:
+ /* fallthrough */
+ case 0x80:
+ /* Raw mode */
+ if (fs->cnt) {
+ val = asc_fifo_get(fs);
+ } else {
+ val = 0x80;
+ }
+
+ buf[count * 2 + i] = val;
+ break;
+ }
+ }
+
+ if (!hasdata) {
+ break;
+ }
+
+ count++;
+ }
+
+ return count;
+}
+
+static int generate_wavetable(ASCState *s, int maxsamples)
+{
+ uint8_t *buf = s->mixbuf;
+ int channel, count = 0;
+
+ while (count < maxsamples) {
+ uint32_t left = 0, right = 0;
+ uint8_t sample;
+
+ for (channel = 0; channel < 4; channel++) {
+ ASCFIFOState *fs = &s->fifos[channel >> 1];
+ int chanreg = ASC_WAVETABLE + (channel << 3);
+ uint32_t phase, incr, offset;
+
+ phase = ldl_be_p(&s->regs[chanreg]);
+ incr = ldl_be_p(&s->regs[chanreg + sizeof(uint32_t)]);
+
+ phase += incr;
+ offset = (phase >> 15) & 0x1ff;
+ sample = fs->fifo[0x200 * (channel >> 1) + offset];
+
+ stl_be_p(&s->regs[chanreg], phase);
+
+ left += sample;
+ right += sample;
+ }
+
+ buf[count * 2] = left >> 2;
+ buf[count * 2 + 1] = right >> 2;
+
+ count++;
+ }
+
+ return count;
+}
+
+static void asc_out_cb(void *opaque, int free_b)
+{
+ ASCState *s = opaque;
+ int samples;
+
+ samples = MIN(s->samples, free_b >> s->shift);
+ if (!samples) {
+ return;
+ }
+
+ switch (s->regs[ASC_MODE] & 3) {
+ default:
+ /* Off */
+ samples = 0;
+ break;
+ case 1:
+ /* FIFO mode */
+ samples = generate_fifo(s, samples);
+ break;
+ case 2:
+ /* Wave table mode */
+ samples = generate_wavetable(s, samples);
+ break;
+ }
+
+ if (!samples) {
+ return;
+ }
+
+ AUD_write(s->voice, s->mixbuf, samples << s->shift);
+}
+
+static uint64_t asc_fifo_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ ASCFIFOState *fs = opaque;
+
+ trace_asc_read_fifo('A' + fs->index, addr, size, fs->fifo[addr]);
+ return fs->fifo[addr];
+}
+
+static void asc_fifo_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ ASCFIFOState *fs = opaque;
+ ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
+ bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
+
+ trace_asc_write_fifo('A' + fs->index, addr, size, fs->wptr, fs->cnt, value);
+
+ if (s->regs[ASC_MODE] == 1) {
+ fs->fifo[fs->wptr++] = value;
+ fs->wptr &= 0x3ff;
+ fs->cnt++;
+
+ if (fs->cnt <= 0x1ff) {
+ /* FIFO less than half full */
+ fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
+ } else {
+ /* FIFO at least half full */
+ fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
+ }
+
+ if (fs->cnt == 0x200 && fifo_half_irq_enabled) {
+ /* Raise FIFO half full interrupt */
+ asc_raise_irq(s);
+ }
+
+ if (fs->cnt == 0x3ff) {
+ /* Raise FIFO full interrupt */
+ fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
+ asc_raise_irq(s);
+ }
+ } else {
+ fs->fifo[addr] = value;
+ }
+ return;
+}
+
+static const MemoryRegionOps asc_fifo_ops = {
+ .read = asc_fifo_read,
+ .write = asc_fifo_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void asc_fifo_reset(ASCFIFOState *fs);
+
+static uint64_t asc_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ ASCState *s = opaque;
+ uint64_t prev, value;
+
+ switch (addr) {
+ case ASC_VERSION:
+ switch (s->type) {
+ default:
+ case ASC_TYPE_ASC:
+ value = 0;
+ break;
+ case ASC_TYPE_EASC:
+ value = 0xb0;
+ break;
+ }
+ break;
+ case ASC_FIFOIRQ:
+ prev = (s->fifos[0].int_status & 0x3) |
+ (s->fifos[1].int_status & 0x3) << 2;
+
+ s->fifos[0].int_status = 0;
+ s->fifos[1].int_status = 0;
+ asc_lower_irq(s);
+ value = prev;
+ break;
+ default:
+ value = s->regs[addr];
+ break;
+ }
+
+ trace_asc_read_reg(addr, size, value);
+ return value;
+}
+
+static void asc_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ ASCState *s = opaque;
+
+ switch (addr) {
+ case ASC_MODE:
+ value &= 3;
+ if (value != s->regs[ASC_MODE]) {
+ asc_fifo_reset(&s->fifos[0]);
+ asc_fifo_reset(&s->fifos[1]);
+ asc_lower_irq(s);
+ if (value != 0) {
+ AUD_set_active_out(s->voice, 1);
+ } else {
+ AUD_set_active_out(s->voice, 0);
+ }
+ }
+ break;
+ case ASC_FIFOMODE:
+ if (value & 0x80) {
+ asc_fifo_reset(&s->fifos[0]);
+ asc_fifo_reset(&s->fifos[1]);
+ asc_lower_irq(s);
+ }
+ break;
+ case ASC_WAVECTRL:
+ break;
+ case ASC_VOLUME:
+ {
+ int vol = (value & 0xe0);
+
+ AUD_set_volume_out(s->voice, 0, vol, vol);
+ break;
+ }
+ }
+
+ trace_asc_write_reg(addr, size, value);
+ s->regs[addr] = value;
+}
+
+static const MemoryRegionOps asc_regs_ops = {
+ .read = asc_read,
+ .write = asc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ }
+};
+
+static uint64_t asc_ext_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ ASCFIFOState *fs = opaque;
+ uint64_t value;
+
+ value = fs->extregs[addr];
+
+ trace_asc_read_extreg('A' + fs->index, addr, size, value);
+ return value;
+}
+
+static void asc_ext_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ ASCFIFOState *fs = opaque;
+
+ trace_asc_write_extreg('A' + fs->index, addr, size, value);
+
+ fs->extregs[addr] = value;
+}
+
+static const MemoryRegionOps asc_extregs_ops = {
+ .read = asc_ext_read,
+ .write = asc_ext_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static int asc_post_load(void *opaque, int version)
+{
+ ASCState *s = ASC(opaque);
+
+ if (s->regs[ASC_MODE] != 0) {
+ AUD_set_active_out(s->voice, 1);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_asc_fifo = {
+ .name = "apple-sound-chip.fifo",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(fifo, ASCFIFOState, ASC_FIFO_SIZE),
+ VMSTATE_UINT8(int_status, ASCFIFOState),
+ VMSTATE_INT32(cnt, ASCFIFOState),
+ VMSTATE_INT32(wptr, ASCFIFOState),
+ VMSTATE_INT32(rptr, ASCFIFOState),
+ VMSTATE_UINT8_ARRAY(extregs, ASCFIFOState, ASC_EXTREG_SIZE),
+ VMSTATE_INT32(xa_cnt, ASCFIFOState),
+ VMSTATE_UINT8(xa_val, ASCFIFOState),
+ VMSTATE_UINT8(xa_flags, ASCFIFOState),
+ VMSTATE_INT16_ARRAY(xa_last, ASCFIFOState, 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_asc = {
+ .name = "apple-sound-chip",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .post_load = asc_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(fifos, ASCState, 2, 0, vmstate_asc_fifo,
+ ASCFIFOState),
+ VMSTATE_UINT8_ARRAY(regs, ASCState, ASC_REG_SIZE),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void asc_fifo_reset(ASCFIFOState *fs)
+{
+ fs->wptr = 0;
+ fs->rptr = 0;
+ fs->cnt = 0;
+ fs->xa_cnt = -1;
+ fs->int_status = 0;
+}
+
+static void asc_fifo_init(ASCFIFOState *fs, int index)
+{
+ ASCState *s = container_of(fs, ASCState, fifos[index]);
+ char *name;
+
+ fs->index = index;
+ name = g_strdup_printf("asc.fifo%c", 'A' + index);
+ memory_region_init_io(&fs->mem_fifo, OBJECT(s), &asc_fifo_ops, fs,
+ name, ASC_FIFO_SIZE);
+ g_free(name);
+
+ name = g_strdup_printf("asc.extregs%c", 'A' + index);
+ memory_region_init_io(&fs->mem_extregs, OBJECT(s), &asc_extregs_ops,
+ fs, name, ASC_EXTREG_SIZE);
+ g_free(name);
+}
+
+static void asc_reset(DeviceState *d)
+{
+ ASCState *s = ASC(d);
+
+ AUD_set_active_out(s->voice, 0);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ asc_fifo_reset(&s->fifos[0]);
+ asc_fifo_reset(&s->fifos[1]);
+
+ if (s->type == ASC_TYPE_ASC) {
+ /* FIFO half full IRQs enabled by default */
+ s->fifos[0].extregs[ASC_EXTREGS_INTCTRL] = 1;
+ s->fifos[1].extregs[ASC_EXTREGS_INTCTRL] = 1;
+ }
+}
+
+static void asc_unrealize(DeviceState *dev)
+{
+ ASCState *s = ASC(dev);
+
+ g_free(s->mixbuf);
+
+ AUD_remove_card(&s->card);
+}
+
+static void asc_realize(DeviceState *dev, Error **errp)
+{
+ ASCState *s = ASC(dev);
+ struct audsettings as;
+
+ AUD_register_card("Apple Sound Chip", &s->card);
+
+ as.freq = 22257;
+ as.nchannels = 2;
+ as.fmt = AUDIO_FORMAT_U8;
+ as.endianness = AUDIO_HOST_ENDIANNESS;
+
+ s->voice = AUD_open_out(&s->card, s->voice, "asc.out", s, asc_out_cb,
+ &as);
+ s->shift = 1;
+ s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift;
+ s->mixbuf = g_malloc0(s->samples << s->shift);
+
+ /* Add easc registers if required */
+ if (s->type == ASC_TYPE_EASC) {
+ memory_region_add_subregion(&s->asc, ASC_EXTREG_OFFSET,
+ &s->fifos[0].mem_extregs);
+ memory_region_add_subregion(&s->asc,
+ ASC_EXTREG_OFFSET + ASC_EXTREG_SIZE,
+ &s->fifos[1].mem_extregs);
+ }
+}
+
+static void asc_init(Object *obj)
+{
+ ASCState *s = ASC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ memory_region_init(&s->asc, OBJECT(obj), "asc", ASC_SIZE);
+
+ asc_fifo_init(&s->fifos[0], 0);
+ asc_fifo_init(&s->fifos[1], 1);
+
+ memory_region_add_subregion(&s->asc, ASC_FIFO_OFFSET,
+ &s->fifos[0].mem_fifo);
+ memory_region_add_subregion(&s->asc,
+ ASC_FIFO_OFFSET + ASC_FIFO_SIZE,
+ &s->fifos[1].mem_fifo);
+
+ memory_region_init_io(&s->mem_regs, OBJECT(obj), &asc_regs_ops, s,
+ "asc.regs", ASC_REG_SIZE);
+ memory_region_add_subregion(&s->asc, ASC_REG_OFFSET, &s->mem_regs);
+
+ sysbus_init_irq(sbd, &s->irq);
+ sysbus_init_mmio(sbd, &s->asc);
+}
+
+static Property asc_properties[] = {
+ DEFINE_AUDIO_PROPERTIES(ASCState, card),
+ DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void asc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = asc_realize;
+ dc->unrealize = asc_unrealize;
+ set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
+ dc->reset = asc_reset;
+ dc->vmsd = &vmstate_asc;
+ device_class_set_props(dc, asc_properties);
+}
+
+static const TypeInfo asc_info = {
+ .name = TYPE_ASC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ASCState),
+ .instance_init = asc_init,
+ .class_init = asc_class_init,
+};
+
+static void asc_register_types(void)
+{
+ type_register_static(&asc_info);
+}
+
+type_init(asc_register_types)
diff --git a/hw/audio/meson.build b/hw/audio/meson.build
index e48a9fc73d..2de764912f 100644
--- a/hw/audio/meson.build
+++ b/hw/audio/meson.build
@@ -1,6 +1,7 @@
softmmu_ss.add(files('soundhw.c'))
softmmu_ss.add(when: 'CONFIG_AC97', if_true: files('ac97.c'))
softmmu_ss.add(when: 'CONFIG_ADLIB', if_true: files('fmopl.c', 'adlib.c'))
+softmmu_ss.add(when: 'CONFIG_ASC', if_true: files('asc.c'))
softmmu_ss.add(when: 'CONFIG_CS4231', if_true: files('cs4231.c'))
softmmu_ss.add(when: 'CONFIG_CS4231A', if_true: files('cs4231a.c'))
softmmu_ss.add(when: 'CONFIG_ES1370', if_true: files('es1370.c'))
diff --git a/hw/audio/trace-events b/hw/audio/trace-events
index 4dec48a4fd..89ef2996e5 100644
--- a/hw/audio/trace-events
+++ b/hw/audio/trace-events
@@ -17,3 +17,13 @@ via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x"
via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char flag, uint32_t len) "curr=0x%x addr=0x%x %c%c%c len=%d"
via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64
via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64
+
+# asc.c
+asc_read_fifo(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
+asc_read_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64
+asc_read_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
+asc_fifo_get(const char fifo, int rptr, int cnt, uint64_t value) "fifo %c rptr=0x%x cnt=0x%x value=0x%"PRIx64
+asc_write_fifo(const char fifo, int reg, unsigned size, int wrptr, int cnt, uint64_t value) "fifo %c reg=0x%03x size=%u wptr=0x%x cnt=0x%x value=0x%"PRIx64
+asc_write_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64
+asc_write_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
+asc_update_irq(int irq, int a, int b) "set IRQ to %d (A: 0x%x B: 0x%x)"
diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
index 64fa70a0db..d88741ec9d 100644
--- a/hw/m68k/Kconfig
+++ b/hw/m68k/Kconfig
@@ -25,6 +25,7 @@ config Q800
select OR_IRQ
select DJMEMC
select IOSB
+ select ASC
config M68K_VIRT
bool
diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h
new file mode 100644
index 0000000000..d69aa4ade1
--- /dev/null
+++ b/include/hw/audio/asc.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_AUDIO_ASC_H
+#define HW_AUDIO_ASC_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "audio/audio.h"
+
+enum {
+ ASC_TYPE_ASC = 0, /* original discrete Apple Sound Chip */
+ ASC_TYPE_EASC = 1 /* discrete Enhanced Apple Sound Chip */
+};
+
+#define ASC_FIFO_OFFSET 0x0
+#define ASC_FIFO_SIZE 0x400
+
+#define ASC_REG_OFFSET 0x800
+#define ASC_REG_SIZE 0x60
+
+#define ASC_EXTREG_OFFSET 0xf00
+#define ASC_EXTREG_SIZE 0x20
+
+typedef struct ASCFIFOState {
+ int index;
+
+ MemoryRegion mem_fifo;
+ uint8_t fifo[ASC_FIFO_SIZE];
+ uint8_t int_status;
+
+ int cnt;
+ int wptr;
+ int rptr;
+
+ MemoryRegion mem_extregs;
+ uint8_t extregs[ASC_EXTREG_SIZE];
+
+ int xa_cnt;
+ uint8_t xa_val;
+ uint8_t xa_flags;
+ int16_t xa_last[2];
+} ASCFIFOState;
+
+struct ASCState {
+ SysBusDevice parent_obj;
+
+ uint8_t type;
+ MemoryRegion asc;
+ MemoryRegion mem_fifo;
+ MemoryRegion mem_regs;
+ MemoryRegion mem_extregs;
+
+ QEMUSoundCard card;
+ SWVoiceOut *voice;
+ uint8_t *mixbuf;
+ int samples;
+ int shift;
+
+ qemu_irq irq;
+
+ ASCFIFOState fifos[2];
+
+ uint8_t regs[ASC_REG_SIZE];
+};
+
+#define TYPE_ASC "apple-sound-chip"
+OBJECT_DECLARE_SIMPLE_TYPE(ASCState, ASC)
+
+#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 14/30] audio: add Apple Sound Chip (ASC) emulation
2023-05-24 21:10 ` [PATCH 14/30] audio: add Apple Sound Chip (ASC) emulation Mark Cave-Ayland
@ 2023-05-29 11:43 ` Volker Rümelin
0 siblings, 0 replies; 54+ messages in thread
From: Volker Rümelin @ 2023-05-29 11:43 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
> The Apple Sound Chip was primarily used by the Macintosh II to generate sound
> in hardware which was previously handled by the toolbox ROM with software
> interrupts.
>
> Implement both the standard ASC and also the enhanced ASC (EASC) functionality
> which is used in the Quadra 800.
>
> Note that whilst real ASC hardware uses AUDIO_FORMAT_S8, this implementation uses
> AUDIO_FORMAT_U8 instead because AUDIO_FORMAT_S8 is rarely used and not supported
> by some audio backends like PulseAudio and DirectSound when played directly with
> -audiodev out.mixing-engine=off.
>
> Co-developed-by: Laurent Vivier <laurent@vivier.eu>
> Co-developed-by: Volker Rümelin <vr_qemu@t-online.de>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> MAINTAINERS | 2 +
> hw/audio/Kconfig | 3 +
> hw/audio/asc.c | 688 +++++++++++++++++++++++++++++++++++++++++
> hw/audio/meson.build | 1 +
> hw/audio/trace-events | 10 +
> hw/m68k/Kconfig | 1 +
> include/hw/audio/asc.h | 75 +++++
> 7 files changed, 780 insertions(+)
> create mode 100644 hw/audio/asc.c
> create mode 100644 include/hw/audio/asc.h
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f151aaf99f..1b79ab7965 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1229,6 +1229,7 @@ F: hw/display/macfb.c
> F: hw/block/swim.c
> F: hw/misc/djmemc.c
> F: hw/misc/iosb.c
> +F: hw/audio/asc.c
> F: hw/m68k/bootinfo.h
> F: include/standard-headers/asm-m68k/bootinfo.h
> F: include/standard-headers/asm-m68k/bootinfo-mac.h
> @@ -1239,6 +1240,7 @@ F: include/hw/block/swim.h
> F: include/hw/m68k/q800.h
> F: include/hw/misc/djmemc.c
> F: include/hw/misc/iosb.c
> +F: include/hw/audio/asc.h
>
> virt
> M: Laurent Vivier <laurent@vivier.eu>
> diff --git a/hw/audio/Kconfig b/hw/audio/Kconfig
> index e76c69ca7e..d0993514a1 100644
> --- a/hw/audio/Kconfig
> +++ b/hw/audio/Kconfig
> @@ -47,3 +47,6 @@ config PL041
>
> config CS4231
> bool
> +
> +config ASC
> + bool
> diff --git a/hw/audio/asc.c b/hw/audio/asc.c
> new file mode 100644
> index 0000000000..04194b1e43
> --- /dev/null
> +++ b/hw/audio/asc.c
> @@ -0,0 +1,688 @@
> +/*
> + * QEMU Apple Sound Chip emulation
> + *
> + * Apple Sound Chip (ASC) 344S0063
> + * Enhanced Apple Sound Chip (EASC) 343S1063
> + *
> + * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
> + * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/irq.h"
> +#include "audio/audio.h"
> +#include "hw/audio/asc.h"
> +#include "hw/qdev-properties.h"
> +#include "migration/vmstate.h"
> +#include "trace.h"
> +
> +/*
> + * Linux doesn't provide information about ASC, see arch/m68k/mac/macboing.c
> + * and arch/m68k/include/asm/mac_asc.h
> + *
> + * best information is coming from MAME:
> + * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.h
> + * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.cpp
> + * Emulation by R. Belmont
> + * or MESS:
> + * http://mess.redump.net/mess/driver_info/easc
> + *
> + * 0x800: VERSION
> + * 0x801: MODE
> + * 1=FIFO mode,
> + * 2=wavetable mode
> + * 0x802: CONTROL
> + * bit 0=analog or PWM output,
> + * 1=stereo/mono,
> + * 7=processing time exceeded
> + * 0x803: FIFO MODE
> + * bit 7=clear FIFO,
> + * bit 1="non-ROM companding",
> + * bit 0="ROM companding")
> + * 0x804: FIFO IRQ STATUS
> + * bit 0=ch A 1/2 full,
> + * 1=ch A full,
> + * 2=ch B 1/2 full,
> + * 3=ch B full)
> + * 0x805: WAVETABLE CONTROL
> + * bits 0-3 wavetables 0-3 start
> + * 0x806: VOLUME
> + * bits 2-4 = 3 bit internal ASC volume,
> + * bits 5-7 = volume control sent to Sony sound chip
> + * 0x807: CLOCK RATE
> + * 0 = Mac 22257 Hz,
> + * 1 = undefined,
> + * 2 = 22050 Hz,
> + * 3 = 44100 Hz
> + * 0x80a: PLAY REC A
> + * 0x80f: TEST
> + * bits 6-7 = digital test,
> + * bits 4-5 = analog test
> + * 0x810: WAVETABLE 0 PHASE
> + * big-endian 9.15 fixed-point, only 24 bits valid
> + * 0x814: WAVETABLE 0 INCREMENT
> + * big-endian 9.15 fixed-point, only 24 bits valid
> + * 0x818: WAVETABLE 1 PHASE
> + * 0x81C: WAVETABLE 1 INCREMENT
> + * 0x820: WAVETABLE 2 PHASE
> + * 0x824: WAVETABLE 2 INCREMENT
> + * 0x828: WAVETABLE 3 PHASE
> + * 0x82C: WAVETABLE 3 INCREMENT
> + * 0x830: UNKNOWN START
> + * NetBSD writes Wavetable data here (are there more
> + * wavetables/channels than we know about?)
> + * 0x857: UNKNOWN END
> + */
> +
> +#define ASC_SIZE 0x2000
> +
> +enum {
> + ASC_VERSION = 0x00,
> + ASC_MODE = 0x01,
> + ASC_CONTROL = 0x02,
> + ASC_FIFOMODE = 0x03,
> + ASC_FIFOIRQ = 0x04,
> + ASC_WAVECTRL = 0x05,
> + ASC_VOLUME = 0x06,
> + ASC_CLOCK = 0x07,
> + ASC_PLAYRECA = 0x0a,
> + ASC_TEST = 0x0f,
> + ASC_WAVETABLE = 0x10
> +};
> +
> +#define ASC_FIFO_STATUS_HALF_FULL 1
> +#define ASC_FIFO_STATUS_FULL_EMPTY 2
> +
> +#define ASC_EXTREGS_FIFOCTRL 0x8
> +#define ASC_EXTREGS_INTCTRL 0x9
> +#define ASC_EXTREGS_CDXA_DECOMP_FILT 0x10
> +
> +
> +static void asc_raise_irq(ASCState *s)
> +{
> + qemu_set_irq(s->irq, 1);
> +}
> +
> +static void asc_lower_irq(ASCState *s)
> +{
> + qemu_set_irq(s->irq, 0);
> +}
> +
> +static uint8_t asc_fifo_get(ASCFIFOState *fs)
> +{
> + ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
> + bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
> + uint8_t val;
> +
> + assert(fs->cnt);
> +
> + val = fs->fifo[fs->rptr];
> + trace_asc_fifo_get('A' + fs->index, fs->rptr, fs->cnt, val);
> +
> + fs->rptr++;
> + fs->rptr &= 0x3ff;
> + fs->cnt--;
> +
> + if (fs->cnt <= 0x1ff) {
> + /* FIFO less than half full */
> + fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
> + } else {
> + /* FIFO more than half full */
> + fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
> + }
> +
> + if (fs->cnt == 0x1ff && fifo_half_irq_enabled) {
> + /* Raise FIFO half full IRQ */
> + asc_raise_irq(s);
> + }
> +
> + if (fs->cnt == 0) {
> + /* Raise FIFO empty IRQ */
> + fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
> + asc_raise_irq(s);
> + }
> +
> + return val;
> +}
> +
> +static int generate_fifo(ASCState *s, int maxsamples)
> +{
> + uint8_t *buf = s->mixbuf;
> + int i, limit, count = 0;
> +
> + limit = MIN(MAX(s->fifos[0].cnt, s->fifos[1].cnt), maxsamples);
> +
> + /*
> + * If starting a new run with no FIFO data present, update the IRQ and
> + * continue
> + */
> + if (limit == 0 && s->fifos[0].int_status == 0 &&
> + s->fifos[1].int_status == 0) {
> + s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL |
> + ASC_FIFO_STATUS_FULL_EMPTY;
> + s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
> + ASC_FIFO_STATUS_FULL_EMPTY;
> +
> + asc_raise_irq(s);
> + return 0;
> + }
> +
> + while (count < limit) {
> + uint8_t val;
> + int16_t d, f0, f1;
> + int32_t t;
> + int shift, filter;
> + bool hasdata = true;
> +
> + for (i = 0; i < 2; i++) {
> + ASCFIFOState *fs = &s->fifos[i];
> +
> + switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) {
> + case 0x82:
> + /*
> + * CD-XA BRR mode: exit if there isn't enough data in the FIFO
> + * for a complete 15 byte packet
> + */
> + if (fs->xa_cnt == -1 && fs->cnt < 15) {
> + hasdata = false;
> + continue;
> + }
> +
> + if (fs->xa_cnt == -1) {
> + /* Start of packet, get flags */
> + fs->xa_flags = asc_fifo_get(fs);
> + fs->xa_cnt = 0;
> + }
> +
> + shift = fs->xa_flags & 0xf;
> + filter = fs->xa_flags >> 4;
> + f0 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
> + (filter << 1) + 1];
> + f1 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
> + (filter << 1)];
> + if ((fs->xa_cnt & 1) == 0) {
> + fs->xa_val = asc_fifo_get(fs);
> + d = (fs->xa_val & 0xf) << 12;
> + } else {
> + d = (fs->xa_val & 0xf0) << 8;
> + }
> + t = (d >> shift) + (((fs->xa_last[0] * f0) +
> + (fs->xa_last[1] * f1) + 32) >> 6);
> + if (t < -32768) {
> + t = -32768;
> + } else if (t > 32768) {
> + t = 32768;
> + }
> +
> + /*
> + * CD-XA BRR generates 16-bit signed output, so convert to
> + * 8-bit before writing to buffer. Does real hardware do the
> + * same?
> + */
> + buf[count * 2 + i] = (uint8_t)(t / 256) ^ 0x80;
> + fs->xa_cnt++;
> +
> + fs->xa_last[1] = fs->xa_last[0];
> + fs->xa_last[0] = (int16_t)t;
> +
> + if (fs->xa_cnt == 28) {
> + /* End of packet */
> + fs->xa_cnt = -1;
> + }
> + break;
> +
> + default:
> + /* fallthrough */
> + case 0x80:
> + /* Raw mode */
> + if (fs->cnt) {
> + val = asc_fifo_get(fs);
> + } else {
> + val = 0x80;
> + }
> +
> + buf[count * 2 + i] = val;
> + break;
> + }
> + }
> +
> + if (!hasdata) {
> + break;
> + }
> +
> + count++;
> + }
> +
> + return count;
> +}
> +
> +static int generate_wavetable(ASCState *s, int maxsamples)
> +{
> + uint8_t *buf = s->mixbuf;
> + int channel, count = 0;
> +
> + while (count < maxsamples) {
> + uint32_t left = 0, right = 0;
> + uint8_t sample;
> +
> + for (channel = 0; channel < 4; channel++) {
> + ASCFIFOState *fs = &s->fifos[channel >> 1];
> + int chanreg = ASC_WAVETABLE + (channel << 3);
> + uint32_t phase, incr, offset;
> +
> + phase = ldl_be_p(&s->regs[chanreg]);
> + incr = ldl_be_p(&s->regs[chanreg + sizeof(uint32_t)]);
> +
> + phase += incr;
> + offset = (phase >> 15) & 0x1ff;
> + sample = fs->fifo[0x200 * (channel >> 1) + offset];
> +
> + stl_be_p(&s->regs[chanreg], phase);
> +
> + left += sample;
> + right += sample;
> + }
> +
> + buf[count * 2] = left >> 2;
> + buf[count * 2 + 1] = right >> 2;
> +
> + count++;
> + }
> +
> + return count;
> +}
> +
> +static void asc_out_cb(void *opaque, int free_b)
> +{
> + ASCState *s = opaque;
> + int samples;
> +
> + samples = MIN(s->samples, free_b >> s->shift);
> + if (!samples) {
> + return;
> + }
> +
> + switch (s->regs[ASC_MODE] & 3) {
> + default:
> + /* Off */
> + samples = 0;
> + break;
> + case 1:
> + /* FIFO mode */
> + samples = generate_fifo(s, samples);
> + break;
> + case 2:
> + /* Wave table mode */
> + samples = generate_wavetable(s, samples);
> + break;
> + }
> +
> + if (!samples) {
> + return;
> + }
> +
> + AUD_write(s->voice, s->mixbuf, samples << s->shift);
> +}
> +
> +static uint64_t asc_fifo_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + ASCFIFOState *fs = opaque;
> +
> + trace_asc_read_fifo('A' + fs->index, addr, size, fs->fifo[addr]);
> + return fs->fifo[addr];
> +}
> +
> +static void asc_fifo_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + ASCFIFOState *fs = opaque;
> + ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
> + bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
> +
> + trace_asc_write_fifo('A' + fs->index, addr, size, fs->wptr, fs->cnt, value);
> +
> + if (s->regs[ASC_MODE] == 1) {
> + fs->fifo[fs->wptr++] = value;
> + fs->wptr &= 0x3ff;
> + fs->cnt++;
> +
> + if (fs->cnt <= 0x1ff) {
> + /* FIFO less than half full */
> + fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
> + } else {
> + /* FIFO at least half full */
> + fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
> + }
> +
> + if (fs->cnt == 0x200 && fifo_half_irq_enabled) {
> + /* Raise FIFO half full interrupt */
> + asc_raise_irq(s);
> + }
> +
> + if (fs->cnt == 0x3ff) {
> + /* Raise FIFO full interrupt */
> + fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
> + asc_raise_irq(s);
> + }
> + } else {
> + fs->fifo[addr] = value;
> + }
> + return;
> +}
> +
> +static const MemoryRegionOps asc_fifo_ops = {
> + .read = asc_fifo_read,
> + .write = asc_fifo_write,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void asc_fifo_reset(ASCFIFOState *fs);
> +
> +static uint64_t asc_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + ASCState *s = opaque;
> + uint64_t prev, value;
> +
> + switch (addr) {
> + case ASC_VERSION:
> + switch (s->type) {
> + default:
> + case ASC_TYPE_ASC:
> + value = 0;
> + break;
> + case ASC_TYPE_EASC:
> + value = 0xb0;
> + break;
> + }
> + break;
> + case ASC_FIFOIRQ:
> + prev = (s->fifos[0].int_status & 0x3) |
> + (s->fifos[1].int_status & 0x3) << 2;
> +
> + s->fifos[0].int_status = 0;
> + s->fifos[1].int_status = 0;
> + asc_lower_irq(s);
> + value = prev;
> + break;
> + default:
> + value = s->regs[addr];
> + break;
> + }
> +
> + trace_asc_read_reg(addr, size, value);
> + return value;
> +}
> +
> +static void asc_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + ASCState *s = opaque;
> +
> + switch (addr) {
> + case ASC_MODE:
> + value &= 3;
> + if (value != s->regs[ASC_MODE]) {
> + asc_fifo_reset(&s->fifos[0]);
> + asc_fifo_reset(&s->fifos[1]);
> + asc_lower_irq(s);
> + if (value != 0) {
> + AUD_set_active_out(s->voice, 1);
> + } else {
> + AUD_set_active_out(s->voice, 0);
> + }
> + }
> + break;
> + case ASC_FIFOMODE:
> + if (value & 0x80) {
> + asc_fifo_reset(&s->fifos[0]);
> + asc_fifo_reset(&s->fifos[1]);
> + asc_lower_irq(s);
> + }
> + break;
> + case ASC_WAVECTRL:
> + break;
> + case ASC_VOLUME:
> + {
> + int vol = (value & 0xe0);
> +
> + AUD_set_volume_out(s->voice, 0, vol, vol);
> + break;
> + }
> + }
> +
> + trace_asc_write_reg(addr, size, value);
> + s->regs[addr] = value;
> +}
> +
> +static const MemoryRegionOps asc_regs_ops = {
> + .read = asc_read,
> + .write = asc_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + }
> +};
> +
> +static uint64_t asc_ext_read(void *opaque, hwaddr addr,
> + unsigned size)
> +{
> + ASCFIFOState *fs = opaque;
> + uint64_t value;
> +
> + value = fs->extregs[addr];
> +
> + trace_asc_read_extreg('A' + fs->index, addr, size, value);
> + return value;
> +}
> +
> +static void asc_ext_write(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + ASCFIFOState *fs = opaque;
> +
> + trace_asc_write_extreg('A' + fs->index, addr, size, value);
> +
> + fs->extregs[addr] = value;
> +}
> +
> +static const MemoryRegionOps asc_extregs_ops = {
> + .read = asc_ext_read,
> + .write = asc_ext_write,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static int asc_post_load(void *opaque, int version)
> +{
> + ASCState *s = ASC(opaque);
> +
> + if (s->regs[ASC_MODE] != 0) {
> + AUD_set_active_out(s->voice, 1);
> + }
> +
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_asc_fifo = {
> + .name = "apple-sound-chip.fifo",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8_ARRAY(fifo, ASCFIFOState, ASC_FIFO_SIZE),
> + VMSTATE_UINT8(int_status, ASCFIFOState),
> + VMSTATE_INT32(cnt, ASCFIFOState),
> + VMSTATE_INT32(wptr, ASCFIFOState),
> + VMSTATE_INT32(rptr, ASCFIFOState),
> + VMSTATE_UINT8_ARRAY(extregs, ASCFIFOState, ASC_EXTREG_SIZE),
> + VMSTATE_INT32(xa_cnt, ASCFIFOState),
> + VMSTATE_UINT8(xa_val, ASCFIFOState),
> + VMSTATE_UINT8(xa_flags, ASCFIFOState),
> + VMSTATE_INT16_ARRAY(xa_last, ASCFIFOState, 2),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static const VMStateDescription vmstate_asc = {
> + .name = "apple-sound-chip",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .post_load = asc_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_STRUCT_ARRAY(fifos, ASCState, 2, 0, vmstate_asc_fifo,
> + ASCFIFOState),
> + VMSTATE_UINT8_ARRAY(regs, ASCState, ASC_REG_SIZE),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void asc_fifo_reset(ASCFIFOState *fs)
> +{
> + fs->wptr = 0;
> + fs->rptr = 0;
> + fs->cnt = 0;
> + fs->xa_cnt = -1;
> + fs->int_status = 0;
> +}
> +
> +static void asc_fifo_init(ASCFIFOState *fs, int index)
> +{
> + ASCState *s = container_of(fs, ASCState, fifos[index]);
> + char *name;
> +
> + fs->index = index;
> + name = g_strdup_printf("asc.fifo%c", 'A' + index);
> + memory_region_init_io(&fs->mem_fifo, OBJECT(s), &asc_fifo_ops, fs,
> + name, ASC_FIFO_SIZE);
> + g_free(name);
> +
> + name = g_strdup_printf("asc.extregs%c", 'A' + index);
> + memory_region_init_io(&fs->mem_extregs, OBJECT(s), &asc_extregs_ops,
> + fs, name, ASC_EXTREG_SIZE);
> + g_free(name);
> +}
> +
> +static void asc_reset(DeviceState *d)
> +{
> + ASCState *s = ASC(d);
> +
> + AUD_set_active_out(s->voice, 0);
> +
> + memset(s->regs, 0, sizeof(s->regs));
> + asc_fifo_reset(&s->fifos[0]);
> + asc_fifo_reset(&s->fifos[1]);
> +
> + if (s->type == ASC_TYPE_ASC) {
> + /* FIFO half full IRQs enabled by default */
> + s->fifos[0].extregs[ASC_EXTREGS_INTCTRL] = 1;
> + s->fifos[1].extregs[ASC_EXTREGS_INTCTRL] = 1;
> + }
> +}
> +
> +static void asc_unrealize(DeviceState *dev)
> +{
> + ASCState *s = ASC(dev);
> +
> + g_free(s->mixbuf);
> +
> + AUD_remove_card(&s->card);
> +}
> +
> +static void asc_realize(DeviceState *dev, Error **errp)
> +{
> + ASCState *s = ASC(dev);
> + struct audsettings as;
> +
> + AUD_register_card("Apple Sound Chip", &s->card);
> +
> + as.freq = 22257;
> + as.nchannels = 2;
> + as.fmt = AUDIO_FORMAT_U8;
> + as.endianness = AUDIO_HOST_ENDIANNESS;
> +
> + s->voice = AUD_open_out(&s->card, s->voice, "asc.out", s, asc_out_cb,
> + &as);
> + s->shift = 1;
> + s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift;
> + s->mixbuf = g_malloc0(s->samples << s->shift);
> +
> + /* Add easc registers if required */
> + if (s->type == ASC_TYPE_EASC) {
> + memory_region_add_subregion(&s->asc, ASC_EXTREG_OFFSET,
> + &s->fifos[0].mem_extregs);
> + memory_region_add_subregion(&s->asc,
> + ASC_EXTREG_OFFSET + ASC_EXTREG_SIZE,
> + &s->fifos[1].mem_extregs);
> + }
> +}
> +
> +static void asc_init(Object *obj)
> +{
> + ASCState *s = ASC(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +
> + memory_region_init(&s->asc, OBJECT(obj), "asc", ASC_SIZE);
> +
> + asc_fifo_init(&s->fifos[0], 0);
> + asc_fifo_init(&s->fifos[1], 1);
> +
> + memory_region_add_subregion(&s->asc, ASC_FIFO_OFFSET,
> + &s->fifos[0].mem_fifo);
> + memory_region_add_subregion(&s->asc,
> + ASC_FIFO_OFFSET + ASC_FIFO_SIZE,
> + &s->fifos[1].mem_fifo);
> +
> + memory_region_init_io(&s->mem_regs, OBJECT(obj), &asc_regs_ops, s,
> + "asc.regs", ASC_REG_SIZE);
> + memory_region_add_subregion(&s->asc, ASC_REG_OFFSET, &s->mem_regs);
> +
> + sysbus_init_irq(sbd, &s->irq);
> + sysbus_init_mmio(sbd, &s->asc);
> +}
> +
> +static Property asc_properties[] = {
> + DEFINE_AUDIO_PROPERTIES(ASCState, card),
> + DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void asc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = asc_realize;
> + dc->unrealize = asc_unrealize;
> + set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
> + dc->reset = asc_reset;
> + dc->vmsd = &vmstate_asc;
> + device_class_set_props(dc, asc_properties);
> +}
> +
> +static const TypeInfo asc_info = {
> + .name = TYPE_ASC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ASCState),
> + .instance_init = asc_init,
> + .class_init = asc_class_init,
> +};
> +
> +static void asc_register_types(void)
> +{
> + type_register_static(&asc_info);
> +}
> +
> +type_init(asc_register_types)
> diff --git a/hw/audio/meson.build b/hw/audio/meson.build
> index e48a9fc73d..2de764912f 100644
> --- a/hw/audio/meson.build
> +++ b/hw/audio/meson.build
> @@ -1,6 +1,7 @@
> softmmu_ss.add(files('soundhw.c'))
> softmmu_ss.add(when: 'CONFIG_AC97', if_true: files('ac97.c'))
> softmmu_ss.add(when: 'CONFIG_ADLIB', if_true: files('fmopl.c', 'adlib.c'))
> +softmmu_ss.add(when: 'CONFIG_ASC', if_true: files('asc.c'))
> softmmu_ss.add(when: 'CONFIG_CS4231', if_true: files('cs4231.c'))
> softmmu_ss.add(when: 'CONFIG_CS4231A', if_true: files('cs4231a.c'))
> softmmu_ss.add(when: 'CONFIG_ES1370', if_true: files('es1370.c'))
> diff --git a/hw/audio/trace-events b/hw/audio/trace-events
> index 4dec48a4fd..89ef2996e5 100644
> --- a/hw/audio/trace-events
> +++ b/hw/audio/trace-events
> @@ -17,3 +17,13 @@ via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x"
> via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char flag, uint32_t len) "curr=0x%x addr=0x%x %c%c%c len=%d"
> via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64
> via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64
> +
> +# asc.c
> +asc_read_fifo(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
> +asc_read_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64
> +asc_read_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
> +asc_fifo_get(const char fifo, int rptr, int cnt, uint64_t value) "fifo %c rptr=0x%x cnt=0x%x value=0x%"PRIx64
> +asc_write_fifo(const char fifo, int reg, unsigned size, int wrptr, int cnt, uint64_t value) "fifo %c reg=0x%03x size=%u wptr=0x%x cnt=0x%x value=0x%"PRIx64
> +asc_write_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64
> +asc_write_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64
> +asc_update_irq(int irq, int a, int b) "set IRQ to %d (A: 0x%x B: 0x%x)"
> diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig
> index 64fa70a0db..d88741ec9d 100644
> --- a/hw/m68k/Kconfig
> +++ b/hw/m68k/Kconfig
> @@ -25,6 +25,7 @@ config Q800
> select OR_IRQ
> select DJMEMC
> select IOSB
> + select ASC
>
> config M68K_VIRT
> bool
> diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h
> new file mode 100644
> index 0000000000..d69aa4ade1
> --- /dev/null
> +++ b/include/hw/audio/asc.h
> @@ -0,0 +1,75 @@
> +/*
> + * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_AUDIO_ASC_H
> +#define HW_AUDIO_ASC_H
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "audio/audio.h"
> +
> +enum {
> + ASC_TYPE_ASC = 0, /* original discrete Apple Sound Chip */
> + ASC_TYPE_EASC = 1 /* discrete Enhanced Apple Sound Chip */
> +};
> +
> +#define ASC_FIFO_OFFSET 0x0
> +#define ASC_FIFO_SIZE 0x400
> +
> +#define ASC_REG_OFFSET 0x800
> +#define ASC_REG_SIZE 0x60
> +
> +#define ASC_EXTREG_OFFSET 0xf00
> +#define ASC_EXTREG_SIZE 0x20
> +
> +typedef struct ASCFIFOState {
> + int index;
> +
> + MemoryRegion mem_fifo;
> + uint8_t fifo[ASC_FIFO_SIZE];
> + uint8_t int_status;
> +
> + int cnt;
> + int wptr;
> + int rptr;
> +
> + MemoryRegion mem_extregs;
> + uint8_t extregs[ASC_EXTREG_SIZE];
> +
> + int xa_cnt;
> + uint8_t xa_val;
> + uint8_t xa_flags;
> + int16_t xa_last[2];
> +} ASCFIFOState;
> +
> +struct ASCState {
> + SysBusDevice parent_obj;
> +
> + uint8_t type;
> + MemoryRegion asc;
> + MemoryRegion mem_fifo;
> + MemoryRegion mem_regs;
> + MemoryRegion mem_extregs;
> +
> + QEMUSoundCard card;
> + SWVoiceOut *voice;
> + uint8_t *mixbuf;
> + int samples;
> + int shift;
> +
> + qemu_irq irq;
> +
> + ASCFIFOState fifos[2];
> +
> + uint8_t regs[ASC_REG_SIZE];
> +};
> +
> +#define TYPE_ASC "apple-sound-chip"
> +OBJECT_DECLARE_SIMPLE_TYPE(ASCState, ASC)
> +
> +#endif
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 15/30] asc: generate silence if FIFO empty but engine still running
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (13 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 14/30] audio: add Apple Sound Chip (ASC) emulation Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-29 11:40 ` Volker Rümelin
2023-05-30 11:27 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 16/30] q800: add Apple Sound Chip (ASC) audio to machine Mark Cave-Ayland
` (14 subsequent siblings)
29 siblings, 2 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
MacOS (un)helpfully leaves the FIFO engine running even when all the samples have
been written to the hardware, and expects the FIFO status flags and IRQ to be
updated continuously.
Since not all audio backends guarantee an all-zero output when no data is
provided, explicitly generate an all-zero output when this condition occurs to
avoid the audio backends re-using their internal buffers and looping audio once
the FIFOs are empty.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/audio/asc.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/audio/asc.c b/hw/audio/asc.c
index 04194b1e43..c5173a8d35 100644
--- a/hw/audio/asc.c
+++ b/hw/audio/asc.c
@@ -158,8 +158,10 @@ static int generate_fifo(ASCState *s, int maxsamples)
limit = MIN(MAX(s->fifos[0].cnt, s->fifos[1].cnt), maxsamples);
/*
- * If starting a new run with no FIFO data present, update the IRQ and
- * continue
+ * MacOS (un)helpfully leaves the FIFO engine running even when it has
+ * finished writing out samples. Since not all audio backends guarantee an
+ * all-zero output when no data is provided, zero out the sample buffer
+ * and then update the FIFO flags and IRQ as normal and continue
*/
if (limit == 0 && s->fifos[0].int_status == 0 &&
s->fifos[1].int_status == 0) {
@@ -168,8 +170,9 @@ static int generate_fifo(ASCState *s, int maxsamples)
s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
ASC_FIFO_STATUS_FULL_EMPTY;
+ memset(buf, 0x80, maxsamples << s->shift);
asc_raise_irq(s);
- return 0;
+ return maxsamples;
}
while (count < limit) {
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 15/30] asc: generate silence if FIFO empty but engine still running
2023-05-24 21:10 ` [PATCH 15/30] asc: generate silence if FIFO empty but engine still running Mark Cave-Ayland
@ 2023-05-29 11:40 ` Volker Rümelin
2023-05-30 11:27 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Volker Rümelin @ 2023-05-29 11:40 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
> MacOS (un)helpfully leaves the FIFO engine running even when all the samples have
> been written to the hardware, and expects the FIFO status flags and IRQ to be
> updated continuously.
>
> Since not all audio backends guarantee an all-zero output when no data is
> provided, explicitly generate an all-zero output when this condition occurs to
> avoid the audio backends re-using their internal buffers and looping audio once
> the FIFOs are empty.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/audio/asc.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
> diff --git a/hw/audio/asc.c b/hw/audio/asc.c
> index 04194b1e43..c5173a8d35 100644
> --- a/hw/audio/asc.c
> +++ b/hw/audio/asc.c
> @@ -158,8 +158,10 @@ static int generate_fifo(ASCState *s, int maxsamples)
> limit = MIN(MAX(s->fifos[0].cnt, s->fifos[1].cnt), maxsamples);
>
> /*
> - * If starting a new run with no FIFO data present, update the IRQ and
> - * continue
> + * MacOS (un)helpfully leaves the FIFO engine running even when it has
> + * finished writing out samples. Since not all audio backends guarantee an
> + * all-zero output when no data is provided, zero out the sample buffer
> + * and then update the FIFO flags and IRQ as normal and continue
> */
> if (limit == 0 && s->fifos[0].int_status == 0 &&
> s->fifos[1].int_status == 0) {
> @@ -168,8 +170,9 @@ static int generate_fifo(ASCState *s, int maxsamples)
> s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
> ASC_FIFO_STATUS_FULL_EMPTY;
>
> + memset(buf, 0x80, maxsamples << s->shift);
> asc_raise_irq(s);
> - return 0;
> + return maxsamples;
> }
>
> while (count < limit) {
^ permalink raw reply [flat|nested] 54+ messages in thread* Re: [PATCH 15/30] asc: generate silence if FIFO empty but engine still running
2023-05-24 21:10 ` [PATCH 15/30] asc: generate silence if FIFO empty but engine still running Mark Cave-Ayland
2023-05-29 11:40 ` Volker Rümelin
@ 2023-05-30 11:27 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:27 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> MacOS (un)helpfully leaves the FIFO engine running even when all the samples have
> been written to the hardware, and expects the FIFO status flags and IRQ to be
> updated continuously.
>
> Since not all audio backends guarantee an all-zero output when no data is
> provided, explicitly generate an all-zero output when this condition occurs to
> avoid the audio backends re-using their internal buffers and looping audio once
> the FIFOs are empty.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/audio/asc.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/audio/asc.c b/hw/audio/asc.c
> index 04194b1e43..c5173a8d35 100644
> --- a/hw/audio/asc.c
> +++ b/hw/audio/asc.c
> @@ -158,8 +158,10 @@ static int generate_fifo(ASCState *s, int maxsamples)
> limit = MIN(MAX(s->fifos[0].cnt, s->fifos[1].cnt), maxsamples);
>
> /*
> - * If starting a new run with no FIFO data present, update the IRQ and
> - * continue
> + * MacOS (un)helpfully leaves the FIFO engine running even when it has
> + * finished writing out samples. Since not all audio backends guarantee an
> + * all-zero output when no data is provided, zero out the sample buffer
> + * and then update the FIFO flags and IRQ as normal and continue
> */
> if (limit == 0 && s->fifos[0].int_status == 0 &&
> s->fifos[1].int_status == 0) {
> @@ -168,8 +170,9 @@ static int generate_fifo(ASCState *s, int maxsamples)
> s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
> ASC_FIFO_STATUS_FULL_EMPTY;
>
> + memset(buf, 0x80, maxsamples << s->shift);
> asc_raise_irq(s);
> - return 0;
> + return maxsamples;
> }
>
> while (count < limit) {
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 16/30] q800: add Apple Sound Chip (ASC) audio to machine
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (14 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 15/30] asc: generate silence if FIFO empty but engine still running Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 17/30] q800: add easc bool machine class property to switch between ASC and EASC Mark Cave-Ayland
` (13 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The Quadra 800 has the enhanced ASC (EASC) audio chip which supports both the
legacy IRQ routing through VIA2 and also "A/UX" mode routing direct to the
CPU.
Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index d12aeaa20e..ed862f9e9d 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -43,6 +43,7 @@
#include "hw/misc/djmemc.h"
#include "hw/misc/iosb.h"
#include "hw/input/adb.h"
+#include "hw/audio/asc.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
#include "hw/block/swim.h"
@@ -115,7 +116,7 @@ struct GLUEState {
M68kCPU *cpu;
uint8_t ipr;
uint8_t auxmode;
- qemu_irq irqs[1];
+ qemu_irq irqs[2];
QEMUTimer *nmi_release;
};
@@ -124,8 +125,10 @@ struct GLUEState {
#define GLUE_IRQ_IN_SONIC 2
#define GLUE_IRQ_IN_ESCC 3
#define GLUE_IRQ_IN_NMI 4
+#define GLUE_IRQ_IN_ASC 5
#define GLUE_IRQ_NUBUS_9 0
+#define GLUE_IRQ_ASC 1
/*
* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
@@ -187,6 +190,11 @@ static void GLUE_set_irq(void *opaque, int irq, int level)
irq = 6;
break;
+ case GLUE_IRQ_IN_ASC:
+ /* Route to VIA2 instead, negative edge-triggered */
+ qemu_set_irq(s->irqs[GLUE_IRQ_ASC], !level);
+ return;
+
default:
g_assert_not_reached();
}
@@ -213,6 +221,10 @@ static void GLUE_set_irq(void *opaque, int irq, int level)
irq = 6;
break;
+ case GLUE_IRQ_IN_ASC:
+ irq = 4;
+ break;
+
default:
g_assert_not_reached();
}
@@ -304,7 +316,7 @@ static void glue_init(Object *obj)
qdev_init_gpio_in(dev, GLUE_set_irq, 8);
qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
- qdev_init_gpio_out(dev, s->irqs, 1);
+ qdev_init_gpio_out(dev, s->irqs, 2);
/* NMI release timer */
s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
@@ -695,6 +707,20 @@ static void q800_machine_init(MachineState *machine)
scsi_bus_legacy_handle_cmdline(&esp->bus);
+ /* Apple Sound Chip */
+
+ dev = qdev_new(TYPE_ASC);
+ qdev_prop_set_uint8(dev, "asctype", ASC_TYPE_EASC);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ memory_region_add_subregion(&m->macio, ASC_BASE - IO_BASE,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(m->glue, GLUE_IRQ_IN_ASC));
+
+ /* Wire ASC IRQ via GLUE for use in classic mode */
+ qdev_connect_gpio_out(m->glue, GLUE_IRQ_ASC,
+ qdev_get_gpio_in(via2_dev, VIA2_IRQ_ASC_BIT));
+
/* SWIM floppy controller */
dev = qdev_new(TYPE_SWIM);
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 17/30] q800: add easc bool machine class property to switch between ASC and EASC
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (15 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 16/30] q800: add Apple Sound Chip (ASC) audio to machine Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 11:28 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 18/30] swim: add trace events for IWM and ISM registers Mark Cave-Ayland
` (12 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The real Q800 hardware used an EASC chip however
a lot of older software only works with the older ASC chip.
Adding this as a machine parameter allows QEMU to be used as an developer aid
for testing and migrating code from ASC to EASC.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++-
include/hw/m68k/q800.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index ed862f9e9d..1af1a06f64 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -710,7 +710,8 @@ static void q800_machine_init(MachineState *machine)
/* Apple Sound Chip */
dev = qdev_new(TYPE_ASC);
- qdev_prop_set_uint8(dev, "asctype", ASC_TYPE_EASC);
+ qdev_prop_set_uint8(dev, "asctype", m->easc ? ASC_TYPE_EASC
+ : ASC_TYPE_ASC);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, ASC_BASE - IO_BASE,
@@ -886,6 +887,28 @@ static void q800_machine_init(MachineState *machine)
}
}
+static bool q800_get_easc(Object *obj, Error **errp)
+{
+ Q800MachineState *ms = Q800_MACHINE(obj);
+
+ return ms->easc;
+}
+
+static void q800_set_easc(Object *obj, bool value, Error **errp)
+{
+ Q800MachineState *ms = Q800_MACHINE(obj);
+
+ ms->easc = value;
+}
+
+static void q800_init(Object *obj)
+{
+ Q800MachineState *ms = Q800_MACHINE(obj);
+
+ /* Default to EASC */
+ ms->easc = true;
+}
+
static GlobalProperty hw_compat_q800[] = {
{ "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
{ "scsi-hd", "vendor", " SEAGATE" },
@@ -912,11 +935,16 @@ static void q800_machine_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_SCSI;
mc->default_ram_id = "m68k_mac.ram";
compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len);
+
+ object_class_property_add_bool(oc, "easc", q800_get_easc, q800_set_easc);
+ object_class_property_set_description(oc, "easc",
+ "Set to off to use ASC rather than EASC");
}
static const TypeInfo q800_machine_typeinfo = {
.name = MACHINE_TYPE_NAME("q800"),
.parent = TYPE_MACHINE,
+ .instance_init = q800_init,
.instance_size = sizeof(Q800MachineState),
.class_init = q800_machine_class_init,
};
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 0602d07d3d..0144be5e6e 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -30,6 +30,7 @@
struct Q800MachineState {
MachineState parent_obj;
+ bool easc;
M68kCPU *cpu;
MemoryRegion rom;
DeviceState *glue;
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 17/30] q800: add easc bool machine class property to switch between ASC and EASC
2023-05-24 21:10 ` [PATCH 17/30] q800: add easc bool machine class property to switch between ASC and EASC Mark Cave-Ayland
@ 2023-05-30 11:28 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:28 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
> (default) or to original mode. The real Q800 hardware used an EASC chip however
> a lot of older software only works with the older ASC chip.
>
> Adding this as a machine parameter allows QEMU to be used as an developer aid
> for testing and migrating code from ASC to EASC.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++-
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
> index ed862f9e9d..1af1a06f64 100644
> --- a/hw/m68k/q800.c
> +++ b/hw/m68k/q800.c
> @@ -710,7 +710,8 @@ static void q800_machine_init(MachineState *machine)
> /* Apple Sound Chip */
>
> dev = qdev_new(TYPE_ASC);
> - qdev_prop_set_uint8(dev, "asctype", ASC_TYPE_EASC);
> + qdev_prop_set_uint8(dev, "asctype", m->easc ? ASC_TYPE_EASC
> + : ASC_TYPE_ASC);
> sysbus = SYS_BUS_DEVICE(dev);
> sysbus_realize_and_unref(sysbus, &error_fatal);
> memory_region_add_subregion(&m->macio, ASC_BASE - IO_BASE,
> @@ -886,6 +887,28 @@ static void q800_machine_init(MachineState *machine)
> }
> }
>
> +static bool q800_get_easc(Object *obj, Error **errp)
> +{
> + Q800MachineState *ms = Q800_MACHINE(obj);
> +
> + return ms->easc;
> +}
> +
> +static void q800_set_easc(Object *obj, bool value, Error **errp)
> +{
> + Q800MachineState *ms = Q800_MACHINE(obj);
> +
> + ms->easc = value;
> +}
> +
> +static void q800_init(Object *obj)
> +{
> + Q800MachineState *ms = Q800_MACHINE(obj);
> +
> + /* Default to EASC */
> + ms->easc = true;
> +}
> +
> static GlobalProperty hw_compat_q800[] = {
> { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
> { "scsi-hd", "vendor", " SEAGATE" },
> @@ -912,11 +935,16 @@ static void q800_machine_class_init(ObjectClass *oc, void *data)
> mc->block_default_type = IF_SCSI;
> mc->default_ram_id = "m68k_mac.ram";
> compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len);
> +
> + object_class_property_add_bool(oc, "easc", q800_get_easc, q800_set_easc);
> + object_class_property_set_description(oc, "easc",
> + "Set to off to use ASC rather than EASC");
> }
>
> static const TypeInfo q800_machine_typeinfo = {
> .name = MACHINE_TYPE_NAME("q800"),
> .parent = TYPE_MACHINE,
> + .instance_init = q800_init,
> .instance_size = sizeof(Q800MachineState),
> .class_init = q800_machine_class_init,
> };
> diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
> index 0602d07d3d..0144be5e6e 100644
> --- a/include/hw/m68k/q800.h
> +++ b/include/hw/m68k/q800.h
> @@ -30,6 +30,7 @@
> struct Q800MachineState {
> MachineState parent_obj;
>
> + bool easc;
> M68kCPU *cpu;
> MemoryRegion rom;
> DeviceState *glue;
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 18/30] swim: add trace events for IWM and ISM registers
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (16 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 17/30] q800: add easc bool machine class property to switch between ASC and EASC Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-25 17:58 ` Philippe Mathieu-Daudé
2023-05-30 11:29 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 19/30] swim: split into separate IWM and ISM register blocks Mark Cave-Ayland
` (11 subsequent siblings)
29 siblings, 2 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/block/swim.c | 14 ++++++++++++++
hw/block/trace-events | 7 +++++++
2 files changed, 21 insertions(+)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 333da08ce0..7df36ea139 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -19,6 +19,7 @@
#include "hw/block/block.h"
#include "hw/block/swim.h"
#include "hw/qdev-properties.h"
+#include "trace.h"
/* IWM registers */
@@ -125,6 +126,13 @@
#define SWIM_HEDSEL 0x20
#define SWIM_MOTON 0x80
+static const char *swim_reg_names[] = {
+ "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER",
+ "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1",
+ "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER",
+ "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE"
+};
+
static void fd_recalibrate(FDrive *drive)
{
}
@@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
reg >>= REG_SHIFT;
swimctrl->regs[reg >> 1] = reg & 1;
+ trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1));
if (swimctrl->regs[IWM_Q6] &&
swimctrl->regs[IWM_Q7]) {
@@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
if (value == 0x57) {
swimctrl->mode = SWIM_MODE_SWIM;
swimctrl->iwm_switch = 0;
+ trace_swim_iwm_switch();
}
break;
}
@@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
swimctrl->regs[reg >> 1] = reg & 1;
+ trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1));
return 0;
}
@@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
reg >>= REG_SHIFT;
+ trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value);
+
switch (reg) {
case SWIM_WRITE_PHASE:
swimctrl->swim_phase = value;
@@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
break;
}
+ trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value);
return value;
}
diff --git a/hw/block/trace-events b/hw/block/trace-events
index 34be8b9135..c041ec45e3 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0
m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
+
+# swim.c
+swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
+swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
+swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
+swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
+swim_iwm_switch(void) "switch from IWM to SWIM mode"
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 18/30] swim: add trace events for IWM and ISM registers
2023-05-24 21:10 ` [PATCH 18/30] swim: add trace events for IWM and ISM registers Mark Cave-Ayland
@ 2023-05-25 17:58 ` Philippe Mathieu-Daudé
2023-05-30 11:29 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-05-25 17:58 UTC (permalink / raw)
To: Mark Cave-Ayland, laurent, qemu-devel
On 24/5/23 23:10, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/block/swim.c | 14 ++++++++++++++
> hw/block/trace-events | 7 +++++++
> 2 files changed, 21 insertions(+)
> diff --git a/hw/block/trace-events b/hw/block/trace-events
> index 34be8b9135..c041ec45e3 100644
> --- a/hw/block/trace-events
> +++ b/hw/block/trace-events
> @@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0
> m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
> m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
> m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
> +
> +# swim.c
> +swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
> +swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
> +swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
> +swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
Preferably 'unsigned reg', otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 54+ messages in thread
* Re: [PATCH 18/30] swim: add trace events for IWM and ISM registers
2023-05-24 21:10 ` [PATCH 18/30] swim: add trace events for IWM and ISM registers Mark Cave-Ayland
2023-05-25 17:58 ` Philippe Mathieu-Daudé
@ 2023-05-30 11:29 ` Laurent Vivier
1 sibling, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 11:29 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/block/swim.c | 14 ++++++++++++++
> hw/block/trace-events | 7 +++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/hw/block/swim.c b/hw/block/swim.c
> index 333da08ce0..7df36ea139 100644
> --- a/hw/block/swim.c
> +++ b/hw/block/swim.c
> @@ -19,6 +19,7 @@
> #include "hw/block/block.h"
> #include "hw/block/swim.h"
> #include "hw/qdev-properties.h"
> +#include "trace.h"
>
> /* IWM registers */
>
> @@ -125,6 +126,13 @@
> #define SWIM_HEDSEL 0x20
> #define SWIM_MOTON 0x80
>
> +static const char *swim_reg_names[] = {
> + "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER",
> + "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1",
> + "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER",
> + "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE"
> +};
> +
> static void fd_recalibrate(FDrive *drive)
> {
> }
> @@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
> reg >>= REG_SHIFT;
>
> swimctrl->regs[reg >> 1] = reg & 1;
> + trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1));
>
> if (swimctrl->regs[IWM_Q6] &&
> swimctrl->regs[IWM_Q7]) {
> @@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
> if (value == 0x57) {
> swimctrl->mode = SWIM_MODE_SWIM;
> swimctrl->iwm_switch = 0;
> + trace_swim_iwm_switch();
> }
> break;
> }
> @@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
>
> swimctrl->regs[reg >> 1] = reg & 1;
>
> + trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1));
> return 0;
> }
>
> @@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
>
> reg >>= REG_SHIFT;
>
> + trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value);
> +
> switch (reg) {
> case SWIM_WRITE_PHASE:
> swimctrl->swim_phase = value;
> @@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
> break;
> }
>
> + trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value);
> return value;
> }
>
> diff --git a/hw/block/trace-events b/hw/block/trace-events
> index 34be8b9135..c041ec45e3 100644
> --- a/hw/block/trace-events
> +++ b/hw/block/trace-events
> @@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0
> m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
> m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
> m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
> +
> +# swim.c
> +swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
> +swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
> +swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
> +swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
> +swim_iwm_switch(void) "switch from IWM to SWIM mode"
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 19/30] swim: split into separate IWM and ISM register blocks
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (17 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 18/30] swim: add trace events for IWM and ISM registers Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 20/30] swim: update IWM/ISM register block decoding Mark Cave-Ayland
` (10 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk
controllers. Split the existing implementation into separate register banks for
each controller, whilst also switching the IWM registers from 16-bit to 8-bit
as implemented in real hardware.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/block/swim.c | 85 ++++++++++++++++++++++++-----------------
hw/block/trace-events | 4 +-
include/hw/block/swim.h | 15 +++-----
3 files changed, 58 insertions(+), 46 deletions(-)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 7df36ea139..735b335883 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -126,7 +126,14 @@
#define SWIM_HEDSEL 0x20
#define SWIM_MOTON 0x80
-static const char *swim_reg_names[] = {
+static const char *iwm_reg_names[] = {
+ "PH0L", "PH0H", "PH1L", "PH1H",
+ "PH2L", "PH2H", "PH3L", "PH3H",
+ "MTROFF", "MTRON", "INTDRIVE", "EXTDRIVE",
+ "Q6L", "Q6H", "Q7L", "Q7H"
+};
+
+static const char *ism_reg_names[] = {
"WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER",
"WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1",
"READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER",
@@ -274,12 +281,11 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
reg >>= REG_SHIFT;
- swimctrl->regs[reg >> 1] = reg & 1;
- trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1));
+ swimctrl->iwmregs[reg] = value;
+ trace_swim_iwmctrl_write(reg, iwm_reg_names[reg], size, value);
- if (swimctrl->regs[IWM_Q6] &&
- swimctrl->regs[IWM_Q7]) {
- if (swimctrl->regs[IWM_MTR]) {
+ if (swimctrl->iwmregs[IWM_Q7H]) {
+ if (swimctrl->iwmregs[IWM_MTRON]) {
/* data register */
swimctrl->iwm_data = value;
} else {
@@ -307,6 +313,12 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
swimctrl->mode = SWIM_MODE_SWIM;
swimctrl->iwm_switch = 0;
trace_swim_iwm_switch();
+
+ /* Switch to ISM registers */
+ memory_region_del_subregion(&swimctrl->swim,
+ &swimctrl->iwm);
+ memory_region_add_subregion(&swimctrl->swim, 0x0,
+ &swimctrl->ism);
}
break;
}
@@ -317,28 +329,30 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
{
SWIMCtrl *swimctrl = opaque;
+ uint16_t value;
reg >>= REG_SHIFT;
- swimctrl->regs[reg >> 1] = reg & 1;
+ value = swimctrl->iwmregs[reg];
+ trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value);
- trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1));
- return 0;
+ return value;
}
-static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
- unsigned size)
+static const MemoryRegionOps swimctrl_iwm_ops = {
+ .write = iwmctrl_write,
+ .read = iwmctrl_read,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value,
+ unsigned size)
{
SWIMCtrl *swimctrl = opaque;
- if (swimctrl->mode == SWIM_MODE_IWM) {
- iwmctrl_write(opaque, reg, value, size);
- return;
- }
-
reg >>= REG_SHIFT;
- trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value);
+ trace_swim_swimctrl_write(reg, ism_reg_names[reg], size, value);
switch (reg) {
case SWIM_WRITE_PHASE:
@@ -359,15 +373,11 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
}
}
-static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
+static uint64_t ismctrl_read(void *opaque, hwaddr reg, unsigned size)
{
SWIMCtrl *swimctrl = opaque;
uint32_t value = 0;
- if (swimctrl->mode == SWIM_MODE_IWM) {
- return iwmctrl_read(opaque, reg, size);
- }
-
reg >>= REG_SHIFT;
switch (reg) {
@@ -389,14 +399,14 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
break;
}
- trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value);
+ trace_swim_swimctrl_read(reg, ism_reg_names[reg], size, value);
return value;
}
-static const MemoryRegionOps swimctrl_mem_ops = {
- .write = swimctrl_write,
- .read = swimctrl_read,
- .endianness = DEVICE_NATIVE_ENDIAN,
+static const MemoryRegionOps swimctrl_ism_ops = {
+ .write = ismctrl_write,
+ .read = ismctrl_read,
+ .endianness = DEVICE_BIG_ENDIAN,
};
static void sysbus_swim_reset(DeviceState *d)
@@ -407,13 +417,13 @@ static void sysbus_swim_reset(DeviceState *d)
ctrl->mode = 0;
ctrl->iwm_switch = 0;
- for (i = 0; i < 8; i++) {
- ctrl->regs[i] = 0;
- }
ctrl->iwm_data = 0;
ctrl->iwm_mode = 0;
+ memset(ctrl->iwmregs, 0, 16);
+
ctrl->swim_phase = 0;
ctrl->swim_mode = 0;
+ memset(ctrl->ismregs, 0, 16);
for (i = 0; i < SWIM_MAX_FD; i++) {
fd_recalibrate(&ctrl->drives[i]);
}
@@ -425,9 +435,12 @@ static void sysbus_swim_init(Object *obj)
Swim *sbs = SWIM(obj);
SWIMCtrl *swimctrl = &sbs->ctrl;
- memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimctrl,
- "swim", 0x2000);
- sysbus_init_mmio(sbd, &swimctrl->iomem);
+ memory_region_init(&swimctrl->swim, obj, "swim", 0x2000);
+ memory_region_init_io(&swimctrl->iwm, obj, &swimctrl_iwm_ops, swimctrl,
+ "iwm", 0x2000);
+ memory_region_init_io(&swimctrl->ism, obj, &swimctrl_ism_ops, swimctrl,
+ "ism", 0x2000);
+ sysbus_init_mmio(sbd, &swimctrl->swim);
}
static void sysbus_swim_realize(DeviceState *dev, Error **errp)
@@ -437,6 +450,9 @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp)
qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);
swimctrl->bus.ctrl = swimctrl;
+
+ /* Default register set is IWM */
+ memory_region_add_subregion(&swimctrl->swim, 0x0, &swimctrl->iwm);
}
static const VMStateDescription vmstate_fdrive = {
@@ -456,10 +472,11 @@ static const VMStateDescription vmstate_swim = {
VMSTATE_INT32(mode, SWIMCtrl),
/* IWM mode */
VMSTATE_INT32(iwm_switch, SWIMCtrl),
- VMSTATE_UINT16_ARRAY(regs, SWIMCtrl, 8),
+ VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 16),
VMSTATE_UINT8(iwm_data, SWIMCtrl),
VMSTATE_UINT8(iwm_mode, SWIMCtrl),
/* SWIM mode */
+ VMSTATE_UINT8_ARRAY(ismregs, SWIMCtrl, 16),
VMSTATE_UINT8(swim_phase, SWIMCtrl),
VMSTATE_UINT8(swim_mode, SWIMCtrl),
/* Drives */
diff --git a/hw/block/trace-events b/hw/block/trace-events
index c041ec45e3..ea84ad6c77 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -94,6 +94,6 @@ m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
# swim.c
swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
-swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
-swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64
+swim_iwmctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
+swim_iwmctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
swim_iwm_switch(void) "switch from IWM to SWIM mode"
diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h
index 9b3dcb029d..1bc7635d02 100644
--- a/include/hw/block/swim.h
+++ b/include/hw/block/swim.h
@@ -43,23 +43,18 @@ typedef struct FDrive {
} FDrive;
struct SWIMCtrl {
- MemoryRegion iomem;
+ MemoryRegion swim;
+ MemoryRegion iwm;
+ MemoryRegion ism;
FDrive drives[SWIM_MAX_FD];
int mode;
/* IWM mode */
int iwm_switch;
- uint16_t regs[8];
-#define IWM_PH0 0
-#define IWM_PH1 1
-#define IWM_PH2 2
-#define IWM_PH3 3
-#define IWM_MTR 4
-#define IWM_DRIVE 5
-#define IWM_Q6 6
-#define IWM_Q7 7
+ uint8_t iwmregs[16];
uint8_t iwm_data;
uint8_t iwm_mode;
/* SWIM mode */
+ uint8_t ismregs[16];
uint8_t swim_phase;
uint8_t swim_mode;
SWIMBus bus;
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 20/30] swim: update IWM/ISM register block decoding
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (18 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 19/30] swim: split into separate IWM and ISM register blocks Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 21/30] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK Mark Cave-Ayland
` (9 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Update the IWM/ISM register block decoding to match the description given in the
"SWIM Chip Users Reference". This allows us to validate the device response to
the guest OS which currently only does just enough to indicate that the floppy
drive is unavailable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/block/swim.c | 212 +++++++++++++++++++++++++---------------
hw/block/trace-events | 7 +-
include/hw/block/swim.h | 8 +-
3 files changed, 143 insertions(+), 84 deletions(-)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 735b335883..fd65c59f8a 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -21,24 +21,28 @@
#include "hw/qdev-properties.h"
#include "trace.h"
+
+/* IWM latch bits */
+
+#define IWMLB_PHASE0 0
+#define IWMLB_PHASE1 1
+#define IWMLB_PHASE2 2
+#define IWMLB_PHASE3 3
+#define IWMLB_MOTORON 4
+#define IWMLB_DRIVESEL 5
+#define IWMLB_L6 6
+#define IWMLB_L7 7
+
/* IWM registers */
-#define IWM_PH0L 0
-#define IWM_PH0H 1
-#define IWM_PH1L 2
-#define IWM_PH1H 3
-#define IWM_PH2L 4
-#define IWM_PH2H 5
-#define IWM_PH3L 6
-#define IWM_PH3H 7
-#define IWM_MTROFF 8
-#define IWM_MTRON 9
-#define IWM_INTDRIVE 10
-#define IWM_EXTDRIVE 11
-#define IWM_Q6L 12
-#define IWM_Q6H 13
-#define IWM_Q7L 14
-#define IWM_Q7H 15
+#define IWM_READALLONES 0
+#define IWM_READDATA 1
+#define IWM_READSTATUS0 2
+#define IWM_READSTATUS1 3
+#define IWM_READWHANDSHAKE0 4
+#define IWM_READWHANDSHAKE1 5
+#define IWM_WRITESETMODE 6
+#define IWM_WRITEDATA 7
/* SWIM registers */
@@ -62,8 +66,9 @@
#define REG_SHIFT 9
-#define SWIM_MODE_IWM 0
-#define SWIM_MODE_SWIM 1
+#define SWIM_MODE_STATUS_BIT 6
+#define SWIM_MODE_IWM 0
+#define SWIM_MODE_ISM 1
/* bits in phase register */
@@ -127,10 +132,8 @@
#define SWIM_MOTON 0x80
static const char *iwm_reg_names[] = {
- "PH0L", "PH0H", "PH1L", "PH1H",
- "PH2L", "PH2H", "PH3L", "PH3H",
- "MTROFF", "MTRON", "INTDRIVE", "EXTDRIVE",
- "Q6L", "Q6H", "Q7L", "Q7H"
+ "READALLONES", "READDATA", "READSTATUS0", "READSTATUS1",
+ "READWHANDSHAKE0", "READWHANDSHAKE1", "WRITESETMODE", "WRITEDATA"
};
static const char *ism_reg_names[] = {
@@ -274,68 +277,99 @@ static const TypeInfo swim_bus_info = {
.instance_size = sizeof(SWIMBus),
};
-static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
+static void iwmctrl_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
SWIMCtrl *swimctrl = opaque;
+ uint8_t latch, reg, ism_bit;
- reg >>= REG_SHIFT;
+ addr >>= REG_SHIFT;
+
+ /* A3-A1 select a latch, A0 specifies the value */
+ latch = (addr >> 1) & 7;
+ if (addr & 1) {
+ swimctrl->iwm_latches |= (1 << latch);
+ } else {
+ swimctrl->iwm_latches &= ~(1 << latch);
+ }
+
+ reg = (swimctrl->iwm_latches & 0xc0) >> 5 |
+ (swimctrl->iwm_latches & 0x10) >> 4;
swimctrl->iwmregs[reg] = value;
trace_swim_iwmctrl_write(reg, iwm_reg_names[reg], size, value);
- if (swimctrl->iwmregs[IWM_Q7H]) {
- if (swimctrl->iwmregs[IWM_MTRON]) {
- /* data register */
- swimctrl->iwm_data = value;
- } else {
- /* mode register */
- swimctrl->iwm_mode = value;
- /* detect sequence to switch from IWM mode to SWIM mode */
- switch (swimctrl->iwm_switch) {
- case 0:
- if (value == 0x57) {
- swimctrl->iwm_switch++;
- }
- break;
- case 1:
- if (value == 0x17) {
- swimctrl->iwm_switch++;
- }
- break;
- case 2:
- if (value == 0x57) {
- swimctrl->iwm_switch++;
- }
- break;
- case 3:
- if (value == 0x57) {
- swimctrl->mode = SWIM_MODE_SWIM;
- swimctrl->iwm_switch = 0;
- trace_swim_iwm_switch();
-
- /* Switch to ISM registers */
- memory_region_del_subregion(&swimctrl->swim,
- &swimctrl->iwm);
- memory_region_add_subregion(&swimctrl->swim, 0x0,
- &swimctrl->ism);
- }
- break;
+ switch (reg) {
+ case IWM_WRITESETMODE:
+ /* detect sequence to switch from IWM mode to SWIM mode */
+ ism_bit = (value & (1 << SWIM_MODE_STATUS_BIT));
+
+ switch (swimctrl->iwm_switch) {
+ case 0:
+ if (ism_bit) { /* 1 */
+ swimctrl->iwm_switch++;
+ }
+ break;
+ case 1:
+ if (!ism_bit) { /* 0 */
+ swimctrl->iwm_switch++;
+ }
+ break;
+ case 2:
+ if (ism_bit) { /* 1 */
+ swimctrl->iwm_switch++;
}
+ break;
+ case 3:
+ if (ism_bit) { /* 1 */
+ swimctrl->iwm_switch++;
+
+ swimctrl->mode = SWIM_MODE_ISM;
+ swimctrl->swim_mode |= (1 << SWIM_MODE_STATUS_BIT);
+ swimctrl->iwm_switch = 0;
+ trace_swim_switch_to_ism();
+
+ /* Switch to ISM registers */
+ memory_region_del_subregion(&swimctrl->swim, &swimctrl->iwm);
+ memory_region_add_subregion(&swimctrl->swim, 0x0,
+ &swimctrl->ism);
+ }
+ break;
}
+ break;
+ default:
+ break;
}
}
-static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
+static uint64_t iwmctrl_read(void *opaque, hwaddr addr, unsigned size)
{
SWIMCtrl *swimctrl = opaque;
- uint16_t value;
+ uint8_t latch, reg, value;
- reg >>= REG_SHIFT;
+ addr >>= REG_SHIFT;
- value = swimctrl->iwmregs[reg];
- trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value);
+ /* A3-A1 select a latch, A0 specifies the value */
+ latch = (addr >> 1) & 7;
+ if (addr & 1) {
+ swimctrl->iwm_latches |= (1 << latch);
+ } else {
+ swimctrl->iwm_latches &= ~(1 << latch);
+ }
+
+ reg = (swimctrl->iwm_latches & 0xc0) >> 5 |
+ (swimctrl->iwm_latches & 0x10) >> 4;
+
+ switch (reg) {
+ case IWM_READALLONES:
+ value = 0xff;
+ break;
+ default:
+ value = 0;
+ break;
+ }
+ trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value);
return value;
}
@@ -352,7 +386,7 @@ static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value,
reg >>= REG_SHIFT;
- trace_swim_swimctrl_write(reg, ism_reg_names[reg], size, value);
+ trace_swim_ismctrl_write(reg, ism_reg_names[reg], size, value);
switch (reg) {
case SWIM_WRITE_PHASE:
@@ -360,14 +394,31 @@ static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value,
break;
case SWIM_WRITE_MODE0:
swimctrl->swim_mode &= ~value;
+ /* Any access to MODE0 register resets PRAM index */
+ swimctrl->pram_idx = 0;
+
+ if (!(swimctrl->swim_mode & (1 << SWIM_MODE_STATUS_BIT))) {
+ /* Clearing the mode bit switches to IWM mode */
+ swimctrl->mode = SWIM_MODE_IWM;
+ swimctrl->iwm_latches = 0;
+ trace_swim_switch_to_iwm();
+
+ /* Switch to IWM registers */
+ memory_region_del_subregion(&swimctrl->swim, &swimctrl->ism);
+ memory_region_add_subregion(&swimctrl->swim, 0x0,
+ &swimctrl->iwm);
+ }
break;
case SWIM_WRITE_MODE1:
swimctrl->swim_mode |= value;
break;
+ case SWIM_WRITE_PARAMETER:
+ swimctrl->pram[swimctrl->pram_idx++] = value;
+ swimctrl->pram_idx &= 0xf;
+ break;
case SWIM_WRITE_DATA:
case SWIM_WRITE_MARK:
case SWIM_WRITE_CRC:
- case SWIM_WRITE_PARAMETER:
case SWIM_WRITE_SETUP:
break;
}
@@ -390,16 +441,24 @@ static uint64_t ismctrl_read(void *opaque, hwaddr reg, unsigned size)
value = SWIM_SENSE;
}
break;
+ case SWIM_READ_PARAMETER:
+ value = swimctrl->pram[swimctrl->pram_idx++];
+ swimctrl->pram_idx &= 0xf;
+ break;
+ case SWIM_READ_STATUS:
+ value = swimctrl->swim_status & ~(1 << SWIM_MODE_STATUS_BIT);
+ if (swimctrl->swim_mode == SWIM_MODE_ISM) {
+ value |= (1 << SWIM_MODE_STATUS_BIT);
+ }
+ break;
case SWIM_READ_DATA:
case SWIM_READ_MARK:
case SWIM_READ_ERROR:
- case SWIM_READ_PARAMETER:
case SWIM_READ_SETUP:
- case SWIM_READ_STATUS:
break;
}
- trace_swim_swimctrl_read(reg, ism_reg_names[reg], size, value);
+ trace_swim_ismctrl_read(reg, ism_reg_names[reg], size, value);
return value;
}
@@ -417,13 +476,11 @@ static void sysbus_swim_reset(DeviceState *d)
ctrl->mode = 0;
ctrl->iwm_switch = 0;
- ctrl->iwm_data = 0;
- ctrl->iwm_mode = 0;
- memset(ctrl->iwmregs, 0, 16);
+ memset(ctrl->iwmregs, 0, sizeof(ctrl->iwmregs));
ctrl->swim_phase = 0;
ctrl->swim_mode = 0;
- memset(ctrl->ismregs, 0, 16);
+ memset(ctrl->ismregs, 0, sizeof(ctrl->ismregs));
for (i = 0; i < SWIM_MAX_FD; i++) {
fd_recalibrate(&ctrl->drives[i]);
}
@@ -472,9 +529,8 @@ static const VMStateDescription vmstate_swim = {
VMSTATE_INT32(mode, SWIMCtrl),
/* IWM mode */
VMSTATE_INT32(iwm_switch, SWIMCtrl),
- VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 16),
- VMSTATE_UINT8(iwm_data, SWIMCtrl),
- VMSTATE_UINT8(iwm_mode, SWIMCtrl),
+ VMSTATE_UINT8(iwm_latches, SWIMCtrl),
+ VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 8),
/* SWIM mode */
VMSTATE_UINT8_ARRAY(ismregs, SWIMCtrl, 16),
VMSTATE_UINT8(swim_phase, SWIMCtrl),
diff --git a/hw/block/trace-events b/hw/block/trace-events
index ea84ad6c77..bab21d3a1c 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -92,8 +92,9 @@ m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
# swim.c
-swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
-swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
+swim_ismctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
+swim_ismctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
swim_iwmctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
swim_iwmctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64
-swim_iwm_switch(void) "switch from IWM to SWIM mode"
+swim_switch_to_ism(void) "switch from IWM to ISM mode"
+swim_switch_to_iwm(void) "switch from ISM to IWM mode"
diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h
index 1bc7635d02..5f567e8d59 100644
--- a/include/hw/block/swim.h
+++ b/include/hw/block/swim.h
@@ -50,13 +50,15 @@ struct SWIMCtrl {
int mode;
/* IWM mode */
int iwm_switch;
- uint8_t iwmregs[16];
- uint8_t iwm_data;
- uint8_t iwm_mode;
+ uint8_t iwm_latches;
+ uint8_t iwmregs[8];
/* SWIM mode */
uint8_t ismregs[16];
uint8_t swim_phase;
uint8_t swim_mode;
+ uint8_t swim_status;
+ uint8_t pram[16];
+ uint8_t pram_idx;
SWIMBus bus;
};
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 21/30] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (19 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 20/30] swim: update IWM/ISM register block decoding Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 22/30] mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf Mark Cave-Ayland
` (8 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
The MacOS toolbox ROM calculates the number of branches that can be executed
per millisecond as part of its timer calibration. Since modern hosts are
considerably quicker than original hardware, the negative counter reaches zero
before the calibration completes leading to division by zero later in
CALCULATESLOD.
Instead of trying to fudge the timing loop (which won't work for TimeDBRA/TimeSCCDB
anyhow), use the pattern of access to the VIA1 registers to detect when SETUPTIMEK
has finished executing and write some well-known good timer values to TimeDBRA
and TimeSCCDB taken from real hardware with a suitable scaling factor.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 115 ++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 1 +
include/hw/misc/mac_via.h | 3 +
3 files changed, 119 insertions(+)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index f90a22a067..62f0988537 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -16,6 +16,7 @@
*/
#include "qemu/osdep.h"
+#include "exec/address-spaces.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
@@ -870,6 +871,112 @@ static void via1_auxmode_update(MOS6522Q800VIA1State *v1s)
}
}
+/*
+ * Addresses and real values for TimeDBRA/TimeSCCB to allow timer calibration
+ * to succeed (NOTE: both values have been multiplied by 3 to cope with the
+ * speed of QEMU execution on a modern host
+ */
+#define MACOS_TIMEDBRA 0xd00
+#define MACOS_TIMESCCB 0xd02
+
+#define MACOS_TIMEDBRA_VALUE (0x2a00 * 3)
+#define MACOS_TIMESCCB_VALUE (0x079d * 3)
+
+static bool via1_is_toolbox_timer_calibrated(void)
+{
+ /*
+ * Indicate whether the MacOS toolbox has been calibrated by checking
+ * for the value of our magic constants
+ */
+ uint16_t timedbra = lduw_be_phys(&address_space_memory, MACOS_TIMEDBRA);
+ uint16_t timesccdb = lduw_be_phys(&address_space_memory, MACOS_TIMESCCB);
+
+ return (timedbra == MACOS_TIMEDBRA_VALUE &&
+ timesccdb == MACOS_TIMESCCB_VALUE);
+}
+
+static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr,
+ uint8_t val)
+{
+ /*
+ * Work around timer calibration to ensure we that we have non-zero and
+ * known good values for TIMEDRBA and TIMESCCDB.
+ *
+ * This works by attempting to detect the reset and calibration sequence
+ * of writes to VIA1
+ */
+ int old_timer_hack_state = v1s->timer_hack_state;
+
+ switch (v1s->timer_hack_state) {
+ case 0:
+ if (addr == VIA_REG_PCR && val == 0x22) {
+ /* VIA_REG_PCR: configure VIA1 edge triggering */
+ v1s->timer_hack_state = 1;
+ }
+ break;
+ case 1:
+ if (addr == VIA_REG_T2CL && val == 0xc) {
+ /* VIA_REG_T2CL: low byte of 1ms counter */
+ if (!via1_is_toolbox_timer_calibrated()) {
+ v1s->timer_hack_state = 2;
+ } else {
+ v1s->timer_hack_state = 0;
+ }
+ }
+ break;
+ case 2:
+ if (addr == VIA_REG_T2CH && val == 0x3) {
+ /*
+ * VIA_REG_T2CH: high byte of 1ms counter (very likely at the
+ * start of SETUPTIMEK)
+ */
+ if (!via1_is_toolbox_timer_calibrated()) {
+ v1s->timer_hack_state = 3;
+ } else {
+ v1s->timer_hack_state = 0;
+ }
+ }
+ break;
+ case 3:
+ if (addr == VIA_REG_IER && val == 0x20) {
+ /*
+ * VIA_REG_IER: update at end of SETUPTIMEK
+ *
+ * Timer calibration has finished: unfortunately the values in
+ * TIMEDBRA (0xd00) and TIMESCCDB (0xd02) are so far out they
+ * cause divide by zero errors.
+ *
+ * Update them with values obtained from a real Q800 but with
+ * a x3 scaling factor which seems to work well
+ */
+ stw_be_phys(&address_space_memory, MACOS_TIMEDBRA,
+ MACOS_TIMEDBRA_VALUE);
+ stw_be_phys(&address_space_memory, MACOS_TIMESCCB,
+ MACOS_TIMESCCB_VALUE);
+
+ v1s->timer_hack_state = 4;
+ }
+ break;
+ case 4:
+ /*
+ * This is the normal post-calibration timer state: we should
+ * generally remain here unless we detect the A/UX calibration
+ * loop, or a write to VIA_REG_PCR suggesting a reset
+ */
+ if (addr == VIA_REG_PCR && val == 0x22) {
+ /* Looks like there has been a reset? */
+ v1s->timer_hack_state = 1;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (old_timer_hack_state != v1s->timer_hack_state) {
+ trace_via1_timer_hack_state(v1s->timer_hack_state);
+ }
+}
+
static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
@@ -895,6 +1002,9 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
MOS6522State *ms = MOS6522(v1s);
addr = (addr >> 9) & 0xf;
+
+ via1_timer_calibration_hack(v1s, addr, val);
+
mos6522_write(ms, addr, val, size);
switch (addr) {
@@ -1007,6 +1117,9 @@ static void mos6522_q800_via1_reset_hold(Object *obj)
adb_set_autopoll_enabled(adb_bus, true);
v1s->cmd = REG_EMPTY;
v1s->alt = REG_EMPTY;
+
+ /* Timer calibration hack */
+ v1s->timer_hack_state = 0;
}
static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp)
@@ -1099,6 +1212,8 @@ static const VMStateDescription vmstate_q800_via1 = {
VMSTATE_INT64(next_second, MOS6522Q800VIA1State),
VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State),
VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State),
+ /* Timer hack */
+ VMSTATE_INT32(timer_hack_state, MOS6522Q800VIA1State),
VMSTATE_END_OF_LIST()
}
};
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 85d2601de9..d3a9295d2f 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -250,6 +250,7 @@ via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s da
via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
via1_auxmode(int mode) "setting auxmode to %d"
+via1_timer_hack_state(int state) "setting timer_hack_state to %d"
# grlib_ahb_apb_pnp.c
grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h
index 422da43bf9..63cdcf7c69 100644
--- a/include/hw/misc/mac_via.h
+++ b/include/hw/misc/mac_via.h
@@ -74,6 +74,9 @@ struct MOS6522Q800VIA1State {
int64_t next_second;
QEMUTimer *sixty_hz_timer;
int64_t next_sixty_hz;
+
+ /* SETUPTIMEK hack */
+ int timer_hack_state;
};
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 22/30] mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (20 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 21/30] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 13:37 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 23/30] mac_via: fix rtc command decoding for the PRAM seconds registers Mark Cave-Ayland
` (7 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
A comparison between the rtc command table included in the comment and the code
itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
the raw command, and not the shifted version held in value.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 62f0988537..d7067030db 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -403,7 +403,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
} else if ((value & 0x1c) == 0x08) {
/* RAM address 0x10 to 0x13 */
return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03));
- } else if ((value & 0x43) == 0x41) {
+ } else if ((value & 0x10) == 0x10) {
/* RAM address 0x00 to 0x0f */
return read | (REG_PRAM_ADDR + (value & 0x0f));
}
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 22/30] mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf
2023-05-24 21:10 ` [PATCH 22/30] mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf Mark Cave-Ayland
@ 2023-05-30 13:37 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 13:37 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> A comparison between the rtc command table included in the comment and the code
> itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
> the raw command, and not the shifted version held in value.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/misc/mac_via.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
> index 62f0988537..d7067030db 100644
> --- a/hw/misc/mac_via.c
> +++ b/hw/misc/mac_via.c
> @@ -403,7 +403,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
> } else if ((value & 0x1c) == 0x08) {
> /* RAM address 0x10 to 0x13 */
> return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03));
> - } else if ((value & 0x43) == 0x41) {
> + } else if ((value & 0x10) == 0x10) {
> /* RAM address 0x00 to 0x0f */
> return read | (REG_PRAM_ADDR + (value & 0x0f));
> }
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 23/30] mac_via: fix rtc command decoding for the PRAM seconds registers
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (21 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 22/30] mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-30 13:38 ` Laurent Vivier
2023-05-24 21:10 ` [PATCH 24/30] mac_via: workaround NetBSD ADB bus enumeration issue Mark Cave-Ayland
` (6 subsequent siblings)
29 siblings, 1 reply; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
separate reads of the seconds registers with commands 0x9d...0x91 followed by
0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
value is only accepted when the values of the 2 separate reads match.
From this we conclude that bit 4 of the rtc command is not decoded or we don't
care about its value when reading the PRAM seconds registers. Implement this
decoding change so that both reads return successfully which allows the MacOS
toolbox ROM to correctly set the date/time.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index d7067030db..5d5334b0f6 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -366,10 +366,10 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
*
* Command byte Register addressed by the command
*
- * z0000001 Seconds register 0 (lowest-order byte)
- * z0000101 Seconds register 1
- * z0001001 Seconds register 2
- * z0001101 Seconds register 3 (highest-order byte)
+ * z00x0001 Seconds register 0 (lowest-order byte)
+ * z00x0101 Seconds register 1
+ * z00x1001 Seconds register 2
+ * z00x1101 Seconds register 3 (highest-order byte)
* 00110001 Test register (write-only)
* 00110101 Write-Protect Register (write-only)
* z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only)
@@ -377,6 +377,7 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
* z0111aaa Extended memory designator and sector number
*
* For a read request, z=1, for a write z=0
+ * The letter x indicates don't care
* The letter a indicates bits whose value depend on what parameter
* RAM byte you want to address
*/
@@ -393,7 +394,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
}
if ((value & 0x03) == 0x01) {
value >>= 2;
- if ((value & 0x1c) == 0) {
+ if ((value & 0x18) == 0) {
/* seconds registers */
return read | (REG_0 + (value & 0x03));
} else if ((value == 0x0c) && !read) {
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* Re: [PATCH 23/30] mac_via: fix rtc command decoding for the PRAM seconds registers
2023-05-24 21:10 ` [PATCH 23/30] mac_via: fix rtc command decoding for the PRAM seconds registers Mark Cave-Ayland
@ 2023-05-30 13:38 ` Laurent Vivier
0 siblings, 0 replies; 54+ messages in thread
From: Laurent Vivier @ 2023-05-30 13:38 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel
Le 24/05/2023 à 23:10, Mark Cave-Ayland a écrit :
> Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
> separate reads of the seconds registers with commands 0x9d...0x91 followed by
> 0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
> value is only accepted when the values of the 2 separate reads match.
>
> From this we conclude that bit 4 of the rtc command is not decoded or we don't
> care about its value when reading the PRAM seconds registers. Implement this
> decoding change so that both reads return successfully which allows the MacOS
> toolbox ROM to correctly set the date/time.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/misc/mac_via.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
> index d7067030db..5d5334b0f6 100644
> --- a/hw/misc/mac_via.c
> +++ b/hw/misc/mac_via.c
> @@ -366,10 +366,10 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
> *
> * Command byte Register addressed by the command
> *
> - * z0000001 Seconds register 0 (lowest-order byte)
> - * z0000101 Seconds register 1
> - * z0001001 Seconds register 2
> - * z0001101 Seconds register 3 (highest-order byte)
> + * z00x0001 Seconds register 0 (lowest-order byte)
> + * z00x0101 Seconds register 1
> + * z00x1001 Seconds register 2
> + * z00x1101 Seconds register 3 (highest-order byte)
> * 00110001 Test register (write-only)
> * 00110101 Write-Protect Register (write-only)
> * z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only)
> @@ -377,6 +377,7 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
> * z0111aaa Extended memory designator and sector number
> *
> * For a read request, z=1, for a write z=0
> + * The letter x indicates don't care
> * The letter a indicates bits whose value depend on what parameter
> * RAM byte you want to address
> */
> @@ -393,7 +394,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
> }
> if ((value & 0x03) == 0x01) {
> value >>= 2;
> - if ((value & 0x1c) == 0) {
> + if ((value & 0x18) == 0) {
> /* seconds registers */
> return read | (REG_0 + (value & 0x03));
> } else if ((value == 0x0c) && !read) {
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 54+ messages in thread
* [PATCH 24/30] mac_via: workaround NetBSD ADB bus enumeration issue
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (22 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 23/30] mac_via: fix rtc command decoding for the PRAM seconds registers Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:10 ` [PATCH 25/30] mac_via: implement ADB_STATE_IDLE state if shift register in input mode Mark Cave-Ayland
` (5 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET
command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE
first as detailed in the ADB protocol.
Add a workaround to detect this condition at the start of ADB enumeration
and send the next command written to SR after a ADB_BUSRESET onto the bus
regardless, even if we don't detect a state transition to ADB_STATE_NEW.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 34 ++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 1 +
2 files changed, 35 insertions(+)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 5d5334b0f6..564db8337e 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -1001,6 +1001,8 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
{
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
MOS6522State *ms = MOS6522(v1s);
+ int oldstate, state;
+ int oldsr = ms->sr;
addr = (addr >> 9) & 0xf;
@@ -1016,6 +1018,38 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
v1s->last_b = ms->b;
break;
+
+ case VIA_REG_SR:
+ {
+ /*
+ * NetBSD assumes it can send its first ADB command after sending
+ * the ADB_BUSRESET command in ADB_STATE_NEW without changing the
+ * state back to ADB_STATE_IDLE first as detailed in the ADB
+ * protocol.
+ *
+ * Add a workaround to detect this condition at the start of ADB
+ * enumeration and send the next command written to SR after a
+ * ADB_BUSRESET onto the bus regardless, even if we don't detect a
+ * state transition to ADB_STATE_NEW.
+ *
+ * Note that in my tests the NetBSD state machine takes one ADB
+ * operation to recover which means the probe for an ADB device at
+ * address 1 always fails. However since the first device is at
+ * address 2 then this will work fine, without having to come up
+ * with a more complicated and invasive solution.
+ */
+ oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >>
+ VIA1B_vADB_StateShift;
+ state = (ms->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift;
+
+ if (oldstate == ADB_STATE_NEW && state == ADB_STATE_NEW &&
+ (ms->acr & VIA1ACR_vShiftOut) &&
+ oldsr == 0 /* ADB_BUSRESET */) {
+ trace_via1_adb_netbsd_enum_hack();
+ adb_via_send(v1s, state, ms->sr);
+ }
+ }
+ break;
}
}
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index d3a9295d2f..7206bd5d93 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -249,6 +249,7 @@ via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "secto
via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s"
via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d"
+via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack"
via1_auxmode(int mode) "setting auxmode to %d"
via1_timer_hack_state(int state) "setting timer_hack_state to %d"
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 25/30] mac_via: implement ADB_STATE_IDLE state if shift register in input mode
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (23 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 24/30] mac_via: workaround NetBSD ADB bus enumeration issue Mark Cave-Ayland
@ 2023-05-24 21:10 ` Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 26/30] mac_via: always clear ADB interrupt when switching to A/UX mode Mark Cave-Ayland
` (4 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:10 UTC (permalink / raw)
To: laurent, qemu-devel
NetBSD switches directly to IDLE state without switching the shift register to
input mode. Duplicate the existing ADB_STATE_IDLE logic in input mode from when
the shift register is in output mode which allows the ADB autopoll handler to
handle the response.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 564db8337e..c1d2866ec9 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -702,6 +702,12 @@ static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data)
break;
case ADB_STATE_IDLE:
+ ms->b |= VIA1B_vADBInt;
+ adb_autopoll_unblock(adb_bus);
+
+ trace_via1_adb_send("IDLE", data,
+ (ms->b & VIA1B_vADBInt) ? "+" : "-");
+
return;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 26/30] mac_via: always clear ADB interrupt when switching to A/UX mode
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (24 preceding siblings ...)
2023-05-24 21:10 ` [PATCH 25/30] mac_via: implement ADB_STATE_IDLE state if shift register in input mode Mark Cave-Ayland
@ 2023-05-24 21:11 ` Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 27/30] q800: add ESCC alias at 0xc000 Mark Cave-Ayland
` (3 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:11 UTC (permalink / raw)
To: laurent, qemu-devel
When the NetBSD kernel initialises it can leave the ADB interrupt asserted
depending upon where in the ADB poll cycle the MacOS ADB interrupt handler
is when the NetBSD kernel disables interrupts.
The NetBSD ADB driver uses the ADB interrupt state to determine if the ADB
is busy and refuses to send ADB commands unless it is clear. To ensure that
this doesn't happen, always clear the ADB interrupt when switching to A/UX
mode to ensure that the bus enumeration always occurs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index c1d2866ec9..ee44cb4437 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -875,6 +875,15 @@ static void via1_auxmode_update(MOS6522Q800VIA1State *v1s)
if (irq != oldirq) {
trace_via1_auxmode(irq);
qemu_set_irq(v1s->auxmode_irq, irq);
+
+ /*
+ * Clear the ADB interrupt. MacOS can leave VIA1B_vADBInt asserted
+ * (low) if a poll sequence doesn't complete before NetBSD disables
+ * interrupts upon boot. Fortunately NetBSD switches to the so-called
+ * "A/UX" interrupt mode after it initialises, so we can use this as
+ * a convenient place to clear the ADB interrupt for now.
+ */
+ s->b |= VIA1B_vADBInt;
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 27/30] q800: add ESCC alias at 0xc000
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (25 preceding siblings ...)
2023-05-24 21:11 ` [PATCH 26/30] mac_via: always clear ADB interrupt when switching to A/UX mode Mark Cave-Ayland
@ 2023-05-24 21:11 ` Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 28/30] q800: add alias for MacOS toolbox ROM at 0x40000000 Mark Cave-Ayland
` (2 subsequent siblings)
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:11 UTC (permalink / raw)
To: laurent, qemu-devel
Tests on real Q800 hardware show that the ESCC is addressable at multiple locations
within the ESCC memory region - at least 0xc000, 0xc020 (as expected by the MacOS
toolbox ROM) and 0xc040.
All released NetBSD kernels before 10 use the 0xc000 address which causes a fatal
error when running the MacOS booter. Add a single memory region alias at 0xc000
to enable NetBSD kernels to start booting under QEMU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 6 ++++++
include/hw/m68k/q800.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 1af1a06f64..3acdb5dd8d 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -682,6 +682,12 @@ static void q800_machine_init(MachineState *machine)
memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
+ /* Create alias for NetBSD */
+ memory_region_init_alias(&m->escc_alias, NULL, "escc-alias",
+ sysbus_mmio_get_region(sysbus, 0), 0, 0x8);
+ memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE - 0x20,
+ &m->escc_alias);
+
/* SCSI */
dev = qdev_new(TYPE_SYSBUS_ESP);
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 0144be5e6e..3039b24d30 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -40,6 +40,7 @@ struct Q800MachineState {
MemoryRegion macio;
MemoryRegion macio_alias;
MemoryRegion machine_id;
+ MemoryRegion escc_alias;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 28/30] q800: add alias for MacOS toolbox ROM at 0x40000000
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (26 preceding siblings ...)
2023-05-24 21:11 ` [PATCH 27/30] q800: add ESCC alias at 0xc000 Mark Cave-Ayland
@ 2023-05-24 21:11 ` Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 29/30] mac_via: extend timer calibration hack to work with A/UX Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 30/30] mac_via: work around QEMU unaligned MMIO access bug Mark Cave-Ayland
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:11 UTC (permalink / raw)
To: laurent, qemu-devel
According to the Apple Quadra 800 Developer Note document, the Quadra 800 ROM
consists of 2 ROM code sections based at offsets 0x0 and 0x800000. A/UX attempts
to access the toolbox ROM at the lower offset during startup, so provide a
memory alias to allow the access to succeed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 5 +++++
include/hw/m68k/q800.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 3acdb5dd8d..bf4acb5db7 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -869,6 +869,11 @@ static void q800_machine_init(MachineState *machine)
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
+ memory_region_init_alias(&m->rom_alias, NULL, "m68k_mac.rom-alias",
+ &m->rom, 0, MACROM_SIZE);
+ memory_region_add_subregion(get_system_memory(), 0x40000000,
+ &m->rom_alias);
+
/* Load MacROM binary */
if (filename) {
bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE);
diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h
index 3039b24d30..1a0dbb5ecd 100644
--- a/include/hw/m68k/q800.h
+++ b/include/hw/m68k/q800.h
@@ -33,6 +33,7 @@ struct Q800MachineState {
bool easc;
M68kCPU *cpu;
MemoryRegion rom;
+ MemoryRegion rom_alias;
DeviceState *glue;
DeviceState *djmemc;
MemoryRegion ramio;
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 29/30] mac_via: extend timer calibration hack to work with A/UX
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (27 preceding siblings ...)
2023-05-24 21:11 ` [PATCH 28/30] q800: add alias for MacOS toolbox ROM at 0x40000000 Mark Cave-Ayland
@ 2023-05-24 21:11 ` Mark Cave-Ayland
2023-05-24 21:11 ` [PATCH 30/30] mac_via: work around QEMU unaligned MMIO access bug Mark Cave-Ayland
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:11 UTC (permalink / raw)
To: laurent, qemu-devel
The A/UX timer calibration loop runs continuously until 2 consecutive iterations
differ by at least 0x492 timer ticks. Modern hosts execute the timer calibration
loop so fast that this situation never occurs causing a hang on boot.
Use a similar method to Shoebill which is to randomly add 0x500 to the T2
counter value during calibration to enable it to eventually succeed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/misc/mac_via.c | 55 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index ee44cb4437..4ec1ee18dd 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -973,6 +973,7 @@ static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr,
v1s->timer_hack_state = 4;
}
break;
+
case 4:
/*
* This is the normal post-calibration timer state: we should
@@ -983,6 +984,38 @@ static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr,
/* Looks like there has been a reset? */
v1s->timer_hack_state = 1;
}
+
+ if (addr == VIA_REG_T2CL && val == 0xf0) {
+ /* VIA_REG_T2CH: high byte of counter (A/UX) */
+ v1s->timer_hack_state = 5;
+ }
+ break;
+ case 5:
+ if (addr == VIA_REG_T2CH && val == 0x3c) {
+ /* VIA_REG_T2CL: low byte of counter (A/UX) */
+ v1s->timer_hack_state = 6;
+ } else {
+ v1s->timer_hack_state = 0;
+ }
+ break;
+ case 6:
+ if ((addr == VIA_REG_IER && val == 0x20) || addr == VIA_REG_T2CH) {
+ /* End of A/UX timer calibration routine, or another write */
+ v1s->timer_hack_state = 7;
+ } else {
+ v1s->timer_hack_state = 0;
+ }
+ break;
+ case 7:
+ /*
+ * This is the normal post-calibration timer state once both the
+ * MacOS toolbox and A/UX have been calibrated, until we see a write
+ * to VIA_REG_PCR to suggest a reset
+ */
+ if (addr == VIA_REG_PCR && val == 0x22) {
+ /* Looks like there has been a reset? */
+ v1s->timer_hack_state = 1;
+ }
break;
default:
g_assert_not_reached();
@@ -995,8 +1028,9 @@ static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr,
static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
{
- MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
- MOS6522State *ms = MOS6522(s);
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
+ MOS6522State *ms = MOS6522(v1s);
+ int64_t now;
uint64_t ret;
addr = (addr >> 9) & 0xf;
@@ -1007,6 +1041,23 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
/* Quadra 800 Id */
ret = (ret & ~VIA1A_CPUID_MASK) | VIA1A_CPUID_Q800;
break;
+ case VIA_REG_T2CH:
+ if (v1s->timer_hack_state == 6) {
+ /*
+ * The A/UX timer calibration loop runs continuously until 2
+ * consecutive iterations differ by at least 0x492 timer ticks.
+ * Modern hosts execute the timer calibration loop so fast that
+ * this situation never occurs causing a hang on boot. Use a
+ * similar method to Shoebill which is to randomly add 0x500 to
+ * the T2 counter value during calibration to enable it to
+ * eventually succeed.
+ */
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ if (now & 1) {
+ ret += 0x5;
+ }
+ }
+ break;
}
return ret;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread* [PATCH 30/30] mac_via: work around QEMU unaligned MMIO access bug
2023-05-24 21:10 [PATCH 00/30] q800: add support for booting MacOS Classic Mark Cave-Ayland
` (28 preceding siblings ...)
2023-05-24 21:11 ` [PATCH 29/30] mac_via: extend timer calibration hack to work with A/UX Mark Cave-Ayland
@ 2023-05-24 21:11 ` Mark Cave-Ayland
29 siblings, 0 replies; 54+ messages in thread
From: Mark Cave-Ayland @ 2023-05-24 21:11 UTC (permalink / raw)
To: laurent, qemu-devel
During the kernel timer calibration routine A/UX performs an unaligned access
across the T1CL and T1CH registers to read the entire 16-bit value in a
single memory access.
This triggers a bug in the QEMU softtlb implementation whereby the 2 separate
accesses are combined incorrectly losing the high byte of the counter (see
https://gitlab.com/qemu-project/qemu/-/issues/360 for more detail). Since
A/UX requires a minimum difference of 0x500 between 2 subsequent reads to
succeed then this causes the timer calibration routine to get stuck in an
infinite loop.
Add a temporary workaround for the QEMU unaligned MMIO access bug whereby
these special accesses are detected and the 8-byte result copied into both
halves of the 16-bit access which allows the existing softtlb implementation
to return the correct result.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/m68k/q800.c | 1 +
hw/misc/mac_via.c | 42 +++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 1 +
include/hw/misc/mac_via.h | 4 +++-
4 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index bf4acb5db7..918cc8f695 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -443,6 +443,7 @@ static const MemoryRegionOps macio_alias_ops = {
.valid = {
.min_access_size = 1,
.max_access_size = 4,
+ .unaligned = true, /* For VIA1 via1_unaligned_hack_state() */
},
};
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 4ec1ee18dd..45c8dee9f4 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -1026,12 +1026,47 @@ static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr,
}
}
+static bool via1_unaligned_hack_state(MOS6522Q800VIA1State *v1s, hwaddr addr,
+ int size)
+{
+ /*
+ * Workaround for bug in QEMU whereby load_helper() doesn't correctly
+ * handle combining unaligned memory accesses: see QEMU issue
+ * https://gitlab.com/qemu-project/qemu/-/issues/360 for all the
+ * details.
+ *
+ * Its only known use is during the A/UX timer calibration loop which
+ * runs on kernel startup.
+ */
+ switch (v1s->unaligned_hack_state) {
+ case 0:
+ /* First half of unaligned access */
+ if (addr == 0x11fe && size == 2) {
+ v1s->unaligned_hack_state = 1;
+ trace_via1_unaligned_hack_state(v1s->unaligned_hack_state);
+ return true;
+ }
+ return false;
+ case 1:
+ /* Second half of unaligned access */
+ if (addr == 0x1200 && size == 2) {
+ v1s->unaligned_hack_state = 0;
+ trace_via1_unaligned_hack_state(v1s->unaligned_hack_state);
+ return true;
+ }
+ return false;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque);
MOS6522State *ms = MOS6522(v1s);
int64_t now;
uint64_t ret;
+ hwaddr oldaddr = addr;
addr = (addr >> 9) & 0xf;
ret = mos6522_read(ms, addr, size);
@@ -1059,6 +1094,12 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
}
break;
}
+
+ if (via1_unaligned_hack_state(v1s, oldaddr, size)) {
+ /* Splat return byte into word to fix unaligned access combine */
+ ret |= ret << 8;
+ }
+
return ret;
}
@@ -1126,6 +1167,7 @@ static const MemoryRegionOps mos6522_q800_via1_ops = {
.valid = {
.min_access_size = 1,
.max_access_size = 4,
+ .unaligned = true, /* For VIA1 via1_unaligned_hack_state() */
},
};
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 7206bd5d93..8867cef356 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -252,6 +252,7 @@ via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size
via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack"
via1_auxmode(int mode) "setting auxmode to %d"
via1_timer_hack_state(int state) "setting timer_hack_state to %d"
+via1_unaligned_hack_state(int state) "setting unaligned_hack_state to %d"
# grlib_ahb_apb_pnp.c
grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h
index 63cdcf7c69..0a12737552 100644
--- a/include/hw/misc/mac_via.h
+++ b/include/hw/misc/mac_via.h
@@ -77,8 +77,10 @@ struct MOS6522Q800VIA1State {
/* SETUPTIMEK hack */
int timer_hack_state;
-};
+ /* Unaligned access hack */
+ int unaligned_hack_state;
+};
/* VIA 2 */
#define VIA2_IRQ_SCSI_DATA_BIT CA2_INT_BIT
--
2.30.2
^ permalink raw reply related [flat|nested] 54+ messages in thread